2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/dma-fence-array.h>
38 #include <linux/reservation.h>
39 #include <linux/shmem_fs.h>
40 #include <linux/slab.h>
41 #include <linux/swap.h>
42 #include <linux/pci.h>
43 #include <linux/dma-buf.h>
45 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
46 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
47 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
49 static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
52 return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
57 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
60 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
63 return obj->pin_display;
67 insert_mappable_node(struct i915_ggtt *ggtt,
68 struct drm_mm_node *node, u32 size)
70 memset(node, 0, sizeof(*node));
71 return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node,
73 0, ggtt->mappable_end,
74 DRM_MM_SEARCH_DEFAULT,
75 DRM_MM_CREATE_DEFAULT);
79 remove_mappable_node(struct drm_mm_node *node)
81 drm_mm_remove_node(node);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
88 spin_lock(&dev_priv->mm.object_stat_lock);
89 dev_priv->mm.object_count++;
90 dev_priv->mm.object_memory += size;
91 spin_unlock(&dev_priv->mm.object_stat_lock);
94 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
97 spin_lock(&dev_priv->mm.object_stat_lock);
98 dev_priv->mm.object_count--;
99 dev_priv->mm.object_memory -= size;
100 spin_unlock(&dev_priv->mm.object_stat_lock);
104 i915_gem_wait_for_error(struct i915_gpu_error *error)
110 if (!i915_reset_in_progress(error))
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
118 ret = wait_event_interruptible_timeout(error->reset_queue,
119 !i915_reset_in_progress(error),
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
124 } else if (ret < 0) {
131 int i915_mutex_lock_interruptible(struct drm_device *dev)
133 struct drm_i915_private *dev_priv = to_i915(dev);
136 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
140 ret = mutex_lock_interruptible(&dev->struct_mutex);
148 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
149 struct drm_file *file)
151 struct drm_i915_private *dev_priv = to_i915(dev);
152 struct i915_ggtt *ggtt = &dev_priv->ggtt;
153 struct drm_i915_gem_get_aperture *args = data;
154 struct i915_vma *vma;
158 mutex_lock(&dev->struct_mutex);
159 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
160 if (i915_vma_is_pinned(vma))
161 pinned += vma->node.size;
162 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
163 if (i915_vma_is_pinned(vma))
164 pinned += vma->node.size;
165 mutex_unlock(&dev->struct_mutex);
167 args->aper_size = ggtt->base.total;
168 args->aper_available_size = args->aper_size - pinned;
173 static struct sg_table *
174 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
176 struct address_space *mapping = obj->base.filp->f_mapping;
177 char *vaddr = obj->phys_handle->vaddr;
179 struct scatterlist *sg;
182 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
183 return ERR_PTR(-EINVAL);
185 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
189 page = shmem_read_mapping_page(mapping, i);
191 return ERR_CAST(page);
193 src = kmap_atomic(page);
194 memcpy(vaddr, src, PAGE_SIZE);
195 drm_clflush_virt_range(vaddr, PAGE_SIZE);
202 i915_gem_chipset_flush(to_i915(obj->base.dev));
204 st = kmalloc(sizeof(*st), GFP_KERNEL);
206 return ERR_PTR(-ENOMEM);
208 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
210 return ERR_PTR(-ENOMEM);
215 sg->length = obj->base.size;
217 sg_dma_address(sg) = obj->phys_handle->busaddr;
218 sg_dma_len(sg) = obj->base.size;
224 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
225 struct sg_table *pages)
227 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
229 if (obj->mm.madv == I915_MADV_DONTNEED)
230 obj->mm.dirty = false;
232 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
233 drm_clflush_sg(pages);
235 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
236 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
240 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
241 struct sg_table *pages)
243 __i915_gem_object_release_shmem(obj, pages);
246 struct address_space *mapping = obj->base.filp->f_mapping;
247 char *vaddr = obj->phys_handle->vaddr;
250 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
254 page = shmem_read_mapping_page(mapping, i);
258 dst = kmap_atomic(page);
259 drm_clflush_virt_range(vaddr, PAGE_SIZE);
260 memcpy(dst, vaddr, PAGE_SIZE);
263 set_page_dirty(page);
264 if (obj->mm.madv == I915_MADV_WILLNEED)
265 mark_page_accessed(page);
269 obj->mm.dirty = false;
272 sg_free_table(pages);
277 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
279 drm_pci_free(obj->base.dev, obj->phys_handle);
280 i915_gem_object_unpin_pages(obj);
283 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
284 .get_pages = i915_gem_object_get_pages_phys,
285 .put_pages = i915_gem_object_put_pages_phys,
286 .release = i915_gem_object_release_phys,
289 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
291 struct i915_vma *vma;
292 LIST_HEAD(still_in_list);
295 lockdep_assert_held(&obj->base.dev->struct_mutex);
297 /* Closed vma are removed from the obj->vma_list - but they may
298 * still have an active binding on the object. To remove those we
299 * must wait for all rendering to complete to the object (as unbinding
300 * must anyway), and retire the requests.
302 ret = i915_gem_object_wait(obj,
303 I915_WAIT_INTERRUPTIBLE |
306 MAX_SCHEDULE_TIMEOUT,
311 i915_gem_retire_requests(to_i915(obj->base.dev));
313 while ((vma = list_first_entry_or_null(&obj->vma_list,
316 list_move_tail(&vma->obj_link, &still_in_list);
317 ret = i915_vma_unbind(vma);
321 list_splice(&still_in_list, &obj->vma_list);
327 i915_gem_object_wait_fence(struct dma_fence *fence,
330 struct intel_rps_client *rps)
332 struct drm_i915_gem_request *rq;
334 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
336 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
339 if (!dma_fence_is_i915(fence))
340 return dma_fence_wait_timeout(fence,
341 flags & I915_WAIT_INTERRUPTIBLE,
344 rq = to_request(fence);
345 if (i915_gem_request_completed(rq))
348 /* This client is about to stall waiting for the GPU. In many cases
349 * this is undesirable and limits the throughput of the system, as
350 * many clients cannot continue processing user input/output whilst
351 * blocked. RPS autotuning may take tens of milliseconds to respond
352 * to the GPU load and thus incurs additional latency for the client.
353 * We can circumvent that by promoting the GPU frequency to maximum
354 * before we wait. This makes the GPU throttle up much more quickly
355 * (good for benchmarks and user experience, e.g. window animations),
356 * but at a cost of spending more power processing the workload
357 * (bad for battery). Not all clients even want their results
358 * immediately and for them we should just let the GPU select its own
359 * frequency to maximise efficiency. To prevent a single client from
360 * forcing the clocks too high for the whole system, we only allow
361 * each client to waitboost once in a busy period.
364 if (INTEL_GEN(rq->i915) >= 6)
365 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
370 timeout = i915_wait_request(rq, flags, timeout);
373 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
374 i915_gem_request_retire_upto(rq);
376 if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
377 /* The GPU is now idle and this client has stalled.
378 * Since no other client has submitted a request in the
379 * meantime, assume that this client is the only one
380 * supplying work to the GPU but is unable to keep that
381 * work supplied because it is waiting. Since the GPU is
382 * then never kept fully busy, RPS autoclocking will
383 * keep the clocks relatively low, causing further delays.
384 * Compensate by giving the synchronous client credit for
385 * a waitboost next time.
387 spin_lock(&rq->i915->rps.client_lock);
388 list_del_init(&rps->link);
389 spin_unlock(&rq->i915->rps.client_lock);
396 i915_gem_object_wait_reservation(struct reservation_object *resv,
399 struct intel_rps_client *rps)
401 struct dma_fence *excl;
403 if (flags & I915_WAIT_ALL) {
404 struct dma_fence **shared;
405 unsigned int count, i;
408 ret = reservation_object_get_fences_rcu(resv,
409 &excl, &count, &shared);
413 for (i = 0; i < count; i++) {
414 timeout = i915_gem_object_wait_fence(shared[i],
420 dma_fence_put(shared[i]);
423 for (; i < count; i++)
424 dma_fence_put(shared[i]);
427 excl = reservation_object_get_excl_rcu(resv);
430 if (excl && timeout > 0)
431 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
438 static void __fence_set_priority(struct dma_fence *fence, int prio)
440 struct drm_i915_gem_request *rq;
441 struct intel_engine_cs *engine;
443 if (!dma_fence_is_i915(fence))
446 rq = to_request(fence);
448 if (!engine->schedule)
451 engine->schedule(rq, prio);
454 static void fence_set_priority(struct dma_fence *fence, int prio)
456 /* Recurse once into a fence-array */
457 if (dma_fence_is_array(fence)) {
458 struct dma_fence_array *array = to_dma_fence_array(fence);
461 for (i = 0; i < array->num_fences; i++)
462 __fence_set_priority(array->fences[i], prio);
464 __fence_set_priority(fence, prio);
469 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
473 struct dma_fence *excl;
475 if (flags & I915_WAIT_ALL) {
476 struct dma_fence **shared;
477 unsigned int count, i;
480 ret = reservation_object_get_fences_rcu(obj->resv,
481 &excl, &count, &shared);
485 for (i = 0; i < count; i++) {
486 fence_set_priority(shared[i], prio);
487 dma_fence_put(shared[i]);
492 excl = reservation_object_get_excl_rcu(obj->resv);
496 fence_set_priority(excl, prio);
503 * Waits for rendering to the object to be completed
504 * @obj: i915 gem object
505 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
506 * @timeout: how long to wait
507 * @rps: client (user process) to charge for any waitboosting
510 i915_gem_object_wait(struct drm_i915_gem_object *obj,
513 struct intel_rps_client *rps)
516 #if IS_ENABLED(CONFIG_LOCKDEP)
517 GEM_BUG_ON(debug_locks &&
518 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
519 !!(flags & I915_WAIT_LOCKED));
521 GEM_BUG_ON(timeout < 0);
523 timeout = i915_gem_object_wait_reservation(obj->resv,
526 return timeout < 0 ? timeout : 0;
529 static struct intel_rps_client *to_rps_client(struct drm_file *file)
531 struct drm_i915_file_private *fpriv = file->driver_priv;
537 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
540 drm_dma_handle_t *phys;
543 if (obj->phys_handle) {
544 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
550 if (obj->mm.madv != I915_MADV_WILLNEED)
553 if (obj->base.filp == NULL)
556 ret = i915_gem_object_unbind(obj);
560 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
564 /* create a new object */
565 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
569 obj->phys_handle = phys;
570 obj->ops = &i915_gem_phys_ops;
572 return i915_gem_object_pin_pages(obj);
576 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
577 struct drm_i915_gem_pwrite *args,
578 struct drm_file *file)
580 struct drm_device *dev = obj->base.dev;
581 void *vaddr = obj->phys_handle->vaddr + args->offset;
582 char __user *user_data = u64_to_user_ptr(args->data_ptr);
585 /* We manually control the domain here and pretend that it
586 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
588 lockdep_assert_held(&obj->base.dev->struct_mutex);
589 ret = i915_gem_object_wait(obj,
590 I915_WAIT_INTERRUPTIBLE |
593 MAX_SCHEDULE_TIMEOUT,
594 to_rps_client(file));
598 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
599 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
600 unsigned long unwritten;
602 /* The physical object once assigned is fixed for the lifetime
603 * of the obj, so we can safely drop the lock and continue
606 mutex_unlock(&dev->struct_mutex);
607 unwritten = copy_from_user(vaddr, user_data, args->size);
608 mutex_lock(&dev->struct_mutex);
615 drm_clflush_virt_range(vaddr, args->size);
616 i915_gem_chipset_flush(to_i915(dev));
619 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
623 void *i915_gem_object_alloc(struct drm_device *dev)
625 struct drm_i915_private *dev_priv = to_i915(dev);
626 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
629 void i915_gem_object_free(struct drm_i915_gem_object *obj)
631 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
632 kmem_cache_free(dev_priv->objects, obj);
636 i915_gem_create(struct drm_file *file,
637 struct drm_device *dev,
641 struct drm_i915_gem_object *obj;
645 size = roundup(size, PAGE_SIZE);
649 /* Allocate the new object */
650 obj = i915_gem_object_create(dev, size);
654 ret = drm_gem_handle_create(file, &obj->base, &handle);
655 /* drop reference from allocate - handle holds it now */
656 i915_gem_object_put(obj);
665 i915_gem_dumb_create(struct drm_file *file,
666 struct drm_device *dev,
667 struct drm_mode_create_dumb *args)
669 /* have to work out size/pitch and return them */
670 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
671 args->size = args->pitch * args->height;
672 return i915_gem_create(file, dev,
673 args->size, &args->handle);
677 * Creates a new mm object and returns a handle to it.
678 * @dev: drm device pointer
679 * @data: ioctl data blob
680 * @file: drm file pointer
683 i915_gem_create_ioctl(struct drm_device *dev, void *data,
684 struct drm_file *file)
686 struct drm_i915_gem_create *args = data;
688 i915_gem_flush_free_objects(to_i915(dev));
690 return i915_gem_create(file, dev,
691 args->size, &args->handle);
695 __copy_to_user_swizzled(char __user *cpu_vaddr,
696 const char *gpu_vaddr, int gpu_offset,
699 int ret, cpu_offset = 0;
702 int cacheline_end = ALIGN(gpu_offset + 1, 64);
703 int this_length = min(cacheline_end - gpu_offset, length);
704 int swizzled_gpu_offset = gpu_offset ^ 64;
706 ret = __copy_to_user(cpu_vaddr + cpu_offset,
707 gpu_vaddr + swizzled_gpu_offset,
712 cpu_offset += this_length;
713 gpu_offset += this_length;
714 length -= this_length;
721 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
722 const char __user *cpu_vaddr,
725 int ret, cpu_offset = 0;
728 int cacheline_end = ALIGN(gpu_offset + 1, 64);
729 int this_length = min(cacheline_end - gpu_offset, length);
730 int swizzled_gpu_offset = gpu_offset ^ 64;
732 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
733 cpu_vaddr + cpu_offset,
738 cpu_offset += this_length;
739 gpu_offset += this_length;
740 length -= this_length;
747 * Pins the specified object's pages and synchronizes the object with
748 * GPU accesses. Sets needs_clflush to non-zero if the caller should
749 * flush the object from the CPU cache.
751 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
752 unsigned int *needs_clflush)
756 lockdep_assert_held(&obj->base.dev->struct_mutex);
759 if (!i915_gem_object_has_struct_page(obj))
762 ret = i915_gem_object_wait(obj,
763 I915_WAIT_INTERRUPTIBLE |
765 MAX_SCHEDULE_TIMEOUT,
770 ret = i915_gem_object_pin_pages(obj);
774 i915_gem_object_flush_gtt_write_domain(obj);
776 /* If we're not in the cpu read domain, set ourself into the gtt
777 * read domain and manually flush cachelines (if required). This
778 * optimizes for the case when the gpu will dirty the data
779 * anyway again before the next pread happens.
781 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
782 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
785 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
786 ret = i915_gem_object_set_to_cpu_domain(obj, false);
793 /* return with the pages pinned */
797 i915_gem_object_unpin_pages(obj);
801 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
802 unsigned int *needs_clflush)
806 lockdep_assert_held(&obj->base.dev->struct_mutex);
809 if (!i915_gem_object_has_struct_page(obj))
812 ret = i915_gem_object_wait(obj,
813 I915_WAIT_INTERRUPTIBLE |
816 MAX_SCHEDULE_TIMEOUT,
821 ret = i915_gem_object_pin_pages(obj);
825 i915_gem_object_flush_gtt_write_domain(obj);
827 /* If we're not in the cpu write domain, set ourself into the
828 * gtt write domain and manually flush cachelines (as required).
829 * This optimizes for the case when the gpu will use the data
830 * right away and we therefore have to clflush anyway.
832 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
833 *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
835 /* Same trick applies to invalidate partially written cachelines read
838 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
839 *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,
842 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
843 ret = i915_gem_object_set_to_cpu_domain(obj, true);
850 if ((*needs_clflush & CLFLUSH_AFTER) == 0)
851 obj->cache_dirty = true;
853 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
854 obj->mm.dirty = true;
855 /* return with the pages pinned */
859 i915_gem_object_unpin_pages(obj);
864 shmem_clflush_swizzled_range(char *addr, unsigned long length,
867 if (unlikely(swizzled)) {
868 unsigned long start = (unsigned long) addr;
869 unsigned long end = (unsigned long) addr + length;
871 /* For swizzling simply ensure that we always flush both
872 * channels. Lame, but simple and it works. Swizzled
873 * pwrite/pread is far from a hotpath - current userspace
874 * doesn't use it at all. */
875 start = round_down(start, 128);
876 end = round_up(end, 128);
878 drm_clflush_virt_range((void *)start, end - start);
880 drm_clflush_virt_range(addr, length);
885 /* Only difference to the fast-path function is that this can handle bit17
886 * and uses non-atomic copy and kmap functions. */
888 shmem_pread_slow(struct page *page, int offset, int length,
889 char __user *user_data,
890 bool page_do_bit17_swizzling, bool needs_clflush)
897 shmem_clflush_swizzled_range(vaddr + offset, length,
898 page_do_bit17_swizzling);
900 if (page_do_bit17_swizzling)
901 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
903 ret = __copy_to_user(user_data, vaddr + offset, length);
906 return ret ? - EFAULT : 0;
910 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
911 bool page_do_bit17_swizzling, bool needs_clflush)
916 if (!page_do_bit17_swizzling) {
917 char *vaddr = kmap_atomic(page);
920 drm_clflush_virt_range(vaddr + offset, length);
921 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
922 kunmap_atomic(vaddr);
927 return shmem_pread_slow(page, offset, length, user_data,
928 page_do_bit17_swizzling, needs_clflush);
932 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
933 struct drm_i915_gem_pread *args)
935 char __user *user_data;
937 unsigned int obj_do_bit17_swizzling;
938 unsigned int needs_clflush;
939 unsigned int idx, offset;
942 obj_do_bit17_swizzling = 0;
943 if (i915_gem_object_needs_bit17_swizzle(obj))
944 obj_do_bit17_swizzling = BIT(17);
946 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
950 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
951 mutex_unlock(&obj->base.dev->struct_mutex);
956 user_data = u64_to_user_ptr(args->data_ptr);
957 offset = offset_in_page(args->offset);
958 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
959 struct page *page = i915_gem_object_get_page(obj, idx);
963 if (offset + length > PAGE_SIZE)
964 length = PAGE_SIZE - offset;
966 ret = shmem_pread(page, offset, length, user_data,
967 page_to_phys(page) & obj_do_bit17_swizzling,
977 i915_gem_obj_finish_shmem_access(obj);
982 gtt_user_read(struct io_mapping *mapping,
983 loff_t base, int offset,
984 char __user *user_data, int length)
987 unsigned long unwritten;
989 /* We can use the cpu mem copy function because this is X86. */
990 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
991 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
992 io_mapping_unmap_atomic(vaddr);
994 vaddr = (void __force *)
995 io_mapping_map_wc(mapping, base, PAGE_SIZE);
996 unwritten = copy_to_user(user_data, vaddr + offset, length);
997 io_mapping_unmap(vaddr);
1003 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1004 const struct drm_i915_gem_pread *args)
1006 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1007 struct i915_ggtt *ggtt = &i915->ggtt;
1008 struct drm_mm_node node;
1009 struct i915_vma *vma;
1010 void __user *user_data;
1014 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1018 intel_runtime_pm_get(i915);
1019 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1020 PIN_MAPPABLE | PIN_NONBLOCK);
1022 node.start = i915_ggtt_offset(vma);
1023 node.allocated = false;
1024 ret = i915_vma_put_fence(vma);
1026 i915_vma_unpin(vma);
1031 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1034 GEM_BUG_ON(!node.allocated);
1037 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1041 mutex_unlock(&i915->drm.struct_mutex);
1043 user_data = u64_to_user_ptr(args->data_ptr);
1044 remain = args->size;
1045 offset = args->offset;
1047 while (remain > 0) {
1048 /* Operation in this page
1050 * page_base = page offset within aperture
1051 * page_offset = offset within page
1052 * page_length = bytes to copy for this page
1054 u32 page_base = node.start;
1055 unsigned page_offset = offset_in_page(offset);
1056 unsigned page_length = PAGE_SIZE - page_offset;
1057 page_length = remain < page_length ? remain : page_length;
1058 if (node.allocated) {
1060 ggtt->base.insert_page(&ggtt->base,
1061 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1062 node.start, I915_CACHE_NONE, 0);
1065 page_base += offset & PAGE_MASK;
1068 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1069 user_data, page_length)) {
1074 remain -= page_length;
1075 user_data += page_length;
1076 offset += page_length;
1079 mutex_lock(&i915->drm.struct_mutex);
1081 if (node.allocated) {
1083 ggtt->base.clear_range(&ggtt->base,
1084 node.start, node.size);
1085 remove_mappable_node(&node);
1087 i915_vma_unpin(vma);
1090 intel_runtime_pm_put(i915);
1091 mutex_unlock(&i915->drm.struct_mutex);
1097 * Reads data from the object referenced by handle.
1098 * @dev: drm device pointer
1099 * @data: ioctl data blob
1100 * @file: drm file pointer
1102 * On error, the contents of *data are undefined.
1105 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1106 struct drm_file *file)
1108 struct drm_i915_gem_pread *args = data;
1109 struct drm_i915_gem_object *obj;
1112 if (args->size == 0)
1115 if (!access_ok(VERIFY_WRITE,
1116 u64_to_user_ptr(args->data_ptr),
1120 obj = i915_gem_object_lookup(file, args->handle);
1124 /* Bounds check source. */
1125 if (args->offset > obj->base.size ||
1126 args->size > obj->base.size - args->offset) {
1131 trace_i915_gem_object_pread(obj, args->offset, args->size);
1133 ret = i915_gem_object_wait(obj,
1134 I915_WAIT_INTERRUPTIBLE,
1135 MAX_SCHEDULE_TIMEOUT,
1136 to_rps_client(file));
1140 ret = i915_gem_object_pin_pages(obj);
1144 ret = i915_gem_shmem_pread(obj, args);
1145 if (ret == -EFAULT || ret == -ENODEV)
1146 ret = i915_gem_gtt_pread(obj, args);
1148 i915_gem_object_unpin_pages(obj);
1150 i915_gem_object_put(obj);
1154 /* This is the fast write path which cannot handle
1155 * page faults in the source data
1159 ggtt_write(struct io_mapping *mapping,
1160 loff_t base, int offset,
1161 char __user *user_data, int length)
1164 unsigned long unwritten;
1166 /* We can use the cpu mem copy function because this is X86. */
1167 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1168 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1170 io_mapping_unmap_atomic(vaddr);
1172 vaddr = (void __force *)
1173 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1174 unwritten = copy_from_user(vaddr + offset, user_data, length);
1175 io_mapping_unmap(vaddr);
1182 * This is the fast pwrite path, where we copy the data directly from the
1183 * user into the GTT, uncached.
1184 * @obj: i915 GEM object
1185 * @args: pwrite arguments structure
1188 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1189 const struct drm_i915_gem_pwrite *args)
1191 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1192 struct i915_ggtt *ggtt = &i915->ggtt;
1193 struct drm_mm_node node;
1194 struct i915_vma *vma;
1196 void __user *user_data;
1199 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1203 intel_runtime_pm_get(i915);
1204 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1205 PIN_MAPPABLE | PIN_NONBLOCK);
1207 node.start = i915_ggtt_offset(vma);
1208 node.allocated = false;
1209 ret = i915_vma_put_fence(vma);
1211 i915_vma_unpin(vma);
1216 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1219 GEM_BUG_ON(!node.allocated);
1222 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1226 mutex_unlock(&i915->drm.struct_mutex);
1228 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1230 user_data = u64_to_user_ptr(args->data_ptr);
1231 offset = args->offset;
1232 remain = args->size;
1234 /* Operation in this page
1236 * page_base = page offset within aperture
1237 * page_offset = offset within page
1238 * page_length = bytes to copy for this page
1240 u32 page_base = node.start;
1241 unsigned int page_offset = offset_in_page(offset);
1242 unsigned int page_length = PAGE_SIZE - page_offset;
1243 page_length = remain < page_length ? remain : page_length;
1244 if (node.allocated) {
1245 wmb(); /* flush the write before we modify the GGTT */
1246 ggtt->base.insert_page(&ggtt->base,
1247 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1248 node.start, I915_CACHE_NONE, 0);
1249 wmb(); /* flush modifications to the GGTT (insert_page) */
1251 page_base += offset & PAGE_MASK;
1253 /* If we get a fault while copying data, then (presumably) our
1254 * source page isn't available. Return the error and we'll
1255 * retry in the slow path.
1256 * If the object is non-shmem backed, we retry again with the
1257 * path that handles page fault.
1259 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1260 user_data, page_length)) {
1265 remain -= page_length;
1266 user_data += page_length;
1267 offset += page_length;
1269 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1271 mutex_lock(&i915->drm.struct_mutex);
1273 if (node.allocated) {
1275 ggtt->base.clear_range(&ggtt->base,
1276 node.start, node.size);
1277 remove_mappable_node(&node);
1279 i915_vma_unpin(vma);
1282 intel_runtime_pm_put(i915);
1283 mutex_unlock(&i915->drm.struct_mutex);
1288 shmem_pwrite_slow(struct page *page, int offset, int length,
1289 char __user *user_data,
1290 bool page_do_bit17_swizzling,
1291 bool needs_clflush_before,
1292 bool needs_clflush_after)
1298 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1299 shmem_clflush_swizzled_range(vaddr + offset, length,
1300 page_do_bit17_swizzling);
1301 if (page_do_bit17_swizzling)
1302 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1305 ret = __copy_from_user(vaddr + offset, user_data, length);
1306 if (needs_clflush_after)
1307 shmem_clflush_swizzled_range(vaddr + offset, length,
1308 page_do_bit17_swizzling);
1311 return ret ? -EFAULT : 0;
1314 /* Per-page copy function for the shmem pwrite fastpath.
1315 * Flushes invalid cachelines before writing to the target if
1316 * needs_clflush_before is set and flushes out any written cachelines after
1317 * writing if needs_clflush is set.
1320 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1321 bool page_do_bit17_swizzling,
1322 bool needs_clflush_before,
1323 bool needs_clflush_after)
1328 if (!page_do_bit17_swizzling) {
1329 char *vaddr = kmap_atomic(page);
1331 if (needs_clflush_before)
1332 drm_clflush_virt_range(vaddr + offset, len);
1333 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1334 if (needs_clflush_after)
1335 drm_clflush_virt_range(vaddr + offset, len);
1337 kunmap_atomic(vaddr);
1342 return shmem_pwrite_slow(page, offset, len, user_data,
1343 page_do_bit17_swizzling,
1344 needs_clflush_before,
1345 needs_clflush_after);
1349 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1350 const struct drm_i915_gem_pwrite *args)
1352 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1353 void __user *user_data;
1355 unsigned int obj_do_bit17_swizzling;
1356 unsigned int partial_cacheline_write;
1357 unsigned int needs_clflush;
1358 unsigned int offset, idx;
1361 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1365 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1366 mutex_unlock(&i915->drm.struct_mutex);
1370 obj_do_bit17_swizzling = 0;
1371 if (i915_gem_object_needs_bit17_swizzle(obj))
1372 obj_do_bit17_swizzling = BIT(17);
1374 /* If we don't overwrite a cacheline completely we need to be
1375 * careful to have up-to-date data by first clflushing. Don't
1376 * overcomplicate things and flush the entire patch.
1378 partial_cacheline_write = 0;
1379 if (needs_clflush & CLFLUSH_BEFORE)
1380 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1382 user_data = u64_to_user_ptr(args->data_ptr);
1383 remain = args->size;
1384 offset = offset_in_page(args->offset);
1385 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1386 struct page *page = i915_gem_object_get_page(obj, idx);
1390 if (offset + length > PAGE_SIZE)
1391 length = PAGE_SIZE - offset;
1393 ret = shmem_pwrite(page, offset, length, user_data,
1394 page_to_phys(page) & obj_do_bit17_swizzling,
1395 (offset | length) & partial_cacheline_write,
1396 needs_clflush & CLFLUSH_AFTER);
1401 user_data += length;
1405 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1406 i915_gem_obj_finish_shmem_access(obj);
1411 * Writes data to the object referenced by handle.
1413 * @data: ioctl data blob
1416 * On error, the contents of the buffer that were to be modified are undefined.
1419 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1420 struct drm_file *file)
1422 struct drm_i915_gem_pwrite *args = data;
1423 struct drm_i915_gem_object *obj;
1426 if (args->size == 0)
1429 if (!access_ok(VERIFY_READ,
1430 u64_to_user_ptr(args->data_ptr),
1434 obj = i915_gem_object_lookup(file, args->handle);
1438 /* Bounds check destination. */
1439 if (args->offset > obj->base.size ||
1440 args->size > obj->base.size - args->offset) {
1445 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1447 ret = i915_gem_object_wait(obj,
1448 I915_WAIT_INTERRUPTIBLE |
1450 MAX_SCHEDULE_TIMEOUT,
1451 to_rps_client(file));
1455 ret = i915_gem_object_pin_pages(obj);
1460 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1461 * it would end up going through the fenced access, and we'll get
1462 * different detiling behavior between reading and writing.
1463 * pread/pwrite currently are reading and writing from the CPU
1464 * perspective, requiring manual detiling by the client.
1466 if (!i915_gem_object_has_struct_page(obj) ||
1467 cpu_write_needs_clflush(obj))
1468 /* Note that the gtt paths might fail with non-page-backed user
1469 * pointers (e.g. gtt mappings when moving data between
1470 * textures). Fallback to the shmem path in that case.
1472 ret = i915_gem_gtt_pwrite_fast(obj, args);
1474 if (ret == -EFAULT || ret == -ENOSPC) {
1475 if (obj->phys_handle)
1476 ret = i915_gem_phys_pwrite(obj, args, file);
1478 ret = i915_gem_shmem_pwrite(obj, args);
1481 i915_gem_object_unpin_pages(obj);
1483 i915_gem_object_put(obj);
1487 static inline enum fb_op_origin
1488 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1490 return (domain == I915_GEM_DOMAIN_GTT ?
1491 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1494 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1496 struct drm_i915_private *i915;
1497 struct list_head *list;
1498 struct i915_vma *vma;
1500 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1501 if (!i915_vma_is_ggtt(vma))
1504 if (i915_vma_is_active(vma))
1507 if (!drm_mm_node_allocated(&vma->node))
1510 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1513 i915 = to_i915(obj->base.dev);
1514 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1515 list_move_tail(&obj->global_link, list);
1519 * Called when user space prepares to use an object with the CPU, either
1520 * through the mmap ioctl's mapping or a GTT mapping.
1522 * @data: ioctl data blob
1526 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1527 struct drm_file *file)
1529 struct drm_i915_gem_set_domain *args = data;
1530 struct drm_i915_gem_object *obj;
1531 uint32_t read_domains = args->read_domains;
1532 uint32_t write_domain = args->write_domain;
1535 /* Only handle setting domains to types used by the CPU. */
1536 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1539 /* Having something in the write domain implies it's in the read
1540 * domain, and only that read domain. Enforce that in the request.
1542 if (write_domain != 0 && read_domains != write_domain)
1545 obj = i915_gem_object_lookup(file, args->handle);
1549 /* Try to flush the object off the GPU without holding the lock.
1550 * We will repeat the flush holding the lock in the normal manner
1551 * to catch cases where we are gazumped.
1553 err = i915_gem_object_wait(obj,
1554 I915_WAIT_INTERRUPTIBLE |
1555 (write_domain ? I915_WAIT_ALL : 0),
1556 MAX_SCHEDULE_TIMEOUT,
1557 to_rps_client(file));
1561 /* Flush and acquire obj->pages so that we are coherent through
1562 * direct access in memory with previous cached writes through
1563 * shmemfs and that our cache domain tracking remains valid.
1564 * For example, if the obj->filp was moved to swap without us
1565 * being notified and releasing the pages, we would mistakenly
1566 * continue to assume that the obj remained out of the CPU cached
1569 err = i915_gem_object_pin_pages(obj);
1573 err = i915_mutex_lock_interruptible(dev);
1577 if (read_domains & I915_GEM_DOMAIN_GTT)
1578 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1580 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1582 /* And bump the LRU for this access */
1583 i915_gem_object_bump_inactive_ggtt(obj);
1585 mutex_unlock(&dev->struct_mutex);
1587 if (write_domain != 0)
1588 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1591 i915_gem_object_unpin_pages(obj);
1593 i915_gem_object_put(obj);
1598 * Called when user space has done writes to this buffer
1600 * @data: ioctl data blob
1604 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1605 struct drm_file *file)
1607 struct drm_i915_gem_sw_finish *args = data;
1608 struct drm_i915_gem_object *obj;
1611 obj = i915_gem_object_lookup(file, args->handle);
1615 /* Pinned buffers may be scanout, so flush the cache */
1616 if (READ_ONCE(obj->pin_display)) {
1617 err = i915_mutex_lock_interruptible(dev);
1619 i915_gem_object_flush_cpu_write_domain(obj);
1620 mutex_unlock(&dev->struct_mutex);
1624 i915_gem_object_put(obj);
1629 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1632 * @data: ioctl data blob
1635 * While the mapping holds a reference on the contents of the object, it doesn't
1636 * imply a ref on the object itself.
1640 * DRM driver writers who look a this function as an example for how to do GEM
1641 * mmap support, please don't implement mmap support like here. The modern way
1642 * to implement DRM mmap support is with an mmap offset ioctl (like
1643 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1644 * That way debug tooling like valgrind will understand what's going on, hiding
1645 * the mmap call in a driver private ioctl will break that. The i915 driver only
1646 * does cpu mmaps this way because we didn't know better.
1649 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1650 struct drm_file *file)
1652 struct drm_i915_gem_mmap *args = data;
1653 struct drm_i915_gem_object *obj;
1656 if (args->flags & ~(I915_MMAP_WC))
1659 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1662 obj = i915_gem_object_lookup(file, args->handle);
1666 /* prime objects have no backing filp to GEM mmap
1669 if (!obj->base.filp) {
1670 i915_gem_object_put(obj);
1674 addr = vm_mmap(obj->base.filp, 0, args->size,
1675 PROT_READ | PROT_WRITE, MAP_SHARED,
1677 if (args->flags & I915_MMAP_WC) {
1678 struct mm_struct *mm = current->mm;
1679 struct vm_area_struct *vma;
1681 if (down_write_killable(&mm->mmap_sem)) {
1682 i915_gem_object_put(obj);
1685 vma = find_vma(mm, addr);
1688 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1691 up_write(&mm->mmap_sem);
1693 /* This may race, but that's ok, it only gets set */
1694 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1696 i915_gem_object_put(obj);
1697 if (IS_ERR((void *)addr))
1700 args->addr_ptr = (uint64_t) addr;
1705 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1709 size = i915_gem_object_get_stride(obj);
1710 size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8;
1712 return size >> PAGE_SHIFT;
1716 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1718 * A history of the GTT mmap interface:
1720 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1721 * aligned and suitable for fencing, and still fit into the available
1722 * mappable space left by the pinned display objects. A classic problem
1723 * we called the page-fault-of-doom where we would ping-pong between
1724 * two objects that could not fit inside the GTT and so the memcpy
1725 * would page one object in at the expense of the other between every
1728 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1729 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1730 * object is too large for the available space (or simply too large
1731 * for the mappable aperture!), a view is created instead and faulted
1732 * into userspace. (This view is aligned and sized appropriately for
1737 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1738 * hangs on some architectures, corruption on others. An attempt to service
1739 * a GTT page fault from a snoopable object will generate a SIGBUS.
1741 * * the object must be able to fit into RAM (physical memory, though no
1742 * limited to the mappable aperture).
1747 * * a new GTT page fault will synchronize rendering from the GPU and flush
1748 * all data to system memory. Subsequent access will not be synchronized.
1750 * * all mappings are revoked on runtime device suspend.
1752 * * there are only 8, 16 or 32 fence registers to share between all users
1753 * (older machines require fence register for display and blitter access
1754 * as well). Contention of the fence registers will cause the previous users
1755 * to be unmapped and any new access will generate new page faults.
1757 * * running out of memory while servicing a fault may generate a SIGBUS,
1758 * rather than the expected SIGSEGV.
1760 int i915_gem_mmap_gtt_version(void)
1766 * i915_gem_fault - fault a page into the GTT
1767 * @area: CPU VMA in question
1770 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1771 * from userspace. The fault handler takes care of binding the object to
1772 * the GTT (if needed), allocating and programming a fence register (again,
1773 * only if needed based on whether the old reg is still valid or the object
1774 * is tiled) and inserting a new PTE into the faulting process.
1776 * Note that the faulting process may involve evicting existing objects
1777 * from the GTT and/or fence registers to make room. So performance may
1778 * suffer if the GTT working set is large or there are few fence registers
1781 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1782 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1784 int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
1786 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1787 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1788 struct drm_device *dev = obj->base.dev;
1789 struct drm_i915_private *dev_priv = to_i915(dev);
1790 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1791 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1792 struct i915_vma *vma;
1793 pgoff_t page_offset;
1797 /* We don't use vmf->pgoff since that has the fake offset */
1798 page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >>
1801 trace_i915_gem_object_fault(obj, page_offset, true, write);
1803 /* Try to flush the object off the GPU first without holding the lock.
1804 * Upon acquiring the lock, we will perform our sanity checks and then
1805 * repeat the flush holding the lock in the normal manner to catch cases
1806 * where we are gazumped.
1808 ret = i915_gem_object_wait(obj,
1809 I915_WAIT_INTERRUPTIBLE,
1810 MAX_SCHEDULE_TIMEOUT,
1815 ret = i915_gem_object_pin_pages(obj);
1819 intel_runtime_pm_get(dev_priv);
1821 ret = i915_mutex_lock_interruptible(dev);
1825 /* Access to snoopable pages through the GTT is incoherent. */
1826 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1831 /* If the object is smaller than a couple of partial vma, it is
1832 * not worth only creating a single partial vma - we may as well
1833 * clear enough space for the full object.
1835 flags = PIN_MAPPABLE;
1836 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1837 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1839 /* Now pin it into the GTT as needed */
1840 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1842 struct i915_ggtt_view view;
1843 unsigned int chunk_size;
1845 /* Use a partial view if it is bigger than available space */
1846 chunk_size = MIN_CHUNK_PAGES;
1847 if (i915_gem_object_is_tiled(obj))
1848 chunk_size = roundup(chunk_size, tile_row_pages(obj));
1850 memset(&view, 0, sizeof(view));
1851 view.type = I915_GGTT_VIEW_PARTIAL;
1852 view.params.partial.offset = rounddown(page_offset, chunk_size);
1853 view.params.partial.size =
1854 min_t(unsigned int, chunk_size,
1855 vma_pages(area) - view.params.partial.offset);
1857 /* If the partial covers the entire object, just create a
1860 if (chunk_size >= obj->base.size >> PAGE_SHIFT)
1861 view.type = I915_GGTT_VIEW_NORMAL;
1863 /* Userspace is now writing through an untracked VMA, abandon
1864 * all hope that the hardware is able to track future writes.
1866 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1868 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1875 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1879 ret = i915_vma_get_fence(vma);
1883 /* Mark as being mmapped into userspace for later revocation */
1884 assert_rpm_wakelock_held(dev_priv);
1885 if (list_empty(&obj->userfault_link))
1886 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1888 /* Finally, remap it using the new GTT offset */
1889 ret = remap_io_mapping(area,
1890 area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
1891 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1892 min_t(u64, vma->size, area->vm_end - area->vm_start),
1896 __i915_vma_unpin(vma);
1898 mutex_unlock(&dev->struct_mutex);
1900 intel_runtime_pm_put(dev_priv);
1901 i915_gem_object_unpin_pages(obj);
1906 * We eat errors when the gpu is terminally wedged to avoid
1907 * userspace unduly crashing (gl has no provisions for mmaps to
1908 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1909 * and so needs to be reported.
1911 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1912 ret = VM_FAULT_SIGBUS;
1917 * EAGAIN means the gpu is hung and we'll wait for the error
1918 * handler to reset everything when re-faulting in
1919 * i915_mutex_lock_interruptible.
1926 * EBUSY is ok: this just means that another thread
1927 * already did the job.
1929 ret = VM_FAULT_NOPAGE;
1936 ret = VM_FAULT_SIGBUS;
1939 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1940 ret = VM_FAULT_SIGBUS;
1947 * i915_gem_release_mmap - remove physical page mappings
1948 * @obj: obj in question
1950 * Preserve the reservation of the mmapping with the DRM core code, but
1951 * relinquish ownership of the pages back to the system.
1953 * It is vital that we remove the page mapping if we have mapped a tiled
1954 * object through the GTT and then lose the fence register due to
1955 * resource pressure. Similarly if the object has been moved out of the
1956 * aperture, than pages mapped into userspace must be revoked. Removing the
1957 * mapping will then trigger a page fault on the next user access, allowing
1958 * fixup by i915_gem_fault().
1961 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1963 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1965 /* Serialisation between user GTT access and our code depends upon
1966 * revoking the CPU's PTE whilst the mutex is held. The next user
1967 * pagefault then has to wait until we release the mutex.
1969 * Note that RPM complicates somewhat by adding an additional
1970 * requirement that operations to the GGTT be made holding the RPM
1973 lockdep_assert_held(&i915->drm.struct_mutex);
1974 intel_runtime_pm_get(i915);
1976 if (list_empty(&obj->userfault_link))
1979 list_del_init(&obj->userfault_link);
1980 drm_vma_node_unmap(&obj->base.vma_node,
1981 obj->base.dev->anon_inode->i_mapping);
1983 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1984 * memory transactions from userspace before we return. The TLB
1985 * flushing implied above by changing the PTE above *should* be
1986 * sufficient, an extra barrier here just provides us with a bit
1987 * of paranoid documentation about our requirement to serialise
1988 * memory writes before touching registers / GSM.
1993 intel_runtime_pm_put(i915);
1996 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
1998 struct drm_i915_gem_object *obj, *on;
2002 * Only called during RPM suspend. All users of the userfault_list
2003 * must be holding an RPM wakeref to ensure that this can not
2004 * run concurrently with themselves (and use the struct_mutex for
2005 * protection between themselves).
2008 list_for_each_entry_safe(obj, on,
2009 &dev_priv->mm.userfault_list, userfault_link) {
2010 list_del_init(&obj->userfault_link);
2011 drm_vma_node_unmap(&obj->base.vma_node,
2012 obj->base.dev->anon_inode->i_mapping);
2015 /* The fence will be lost when the device powers down. If any were
2016 * in use by hardware (i.e. they are pinned), we should not be powering
2017 * down! All other fences will be reacquired by the user upon waking.
2019 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2020 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2022 if (WARN_ON(reg->pin_count))
2028 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2034 * i915_gem_get_ggtt_size - return required global GTT size for an object
2035 * @dev_priv: i915 device
2036 * @size: object size
2037 * @tiling_mode: tiling mode
2039 * Return the required global GTT size for an object, taking into account
2040 * potential fence register mapping.
2042 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
2043 u64 size, int tiling_mode)
2047 GEM_BUG_ON(size == 0);
2049 if (INTEL_GEN(dev_priv) >= 4 ||
2050 tiling_mode == I915_TILING_NONE)
2053 /* Previous chips need a power-of-two fence region when tiling */
2054 if (IS_GEN3(dev_priv))
2055 ggtt_size = 1024*1024;
2057 ggtt_size = 512*1024;
2059 while (ggtt_size < size)
2066 * i915_gem_get_ggtt_alignment - return required global GTT alignment
2067 * @dev_priv: i915 device
2068 * @size: object size
2069 * @tiling_mode: tiling mode
2070 * @fenced: is fenced alignment required or not
2072 * Return the required global GTT alignment for an object, taking into account
2073 * potential fence register mapping.
2075 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
2076 int tiling_mode, bool fenced)
2078 GEM_BUG_ON(size == 0);
2081 * Minimum alignment is 4k (GTT page size), but might be greater
2082 * if a fence register is needed for the object.
2084 if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) ||
2085 tiling_mode == I915_TILING_NONE)
2089 * Previous chips need to be aligned to the size of the smallest
2090 * fence register that can contain the object.
2092 return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode);
2095 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2097 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2100 err = drm_gem_create_mmap_offset(&obj->base);
2104 /* We can idle the GPU locklessly to flush stale objects, but in order
2105 * to claim that space for ourselves, we need to take the big
2106 * struct_mutex to free the requests+objects and allocate our slot.
2108 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2112 err = i915_mutex_lock_interruptible(&dev_priv->drm);
2114 i915_gem_retire_requests(dev_priv);
2115 err = drm_gem_create_mmap_offset(&obj->base);
2116 mutex_unlock(&dev_priv->drm.struct_mutex);
2122 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2124 drm_gem_free_mmap_offset(&obj->base);
2128 i915_gem_mmap_gtt(struct drm_file *file,
2129 struct drm_device *dev,
2133 struct drm_i915_gem_object *obj;
2136 obj = i915_gem_object_lookup(file, handle);
2140 ret = i915_gem_object_create_mmap_offset(obj);
2142 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2144 i915_gem_object_put(obj);
2149 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2151 * @data: GTT mapping ioctl data
2152 * @file: GEM object info
2154 * Simply returns the fake offset to userspace so it can mmap it.
2155 * The mmap call will end up in drm_gem_mmap(), which will set things
2156 * up so we can get faults in the handler above.
2158 * The fault handler will take care of binding the object into the GTT
2159 * (since it may have been evicted to make room for something), allocating
2160 * a fence register, and mapping the appropriate aperture address into
2164 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2165 struct drm_file *file)
2167 struct drm_i915_gem_mmap_gtt *args = data;
2169 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2172 /* Immediately discard the backing storage */
2174 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2176 i915_gem_object_free_mmap_offset(obj);
2178 if (obj->base.filp == NULL)
2181 /* Our goal here is to return as much of the memory as
2182 * is possible back to the system as we are called from OOM.
2183 * To do this we must instruct the shmfs to drop all of its
2184 * backing pages, *now*.
2186 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2187 obj->mm.madv = __I915_MADV_PURGED;
2190 /* Try to discard unwanted pages */
2191 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2193 struct address_space *mapping;
2195 lockdep_assert_held(&obj->mm.lock);
2196 GEM_BUG_ON(obj->mm.pages);
2198 switch (obj->mm.madv) {
2199 case I915_MADV_DONTNEED:
2200 i915_gem_object_truncate(obj);
2201 case __I915_MADV_PURGED:
2205 if (obj->base.filp == NULL)
2208 mapping = obj->base.filp->f_mapping,
2209 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2213 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2214 struct sg_table *pages)
2216 struct sgt_iter sgt_iter;
2219 __i915_gem_object_release_shmem(obj, pages);
2221 i915_gem_gtt_finish_pages(obj, pages);
2223 if (i915_gem_object_needs_bit17_swizzle(obj))
2224 i915_gem_object_save_bit_17_swizzle(obj, pages);
2226 for_each_sgt_page(page, sgt_iter, pages) {
2228 set_page_dirty(page);
2230 if (obj->mm.madv == I915_MADV_WILLNEED)
2231 mark_page_accessed(page);
2235 obj->mm.dirty = false;
2237 sg_free_table(pages);
2241 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2243 struct radix_tree_iter iter;
2246 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2247 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2250 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2251 enum i915_mm_subclass subclass)
2253 struct sg_table *pages;
2255 if (i915_gem_object_has_pinned_pages(obj))
2258 GEM_BUG_ON(obj->bind_count);
2259 if (!READ_ONCE(obj->mm.pages))
2262 /* May be called by shrinker from within get_pages() (on another bo) */
2263 mutex_lock_nested(&obj->mm.lock, subclass);
2264 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2267 /* ->put_pages might need to allocate memory for the bit17 swizzle
2268 * array, hence protect them from being reaped by removing them from gtt
2270 pages = fetch_and_zero(&obj->mm.pages);
2273 if (obj->mm.mapping) {
2276 ptr = ptr_mask_bits(obj->mm.mapping);
2277 if (is_vmalloc_addr(ptr))
2280 kunmap(kmap_to_page(ptr));
2282 obj->mm.mapping = NULL;
2285 __i915_gem_object_reset_page_iter(obj);
2287 obj->ops->put_pages(obj, pages);
2289 mutex_unlock(&obj->mm.lock);
2292 static unsigned int swiotlb_max_size(void)
2294 #if IS_ENABLED(CONFIG_SWIOTLB)
2295 return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE);
2301 static void i915_sg_trim(struct sg_table *orig_st)
2303 struct sg_table new_st;
2304 struct scatterlist *sg, *new_sg;
2307 if (orig_st->nents == orig_st->orig_nents)
2310 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL))
2313 new_sg = new_st.sgl;
2314 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2315 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2316 /* called before being DMA mapped, no need to copy sg->dma_* */
2317 new_sg = sg_next(new_sg);
2320 sg_free_table(orig_st);
2325 static struct sg_table *
2326 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2328 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2330 struct address_space *mapping;
2331 struct sg_table *st;
2332 struct scatterlist *sg;
2333 struct sgt_iter sgt_iter;
2335 unsigned long last_pfn = 0; /* suppress gcc warning */
2336 unsigned int max_segment;
2340 /* Assert that the object is not currently in any GPU domain. As it
2341 * wasn't in the GTT, there shouldn't be any way it could have been in
2344 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2345 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2347 max_segment = swiotlb_max_size();
2349 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2351 st = kmalloc(sizeof(*st), GFP_KERNEL);
2353 return ERR_PTR(-ENOMEM);
2355 page_count = obj->base.size / PAGE_SIZE;
2356 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2358 return ERR_PTR(-ENOMEM);
2361 /* Get the list of pages out of our struct file. They'll be pinned
2362 * at this point until we release them.
2364 * Fail silently without starting the shrinker
2366 mapping = obj->base.filp->f_mapping;
2367 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2368 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2371 for (i = 0; i < page_count; i++) {
2372 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2374 i915_gem_shrink(dev_priv,
2377 I915_SHRINK_UNBOUND |
2378 I915_SHRINK_PURGEABLE);
2379 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2382 /* We've tried hard to allocate the memory by reaping
2383 * our own buffer, now let the real VM do its job and
2384 * go down in flames if truly OOM.
2386 page = shmem_read_mapping_page(mapping, i);
2388 ret = PTR_ERR(page);
2393 sg->length >= max_segment ||
2394 page_to_pfn(page) != last_pfn + 1) {
2398 sg_set_page(sg, page, PAGE_SIZE, 0);
2400 sg->length += PAGE_SIZE;
2402 last_pfn = page_to_pfn(page);
2404 /* Check that the i965g/gm workaround works. */
2405 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2407 if (sg) /* loop terminated early; short sg table */
2410 /* Trim unused sg entries to avoid wasting memory. */
2413 ret = i915_gem_gtt_prepare_pages(obj, st);
2417 if (i915_gem_object_needs_bit17_swizzle(obj))
2418 i915_gem_object_do_bit_17_swizzle(obj, st);
2424 for_each_sgt_page(page, sgt_iter, st)
2429 /* shmemfs first checks if there is enough memory to allocate the page
2430 * and reports ENOSPC should there be insufficient, along with the usual
2431 * ENOMEM for a genuine allocation failure.
2433 * We use ENOSPC in our driver to mean that we have run out of aperture
2434 * space and so want to translate the error from shmemfs back to our
2435 * usual understanding of ENOMEM.
2440 return ERR_PTR(ret);
2443 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2444 struct sg_table *pages)
2446 lockdep_assert_held(&obj->mm.lock);
2448 obj->mm.get_page.sg_pos = pages->sgl;
2449 obj->mm.get_page.sg_idx = 0;
2451 obj->mm.pages = pages;
2453 if (i915_gem_object_is_tiled(obj) &&
2454 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2455 GEM_BUG_ON(obj->mm.quirked);
2456 __i915_gem_object_pin_pages(obj);
2457 obj->mm.quirked = true;
2461 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2463 struct sg_table *pages;
2465 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2467 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2468 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2472 pages = obj->ops->get_pages(obj);
2473 if (unlikely(IS_ERR(pages)))
2474 return PTR_ERR(pages);
2476 __i915_gem_object_set_pages(obj, pages);
2480 /* Ensure that the associated pages are gathered from the backing storage
2481 * and pinned into our object. i915_gem_object_pin_pages() may be called
2482 * multiple times before they are released by a single call to
2483 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2484 * either as a result of memory pressure (reaping pages under the shrinker)
2485 * or as the object is itself released.
2487 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2491 err = mutex_lock_interruptible(&obj->mm.lock);
2495 if (unlikely(!obj->mm.pages)) {
2496 err = ____i915_gem_object_get_pages(obj);
2500 smp_mb__before_atomic();
2502 atomic_inc(&obj->mm.pages_pin_count);
2505 mutex_unlock(&obj->mm.lock);
2509 /* The 'mapping' part of i915_gem_object_pin_map() below */
2510 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2511 enum i915_map_type type)
2513 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2514 struct sg_table *sgt = obj->mm.pages;
2515 struct sgt_iter sgt_iter;
2517 struct page *stack_pages[32];
2518 struct page **pages = stack_pages;
2519 unsigned long i = 0;
2523 /* A single page can always be kmapped */
2524 if (n_pages == 1 && type == I915_MAP_WB)
2525 return kmap(sg_page(sgt->sgl));
2527 if (n_pages > ARRAY_SIZE(stack_pages)) {
2528 /* Too big for stack -- allocate temporary array instead */
2529 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2534 for_each_sgt_page(page, sgt_iter, sgt)
2537 /* Check that we have the expected number of pages */
2538 GEM_BUG_ON(i != n_pages);
2542 pgprot = PAGE_KERNEL;
2545 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2548 addr = vmap(pages, n_pages, 0, pgprot);
2550 if (pages != stack_pages)
2551 drm_free_large(pages);
2556 /* get, pin, and map the pages of the object into kernel space */
2557 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2558 enum i915_map_type type)
2560 enum i915_map_type has_type;
2565 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2567 ret = mutex_lock_interruptible(&obj->mm.lock);
2569 return ERR_PTR(ret);
2572 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2573 if (unlikely(!obj->mm.pages)) {
2574 ret = ____i915_gem_object_get_pages(obj);
2578 smp_mb__before_atomic();
2580 atomic_inc(&obj->mm.pages_pin_count);
2583 GEM_BUG_ON(!obj->mm.pages);
2585 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2586 if (ptr && has_type != type) {
2592 if (is_vmalloc_addr(ptr))
2595 kunmap(kmap_to_page(ptr));
2597 ptr = obj->mm.mapping = NULL;
2601 ptr = i915_gem_object_map(obj, type);
2607 obj->mm.mapping = ptr_pack_bits(ptr, type);
2611 mutex_unlock(&obj->mm.lock);
2615 atomic_dec(&obj->mm.pages_pin_count);
2621 static bool i915_context_is_banned(const struct i915_gem_context *ctx)
2623 unsigned long elapsed;
2625 if (ctx->hang_stats.banned)
2628 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2629 if (ctx->hang_stats.ban_period_seconds &&
2630 elapsed <= ctx->hang_stats.ban_period_seconds) {
2631 DRM_DEBUG("context hanging too fast, banning!\n");
2638 static void i915_set_reset_status(struct i915_gem_context *ctx,
2641 struct i915_ctx_hang_stats *hs = &ctx->hang_stats;
2644 hs->banned = i915_context_is_banned(ctx);
2646 hs->guilty_ts = get_seconds();
2648 hs->batch_pending++;
2652 struct drm_i915_gem_request *
2653 i915_gem_find_active_request(struct intel_engine_cs *engine)
2655 struct drm_i915_gem_request *request;
2657 /* We are called by the error capture and reset at a random
2658 * point in time. In particular, note that neither is crucially
2659 * ordered with an interrupt. After a hang, the GPU is dead and we
2660 * assume that no more writes can happen (we waited long enough for
2661 * all writes that were in transaction to be flushed) - adding an
2662 * extra delay for a recent interrupt is pointless. Hence, we do
2663 * not need an engine->irq_seqno_barrier() before the seqno reads.
2665 list_for_each_entry(request, &engine->timeline->requests, link) {
2666 if (__i915_gem_request_completed(request))
2675 static void reset_request(struct drm_i915_gem_request *request)
2677 void *vaddr = request->ring->vaddr;
2680 /* As this request likely depends on state from the lost
2681 * context, clear out all the user operations leaving the
2682 * breadcrumb at the end (so we get the fence notifications).
2684 head = request->head;
2685 if (request->postfix < head) {
2686 memset(vaddr + head, 0, request->ring->size - head);
2689 memset(vaddr + head, 0, request->postfix - head);
2692 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2694 struct drm_i915_gem_request *request;
2695 struct i915_gem_context *incomplete_ctx;
2696 struct intel_timeline *timeline;
2699 if (engine->irq_seqno_barrier)
2700 engine->irq_seqno_barrier(engine);
2702 request = i915_gem_find_active_request(engine);
2706 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2707 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
2710 i915_set_reset_status(request->ctx, ring_hung);
2714 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2715 engine->name, request->global_seqno);
2717 /* Setup the CS to resume from the breadcrumb of the hung request */
2718 engine->reset_hw(engine, request);
2720 /* Users of the default context do not rely on logical state
2721 * preserved between batches. They have to emit full state on
2722 * every batch and so it is safe to execute queued requests following
2725 * Other contexts preserve state, now corrupt. We want to skip all
2726 * queued requests that reference the corrupt context.
2728 incomplete_ctx = request->ctx;
2729 if (i915_gem_context_is_default(incomplete_ctx))
2732 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2733 if (request->ctx == incomplete_ctx)
2734 reset_request(request);
2736 timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine);
2737 list_for_each_entry(request, &timeline->requests, link)
2738 reset_request(request);
2741 void i915_gem_reset(struct drm_i915_private *dev_priv)
2743 struct intel_engine_cs *engine;
2744 enum intel_engine_id id;
2746 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2748 i915_gem_retire_requests(dev_priv);
2750 for_each_engine(engine, dev_priv, id)
2751 i915_gem_reset_engine(engine);
2753 i915_gem_restore_fences(&dev_priv->drm);
2755 if (dev_priv->gt.awake) {
2756 intel_sanitize_gt_powersave(dev_priv);
2757 intel_enable_gt_powersave(dev_priv);
2758 if (INTEL_GEN(dev_priv) >= 6)
2759 gen6_rps_busy(dev_priv);
2763 static void nop_submit_request(struct drm_i915_gem_request *request)
2767 static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
2769 engine->submit_request = nop_submit_request;
2771 /* Mark all pending requests as complete so that any concurrent
2772 * (lockless) lookup doesn't try and wait upon the request as we
2775 intel_engine_init_global_seqno(engine,
2776 intel_engine_last_submit(engine));
2779 * Clear the execlists queue up before freeing the requests, as those
2780 * are the ones that keep the context and ringbuffer backing objects
2784 if (i915.enable_execlists) {
2785 unsigned long flags;
2787 spin_lock_irqsave(&engine->timeline->lock, flags);
2789 i915_gem_request_put(engine->execlist_port[0].request);
2790 i915_gem_request_put(engine->execlist_port[1].request);
2791 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2792 engine->execlist_queue = RB_ROOT;
2793 engine->execlist_first = NULL;
2795 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2799 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2801 struct intel_engine_cs *engine;
2802 enum intel_engine_id id;
2804 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2805 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
2807 i915_gem_context_lost(dev_priv);
2808 for_each_engine(engine, dev_priv, id)
2809 i915_gem_cleanup_engine(engine);
2810 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2812 i915_gem_retire_requests(dev_priv);
2816 i915_gem_retire_work_handler(struct work_struct *work)
2818 struct drm_i915_private *dev_priv =
2819 container_of(work, typeof(*dev_priv), gt.retire_work.work);
2820 struct drm_device *dev = &dev_priv->drm;
2822 /* Come back later if the device is busy... */
2823 if (mutex_trylock(&dev->struct_mutex)) {
2824 i915_gem_retire_requests(dev_priv);
2825 mutex_unlock(&dev->struct_mutex);
2828 /* Keep the retire handler running until we are finally idle.
2829 * We do not need to do this test under locking as in the worst-case
2830 * we queue the retire worker once too often.
2832 if (READ_ONCE(dev_priv->gt.awake)) {
2833 i915_queue_hangcheck(dev_priv);
2834 queue_delayed_work(dev_priv->wq,
2835 &dev_priv->gt.retire_work,
2836 round_jiffies_up_relative(HZ));
2841 i915_gem_idle_work_handler(struct work_struct *work)
2843 struct drm_i915_private *dev_priv =
2844 container_of(work, typeof(*dev_priv), gt.idle_work.work);
2845 struct drm_device *dev = &dev_priv->drm;
2846 struct intel_engine_cs *engine;
2847 enum intel_engine_id id;
2848 bool rearm_hangcheck;
2850 if (!READ_ONCE(dev_priv->gt.awake))
2854 * Wait for last execlists context complete, but bail out in case a
2855 * new request is submitted.
2857 wait_for(READ_ONCE(dev_priv->gt.active_requests) ||
2858 intel_execlists_idle(dev_priv), 10);
2860 if (READ_ONCE(dev_priv->gt.active_requests))
2864 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2866 if (!mutex_trylock(&dev->struct_mutex)) {
2867 /* Currently busy, come back later */
2868 mod_delayed_work(dev_priv->wq,
2869 &dev_priv->gt.idle_work,
2870 msecs_to_jiffies(50));
2875 * New request retired after this work handler started, extend active
2876 * period until next instance of the work.
2878 if (work_pending(work))
2881 if (dev_priv->gt.active_requests)
2884 if (wait_for(intel_execlists_idle(dev_priv), 10))
2885 DRM_ERROR("Timeout waiting for engines to idle\n");
2887 for_each_engine(engine, dev_priv, id)
2888 i915_gem_batch_pool_fini(&engine->batch_pool);
2890 GEM_BUG_ON(!dev_priv->gt.awake);
2891 dev_priv->gt.awake = false;
2892 rearm_hangcheck = false;
2894 if (INTEL_GEN(dev_priv) >= 6)
2895 gen6_rps_idle(dev_priv);
2896 intel_runtime_pm_put(dev_priv);
2898 mutex_unlock(&dev->struct_mutex);
2901 if (rearm_hangcheck) {
2902 GEM_BUG_ON(!dev_priv->gt.awake);
2903 i915_queue_hangcheck(dev_priv);
2907 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
2909 struct drm_i915_gem_object *obj = to_intel_bo(gem);
2910 struct drm_i915_file_private *fpriv = file->driver_priv;
2911 struct i915_vma *vma, *vn;
2913 mutex_lock(&obj->base.dev->struct_mutex);
2914 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
2915 if (vma->vm->file == fpriv)
2916 i915_vma_close(vma);
2918 if (i915_gem_object_is_active(obj) &&
2919 !i915_gem_object_has_active_reference(obj)) {
2920 i915_gem_object_set_active_reference(obj);
2921 i915_gem_object_get(obj);
2923 mutex_unlock(&obj->base.dev->struct_mutex);
2926 static unsigned long to_wait_timeout(s64 timeout_ns)
2929 return MAX_SCHEDULE_TIMEOUT;
2931 if (timeout_ns == 0)
2934 return nsecs_to_jiffies_timeout(timeout_ns);
2938 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2939 * @dev: drm device pointer
2940 * @data: ioctl data blob
2941 * @file: drm file pointer
2943 * Returns 0 if successful, else an error is returned with the remaining time in
2944 * the timeout parameter.
2945 * -ETIME: object is still busy after timeout
2946 * -ERESTARTSYS: signal interrupted the wait
2947 * -ENONENT: object doesn't exist
2948 * Also possible, but rare:
2949 * -EAGAIN: GPU wedged
2951 * -ENODEV: Internal IRQ fail
2952 * -E?: The add request failed
2954 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2955 * non-zero timeout parameter the wait ioctl will wait for the given number of
2956 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2957 * without holding struct_mutex the object may become re-busied before this
2958 * function completes. A similar but shorter * race condition exists in the busy
2962 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2964 struct drm_i915_gem_wait *args = data;
2965 struct drm_i915_gem_object *obj;
2969 if (args->flags != 0)
2972 obj = i915_gem_object_lookup(file, args->bo_handle);
2976 start = ktime_get();
2978 ret = i915_gem_object_wait(obj,
2979 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
2980 to_wait_timeout(args->timeout_ns),
2981 to_rps_client(file));
2983 if (args->timeout_ns > 0) {
2984 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
2985 if (args->timeout_ns < 0)
2986 args->timeout_ns = 0;
2989 i915_gem_object_put(obj);
2993 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
2997 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
2998 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3006 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3010 if (flags & I915_WAIT_LOCKED) {
3011 struct i915_gem_timeline *tl;
3013 lockdep_assert_held(&i915->drm.struct_mutex);
3015 list_for_each_entry(tl, &i915->gt.timelines, link) {
3016 ret = wait_for_timeline(tl, flags);
3021 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3029 void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3032 /* If we don't have a page list set up, then we're not pinned
3033 * to GPU, and we can ignore the cache flush because it'll happen
3034 * again at bind time.
3040 * Stolen memory is always coherent with the GPU as it is explicitly
3041 * marked as wc by the system, or the system is cache-coherent.
3043 if (obj->stolen || obj->phys_handle)
3046 /* If the GPU is snooping the contents of the CPU cache,
3047 * we do not need to manually clear the CPU cache lines. However,
3048 * the caches are only snooped when the render cache is
3049 * flushed/invalidated. As we always have to emit invalidations
3050 * and flushes when moving into and out of the RENDER domain, correct
3051 * snooping behaviour occurs naturally as the result of our domain
3054 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3055 obj->cache_dirty = true;
3059 trace_i915_gem_object_clflush(obj);
3060 drm_clflush_sg(obj->mm.pages);
3061 obj->cache_dirty = false;
3064 /** Flushes the GTT write domain for the object if it's dirty. */
3066 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3068 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3070 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3073 /* No actual flushing is required for the GTT write domain. Writes
3074 * to it "immediately" go to main memory as far as we know, so there's
3075 * no chipset flush. It also doesn't land in render cache.
3077 * However, we do have to enforce the order so that all writes through
3078 * the GTT land before any writes to the device, such as updates to
3081 * We also have to wait a bit for the writes to land from the GTT.
3082 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3083 * timing. This issue has only been observed when switching quickly
3084 * between GTT writes and CPU reads from inside the kernel on recent hw,
3085 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3086 * system agents we cannot reproduce this behaviour).
3089 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3090 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3092 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
3094 obj->base.write_domain = 0;
3095 trace_i915_gem_object_change_domain(obj,
3096 obj->base.read_domains,
3097 I915_GEM_DOMAIN_GTT);
3100 /** Flushes the CPU write domain for the object if it's dirty. */
3102 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3104 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3107 i915_gem_clflush_object(obj, obj->pin_display);
3108 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3110 obj->base.write_domain = 0;
3111 trace_i915_gem_object_change_domain(obj,
3112 obj->base.read_domains,
3113 I915_GEM_DOMAIN_CPU);
3117 * Moves a single object to the GTT read, and possibly write domain.
3118 * @obj: object to act on
3119 * @write: ask for write access or read only
3121 * This function returns when the move is complete, including waiting on
3125 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3127 uint32_t old_write_domain, old_read_domains;
3130 lockdep_assert_held(&obj->base.dev->struct_mutex);
3132 ret = i915_gem_object_wait(obj,
3133 I915_WAIT_INTERRUPTIBLE |
3135 (write ? I915_WAIT_ALL : 0),
3136 MAX_SCHEDULE_TIMEOUT,
3141 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3144 /* Flush and acquire obj->pages so that we are coherent through
3145 * direct access in memory with previous cached writes through
3146 * shmemfs and that our cache domain tracking remains valid.
3147 * For example, if the obj->filp was moved to swap without us
3148 * being notified and releasing the pages, we would mistakenly
3149 * continue to assume that the obj remained out of the CPU cached
3152 ret = i915_gem_object_pin_pages(obj);
3156 i915_gem_object_flush_cpu_write_domain(obj);
3158 /* Serialise direct access to this object with the barriers for
3159 * coherent writes from the GPU, by effectively invalidating the
3160 * GTT domain upon first access.
3162 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3165 old_write_domain = obj->base.write_domain;
3166 old_read_domains = obj->base.read_domains;
3168 /* It should now be out of any other write domains, and we can update
3169 * the domain values for our changes.
3171 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3172 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3174 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3175 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3176 obj->mm.dirty = true;
3179 trace_i915_gem_object_change_domain(obj,
3183 i915_gem_object_unpin_pages(obj);
3188 * Changes the cache-level of an object across all VMA.
3189 * @obj: object to act on
3190 * @cache_level: new cache level to set for the object
3192 * After this function returns, the object will be in the new cache-level
3193 * across all GTT and the contents of the backing storage will be coherent,
3194 * with respect to the new cache-level. In order to keep the backing storage
3195 * coherent for all users, we only allow a single cache level to be set
3196 * globally on the object and prevent it from being changed whilst the
3197 * hardware is reading from the object. That is if the object is currently
3198 * on the scanout it will be set to uncached (or equivalent display
3199 * cache coherency) and all non-MOCS GPU access will also be uncached so
3200 * that all direct access to the scanout remains coherent.
3202 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3203 enum i915_cache_level cache_level)
3205 struct i915_vma *vma;
3208 lockdep_assert_held(&obj->base.dev->struct_mutex);
3210 if (obj->cache_level == cache_level)
3213 /* Inspect the list of currently bound VMA and unbind any that would
3214 * be invalid given the new cache-level. This is principally to
3215 * catch the issue of the CS prefetch crossing page boundaries and
3216 * reading an invalid PTE on older architectures.
3219 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3220 if (!drm_mm_node_allocated(&vma->node))
3223 if (i915_vma_is_pinned(vma)) {
3224 DRM_DEBUG("can not change the cache level of pinned objects\n");
3228 if (i915_gem_valid_gtt_space(vma, cache_level))
3231 ret = i915_vma_unbind(vma);
3235 /* As unbinding may affect other elements in the
3236 * obj->vma_list (due to side-effects from retiring
3237 * an active vma), play safe and restart the iterator.
3242 /* We can reuse the existing drm_mm nodes but need to change the
3243 * cache-level on the PTE. We could simply unbind them all and
3244 * rebind with the correct cache-level on next use. However since
3245 * we already have a valid slot, dma mapping, pages etc, we may as
3246 * rewrite the PTE in the belief that doing so tramples upon less
3247 * state and so involves less work.
3249 if (obj->bind_count) {
3250 /* Before we change the PTE, the GPU must not be accessing it.
3251 * If we wait upon the object, we know that all the bound
3252 * VMA are no longer active.
3254 ret = i915_gem_object_wait(obj,
3255 I915_WAIT_INTERRUPTIBLE |
3258 MAX_SCHEDULE_TIMEOUT,
3263 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3264 cache_level != I915_CACHE_NONE) {
3265 /* Access to snoopable pages through the GTT is
3266 * incoherent and on some machines causes a hard
3267 * lockup. Relinquish the CPU mmaping to force
3268 * userspace to refault in the pages and we can
3269 * then double check if the GTT mapping is still
3270 * valid for that pointer access.
3272 i915_gem_release_mmap(obj);
3274 /* As we no longer need a fence for GTT access,
3275 * we can relinquish it now (and so prevent having
3276 * to steal a fence from someone else on the next
3277 * fence request). Note GPU activity would have
3278 * dropped the fence as all snoopable access is
3279 * supposed to be linear.
3281 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3282 ret = i915_vma_put_fence(vma);
3287 /* We either have incoherent backing store and
3288 * so no GTT access or the architecture is fully
3289 * coherent. In such cases, existing GTT mmaps
3290 * ignore the cache bit in the PTE and we can
3291 * rewrite it without confusing the GPU or having
3292 * to force userspace to fault back in its mmaps.
3296 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3297 if (!drm_mm_node_allocated(&vma->node))
3300 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3306 list_for_each_entry(vma, &obj->vma_list, obj_link)
3307 vma->node.color = cache_level;
3308 obj->cache_level = cache_level;
3311 /* Flush the dirty CPU caches to the backing storage so that the
3312 * object is now coherent at its new cache level (with respect
3313 * to the access domain).
3315 if (obj->cache_dirty && cpu_write_needs_clflush(obj))
3316 i915_gem_clflush_object(obj, true);
3321 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3322 struct drm_file *file)
3324 struct drm_i915_gem_caching *args = data;
3325 struct drm_i915_gem_object *obj;
3329 obj = i915_gem_object_lookup_rcu(file, args->handle);
3335 switch (obj->cache_level) {
3336 case I915_CACHE_LLC:
3337 case I915_CACHE_L3_LLC:
3338 args->caching = I915_CACHING_CACHED;
3342 args->caching = I915_CACHING_DISPLAY;
3346 args->caching = I915_CACHING_NONE;
3354 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3355 struct drm_file *file)
3357 struct drm_i915_private *i915 = to_i915(dev);
3358 struct drm_i915_gem_caching *args = data;
3359 struct drm_i915_gem_object *obj;
3360 enum i915_cache_level level;
3363 switch (args->caching) {
3364 case I915_CACHING_NONE:
3365 level = I915_CACHE_NONE;
3367 case I915_CACHING_CACHED:
3369 * Due to a HW issue on BXT A stepping, GPU stores via a
3370 * snooped mapping may leave stale data in a corresponding CPU
3371 * cacheline, whereas normally such cachelines would get
3374 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3377 level = I915_CACHE_LLC;
3379 case I915_CACHING_DISPLAY:
3380 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3386 ret = i915_mutex_lock_interruptible(dev);
3390 obj = i915_gem_object_lookup(file, args->handle);
3396 ret = i915_gem_object_set_cache_level(obj, level);
3397 i915_gem_object_put(obj);
3399 mutex_unlock(&dev->struct_mutex);
3404 * Prepare buffer for display plane (scanout, cursors, etc).
3405 * Can be called from an uninterruptible phase (modesetting) and allows
3406 * any flushes to be pipelined (for pageflips).
3409 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3411 const struct i915_ggtt_view *view)
3413 struct i915_vma *vma;
3414 u32 old_read_domains, old_write_domain;
3417 lockdep_assert_held(&obj->base.dev->struct_mutex);
3419 /* Mark the pin_display early so that we account for the
3420 * display coherency whilst setting up the cache domains.
3424 /* The display engine is not coherent with the LLC cache on gen6. As
3425 * a result, we make sure that the pinning that is about to occur is
3426 * done with uncached PTEs. This is lowest common denominator for all
3429 * However for gen6+, we could do better by using the GFDT bit instead
3430 * of uncaching, which would allow us to flush all the LLC-cached data
3431 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3433 ret = i915_gem_object_set_cache_level(obj,
3434 HAS_WT(to_i915(obj->base.dev)) ?
3435 I915_CACHE_WT : I915_CACHE_NONE);
3438 goto err_unpin_display;
3441 /* As the user may map the buffer once pinned in the display plane
3442 * (e.g. libkms for the bootup splash), we have to ensure that we
3443 * always use map_and_fenceable for all scanout buffers. However,
3444 * it may simply be too big to fit into mappable, in which case
3445 * put it anyway and hope that userspace can cope (but always first
3446 * try to preserve the existing ABI).
3448 vma = ERR_PTR(-ENOSPC);
3449 if (view->type == I915_GGTT_VIEW_NORMAL)
3450 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3451 PIN_MAPPABLE | PIN_NONBLOCK);
3453 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3456 /* Valleyview is definitely limited to scanning out the first
3457 * 512MiB. Lets presume this behaviour was inherited from the
3458 * g4x display engine and that all earlier gen are similarly
3459 * limited. Testing suggests that it is a little more
3460 * complicated than this. For example, Cherryview appears quite
3461 * happy to scanout from anywhere within its global aperture.
3464 if (HAS_GMCH_DISPLAY(i915))
3465 flags = PIN_MAPPABLE;
3466 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3469 goto err_unpin_display;
3471 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3473 i915_gem_object_flush_cpu_write_domain(obj);
3475 old_write_domain = obj->base.write_domain;
3476 old_read_domains = obj->base.read_domains;
3478 /* It should now be out of any other write domains, and we can update
3479 * the domain values for our changes.
3481 obj->base.write_domain = 0;
3482 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3484 trace_i915_gem_object_change_domain(obj,
3496 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3498 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3500 if (WARN_ON(vma->obj->pin_display == 0))
3503 if (--vma->obj->pin_display == 0)
3504 vma->display_alignment = 0;
3506 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3507 if (!i915_vma_is_active(vma))
3508 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3510 i915_vma_unpin(vma);
3514 * Moves a single object to the CPU read, and possibly write domain.
3515 * @obj: object to act on
3516 * @write: requesting write or read-only access
3518 * This function returns when the move is complete, including waiting on
3522 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3524 uint32_t old_write_domain, old_read_domains;
3527 lockdep_assert_held(&obj->base.dev->struct_mutex);
3529 ret = i915_gem_object_wait(obj,
3530 I915_WAIT_INTERRUPTIBLE |
3532 (write ? I915_WAIT_ALL : 0),
3533 MAX_SCHEDULE_TIMEOUT,
3538 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3541 i915_gem_object_flush_gtt_write_domain(obj);
3543 old_write_domain = obj->base.write_domain;
3544 old_read_domains = obj->base.read_domains;
3546 /* Flush the CPU cache if it's still invalid. */
3547 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3548 i915_gem_clflush_object(obj, false);
3550 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3553 /* It should now be out of any other write domains, and we can update
3554 * the domain values for our changes.
3556 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3558 /* If we're writing through the CPU, then the GPU read domains will
3559 * need to be invalidated at next use.
3562 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3563 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3566 trace_i915_gem_object_change_domain(obj,
3573 /* Throttle our rendering by waiting until the ring has completed our requests
3574 * emitted over 20 msec ago.
3576 * Note that if we were to use the current jiffies each time around the loop,
3577 * we wouldn't escape the function with any frames outstanding if the time to
3578 * render a frame was over 20ms.
3580 * This should get us reasonable parallelism between CPU and GPU but also
3581 * relatively low latency when blocking on a particular request to finish.
3584 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3586 struct drm_i915_private *dev_priv = to_i915(dev);
3587 struct drm_i915_file_private *file_priv = file->driver_priv;
3588 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3589 struct drm_i915_gem_request *request, *target = NULL;
3592 /* ABI: return -EIO if already wedged */
3593 if (i915_terminally_wedged(&dev_priv->gpu_error))
3596 spin_lock(&file_priv->mm.lock);
3597 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3598 if (time_after_eq(request->emitted_jiffies, recent_enough))
3602 * Note that the request might not have been submitted yet.
3603 * In which case emitted_jiffies will be zero.
3605 if (!request->emitted_jiffies)
3611 i915_gem_request_get(target);
3612 spin_unlock(&file_priv->mm.lock);
3617 ret = i915_wait_request(target,
3618 I915_WAIT_INTERRUPTIBLE,
3619 MAX_SCHEDULE_TIMEOUT);
3620 i915_gem_request_put(target);
3622 return ret < 0 ? ret : 0;
3626 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3627 const struct i915_ggtt_view *view,
3632 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3633 struct i915_address_space *vm = &dev_priv->ggtt.base;
3634 struct i915_vma *vma;
3637 lockdep_assert_held(&obj->base.dev->struct_mutex);
3639 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view);
3643 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3644 if (flags & PIN_NONBLOCK &&
3645 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3646 return ERR_PTR(-ENOSPC);
3648 if (flags & PIN_MAPPABLE) {
3651 fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
3652 i915_gem_object_get_tiling(obj));
3653 /* If the required space is larger than the available
3654 * aperture, we will not able to find a slot for the
3655 * object and unbinding the object now will be in
3656 * vain. Worse, doing so may cause us to ping-pong
3657 * the object in and out of the Global GTT and
3658 * waste a lot of cycles under the mutex.
3660 if (fence_size > dev_priv->ggtt.mappable_end)
3661 return ERR_PTR(-E2BIG);
3663 /* If NONBLOCK is set the caller is optimistically
3664 * trying to cache the full object within the mappable
3665 * aperture, and *must* have a fallback in place for
3666 * situations where we cannot bind the object. We
3667 * can be a little more lax here and use the fallback
3668 * more often to avoid costly migrations of ourselves
3669 * and other objects within the aperture.
3671 * Half-the-aperture is used as a simple heuristic.
3672 * More interesting would to do search for a free
3673 * block prior to making the commitment to unbind.
3674 * That caters for the self-harm case, and with a
3675 * little more heuristics (e.g. NOFAULT, NOEVICT)
3676 * we could try to minimise harm to others.
3678 if (flags & PIN_NONBLOCK &&
3679 fence_size > dev_priv->ggtt.mappable_end / 2)
3680 return ERR_PTR(-ENOSPC);
3683 WARN(i915_vma_is_pinned(vma),
3684 "bo is already pinned in ggtt with incorrect alignment:"
3685 " offset=%08x, req.alignment=%llx,"
3686 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3687 i915_ggtt_offset(vma), alignment,
3688 !!(flags & PIN_MAPPABLE),
3689 i915_vma_is_map_and_fenceable(vma));
3690 ret = i915_vma_unbind(vma);
3692 return ERR_PTR(ret);
3695 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3697 return ERR_PTR(ret);
3702 static __always_inline unsigned int __busy_read_flag(unsigned int id)
3704 /* Note that we could alias engines in the execbuf API, but
3705 * that would be very unwise as it prevents userspace from
3706 * fine control over engine selection. Ahem.
3708 * This should be something like EXEC_MAX_ENGINE instead of
3711 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3712 return 0x10000 << id;
3715 static __always_inline unsigned int __busy_write_id(unsigned int id)
3717 /* The uABI guarantees an active writer is also amongst the read
3718 * engines. This would be true if we accessed the activity tracking
3719 * under the lock, but as we perform the lookup of the object and
3720 * its activity locklessly we can not guarantee that the last_write
3721 * being active implies that we have set the same engine flag from
3722 * last_read - hence we always set both read and write busy for
3725 return id | __busy_read_flag(id);
3728 static __always_inline unsigned int
3729 __busy_set_if_active(const struct dma_fence *fence,
3730 unsigned int (*flag)(unsigned int id))
3732 struct drm_i915_gem_request *rq;
3734 /* We have to check the current hw status of the fence as the uABI
3735 * guarantees forward progress. We could rely on the idle worker
3736 * to eventually flush us, but to minimise latency just ask the
3739 * Note we only report on the status of native fences.
3741 if (!dma_fence_is_i915(fence))
3744 /* opencode to_request() in order to avoid const warnings */
3745 rq = container_of(fence, struct drm_i915_gem_request, fence);
3746 if (i915_gem_request_completed(rq))
3749 return flag(rq->engine->exec_id);
3752 static __always_inline unsigned int
3753 busy_check_reader(const struct dma_fence *fence)
3755 return __busy_set_if_active(fence, __busy_read_flag);
3758 static __always_inline unsigned int
3759 busy_check_writer(const struct dma_fence *fence)
3764 return __busy_set_if_active(fence, __busy_write_id);
3768 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3769 struct drm_file *file)
3771 struct drm_i915_gem_busy *args = data;
3772 struct drm_i915_gem_object *obj;
3773 struct reservation_object_list *list;
3779 obj = i915_gem_object_lookup_rcu(file, args->handle);
3783 /* A discrepancy here is that we do not report the status of
3784 * non-i915 fences, i.e. even though we may report the object as idle,
3785 * a call to set-domain may still stall waiting for foreign rendering.
3786 * This also means that wait-ioctl may report an object as busy,
3787 * where busy-ioctl considers it idle.
3789 * We trade the ability to warn of foreign fences to report on which
3790 * i915 engines are active for the object.
3792 * Alternatively, we can trade that extra information on read/write
3795 * !reservation_object_test_signaled_rcu(obj->resv, true);
3796 * to report the overall busyness. This is what the wait-ioctl does.
3800 seq = raw_read_seqcount(&obj->resv->seq);
3802 /* Translate the exclusive fence to the READ *and* WRITE engine */
3803 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
3805 /* Translate shared fences to READ set of engines */
3806 list = rcu_dereference(obj->resv->fence);
3808 unsigned int shared_count = list->shared_count, i;
3810 for (i = 0; i < shared_count; ++i) {
3811 struct dma_fence *fence =
3812 rcu_dereference(list->shared[i]);
3814 args->busy |= busy_check_reader(fence);
3818 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
3828 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3829 struct drm_file *file_priv)
3831 return i915_gem_ring_throttle(dev, file_priv);
3835 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3836 struct drm_file *file_priv)
3838 struct drm_i915_private *dev_priv = to_i915(dev);
3839 struct drm_i915_gem_madvise *args = data;
3840 struct drm_i915_gem_object *obj;
3843 switch (args->madv) {
3844 case I915_MADV_DONTNEED:
3845 case I915_MADV_WILLNEED:
3851 obj = i915_gem_object_lookup(file_priv, args->handle);
3855 err = mutex_lock_interruptible(&obj->mm.lock);
3859 if (obj->mm.pages &&
3860 i915_gem_object_is_tiled(obj) &&
3861 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
3862 if (obj->mm.madv == I915_MADV_WILLNEED) {
3863 GEM_BUG_ON(!obj->mm.quirked);
3864 __i915_gem_object_unpin_pages(obj);
3865 obj->mm.quirked = false;
3867 if (args->madv == I915_MADV_WILLNEED) {
3868 GEM_BUG_ON(obj->mm.quirked);
3869 __i915_gem_object_pin_pages(obj);
3870 obj->mm.quirked = true;
3874 if (obj->mm.madv != __I915_MADV_PURGED)
3875 obj->mm.madv = args->madv;
3877 /* if the object is no longer attached, discard its backing storage */
3878 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
3879 i915_gem_object_truncate(obj);
3881 args->retained = obj->mm.madv != __I915_MADV_PURGED;
3882 mutex_unlock(&obj->mm.lock);
3885 i915_gem_object_put(obj);
3889 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3890 const struct drm_i915_gem_object_ops *ops)
3892 mutex_init(&obj->mm.lock);
3894 INIT_LIST_HEAD(&obj->global_link);
3895 INIT_LIST_HEAD(&obj->userfault_link);
3896 INIT_LIST_HEAD(&obj->obj_exec_link);
3897 INIT_LIST_HEAD(&obj->vma_list);
3898 INIT_LIST_HEAD(&obj->batch_pool_link);
3902 reservation_object_init(&obj->__builtin_resv);
3903 obj->resv = &obj->__builtin_resv;
3905 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
3907 obj->mm.madv = I915_MADV_WILLNEED;
3908 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
3909 mutex_init(&obj->mm.get_page.lock);
3911 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
3914 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3915 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
3916 I915_GEM_OBJECT_IS_SHRINKABLE,
3917 .get_pages = i915_gem_object_get_pages_gtt,
3918 .put_pages = i915_gem_object_put_pages_gtt,
3921 /* Note we don't consider signbits :| */
3922 #define overflows_type(x, T) \
3923 (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
3925 struct drm_i915_gem_object *
3926 i915_gem_object_create(struct drm_device *dev, u64 size)
3928 struct drm_i915_private *dev_priv = to_i915(dev);
3929 struct drm_i915_gem_object *obj;
3930 struct address_space *mapping;
3934 /* There is a prevalence of the assumption that we fit the object's
3935 * page count inside a 32bit _signed_ variable. Let's document this and
3936 * catch if we ever need to fix it. In the meantime, if you do spot
3937 * such a local variable, please consider fixing!
3939 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
3940 return ERR_PTR(-E2BIG);
3942 if (overflows_type(size, obj->base.size))
3943 return ERR_PTR(-E2BIG);
3945 obj = i915_gem_object_alloc(dev);
3947 return ERR_PTR(-ENOMEM);
3949 ret = drm_gem_object_init(dev, &obj->base, size);
3953 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3954 if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) {
3955 /* 965gm cannot relocate objects above 4GiB. */
3956 mask &= ~__GFP_HIGHMEM;
3957 mask |= __GFP_DMA32;
3960 mapping = obj->base.filp->f_mapping;
3961 mapping_set_gfp_mask(mapping, mask);
3963 i915_gem_object_init(obj, &i915_gem_object_ops);
3965 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3966 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3968 if (HAS_LLC(dev_priv)) {
3969 /* On some devices, we can have the GPU use the LLC (the CPU
3970 * cache) for about a 10% performance improvement
3971 * compared to uncached. Graphics requests other than
3972 * display scanout are coherent with the CPU in
3973 * accessing this cache. This means in this mode we
3974 * don't need to clflush on the CPU side, and on the
3975 * GPU side we only need to flush internal caches to
3976 * get data visible to the CPU.
3978 * However, we maintain the display planes as UC, and so
3979 * need to rebind when first used as such.
3981 obj->cache_level = I915_CACHE_LLC;
3983 obj->cache_level = I915_CACHE_NONE;
3985 trace_i915_gem_object_create(obj);
3990 i915_gem_object_free(obj);
3991 return ERR_PTR(ret);
3994 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
3996 /* If we are the last user of the backing storage (be it shmemfs
3997 * pages or stolen etc), we know that the pages are going to be
3998 * immediately released. In this case, we can then skip copying
3999 * back the contents from the GPU.
4002 if (obj->mm.madv != I915_MADV_WILLNEED)
4005 if (obj->base.filp == NULL)
4008 /* At first glance, this looks racy, but then again so would be
4009 * userspace racing mmap against close. However, the first external
4010 * reference to the filp can only be obtained through the
4011 * i915_gem_mmap_ioctl() which safeguards us against the user
4012 * acquiring such a reference whilst we are in the middle of
4013 * freeing the object.
4015 return atomic_long_read(&obj->base.filp->f_count) == 1;
4018 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4019 struct llist_node *freed)
4021 struct drm_i915_gem_object *obj, *on;
4023 mutex_lock(&i915->drm.struct_mutex);
4024 intel_runtime_pm_get(i915);
4025 llist_for_each_entry(obj, freed, freed) {
4026 struct i915_vma *vma, *vn;
4028 trace_i915_gem_object_destroy(obj);
4030 GEM_BUG_ON(i915_gem_object_is_active(obj));
4031 list_for_each_entry_safe(vma, vn,
4032 &obj->vma_list, obj_link) {
4033 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4034 GEM_BUG_ON(i915_vma_is_active(vma));
4035 vma->flags &= ~I915_VMA_PIN_MASK;
4036 i915_vma_close(vma);
4038 GEM_BUG_ON(!list_empty(&obj->vma_list));
4039 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4041 list_del(&obj->global_link);
4043 intel_runtime_pm_put(i915);
4044 mutex_unlock(&i915->drm.struct_mutex);
4046 llist_for_each_entry_safe(obj, on, freed, freed) {
4047 GEM_BUG_ON(obj->bind_count);
4048 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4050 if (obj->ops->release)
4051 obj->ops->release(obj);
4053 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4054 atomic_set(&obj->mm.pages_pin_count, 0);
4055 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4056 GEM_BUG_ON(obj->mm.pages);
4058 if (obj->base.import_attach)
4059 drm_prime_gem_destroy(&obj->base, NULL);
4061 reservation_object_fini(&obj->__builtin_resv);
4062 drm_gem_object_release(&obj->base);
4063 i915_gem_info_remove_obj(i915, obj->base.size);
4066 i915_gem_object_free(obj);
4070 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4072 struct llist_node *freed;
4074 freed = llist_del_all(&i915->mm.free_list);
4075 if (unlikely(freed))
4076 __i915_gem_free_objects(i915, freed);
4079 static void __i915_gem_free_work(struct work_struct *work)
4081 struct drm_i915_private *i915 =
4082 container_of(work, struct drm_i915_private, mm.free_work);
4083 struct llist_node *freed;
4085 /* All file-owned VMA should have been released by this point through
4086 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4087 * However, the object may also be bound into the global GTT (e.g.
4088 * older GPUs without per-process support, or for direct access through
4089 * the GTT either for the user or for scanout). Those VMA still need to
4093 while ((freed = llist_del_all(&i915->mm.free_list)))
4094 __i915_gem_free_objects(i915, freed);
4097 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4099 struct drm_i915_gem_object *obj =
4100 container_of(head, typeof(*obj), rcu);
4101 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4103 /* We can't simply use call_rcu() from i915_gem_free_object()
4104 * as we need to block whilst unbinding, and the call_rcu
4105 * task may be called from softirq context. So we take a
4106 * detour through a worker.
4108 if (llist_add(&obj->freed, &i915->mm.free_list))
4109 schedule_work(&i915->mm.free_work);
4112 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4114 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4116 if (obj->mm.quirked)
4117 __i915_gem_object_unpin_pages(obj);
4119 if (discard_backing_storage(obj))
4120 obj->mm.madv = I915_MADV_DONTNEED;
4122 /* Before we free the object, make sure any pure RCU-only
4123 * read-side critical sections are complete, e.g.
4124 * i915_gem_busy_ioctl(). For the corresponding synchronized
4125 * lookup see i915_gem_object_lookup_rcu().
4127 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4130 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4132 lockdep_assert_held(&obj->base.dev->struct_mutex);
4134 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4135 if (i915_gem_object_is_active(obj))
4136 i915_gem_object_set_active_reference(obj);
4138 i915_gem_object_put(obj);
4141 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4143 struct intel_engine_cs *engine;
4144 enum intel_engine_id id;
4146 for_each_engine(engine, dev_priv, id)
4147 GEM_BUG_ON(engine->last_context != dev_priv->kernel_context);
4150 int i915_gem_suspend(struct drm_device *dev)
4152 struct drm_i915_private *dev_priv = to_i915(dev);
4155 intel_suspend_gt_powersave(dev_priv);
4157 mutex_lock(&dev->struct_mutex);
4159 /* We have to flush all the executing contexts to main memory so
4160 * that they can saved in the hibernation image. To ensure the last
4161 * context image is coherent, we have to switch away from it. That
4162 * leaves the dev_priv->kernel_context still active when
4163 * we actually suspend, and its image in memory may not match the GPU
4164 * state. Fortunately, the kernel_context is disposable and we do
4165 * not rely on its state.
4167 ret = i915_gem_switch_to_kernel_context(dev_priv);
4171 ret = i915_gem_wait_for_idle(dev_priv,
4172 I915_WAIT_INTERRUPTIBLE |
4177 i915_gem_retire_requests(dev_priv);
4178 GEM_BUG_ON(dev_priv->gt.active_requests);
4180 assert_kernel_context_is_current(dev_priv);
4181 i915_gem_context_lost(dev_priv);
4182 mutex_unlock(&dev->struct_mutex);
4184 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4185 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4186 flush_delayed_work(&dev_priv->gt.idle_work);
4187 flush_work(&dev_priv->mm.free_work);
4189 /* Assert that we sucessfully flushed all the work and
4190 * reset the GPU back to its idle, low power state.
4192 WARN_ON(dev_priv->gt.awake);
4193 WARN_ON(!intel_execlists_idle(dev_priv));
4196 * Neither the BIOS, ourselves or any other kernel
4197 * expects the system to be in execlists mode on startup,
4198 * so we need to reset the GPU back to legacy mode. And the only
4199 * known way to disable logical contexts is through a GPU reset.
4201 * So in order to leave the system in a known default configuration,
4202 * always reset the GPU upon unload and suspend. Afterwards we then
4203 * clean up the GEM state tracking, flushing off the requests and
4204 * leaving the system in a known idle state.
4206 * Note that is of the upmost importance that the GPU is idle and
4207 * all stray writes are flushed *before* we dismantle the backing
4208 * storage for the pinned objects.
4210 * However, since we are uncertain that resetting the GPU on older
4211 * machines is a good idea, we don't - just in case it leaves the
4212 * machine in an unusable condition.
4214 if (HAS_HW_CONTEXTS(dev_priv)) {
4215 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
4216 WARN_ON(reset && reset != -ENODEV);
4222 mutex_unlock(&dev->struct_mutex);
4226 void i915_gem_resume(struct drm_device *dev)
4228 struct drm_i915_private *dev_priv = to_i915(dev);
4230 WARN_ON(dev_priv->gt.awake);
4232 mutex_lock(&dev->struct_mutex);
4233 i915_gem_restore_gtt_mappings(dev);
4235 /* As we didn't flush the kernel context before suspend, we cannot
4236 * guarantee that the context image is complete. So let's just reset
4237 * it and start again.
4239 dev_priv->gt.resume(dev_priv);
4241 mutex_unlock(&dev->struct_mutex);
4244 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4246 if (INTEL_GEN(dev_priv) < 5 ||
4247 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4250 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4251 DISP_TILE_SURFACE_SWIZZLING);
4253 if (IS_GEN5(dev_priv))
4256 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4257 if (IS_GEN6(dev_priv))
4258 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4259 else if (IS_GEN7(dev_priv))
4260 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4261 else if (IS_GEN8(dev_priv))
4262 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4267 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4269 I915_WRITE(RING_CTL(base), 0);
4270 I915_WRITE(RING_HEAD(base), 0);
4271 I915_WRITE(RING_TAIL(base), 0);
4272 I915_WRITE(RING_START(base), 0);
4275 static void init_unused_rings(struct drm_i915_private *dev_priv)
4277 if (IS_I830(dev_priv)) {
4278 init_unused_ring(dev_priv, PRB1_BASE);
4279 init_unused_ring(dev_priv, SRB0_BASE);
4280 init_unused_ring(dev_priv, SRB1_BASE);
4281 init_unused_ring(dev_priv, SRB2_BASE);
4282 init_unused_ring(dev_priv, SRB3_BASE);
4283 } else if (IS_GEN2(dev_priv)) {
4284 init_unused_ring(dev_priv, SRB0_BASE);
4285 init_unused_ring(dev_priv, SRB1_BASE);
4286 } else if (IS_GEN3(dev_priv)) {
4287 init_unused_ring(dev_priv, PRB1_BASE);
4288 init_unused_ring(dev_priv, PRB2_BASE);
4293 i915_gem_init_hw(struct drm_device *dev)
4295 struct drm_i915_private *dev_priv = to_i915(dev);
4296 struct intel_engine_cs *engine;
4297 enum intel_engine_id id;
4300 dev_priv->gt.last_init_time = ktime_get();
4302 /* Double layer security blanket, see i915_gem_init() */
4303 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4305 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4306 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4308 if (IS_HASWELL(dev_priv))
4309 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4310 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4312 if (HAS_PCH_NOP(dev_priv)) {
4313 if (IS_IVYBRIDGE(dev_priv)) {
4314 u32 temp = I915_READ(GEN7_MSG_CTL);
4315 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4316 I915_WRITE(GEN7_MSG_CTL, temp);
4317 } else if (INTEL_GEN(dev_priv) >= 7) {
4318 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4319 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4320 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4324 i915_gem_init_swizzling(dev_priv);
4327 * At least 830 can leave some of the unused rings
4328 * "active" (ie. head != tail) after resume which
4329 * will prevent c3 entry. Makes sure all unused rings
4332 init_unused_rings(dev_priv);
4334 BUG_ON(!dev_priv->kernel_context);
4336 ret = i915_ppgtt_init_hw(dev_priv);
4338 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4342 /* Need to do basic initialisation of all rings first: */
4343 for_each_engine(engine, dev_priv, id) {
4344 ret = engine->init_hw(engine);
4349 intel_mocs_init_l3cc_table(dev);
4351 /* We can't enable contexts until all firmware is loaded */
4352 ret = intel_guc_setup(dev);
4357 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4361 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4363 if (INTEL_INFO(dev_priv)->gen < 6)
4366 /* TODO: make semaphores and Execlists play nicely together */
4367 if (i915.enable_execlists)
4373 #ifdef CONFIG_INTEL_IOMMU
4374 /* Enable semaphores on SNB when IO remapping is off */
4375 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4382 int i915_gem_init(struct drm_device *dev)
4384 struct drm_i915_private *dev_priv = to_i915(dev);
4387 mutex_lock(&dev->struct_mutex);
4389 if (!i915.enable_execlists) {
4390 dev_priv->gt.resume = intel_legacy_submission_resume;
4391 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4393 dev_priv->gt.resume = intel_lr_context_resume;
4394 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4397 /* This is just a security blanket to placate dragons.
4398 * On some systems, we very sporadically observe that the first TLBs
4399 * used by the CS may be stale, despite us poking the TLB reset. If
4400 * we hold the forcewake during initialisation these problems
4401 * just magically go away.
4403 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4405 i915_gem_init_userptr(dev_priv);
4407 ret = i915_gem_init_ggtt(dev_priv);
4411 ret = i915_gem_context_init(dev);
4415 ret = intel_engines_init(dev);
4419 ret = i915_gem_init_hw(dev);
4421 /* Allow engine initialisation to fail by marking the GPU as
4422 * wedged. But we only want to do this where the GPU is angry,
4423 * for all other failure, such as an allocation failure, bail.
4425 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4426 i915_gem_set_wedged(dev_priv);
4431 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4432 mutex_unlock(&dev->struct_mutex);
4438 i915_gem_cleanup_engines(struct drm_device *dev)
4440 struct drm_i915_private *dev_priv = to_i915(dev);
4441 struct intel_engine_cs *engine;
4442 enum intel_engine_id id;
4444 for_each_engine(engine, dev_priv, id)
4445 dev_priv->gt.cleanup_engine(engine);
4449 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4451 struct drm_device *dev = &dev_priv->drm;
4454 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4455 !IS_CHERRYVIEW(dev_priv))
4456 dev_priv->num_fence_regs = 32;
4457 else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
4458 IS_I945GM(dev_priv) || IS_G33(dev_priv))
4459 dev_priv->num_fence_regs = 16;
4461 dev_priv->num_fence_regs = 8;
4463 if (intel_vgpu_active(dev_priv))
4464 dev_priv->num_fence_regs =
4465 I915_READ(vgtif_reg(avail_rs.fence_num));
4467 /* Initialize fence registers to zero */
4468 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4469 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4471 fence->i915 = dev_priv;
4473 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4475 i915_gem_restore_fences(dev);
4477 i915_gem_detect_bit_6_swizzle(dev);
4481 i915_gem_load_init(struct drm_device *dev)
4483 struct drm_i915_private *dev_priv = to_i915(dev);
4486 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4487 if (!dev_priv->objects)
4490 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4491 if (!dev_priv->vmas)
4494 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4495 SLAB_HWCACHE_ALIGN |
4496 SLAB_RECLAIM_ACCOUNT |
4497 SLAB_DESTROY_BY_RCU);
4498 if (!dev_priv->requests)
4501 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4502 SLAB_HWCACHE_ALIGN |
4503 SLAB_RECLAIM_ACCOUNT);
4504 if (!dev_priv->dependencies)
4507 mutex_lock(&dev_priv->drm.struct_mutex);
4508 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4509 err = i915_gem_timeline_init__global(dev_priv);
4510 mutex_unlock(&dev_priv->drm.struct_mutex);
4512 goto err_dependencies;
4514 INIT_LIST_HEAD(&dev_priv->context_list);
4515 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4516 init_llist_head(&dev_priv->mm.free_list);
4517 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4518 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4519 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4520 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4521 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4522 i915_gem_retire_work_handler);
4523 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4524 i915_gem_idle_work_handler);
4525 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4526 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4528 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4530 init_waitqueue_head(&dev_priv->pending_flip_queue);
4532 dev_priv->mm.interruptible = true;
4534 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4536 spin_lock_init(&dev_priv->fb_tracking.lock);
4541 kmem_cache_destroy(dev_priv->dependencies);
4543 kmem_cache_destroy(dev_priv->requests);
4545 kmem_cache_destroy(dev_priv->vmas);
4547 kmem_cache_destroy(dev_priv->objects);
4552 void i915_gem_load_cleanup(struct drm_device *dev)
4554 struct drm_i915_private *dev_priv = to_i915(dev);
4556 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4558 kmem_cache_destroy(dev_priv->dependencies);
4559 kmem_cache_destroy(dev_priv->requests);
4560 kmem_cache_destroy(dev_priv->vmas);
4561 kmem_cache_destroy(dev_priv->objects);
4563 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4567 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4569 intel_runtime_pm_get(dev_priv);
4571 mutex_lock(&dev_priv->drm.struct_mutex);
4572 i915_gem_shrink_all(dev_priv);
4573 mutex_unlock(&dev_priv->drm.struct_mutex);
4575 intel_runtime_pm_put(dev_priv);
4580 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4582 struct drm_i915_gem_object *obj;
4583 struct list_head *phases[] = {
4584 &dev_priv->mm.unbound_list,
4585 &dev_priv->mm.bound_list,
4589 /* Called just before we write the hibernation image.
4591 * We need to update the domain tracking to reflect that the CPU
4592 * will be accessing all the pages to create and restore from the
4593 * hibernation, and so upon restoration those pages will be in the
4596 * To make sure the hibernation image contains the latest state,
4597 * we update that state just before writing out the image.
4599 * To try and reduce the hibernation image, we manually shrink
4600 * the objects as well.
4603 mutex_lock(&dev_priv->drm.struct_mutex);
4604 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4606 for (p = phases; *p; p++) {
4607 list_for_each_entry(obj, *p, global_link) {
4608 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4609 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4612 mutex_unlock(&dev_priv->drm.struct_mutex);
4617 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4619 struct drm_i915_file_private *file_priv = file->driver_priv;
4620 struct drm_i915_gem_request *request;
4622 /* Clean up our request list when the client is going away, so that
4623 * later retire_requests won't dereference our soon-to-be-gone
4626 spin_lock(&file_priv->mm.lock);
4627 list_for_each_entry(request, &file_priv->mm.request_list, client_list)
4628 request->file_priv = NULL;
4629 spin_unlock(&file_priv->mm.lock);
4631 if (!list_empty(&file_priv->rps.link)) {
4632 spin_lock(&to_i915(dev)->rps.client_lock);
4633 list_del(&file_priv->rps.link);
4634 spin_unlock(&to_i915(dev)->rps.client_lock);
4638 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4640 struct drm_i915_file_private *file_priv;
4643 DRM_DEBUG_DRIVER("\n");
4645 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4649 file->driver_priv = file_priv;
4650 file_priv->dev_priv = to_i915(dev);
4651 file_priv->file = file;
4652 INIT_LIST_HEAD(&file_priv->rps.link);
4654 spin_lock_init(&file_priv->mm.lock);
4655 INIT_LIST_HEAD(&file_priv->mm.request_list);
4657 file_priv->bsd_engine = -1;
4659 ret = i915_gem_context_open(dev, file);
4667 * i915_gem_track_fb - update frontbuffer tracking
4668 * @old: current GEM buffer for the frontbuffer slots
4669 * @new: new GEM buffer for the frontbuffer slots
4670 * @frontbuffer_bits: bitmask of frontbuffer slots
4672 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4673 * from @old and setting them in @new. Both @old and @new can be NULL.
4675 void i915_gem_track_fb(struct drm_i915_gem_object *old,
4676 struct drm_i915_gem_object *new,
4677 unsigned frontbuffer_bits)
4679 /* Control of individual bits within the mask are guarded by
4680 * the owning plane->mutex, i.e. we can never see concurrent
4681 * manipulation of individual bits. But since the bitfield as a whole
4682 * is updated using RMW, we need to use atomics in order to update
4685 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4686 sizeof(atomic_t) * BITS_PER_BYTE);
4689 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4690 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4694 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4695 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4699 /* Allocate a new GEM object and fill it with the supplied data */
4700 struct drm_i915_gem_object *
4701 i915_gem_object_create_from_data(struct drm_device *dev,
4702 const void *data, size_t size)
4704 struct drm_i915_gem_object *obj;
4705 struct sg_table *sg;
4709 obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
4713 ret = i915_gem_object_set_to_cpu_domain(obj, true);
4717 ret = i915_gem_object_pin_pages(obj);
4722 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4723 obj->mm.dirty = true; /* Backing store is now out of date */
4724 i915_gem_object_unpin_pages(obj);
4726 if (WARN_ON(bytes != size)) {
4727 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
4735 i915_gem_object_put(obj);
4736 return ERR_PTR(ret);
4739 struct scatterlist *
4740 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
4742 unsigned int *offset)
4744 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
4745 struct scatterlist *sg;
4746 unsigned int idx, count;
4749 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
4750 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
4752 /* As we iterate forward through the sg, we record each entry in a
4753 * radixtree for quick repeated (backwards) lookups. If we have seen
4754 * this index previously, we will have an entry for it.
4756 * Initial lookup is O(N), but this is amortized to O(1) for
4757 * sequential page access (where each new request is consecutive
4758 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4759 * i.e. O(1) with a large constant!
4761 if (n < READ_ONCE(iter->sg_idx))
4764 mutex_lock(&iter->lock);
4766 /* We prefer to reuse the last sg so that repeated lookup of this
4767 * (or the subsequent) sg are fast - comparing against the last
4768 * sg is faster than going through the radixtree.
4773 count = __sg_page_count(sg);
4775 while (idx + count <= n) {
4776 unsigned long exception, i;
4779 /* If we cannot allocate and insert this entry, or the
4780 * individual pages from this range, cancel updating the
4781 * sg_idx so that on this lookup we are forced to linearly
4782 * scan onwards, but on future lookups we will try the
4783 * insertion again (in which case we need to be careful of
4784 * the error return reporting that we have already inserted
4787 ret = radix_tree_insert(&iter->radix, idx, sg);
4788 if (ret && ret != -EEXIST)
4792 RADIX_TREE_EXCEPTIONAL_ENTRY |
4793 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
4794 for (i = 1; i < count; i++) {
4795 ret = radix_tree_insert(&iter->radix, idx + i,
4797 if (ret && ret != -EEXIST)
4802 sg = ____sg_next(sg);
4803 count = __sg_page_count(sg);
4810 mutex_unlock(&iter->lock);
4812 if (unlikely(n < idx)) /* insertion completed by another thread */
4815 /* In case we failed to insert the entry into the radixtree, we need
4816 * to look beyond the current sg.
4818 while (idx + count <= n) {
4820 sg = ____sg_next(sg);
4821 count = __sg_page_count(sg);
4830 sg = radix_tree_lookup(&iter->radix, n);
4833 /* If this index is in the middle of multi-page sg entry,
4834 * the radixtree will contain an exceptional entry that points
4835 * to the start of that range. We will return the pointer to
4836 * the base page and the offset of this page within the
4840 if (unlikely(radix_tree_exception(sg))) {
4841 unsigned long base =
4842 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
4844 sg = radix_tree_lookup(&iter->radix, base);
4856 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
4858 struct scatterlist *sg;
4859 unsigned int offset;
4861 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
4863 sg = i915_gem_object_get_sg(obj, n, &offset);
4864 return nth_page(sg_page(sg), offset);
4867 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
4869 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
4874 page = i915_gem_object_get_page(obj, n);
4876 set_page_dirty(page);
4882 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
4885 struct scatterlist *sg;
4886 unsigned int offset;
4888 sg = i915_gem_object_get_sg(obj, n, &offset);
4889 return sg_dma_address(sg) + (offset << PAGE_SHIFT);