2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <drm/drm_vma_manager.h>
29 #include <drm/i915_drm.h>
30 #include <linux/dma-fence-array.h>
31 #include <linux/kthread.h>
32 #include <linux/dma-resv.h>
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/stop_machine.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
39 #include <linux/mman.h>
41 #include "display/intel_display.h"
42 #include "display/intel_frontbuffer.h"
44 #include "gem/i915_gem_clflush.h"
45 #include "gem/i915_gem_context.h"
46 #include "gem/i915_gem_ioctls.h"
47 #include "gem/i915_gem_mman.h"
48 #include "gem/i915_gem_region.h"
49 #include "gt/intel_engine_user.h"
50 #include "gt/intel_gt.h"
51 #include "gt/intel_gt_pm.h"
52 #include "gt/intel_workarounds.h"
55 #include "i915_trace.h"
56 #include "i915_vgpu.h"
61 insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)
65 err = mutex_lock_interruptible(&ggtt->vm.mutex);
69 memset(node, 0, sizeof(*node));
70 err = drm_mm_insert_node_in_range(&ggtt->vm.mm, node,
71 size, 0, I915_COLOR_UNEVICTABLE,
72 0, ggtt->mappable_end,
75 mutex_unlock(&ggtt->vm.mutex);
81 remove_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node)
83 mutex_lock(&ggtt->vm.mutex);
84 drm_mm_remove_node(node);
85 mutex_unlock(&ggtt->vm.mutex);
89 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
90 struct drm_file *file)
92 struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
93 struct drm_i915_gem_get_aperture *args = data;
97 if (mutex_lock_interruptible(&ggtt->vm.mutex))
100 pinned = ggtt->vm.reserved;
101 list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link)
102 if (i915_vma_is_pinned(vma))
103 pinned += vma->node.size;
105 mutex_unlock(&ggtt->vm.mutex);
107 args->aper_size = ggtt->vm.total;
108 args->aper_available_size = args->aper_size - pinned;
113 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
116 struct intel_runtime_pm *rpm = &to_i915(obj->base.dev)->runtime_pm;
117 LIST_HEAD(still_in_list);
118 intel_wakeref_t wakeref;
119 struct i915_vma *vma;
122 if (!atomic_read(&obj->bind_count))
126 * As some machines use ACPI to handle runtime-resume callbacks, and
127 * ACPI is quite kmalloc happy, we cannot resume beneath the vm->mutex
128 * as they are required by the shrinker. Ergo, we wake the device up
129 * first just in case.
131 wakeref = intel_runtime_pm_get(rpm);
135 spin_lock(&obj->vma.lock);
136 while (!ret && (vma = list_first_entry_or_null(&obj->vma.list,
139 struct i915_address_space *vm = vma->vm;
141 list_move_tail(&vma->obj_link, &still_in_list);
142 if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
146 if (!i915_vm_tryopen(vm))
149 /* Prevent vma being freed by i915_vma_parked as we unbind */
150 vma = __i915_vma_get(vma);
151 spin_unlock(&obj->vma.lock);
155 if (flags & I915_GEM_OBJECT_UNBIND_ACTIVE ||
156 !i915_vma_is_active(vma))
157 ret = i915_vma_unbind(vma);
163 spin_lock(&obj->vma.lock);
165 list_splice_init(&still_in_list, &obj->vma.list);
166 spin_unlock(&obj->vma.lock);
168 if (ret == -EAGAIN && flags & I915_GEM_OBJECT_UNBIND_BARRIER) {
169 rcu_barrier(); /* flush the i915_vm_release() */
173 intel_runtime_pm_put(rpm, wakeref);
179 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
180 struct drm_i915_gem_pwrite *args,
181 struct drm_file *file)
183 void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
184 char __user *user_data = u64_to_user_ptr(args->data_ptr);
187 * We manually control the domain here and pretend that it
188 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
190 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
192 if (copy_from_user(vaddr, user_data, args->size))
195 drm_clflush_virt_range(vaddr, args->size);
196 intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
198 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
203 i915_gem_create(struct drm_file *file,
204 struct intel_memory_region *mr,
208 struct drm_i915_gem_object *obj;
213 GEM_BUG_ON(!is_power_of_2(mr->min_page_size));
214 size = round_up(*size_p, mr->min_page_size);
218 /* For most of the ABI (e.g. mmap) we think in system pages */
219 GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
221 /* Allocate the new object */
222 obj = i915_gem_object_create_region(mr, size, 0);
226 ret = drm_gem_handle_create(file, &obj->base, &handle);
227 /* drop reference from allocate - handle holds it now */
228 i915_gem_object_put(obj);
238 i915_gem_dumb_create(struct drm_file *file,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args)
242 enum intel_memory_type mem_type;
243 int cpp = DIV_ROUND_UP(args->bpp, 8);
248 format = DRM_FORMAT_C8;
251 format = DRM_FORMAT_RGB565;
254 format = DRM_FORMAT_XRGB8888;
260 /* have to work out size/pitch and return them */
261 args->pitch = ALIGN(args->width * cpp, 64);
263 /* align stride to page size so that we can remap */
264 if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
265 DRM_FORMAT_MOD_LINEAR))
266 args->pitch = ALIGN(args->pitch, 4096);
268 if (args->pitch < args->width)
271 args->size = mul_u32_u32(args->pitch, args->height);
273 mem_type = INTEL_MEMORY_SYSTEM;
274 if (HAS_LMEM(to_i915(dev)))
275 mem_type = INTEL_MEMORY_LOCAL;
277 return i915_gem_create(file,
278 intel_memory_region_by_type(to_i915(dev),
280 &args->size, &args->handle);
284 * Creates a new mm object and returns a handle to it.
285 * @dev: drm device pointer
286 * @data: ioctl data blob
287 * @file: drm file pointer
290 i915_gem_create_ioctl(struct drm_device *dev, void *data,
291 struct drm_file *file)
293 struct drm_i915_private *i915 = to_i915(dev);
294 struct drm_i915_gem_create *args = data;
296 i915_gem_flush_free_objects(i915);
298 return i915_gem_create(file,
299 intel_memory_region_by_type(i915,
300 INTEL_MEMORY_SYSTEM),
301 &args->size, &args->handle);
305 shmem_pread(struct page *page, int offset, int len, char __user *user_data,
314 drm_clflush_virt_range(vaddr + offset, len);
316 ret = __copy_to_user(user_data, vaddr + offset, len);
320 return ret ? -EFAULT : 0;
324 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
325 struct drm_i915_gem_pread *args)
327 unsigned int needs_clflush;
328 unsigned int idx, offset;
329 struct dma_fence *fence;
330 char __user *user_data;
334 ret = i915_gem_object_prepare_read(obj, &needs_clflush);
338 fence = i915_gem_object_lock_fence(obj);
339 i915_gem_object_finish_access(obj);
344 user_data = u64_to_user_ptr(args->data_ptr);
345 offset = offset_in_page(args->offset);
346 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
347 struct page *page = i915_gem_object_get_page(obj, idx);
348 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
350 ret = shmem_pread(page, offset, length, user_data,
360 i915_gem_object_unlock_fence(obj, fence);
365 gtt_user_read(struct io_mapping *mapping,
366 loff_t base, int offset,
367 char __user *user_data, int length)
370 unsigned long unwritten;
372 /* We can use the cpu mem copy function because this is X86. */
373 vaddr = io_mapping_map_atomic_wc(mapping, base);
374 unwritten = __copy_to_user_inatomic(user_data,
375 (void __force *)vaddr + offset,
377 io_mapping_unmap_atomic(vaddr);
379 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
380 unwritten = copy_to_user(user_data,
381 (void __force *)vaddr + offset,
383 io_mapping_unmap(vaddr);
389 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
390 const struct drm_i915_gem_pread *args)
392 struct drm_i915_private *i915 = to_i915(obj->base.dev);
393 struct i915_ggtt *ggtt = &i915->ggtt;
394 intel_wakeref_t wakeref;
395 struct drm_mm_node node;
396 struct dma_fence *fence;
397 void __user *user_data;
398 struct i915_vma *vma;
402 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
403 vma = ERR_PTR(-ENODEV);
404 if (!i915_gem_object_is_tiled(obj))
405 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
407 PIN_NONBLOCK /* NOWARN */ |
410 node.start = i915_ggtt_offset(vma);
413 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
416 GEM_BUG_ON(!drm_mm_node_allocated(&node));
419 ret = i915_gem_object_lock_interruptible(obj);
423 ret = i915_gem_object_set_to_gtt_domain(obj, false);
425 i915_gem_object_unlock(obj);
429 fence = i915_gem_object_lock_fence(obj);
430 i915_gem_object_unlock(obj);
436 user_data = u64_to_user_ptr(args->data_ptr);
438 offset = args->offset;
441 /* Operation in this page
443 * page_base = page offset within aperture
444 * page_offset = offset within page
445 * page_length = bytes to copy for this page
447 u32 page_base = node.start;
448 unsigned page_offset = offset_in_page(offset);
449 unsigned page_length = PAGE_SIZE - page_offset;
450 page_length = remain < page_length ? remain : page_length;
451 if (drm_mm_node_allocated(&node)) {
452 ggtt->vm.insert_page(&ggtt->vm,
453 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
454 node.start, I915_CACHE_NONE, 0);
456 page_base += offset & PAGE_MASK;
459 if (gtt_user_read(&ggtt->iomap, page_base, page_offset,
460 user_data, page_length)) {
465 remain -= page_length;
466 user_data += page_length;
467 offset += page_length;
470 i915_gem_object_unlock_fence(obj, fence);
472 if (drm_mm_node_allocated(&node)) {
473 ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
474 remove_mappable_node(ggtt, &node);
479 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
484 * Reads data from the object referenced by handle.
485 * @dev: drm device pointer
486 * @data: ioctl data blob
487 * @file: drm file pointer
489 * On error, the contents of *data are undefined.
492 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
493 struct drm_file *file)
495 struct drm_i915_gem_pread *args = data;
496 struct drm_i915_gem_object *obj;
502 if (!access_ok(u64_to_user_ptr(args->data_ptr),
506 obj = i915_gem_object_lookup(file, args->handle);
510 /* Bounds check source. */
511 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
516 trace_i915_gem_object_pread(obj, args->offset, args->size);
518 ret = i915_gem_object_wait(obj,
519 I915_WAIT_INTERRUPTIBLE,
520 MAX_SCHEDULE_TIMEOUT);
524 ret = i915_gem_object_pin_pages(obj);
528 ret = i915_gem_shmem_pread(obj, args);
529 if (ret == -EFAULT || ret == -ENODEV)
530 ret = i915_gem_gtt_pread(obj, args);
532 i915_gem_object_unpin_pages(obj);
534 i915_gem_object_put(obj);
538 /* This is the fast write path which cannot handle
539 * page faults in the source data
543 ggtt_write(struct io_mapping *mapping,
544 loff_t base, int offset,
545 char __user *user_data, int length)
548 unsigned long unwritten;
550 /* We can use the cpu mem copy function because this is X86. */
551 vaddr = io_mapping_map_atomic_wc(mapping, base);
552 unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
554 io_mapping_unmap_atomic(vaddr);
556 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
557 unwritten = copy_from_user((void __force *)vaddr + offset,
559 io_mapping_unmap(vaddr);
566 * This is the fast pwrite path, where we copy the data directly from the
567 * user into the GTT, uncached.
568 * @obj: i915 GEM object
569 * @args: pwrite arguments structure
572 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
573 const struct drm_i915_gem_pwrite *args)
575 struct drm_i915_private *i915 = to_i915(obj->base.dev);
576 struct i915_ggtt *ggtt = &i915->ggtt;
577 struct intel_runtime_pm *rpm = &i915->runtime_pm;
578 intel_wakeref_t wakeref;
579 struct drm_mm_node node;
580 struct dma_fence *fence;
581 struct i915_vma *vma;
583 void __user *user_data;
586 if (i915_gem_object_has_struct_page(obj)) {
588 * Avoid waking the device up if we can fallback, as
589 * waking/resuming is very slow (worst-case 10-100 ms
590 * depending on PCI sleeps and our own resume time).
591 * This easily dwarfs any performance advantage from
592 * using the cache bypass of indirect GGTT access.
594 wakeref = intel_runtime_pm_get_if_in_use(rpm);
598 /* No backing pages, no fallback, we must force GGTT access */
599 wakeref = intel_runtime_pm_get(rpm);
602 vma = ERR_PTR(-ENODEV);
603 if (!i915_gem_object_is_tiled(obj))
604 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
606 PIN_NONBLOCK /* NOWARN */ |
609 node.start = i915_ggtt_offset(vma);
612 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
615 GEM_BUG_ON(!drm_mm_node_allocated(&node));
618 ret = i915_gem_object_lock_interruptible(obj);
622 ret = i915_gem_object_set_to_gtt_domain(obj, true);
624 i915_gem_object_unlock(obj);
628 fence = i915_gem_object_lock_fence(obj);
629 i915_gem_object_unlock(obj);
635 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
637 user_data = u64_to_user_ptr(args->data_ptr);
638 offset = args->offset;
641 /* Operation in this page
643 * page_base = page offset within aperture
644 * page_offset = offset within page
645 * page_length = bytes to copy for this page
647 u32 page_base = node.start;
648 unsigned int page_offset = offset_in_page(offset);
649 unsigned int page_length = PAGE_SIZE - page_offset;
650 page_length = remain < page_length ? remain : page_length;
651 if (drm_mm_node_allocated(&node)) {
652 /* flush the write before we modify the GGTT */
653 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
654 ggtt->vm.insert_page(&ggtt->vm,
655 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
656 node.start, I915_CACHE_NONE, 0);
657 wmb(); /* flush modifications to the GGTT (insert_page) */
659 page_base += offset & PAGE_MASK;
661 /* If we get a fault while copying data, then (presumably) our
662 * source page isn't available. Return the error and we'll
663 * retry in the slow path.
664 * If the object is non-shmem backed, we retry again with the
665 * path that handles page fault.
667 if (ggtt_write(&ggtt->iomap, page_base, page_offset,
668 user_data, page_length)) {
673 remain -= page_length;
674 user_data += page_length;
675 offset += page_length;
678 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
679 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
681 i915_gem_object_unlock_fence(obj, fence);
683 if (drm_mm_node_allocated(&node)) {
684 ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
685 remove_mappable_node(ggtt, &node);
690 intel_runtime_pm_put(rpm, wakeref);
694 /* Per-page copy function for the shmem pwrite fastpath.
695 * Flushes invalid cachelines before writing to the target if
696 * needs_clflush_before is set and flushes out any written cachelines after
697 * writing if needs_clflush is set.
700 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
701 bool needs_clflush_before,
702 bool needs_clflush_after)
709 if (needs_clflush_before)
710 drm_clflush_virt_range(vaddr + offset, len);
712 ret = __copy_from_user(vaddr + offset, user_data, len);
713 if (!ret && needs_clflush_after)
714 drm_clflush_virt_range(vaddr + offset, len);
718 return ret ? -EFAULT : 0;
722 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
723 const struct drm_i915_gem_pwrite *args)
725 unsigned int partial_cacheline_write;
726 unsigned int needs_clflush;
727 unsigned int offset, idx;
728 struct dma_fence *fence;
729 void __user *user_data;
733 ret = i915_gem_object_prepare_write(obj, &needs_clflush);
737 fence = i915_gem_object_lock_fence(obj);
738 i915_gem_object_finish_access(obj);
742 /* If we don't overwrite a cacheline completely we need to be
743 * careful to have up-to-date data by first clflushing. Don't
744 * overcomplicate things and flush the entire patch.
746 partial_cacheline_write = 0;
747 if (needs_clflush & CLFLUSH_BEFORE)
748 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
750 user_data = u64_to_user_ptr(args->data_ptr);
752 offset = offset_in_page(args->offset);
753 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
754 struct page *page = i915_gem_object_get_page(obj, idx);
755 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
757 ret = shmem_pwrite(page, offset, length, user_data,
758 (offset | length) & partial_cacheline_write,
759 needs_clflush & CLFLUSH_AFTER);
768 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
769 i915_gem_object_unlock_fence(obj, fence);
775 * Writes data to the object referenced by handle.
777 * @data: ioctl data blob
780 * On error, the contents of the buffer that were to be modified are undefined.
783 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
784 struct drm_file *file)
786 struct drm_i915_gem_pwrite *args = data;
787 struct drm_i915_gem_object *obj;
793 if (!access_ok(u64_to_user_ptr(args->data_ptr), args->size))
796 obj = i915_gem_object_lookup(file, args->handle);
800 /* Bounds check destination. */
801 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
806 /* Writes not allowed into this read-only object */
807 if (i915_gem_object_is_readonly(obj)) {
812 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
815 if (obj->ops->pwrite)
816 ret = obj->ops->pwrite(obj, args);
820 ret = i915_gem_object_wait(obj,
821 I915_WAIT_INTERRUPTIBLE |
823 MAX_SCHEDULE_TIMEOUT);
827 ret = i915_gem_object_pin_pages(obj);
832 /* We can only do the GTT pwrite on untiled buffers, as otherwise
833 * it would end up going through the fenced access, and we'll get
834 * different detiling behavior between reading and writing.
835 * pread/pwrite currently are reading and writing from the CPU
836 * perspective, requiring manual detiling by the client.
838 if (!i915_gem_object_has_struct_page(obj) ||
839 cpu_write_needs_clflush(obj))
840 /* Note that the gtt paths might fail with non-page-backed user
841 * pointers (e.g. gtt mappings when moving data between
842 * textures). Fallback to the shmem path in that case.
844 ret = i915_gem_gtt_pwrite_fast(obj, args);
846 if (ret == -EFAULT || ret == -ENOSPC) {
847 if (i915_gem_object_has_struct_page(obj))
848 ret = i915_gem_shmem_pwrite(obj, args);
850 ret = i915_gem_phys_pwrite(obj, args, file);
853 i915_gem_object_unpin_pages(obj);
855 i915_gem_object_put(obj);
860 * Called when user space has done writes to this buffer
862 * @data: ioctl data blob
866 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
867 struct drm_file *file)
869 struct drm_i915_gem_sw_finish *args = data;
870 struct drm_i915_gem_object *obj;
872 obj = i915_gem_object_lookup(file, args->handle);
877 * Proxy objects are barred from CPU access, so there is no
878 * need to ban sw_finish as it is a nop.
881 /* Pinned buffers may be scanout, so flush the cache */
882 i915_gem_object_flush_if_display(obj);
883 i915_gem_object_put(obj);
888 void i915_gem_runtime_suspend(struct drm_i915_private *i915)
890 struct drm_i915_gem_object *obj, *on;
894 * Only called during RPM suspend. All users of the userfault_list
895 * must be holding an RPM wakeref to ensure that this can not
896 * run concurrently with themselves (and use the struct_mutex for
897 * protection between themselves).
900 list_for_each_entry_safe(obj, on,
901 &i915->ggtt.userfault_list, userfault_link)
902 __i915_gem_object_release_mmap_gtt(obj);
905 * The fence will be lost when the device powers down. If any were
906 * in use by hardware (i.e. they are pinned), we should not be powering
907 * down! All other fences will be reacquired by the user upon waking.
909 for (i = 0; i < i915->ggtt.num_fences; i++) {
910 struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
913 * Ideally we want to assert that the fence register is not
914 * live at this point (i.e. that no piece of code will be
915 * trying to write through fence + GTT, as that both violates
916 * our tracking of activity and associated locking/barriers,
917 * but also is illegal given that the hw is powered down).
919 * Previously we used reg->pin_count as a "liveness" indicator.
920 * That is not sufficient, and we need a more fine-grained
921 * tool if we want to have a sanity check here.
927 GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
933 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
934 const struct i915_ggtt_view *view,
939 struct drm_i915_private *i915 = to_i915(obj->base.dev);
940 struct i915_ggtt *ggtt = &i915->ggtt;
941 struct i915_vma *vma;
944 if (i915_gem_object_never_bind_ggtt(obj))
945 return ERR_PTR(-ENODEV);
947 if (flags & PIN_MAPPABLE &&
948 (!view || view->type == I915_GGTT_VIEW_NORMAL)) {
950 * If the required space is larger than the available
951 * aperture, we will not able to find a slot for the
952 * object and unbinding the object now will be in
953 * vain. Worse, doing so may cause us to ping-pong
954 * the object in and out of the Global GTT and
955 * waste a lot of cycles under the mutex.
957 if (obj->base.size > ggtt->mappable_end)
958 return ERR_PTR(-E2BIG);
961 * If NONBLOCK is set the caller is optimistically
962 * trying to cache the full object within the mappable
963 * aperture, and *must* have a fallback in place for
964 * situations where we cannot bind the object. We
965 * can be a little more lax here and use the fallback
966 * more often to avoid costly migrations of ourselves
967 * and other objects within the aperture.
969 * Half-the-aperture is used as a simple heuristic.
970 * More interesting would to do search for a free
971 * block prior to making the commitment to unbind.
972 * That caters for the self-harm case, and with a
973 * little more heuristics (e.g. NOFAULT, NOEVICT)
974 * we could try to minimise harm to others.
976 if (flags & PIN_NONBLOCK &&
977 obj->base.size > ggtt->mappable_end / 2)
978 return ERR_PTR(-ENOSPC);
981 vma = i915_vma_instance(obj, &ggtt->vm, view);
985 if (i915_vma_misplaced(vma, size, alignment, flags)) {
986 if (flags & PIN_NONBLOCK) {
987 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))
988 return ERR_PTR(-ENOSPC);
990 if (flags & PIN_MAPPABLE &&
991 vma->fence_size > ggtt->mappable_end / 2)
992 return ERR_PTR(-ENOSPC);
995 ret = i915_vma_unbind(vma);
1000 if (vma->fence && !i915_gem_object_is_tiled(obj)) {
1001 mutex_lock(&ggtt->vm.mutex);
1002 ret = i915_vma_revoke_fence(vma);
1003 mutex_unlock(&ggtt->vm.mutex);
1005 return ERR_PTR(ret);
1008 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
1010 return ERR_PTR(ret);
1016 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv)
1019 struct drm_i915_private *i915 = to_i915(dev);
1020 struct drm_i915_gem_madvise *args = data;
1021 struct drm_i915_gem_object *obj;
1024 switch (args->madv) {
1025 case I915_MADV_DONTNEED:
1026 case I915_MADV_WILLNEED:
1032 obj = i915_gem_object_lookup(file_priv, args->handle);
1036 err = mutex_lock_interruptible(&obj->mm.lock);
1040 if (i915_gem_object_has_pages(obj) &&
1041 i915_gem_object_is_tiled(obj) &&
1042 i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
1043 if (obj->mm.madv == I915_MADV_WILLNEED) {
1044 GEM_BUG_ON(!obj->mm.quirked);
1045 __i915_gem_object_unpin_pages(obj);
1046 obj->mm.quirked = false;
1048 if (args->madv == I915_MADV_WILLNEED) {
1049 GEM_BUG_ON(obj->mm.quirked);
1050 __i915_gem_object_pin_pages(obj);
1051 obj->mm.quirked = true;
1055 if (obj->mm.madv != __I915_MADV_PURGED)
1056 obj->mm.madv = args->madv;
1058 if (i915_gem_object_has_pages(obj)) {
1059 struct list_head *list;
1061 if (i915_gem_object_is_shrinkable(obj)) {
1062 unsigned long flags;
1064 spin_lock_irqsave(&i915->mm.obj_lock, flags);
1066 if (obj->mm.madv != I915_MADV_WILLNEED)
1067 list = &i915->mm.purge_list;
1069 list = &i915->mm.shrink_list;
1070 list_move_tail(&obj->mm.link, list);
1072 spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
1076 /* if the object is no longer attached, discard its backing storage */
1077 if (obj->mm.madv == I915_MADV_DONTNEED &&
1078 !i915_gem_object_has_pages(obj))
1079 i915_gem_object_truncate(obj);
1081 args->retained = obj->mm.madv != __I915_MADV_PURGED;
1082 mutex_unlock(&obj->mm.lock);
1085 i915_gem_object_put(obj);
1089 int i915_gem_init(struct drm_i915_private *dev_priv)
1093 /* We need to fallback to 4K pages if host doesn't support huge gtt. */
1094 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
1095 mkwrite_device_info(dev_priv)->page_sizes =
1096 I915_GTT_PAGE_SIZE_4K;
1098 ret = i915_gem_init_userptr(dev_priv);
1102 intel_uc_fetch_firmwares(&dev_priv->gt.uc);
1103 intel_wopcm_init(&dev_priv->wopcm);
1105 ret = i915_init_ggtt(dev_priv);
1107 GEM_BUG_ON(ret == -EIO);
1112 * Despite its name intel_init_clock_gating applies both display
1113 * clock gating workarounds; GT mmio workarounds and the occasional
1114 * GT power context workaround. Worse, sometimes it includes a context
1115 * register workaround which we need to apply before we record the
1116 * default HW state for all contexts.
1118 * FIXME: break up the workarounds and apply them at the right time!
1120 intel_init_clock_gating(dev_priv);
1122 ret = intel_gt_init(&dev_priv->gt);
1129 * Unwinding is complicated by that we want to handle -EIO to mean
1130 * disable GPU submission but keep KMS alive. We want to mark the
1131 * HW as irrevisibly wedged, but keep enough state around that the
1132 * driver doesn't explode during runtime.
1135 i915_gem_drain_workqueue(dev_priv);
1138 intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
1139 i915_gem_cleanup_userptr(dev_priv);
1144 * Allow engines or uC initialisation to fail by marking the GPU
1145 * as wedged. But we only want to do this when the GPU is angry,
1146 * for all other failure, such as an allocation failure, bail.
1148 if (!intel_gt_is_wedged(&dev_priv->gt)) {
1149 i915_probe_error(dev_priv,
1150 "Failed to initialize GPU, declaring it wedged!\n");
1151 intel_gt_set_wedged(&dev_priv->gt);
1154 /* Minimal basic recovery for KMS */
1155 ret = i915_ggtt_enable_hw(dev_priv);
1156 i915_gem_restore_gtt_mappings(dev_priv);
1157 i915_gem_restore_fences(&dev_priv->ggtt);
1158 intel_init_clock_gating(dev_priv);
1161 i915_gem_drain_freed_objects(dev_priv);
1165 void i915_gem_driver_register(struct drm_i915_private *i915)
1167 i915_gem_driver_register__shrinker(i915);
1169 intel_engines_driver_register(i915);
1172 void i915_gem_driver_unregister(struct drm_i915_private *i915)
1174 i915_gem_driver_unregister__shrinker(i915);
1177 void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
1179 intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
1181 i915_gem_suspend_late(dev_priv);
1182 intel_gt_driver_remove(&dev_priv->gt);
1183 dev_priv->uabi_engines = RB_ROOT;
1185 /* Flush any outstanding unpin_work. */
1186 i915_gem_drain_workqueue(dev_priv);
1188 i915_gem_drain_freed_objects(dev_priv);
1191 void i915_gem_driver_release(struct drm_i915_private *dev_priv)
1193 i915_gem_driver_release__contexts(dev_priv);
1195 intel_gt_driver_release(&dev_priv->gt);
1197 intel_wa_list_free(&dev_priv->gt_wa_list);
1199 intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
1200 i915_gem_cleanup_userptr(dev_priv);
1202 i915_gem_drain_freed_objects(dev_priv);
1204 WARN_ON(!list_empty(&dev_priv->gem.contexts.list));
1207 static void i915_gem_init__mm(struct drm_i915_private *i915)
1209 spin_lock_init(&i915->mm.obj_lock);
1211 init_llist_head(&i915->mm.free_list);
1213 INIT_LIST_HEAD(&i915->mm.purge_list);
1214 INIT_LIST_HEAD(&i915->mm.shrink_list);
1216 i915_gem_init__objects(i915);
1219 void i915_gem_init_early(struct drm_i915_private *dev_priv)
1221 i915_gem_init__mm(dev_priv);
1222 i915_gem_init__contexts(dev_priv);
1224 spin_lock_init(&dev_priv->fb_tracking.lock);
1227 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
1229 i915_gem_drain_freed_objects(dev_priv);
1230 GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));
1231 GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
1232 WARN_ON(dev_priv->mm.shrink_count);
1235 int i915_gem_freeze(struct drm_i915_private *dev_priv)
1237 /* Discard all purgeable objects, let userspace recover those as
1238 * required after resuming.
1240 i915_gem_shrink_all(dev_priv);
1245 int i915_gem_freeze_late(struct drm_i915_private *i915)
1247 struct drm_i915_gem_object *obj;
1248 intel_wakeref_t wakeref;
1251 * Called just before we write the hibernation image.
1253 * We need to update the domain tracking to reflect that the CPU
1254 * will be accessing all the pages to create and restore from the
1255 * hibernation, and so upon restoration those pages will be in the
1258 * To make sure the hibernation image contains the latest state,
1259 * we update that state just before writing out the image.
1261 * To try and reduce the hibernation image, we manually shrink
1262 * the objects as well, see i915_gem_freeze()
1265 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1267 i915_gem_shrink(i915, -1UL, NULL, ~0);
1268 i915_gem_drain_freed_objects(i915);
1270 list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) {
1271 i915_gem_object_lock(obj);
1272 WARN_ON(i915_gem_object_set_to_cpu_domain(obj, true));
1273 i915_gem_object_unlock(obj);
1276 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1281 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
1283 struct drm_i915_file_private *file_priv = file->driver_priv;
1284 struct i915_request *request;
1286 /* Clean up our request list when the client is going away, so that
1287 * later retire_requests won't dereference our soon-to-be-gone
1290 spin_lock(&file_priv->mm.lock);
1291 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
1292 request->file_priv = NULL;
1293 spin_unlock(&file_priv->mm.lock);
1296 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
1298 struct drm_i915_file_private *file_priv;
1303 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1307 file->driver_priv = file_priv;
1308 file_priv->dev_priv = i915;
1309 file_priv->file = file;
1311 spin_lock_init(&file_priv->mm.lock);
1312 INIT_LIST_HEAD(&file_priv->mm.request_list);
1314 file_priv->bsd_engine = -1;
1315 file_priv->hang_timestamp = jiffies;
1317 ret = i915_gem_context_open(i915, file);
1324 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1325 #include "selftests/mock_gem_device.c"
1326 #include "selftests/i915_gem.c"