2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
159 return i915_gem_obj_bound_any(obj) && !obj->active;
163 i915_gem_init_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_init *args = data;
169 if (drm_core_check_feature(dev, DRIVER_MODESET))
172 if (args->gtt_start >= args->gtt_end ||
173 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
176 /* GEM with user mode setting was never supported on ilk and later. */
177 if (INTEL_INFO(dev)->gen >= 5)
180 mutex_lock(&dev->struct_mutex);
181 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
183 dev_priv->gtt.mappable_end = args->gtt_end;
184 mutex_unlock(&dev->struct_mutex);
190 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
191 struct drm_file *file)
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 struct drm_i915_gem_get_aperture *args = data;
195 struct drm_i915_gem_object *obj;
199 mutex_lock(&dev->struct_mutex);
200 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
201 if (i915_gem_obj_is_pinned(obj))
202 pinned += i915_gem_obj_ggtt_size(obj);
203 mutex_unlock(&dev->struct_mutex);
205 args->aper_size = dev_priv->gtt.base.total;
206 args->aper_available_size = args->aper_size - pinned;
211 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
213 drm_dma_handle_t *phys = obj->phys_handle;
218 if (obj->madv == I915_MADV_WILLNEED) {
219 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
220 char *vaddr = phys->vaddr;
223 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
224 struct page *page = shmem_read_mapping_page(mapping, i);
226 char *dst = kmap_atomic(page);
227 memcpy(dst, vaddr, PAGE_SIZE);
228 drm_clflush_virt_range(dst, PAGE_SIZE);
231 set_page_dirty(page);
232 mark_page_accessed(page);
233 page_cache_release(page);
237 i915_gem_chipset_flush(obj->base.dev);
241 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
243 drm_pci_free(obj->base.dev, phys);
244 obj->phys_handle = NULL;
248 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
251 drm_dma_handle_t *phys;
252 struct address_space *mapping;
256 if (obj->phys_handle) {
257 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
263 if (obj->madv != I915_MADV_WILLNEED)
266 if (obj->base.filp == NULL)
269 /* create a new object */
270 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
276 set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
278 mapping = file_inode(obj->base.filp)->i_mapping;
279 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
283 page = shmem_read_mapping_page(mapping, i);
286 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
288 drm_pci_free(obj->base.dev, phys);
289 return PTR_ERR(page);
292 src = kmap_atomic(page);
293 memcpy(vaddr, src, PAGE_SIZE);
296 mark_page_accessed(page);
297 page_cache_release(page);
302 obj->phys_handle = phys;
307 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
308 struct drm_i915_gem_pwrite *args,
309 struct drm_file *file_priv)
311 struct drm_device *dev = obj->base.dev;
312 void *vaddr = obj->phys_handle->vaddr + args->offset;
313 char __user *user_data = to_user_ptr(args->data_ptr);
315 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
316 unsigned long unwritten;
318 /* The physical object once assigned is fixed for the lifetime
319 * of the obj, so we can safely drop the lock and continue
322 mutex_unlock(&dev->struct_mutex);
323 unwritten = copy_from_user(vaddr, user_data, args->size);
324 mutex_lock(&dev->struct_mutex);
329 i915_gem_chipset_flush(dev);
333 void *i915_gem_object_alloc(struct drm_device *dev)
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
339 void i915_gem_object_free(struct drm_i915_gem_object *obj)
341 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
342 kmem_cache_free(dev_priv->slab, obj);
346 i915_gem_create(struct drm_file *file,
347 struct drm_device *dev,
351 struct drm_i915_gem_object *obj;
355 size = roundup(size, PAGE_SIZE);
359 /* Allocate the new object */
360 obj = i915_gem_alloc_object(dev, size);
364 ret = drm_gem_handle_create(file, &obj->base, &handle);
365 /* drop reference from allocate - handle holds it now */
366 drm_gem_object_unreference_unlocked(&obj->base);
375 i915_gem_dumb_create(struct drm_file *file,
376 struct drm_device *dev,
377 struct drm_mode_create_dumb *args)
379 /* have to work out size/pitch and return them */
380 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
381 args->size = args->pitch * args->height;
382 return i915_gem_create(file, dev,
383 args->size, &args->handle);
387 * Creates a new mm object and returns a handle to it.
390 i915_gem_create_ioctl(struct drm_device *dev, void *data,
391 struct drm_file *file)
393 struct drm_i915_gem_create *args = data;
395 return i915_gem_create(file, dev,
396 args->size, &args->handle);
400 __copy_to_user_swizzled(char __user *cpu_vaddr,
401 const char *gpu_vaddr, int gpu_offset,
404 int ret, cpu_offset = 0;
407 int cacheline_end = ALIGN(gpu_offset + 1, 64);
408 int this_length = min(cacheline_end - gpu_offset, length);
409 int swizzled_gpu_offset = gpu_offset ^ 64;
411 ret = __copy_to_user(cpu_vaddr + cpu_offset,
412 gpu_vaddr + swizzled_gpu_offset,
417 cpu_offset += this_length;
418 gpu_offset += this_length;
419 length -= this_length;
426 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
427 const char __user *cpu_vaddr,
430 int ret, cpu_offset = 0;
433 int cacheline_end = ALIGN(gpu_offset + 1, 64);
434 int this_length = min(cacheline_end - gpu_offset, length);
435 int swizzled_gpu_offset = gpu_offset ^ 64;
437 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
438 cpu_vaddr + cpu_offset,
443 cpu_offset += this_length;
444 gpu_offset += this_length;
445 length -= this_length;
452 * Pins the specified object's pages and synchronizes the object with
453 * GPU accesses. Sets needs_clflush to non-zero if the caller should
454 * flush the object from the CPU cache.
456 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
466 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
467 /* If we're not in the cpu read domain, set ourself into the gtt
468 * read domain and manually flush cachelines (if required). This
469 * optimizes for the case when the gpu will dirty the data
470 * anyway again before the next pread happens. */
471 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
473 ret = i915_gem_object_wait_rendering(obj, true);
477 i915_gem_object_retire(obj);
480 ret = i915_gem_object_get_pages(obj);
484 i915_gem_object_pin_pages(obj);
489 /* Per-page copy function for the shmem pread fastpath.
490 * Flushes invalid cachelines before reading the target if
491 * needs_clflush is set. */
493 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
494 char __user *user_data,
495 bool page_do_bit17_swizzling, bool needs_clflush)
500 if (unlikely(page_do_bit17_swizzling))
503 vaddr = kmap_atomic(page);
505 drm_clflush_virt_range(vaddr + shmem_page_offset,
507 ret = __copy_to_user_inatomic(user_data,
508 vaddr + shmem_page_offset,
510 kunmap_atomic(vaddr);
512 return ret ? -EFAULT : 0;
516 shmem_clflush_swizzled_range(char *addr, unsigned long length,
519 if (unlikely(swizzled)) {
520 unsigned long start = (unsigned long) addr;
521 unsigned long end = (unsigned long) addr + length;
523 /* For swizzling simply ensure that we always flush both
524 * channels. Lame, but simple and it works. Swizzled
525 * pwrite/pread is far from a hotpath - current userspace
526 * doesn't use it at all. */
527 start = round_down(start, 128);
528 end = round_up(end, 128);
530 drm_clflush_virt_range((void *)start, end - start);
532 drm_clflush_virt_range(addr, length);
537 /* Only difference to the fast-path function is that this can handle bit17
538 * and uses non-atomic copy and kmap functions. */
540 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
541 char __user *user_data,
542 bool page_do_bit17_swizzling, bool needs_clflush)
549 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
551 page_do_bit17_swizzling);
553 if (page_do_bit17_swizzling)
554 ret = __copy_to_user_swizzled(user_data,
555 vaddr, shmem_page_offset,
558 ret = __copy_to_user(user_data,
559 vaddr + shmem_page_offset,
563 return ret ? - EFAULT : 0;
567 i915_gem_shmem_pread(struct drm_device *dev,
568 struct drm_i915_gem_object *obj,
569 struct drm_i915_gem_pread *args,
570 struct drm_file *file)
572 char __user *user_data;
575 int shmem_page_offset, page_length, ret = 0;
576 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
578 int needs_clflush = 0;
579 struct sg_page_iter sg_iter;
581 user_data = to_user_ptr(args->data_ptr);
584 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
586 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
590 offset = args->offset;
592 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
593 offset >> PAGE_SHIFT) {
594 struct page *page = sg_page_iter_page(&sg_iter);
599 /* Operation in this page
601 * shmem_page_offset = offset within page in shmem file
602 * page_length = bytes to copy for this page
604 shmem_page_offset = offset_in_page(offset);
605 page_length = remain;
606 if ((shmem_page_offset + page_length) > PAGE_SIZE)
607 page_length = PAGE_SIZE - shmem_page_offset;
609 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
610 (page_to_phys(page) & (1 << 17)) != 0;
612 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
613 user_data, page_do_bit17_swizzling,
618 mutex_unlock(&dev->struct_mutex);
620 if (likely(!i915.prefault_disable) && !prefaulted) {
621 ret = fault_in_multipages_writeable(user_data, remain);
622 /* Userspace is tricking us, but we've already clobbered
623 * its pages with the prefault and promised to write the
624 * data up to the first fault. Hence ignore any errors
625 * and just continue. */
630 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
631 user_data, page_do_bit17_swizzling,
634 mutex_lock(&dev->struct_mutex);
640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
646 i915_gem_object_unpin_pages(obj);
652 * Reads data from the object referenced by handle.
654 * On error, the contents of *data are undefined.
657 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *file)
660 struct drm_i915_gem_pread *args = data;
661 struct drm_i915_gem_object *obj;
667 if (!access_ok(VERIFY_WRITE,
668 to_user_ptr(args->data_ptr),
672 ret = i915_mutex_lock_interruptible(dev);
676 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
677 if (&obj->base == NULL) {
682 /* Bounds check source. */
683 if (args->offset > obj->base.size ||
684 args->size > obj->base.size - args->offset) {
689 /* prime objects have no backing filp to GEM pread/pwrite
692 if (!obj->base.filp) {
697 trace_i915_gem_object_pread(obj, args->offset, args->size);
699 ret = i915_gem_shmem_pread(dev, obj, args, file);
702 drm_gem_object_unreference(&obj->base);
704 mutex_unlock(&dev->struct_mutex);
708 /* This is the fast write path which cannot handle
709 * page faults in the source data
713 fast_user_write(struct io_mapping *mapping,
714 loff_t page_base, int page_offset,
715 char __user *user_data,
718 void __iomem *vaddr_atomic;
720 unsigned long unwritten;
722 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
723 /* We can use the cpu mem copy function because this is X86. */
724 vaddr = (void __force*)vaddr_atomic + page_offset;
725 unwritten = __copy_from_user_inatomic_nocache(vaddr,
727 io_mapping_unmap_atomic(vaddr_atomic);
732 * This is the fast pwrite path, where we copy the data directly from the
733 * user into the GTT, uncached.
736 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
737 struct drm_i915_gem_object *obj,
738 struct drm_i915_gem_pwrite *args,
739 struct drm_file *file)
741 struct drm_i915_private *dev_priv = dev->dev_private;
743 loff_t offset, page_base;
744 char __user *user_data;
745 int page_offset, page_length, ret;
747 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
751 ret = i915_gem_object_set_to_gtt_domain(obj, true);
755 ret = i915_gem_object_put_fence(obj);
759 user_data = to_user_ptr(args->data_ptr);
762 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
765 /* Operation in this page
767 * page_base = page offset within aperture
768 * page_offset = offset within page
769 * page_length = bytes to copy for this page
771 page_base = offset & PAGE_MASK;
772 page_offset = offset_in_page(offset);
773 page_length = remain;
774 if ((page_offset + remain) > PAGE_SIZE)
775 page_length = PAGE_SIZE - page_offset;
777 /* If we get a fault while copying data, then (presumably) our
778 * source page isn't available. Return the error and we'll
779 * retry in the slow path.
781 if (fast_user_write(dev_priv->gtt.mappable, page_base,
782 page_offset, user_data, page_length)) {
787 remain -= page_length;
788 user_data += page_length;
789 offset += page_length;
793 i915_gem_object_ggtt_unpin(obj);
798 /* Per-page copy function for the shmem pwrite fastpath.
799 * Flushes invalid cachelines before writing to the target if
800 * needs_clflush_before is set and flushes out any written cachelines after
801 * writing if needs_clflush is set. */
803 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
804 char __user *user_data,
805 bool page_do_bit17_swizzling,
806 bool needs_clflush_before,
807 bool needs_clflush_after)
812 if (unlikely(page_do_bit17_swizzling))
815 vaddr = kmap_atomic(page);
816 if (needs_clflush_before)
817 drm_clflush_virt_range(vaddr + shmem_page_offset,
819 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
820 user_data, page_length);
821 if (needs_clflush_after)
822 drm_clflush_virt_range(vaddr + shmem_page_offset,
824 kunmap_atomic(vaddr);
826 return ret ? -EFAULT : 0;
829 /* Only difference to the fast-path function is that this can handle bit17
830 * and uses non-atomic copy and kmap functions. */
832 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
833 char __user *user_data,
834 bool page_do_bit17_swizzling,
835 bool needs_clflush_before,
836 bool needs_clflush_after)
842 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
843 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
845 page_do_bit17_swizzling);
846 if (page_do_bit17_swizzling)
847 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
851 ret = __copy_from_user(vaddr + shmem_page_offset,
854 if (needs_clflush_after)
855 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
857 page_do_bit17_swizzling);
860 return ret ? -EFAULT : 0;
864 i915_gem_shmem_pwrite(struct drm_device *dev,
865 struct drm_i915_gem_object *obj,
866 struct drm_i915_gem_pwrite *args,
867 struct drm_file *file)
871 char __user *user_data;
872 int shmem_page_offset, page_length, ret = 0;
873 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
874 int hit_slowpath = 0;
875 int needs_clflush_after = 0;
876 int needs_clflush_before = 0;
877 struct sg_page_iter sg_iter;
879 user_data = to_user_ptr(args->data_ptr);
882 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
884 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
885 /* If we're not in the cpu write domain, set ourself into the gtt
886 * write domain and manually flush cachelines (if required). This
887 * optimizes for the case when the gpu will use the data
888 * right away and we therefore have to clflush anyway. */
889 needs_clflush_after = cpu_write_needs_clflush(obj);
890 ret = i915_gem_object_wait_rendering(obj, false);
894 i915_gem_object_retire(obj);
896 /* Same trick applies to invalidate partially written cachelines read
898 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
899 needs_clflush_before =
900 !cpu_cache_is_coherent(dev, obj->cache_level);
902 ret = i915_gem_object_get_pages(obj);
906 i915_gem_object_pin_pages(obj);
908 offset = args->offset;
911 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
912 offset >> PAGE_SHIFT) {
913 struct page *page = sg_page_iter_page(&sg_iter);
914 int partial_cacheline_write;
919 /* Operation in this page
921 * shmem_page_offset = offset within page in shmem file
922 * page_length = bytes to copy for this page
924 shmem_page_offset = offset_in_page(offset);
926 page_length = remain;
927 if ((shmem_page_offset + page_length) > PAGE_SIZE)
928 page_length = PAGE_SIZE - shmem_page_offset;
930 /* If we don't overwrite a cacheline completely we need to be
931 * careful to have up-to-date data by first clflushing. Don't
932 * overcomplicate things and flush the entire patch. */
933 partial_cacheline_write = needs_clflush_before &&
934 ((shmem_page_offset | page_length)
935 & (boot_cpu_data.x86_clflush_size - 1));
937 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
938 (page_to_phys(page) & (1 << 17)) != 0;
940 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
941 user_data, page_do_bit17_swizzling,
942 partial_cacheline_write,
943 needs_clflush_after);
948 mutex_unlock(&dev->struct_mutex);
949 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
950 user_data, page_do_bit17_swizzling,
951 partial_cacheline_write,
952 needs_clflush_after);
954 mutex_lock(&dev->struct_mutex);
960 remain -= page_length;
961 user_data += page_length;
962 offset += page_length;
966 i915_gem_object_unpin_pages(obj);
970 * Fixup: Flush cpu caches in case we didn't flush the dirty
971 * cachelines in-line while writing and the object moved
972 * out of the cpu write domain while we've dropped the lock.
974 if (!needs_clflush_after &&
975 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
976 if (i915_gem_clflush_object(obj, obj->pin_display))
977 i915_gem_chipset_flush(dev);
981 if (needs_clflush_after)
982 i915_gem_chipset_flush(dev);
988 * Writes data to the object referenced by handle.
990 * On error, the contents of the buffer that were to be modified are undefined.
993 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
994 struct drm_file *file)
996 struct drm_i915_gem_pwrite *args = data;
997 struct drm_i915_gem_object *obj;
1000 if (args->size == 0)
1003 if (!access_ok(VERIFY_READ,
1004 to_user_ptr(args->data_ptr),
1008 if (likely(!i915.prefault_disable)) {
1009 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1015 ret = i915_mutex_lock_interruptible(dev);
1019 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1020 if (&obj->base == NULL) {
1025 /* Bounds check destination. */
1026 if (args->offset > obj->base.size ||
1027 args->size > obj->base.size - args->offset) {
1032 /* prime objects have no backing filp to GEM pread/pwrite
1035 if (!obj->base.filp) {
1040 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1043 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1044 * it would end up going through the fenced access, and we'll get
1045 * different detiling behavior between reading and writing.
1046 * pread/pwrite currently are reading and writing from the CPU
1047 * perspective, requiring manual detiling by the client.
1049 if (obj->phys_handle) {
1050 ret = i915_gem_phys_pwrite(obj, args, file);
1054 if (obj->tiling_mode == I915_TILING_NONE &&
1055 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1056 cpu_write_needs_clflush(obj)) {
1057 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1058 /* Note that the gtt paths might fail with non-page-backed user
1059 * pointers (e.g. gtt mappings when moving data between
1060 * textures). Fallback to the shmem path in that case. */
1063 if (ret == -EFAULT || ret == -ENOSPC)
1064 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1067 drm_gem_object_unreference(&obj->base);
1069 mutex_unlock(&dev->struct_mutex);
1074 i915_gem_check_wedge(struct i915_gpu_error *error,
1077 if (i915_reset_in_progress(error)) {
1078 /* Non-interruptible callers can't handle -EAGAIN, hence return
1079 * -EIO unconditionally for these. */
1083 /* Recovery complete, but the reset failed ... */
1084 if (i915_terminally_wedged(error))
1088 * Check if GPU Reset is in progress - we need intel_ring_begin
1089 * to work properly to reinit the hw state while the gpu is
1090 * still marked as reset-in-progress. Handle this with a flag.
1092 if (!error->reload_in_reset)
1100 * Compare seqno against outstanding lazy request. Emit a request if they are
1104 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1108 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1111 if (seqno == ring->outstanding_lazy_seqno)
1112 ret = i915_add_request(ring, NULL);
1117 static void fake_irq(unsigned long data)
1119 wake_up_process((struct task_struct *)data);
1122 static bool missed_irq(struct drm_i915_private *dev_priv,
1123 struct intel_engine_cs *ring)
1125 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1128 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1130 if (file_priv == NULL)
1133 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1137 * __i915_wait_seqno - wait until execution of seqno has finished
1138 * @ring: the ring expected to report seqno
1140 * @reset_counter: reset sequence associated with the given seqno
1141 * @interruptible: do an interruptible wait (normally yes)
1142 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1144 * Note: It is of utmost importance that the passed in seqno and reset_counter
1145 * values have been read by the caller in an smp safe manner. Where read-side
1146 * locks are involved, it is sufficient to read the reset_counter before
1147 * unlocking the lock that protects the seqno. For lockless tricks, the
1148 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1151 * Returns 0 if the seqno was found within the alloted time. Else returns the
1152 * errno with remaining time filled in timeout argument.
1154 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1155 unsigned reset_counter,
1158 struct drm_i915_file_private *file_priv)
1160 struct drm_device *dev = ring->dev;
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 const bool irq_test_in_progress =
1163 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1165 unsigned long timeout_expire;
1169 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1171 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1174 timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1176 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1177 gen6_rps_boost(dev_priv);
1179 mod_delayed_work(dev_priv->wq,
1180 &file_priv->mm.idle_work,
1181 msecs_to_jiffies(100));
1184 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1187 /* Record current time in case interrupted by signal, or wedged */
1188 trace_i915_gem_request_wait_begin(ring, seqno);
1189 before = ktime_get_raw_ns();
1191 struct timer_list timer;
1193 prepare_to_wait(&ring->irq_queue, &wait,
1194 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1196 /* We need to check whether any gpu reset happened in between
1197 * the caller grabbing the seqno and now ... */
1198 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1199 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1200 * is truely gone. */
1201 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1207 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1212 if (interruptible && signal_pending(current)) {
1217 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1222 timer.function = NULL;
1223 if (timeout || missed_irq(dev_priv, ring)) {
1224 unsigned long expire;
1226 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1227 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1228 mod_timer(&timer, expire);
1233 if (timer.function) {
1234 del_singleshot_timer_sync(&timer);
1235 destroy_timer_on_stack(&timer);
1238 now = ktime_get_raw_ns();
1239 trace_i915_gem_request_wait_end(ring, seqno);
1241 if (!irq_test_in_progress)
1242 ring->irq_put(ring);
1244 finish_wait(&ring->irq_queue, &wait);
1247 s64 tres = *timeout - (now - before);
1249 *timeout = tres < 0 ? 0 : tres;
1256 * Waits for a sequence number to be signaled, and cleans up the
1257 * request and object lists appropriately for that event.
1260 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1262 struct drm_device *dev = ring->dev;
1263 struct drm_i915_private *dev_priv = dev->dev_private;
1264 bool interruptible = dev_priv->mm.interruptible;
1265 unsigned reset_counter;
1268 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1271 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1275 ret = i915_gem_check_olr(ring, seqno);
1279 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1280 return __i915_wait_seqno(ring, seqno, reset_counter, interruptible,
1285 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1290 /* Manually manage the write flush as we may have not yet
1291 * retired the buffer.
1293 * Note that the last_write_seqno is always the earlier of
1294 * the two (read/write) seqno, so if we haved successfully waited,
1295 * we know we have passed the last write.
1297 obj->last_write_seqno = 0;
1303 * Ensures that all rendering to the object has completed and the object is
1304 * safe to unbind from the GTT or access from the CPU.
1306 static __must_check int
1307 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1310 struct intel_engine_cs *ring = obj->ring;
1314 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1318 ret = i915_wait_seqno(ring, seqno);
1322 return i915_gem_object_wait_rendering__tail(obj);
1325 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1326 * as the object state may change during this call.
1328 static __must_check int
1329 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1330 struct drm_i915_file_private *file_priv,
1333 struct drm_device *dev = obj->base.dev;
1334 struct drm_i915_private *dev_priv = dev->dev_private;
1335 struct intel_engine_cs *ring = obj->ring;
1336 unsigned reset_counter;
1340 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1341 BUG_ON(!dev_priv->mm.interruptible);
1343 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1347 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1351 ret = i915_gem_check_olr(ring, seqno);
1355 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1356 mutex_unlock(&dev->struct_mutex);
1357 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL,
1359 mutex_lock(&dev->struct_mutex);
1363 return i915_gem_object_wait_rendering__tail(obj);
1367 * Called when user space prepares to use an object with the CPU, either
1368 * through the mmap ioctl's mapping or a GTT mapping.
1371 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1372 struct drm_file *file)
1374 struct drm_i915_gem_set_domain *args = data;
1375 struct drm_i915_gem_object *obj;
1376 uint32_t read_domains = args->read_domains;
1377 uint32_t write_domain = args->write_domain;
1380 /* Only handle setting domains to types used by the CPU. */
1381 if (write_domain & I915_GEM_GPU_DOMAINS)
1384 if (read_domains & I915_GEM_GPU_DOMAINS)
1387 /* Having something in the write domain implies it's in the read
1388 * domain, and only that read domain. Enforce that in the request.
1390 if (write_domain != 0 && read_domains != write_domain)
1393 ret = i915_mutex_lock_interruptible(dev);
1397 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1398 if (&obj->base == NULL) {
1403 /* Try to flush the object off the GPU without holding the lock.
1404 * We will repeat the flush holding the lock in the normal manner
1405 * to catch cases where we are gazumped.
1407 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1413 if (read_domains & I915_GEM_DOMAIN_GTT) {
1414 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1416 /* Silently promote "you're not bound, there was nothing to do"
1417 * to success, since the client was just asking us to
1418 * make sure everything was done.
1423 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1427 drm_gem_object_unreference(&obj->base);
1429 mutex_unlock(&dev->struct_mutex);
1434 * Called when user space has done writes to this buffer
1437 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1438 struct drm_file *file)
1440 struct drm_i915_gem_sw_finish *args = data;
1441 struct drm_i915_gem_object *obj;
1444 ret = i915_mutex_lock_interruptible(dev);
1448 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1449 if (&obj->base == NULL) {
1454 /* Pinned buffers may be scanout, so flush the cache */
1455 if (obj->pin_display)
1456 i915_gem_object_flush_cpu_write_domain(obj, true);
1458 drm_gem_object_unreference(&obj->base);
1460 mutex_unlock(&dev->struct_mutex);
1465 * Maps the contents of an object, returning the address it is mapped
1468 * While the mapping holds a reference on the contents of the object, it doesn't
1469 * imply a ref on the object itself.
1473 * DRM driver writers who look a this function as an example for how to do GEM
1474 * mmap support, please don't implement mmap support like here. The modern way
1475 * to implement DRM mmap support is with an mmap offset ioctl (like
1476 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1477 * That way debug tooling like valgrind will understand what's going on, hiding
1478 * the mmap call in a driver private ioctl will break that. The i915 driver only
1479 * does cpu mmaps this way because we didn't know better.
1482 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1483 struct drm_file *file)
1485 struct drm_i915_gem_mmap *args = data;
1486 struct drm_gem_object *obj;
1489 obj = drm_gem_object_lookup(dev, file, args->handle);
1493 /* prime objects have no backing filp to GEM mmap
1497 drm_gem_object_unreference_unlocked(obj);
1501 addr = vm_mmap(obj->filp, 0, args->size,
1502 PROT_READ | PROT_WRITE, MAP_SHARED,
1504 drm_gem_object_unreference_unlocked(obj);
1505 if (IS_ERR((void *)addr))
1508 args->addr_ptr = (uint64_t) addr;
1514 * i915_gem_fault - fault a page into the GTT
1515 * vma: VMA in question
1518 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1519 * from userspace. The fault handler takes care of binding the object to
1520 * the GTT (if needed), allocating and programming a fence register (again,
1521 * only if needed based on whether the old reg is still valid or the object
1522 * is tiled) and inserting a new PTE into the faulting process.
1524 * Note that the faulting process may involve evicting existing objects
1525 * from the GTT and/or fence registers to make room. So performance may
1526 * suffer if the GTT working set is large or there are few fence registers
1529 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1531 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1532 struct drm_device *dev = obj->base.dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 pgoff_t page_offset;
1537 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1539 intel_runtime_pm_get(dev_priv);
1541 /* We don't use vmf->pgoff since that has the fake offset */
1542 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1545 ret = i915_mutex_lock_interruptible(dev);
1549 trace_i915_gem_object_fault(obj, page_offset, true, write);
1551 /* Try to flush the object off the GPU first without holding the lock.
1552 * Upon reacquiring the lock, we will perform our sanity checks and then
1553 * repeat the flush holding the lock in the normal manner to catch cases
1554 * where we are gazumped.
1556 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1560 /* Access to snoopable pages through the GTT is incoherent. */
1561 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1566 /* Now bind it into the GTT if needed */
1567 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1571 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1575 ret = i915_gem_object_get_fence(obj);
1579 /* Finally, remap it using the new GTT offset */
1580 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1583 if (!obj->fault_mappable) {
1584 unsigned long size = min_t(unsigned long,
1585 vma->vm_end - vma->vm_start,
1589 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1590 ret = vm_insert_pfn(vma,
1591 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1597 obj->fault_mappable = true;
1599 ret = vm_insert_pfn(vma,
1600 (unsigned long)vmf->virtual_address,
1603 i915_gem_object_ggtt_unpin(obj);
1605 mutex_unlock(&dev->struct_mutex);
1610 * We eat errors when the gpu is terminally wedged to avoid
1611 * userspace unduly crashing (gl has no provisions for mmaps to
1612 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1613 * and so needs to be reported.
1615 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1616 ret = VM_FAULT_SIGBUS;
1621 * EAGAIN means the gpu is hung and we'll wait for the error
1622 * handler to reset everything when re-faulting in
1623 * i915_mutex_lock_interruptible.
1630 * EBUSY is ok: this just means that another thread
1631 * already did the job.
1633 ret = VM_FAULT_NOPAGE;
1640 ret = VM_FAULT_SIGBUS;
1643 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1644 ret = VM_FAULT_SIGBUS;
1648 intel_runtime_pm_put(dev_priv);
1653 * i915_gem_release_mmap - remove physical page mappings
1654 * @obj: obj in question
1656 * Preserve the reservation of the mmapping with the DRM core code, but
1657 * relinquish ownership of the pages back to the system.
1659 * It is vital that we remove the page mapping if we have mapped a tiled
1660 * object through the GTT and then lose the fence register due to
1661 * resource pressure. Similarly if the object has been moved out of the
1662 * aperture, than pages mapped into userspace must be revoked. Removing the
1663 * mapping will then trigger a page fault on the next user access, allowing
1664 * fixup by i915_gem_fault().
1667 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1669 if (!obj->fault_mappable)
1672 drm_vma_node_unmap(&obj->base.vma_node,
1673 obj->base.dev->anon_inode->i_mapping);
1674 obj->fault_mappable = false;
1678 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1680 struct drm_i915_gem_object *obj;
1682 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1683 i915_gem_release_mmap(obj);
1687 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1691 if (INTEL_INFO(dev)->gen >= 4 ||
1692 tiling_mode == I915_TILING_NONE)
1695 /* Previous chips need a power-of-two fence region when tiling */
1696 if (INTEL_INFO(dev)->gen == 3)
1697 gtt_size = 1024*1024;
1699 gtt_size = 512*1024;
1701 while (gtt_size < size)
1708 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1709 * @obj: object to check
1711 * Return the required GTT alignment for an object, taking into account
1712 * potential fence register mapping.
1715 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1716 int tiling_mode, bool fenced)
1719 * Minimum alignment is 4k (GTT page size), but might be greater
1720 * if a fence register is needed for the object.
1722 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1723 tiling_mode == I915_TILING_NONE)
1727 * Previous chips need to be aligned to the size of the smallest
1728 * fence register that can contain the object.
1730 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1733 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1735 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1738 if (drm_vma_node_has_offset(&obj->base.vma_node))
1741 dev_priv->mm.shrinker_no_lock_stealing = true;
1743 ret = drm_gem_create_mmap_offset(&obj->base);
1747 /* Badly fragmented mmap space? The only way we can recover
1748 * space is by destroying unwanted objects. We can't randomly release
1749 * mmap_offsets as userspace expects them to be persistent for the
1750 * lifetime of the objects. The closest we can is to release the
1751 * offsets on purgeable objects by truncating it and marking it purged,
1752 * which prevents userspace from ever using that object again.
1754 i915_gem_shrink(dev_priv,
1755 obj->base.size >> PAGE_SHIFT,
1757 I915_SHRINK_UNBOUND |
1758 I915_SHRINK_PURGEABLE);
1759 ret = drm_gem_create_mmap_offset(&obj->base);
1763 i915_gem_shrink_all(dev_priv);
1764 ret = drm_gem_create_mmap_offset(&obj->base);
1766 dev_priv->mm.shrinker_no_lock_stealing = false;
1771 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1773 drm_gem_free_mmap_offset(&obj->base);
1777 i915_gem_mmap_gtt(struct drm_file *file,
1778 struct drm_device *dev,
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1783 struct drm_i915_gem_object *obj;
1786 ret = i915_mutex_lock_interruptible(dev);
1790 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1791 if (&obj->base == NULL) {
1796 if (obj->base.size > dev_priv->gtt.mappable_end) {
1801 if (obj->madv != I915_MADV_WILLNEED) {
1802 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1807 ret = i915_gem_object_create_mmap_offset(obj);
1811 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1814 drm_gem_object_unreference(&obj->base);
1816 mutex_unlock(&dev->struct_mutex);
1821 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1823 * @data: GTT mapping ioctl data
1824 * @file: GEM object info
1826 * Simply returns the fake offset to userspace so it can mmap it.
1827 * The mmap call will end up in drm_gem_mmap(), which will set things
1828 * up so we can get faults in the handler above.
1830 * The fault handler will take care of binding the object into the GTT
1831 * (since it may have been evicted to make room for something), allocating
1832 * a fence register, and mapping the appropriate aperture address into
1836 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1837 struct drm_file *file)
1839 struct drm_i915_gem_mmap_gtt *args = data;
1841 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1845 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1847 return obj->madv == I915_MADV_DONTNEED;
1850 /* Immediately discard the backing storage */
1852 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1854 i915_gem_object_free_mmap_offset(obj);
1856 if (obj->base.filp == NULL)
1859 /* Our goal here is to return as much of the memory as
1860 * is possible back to the system as we are called from OOM.
1861 * To do this we must instruct the shmfs to drop all of its
1862 * backing pages, *now*.
1864 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1865 obj->madv = __I915_MADV_PURGED;
1868 /* Try to discard unwanted pages */
1870 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1872 struct address_space *mapping;
1874 switch (obj->madv) {
1875 case I915_MADV_DONTNEED:
1876 i915_gem_object_truncate(obj);
1877 case __I915_MADV_PURGED:
1881 if (obj->base.filp == NULL)
1884 mapping = file_inode(obj->base.filp)->i_mapping,
1885 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1889 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1891 struct sg_page_iter sg_iter;
1894 BUG_ON(obj->madv == __I915_MADV_PURGED);
1896 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1898 /* In the event of a disaster, abandon all caches and
1899 * hope for the best.
1901 WARN_ON(ret != -EIO);
1902 i915_gem_clflush_object(obj, true);
1903 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1906 if (i915_gem_object_needs_bit17_swizzle(obj))
1907 i915_gem_object_save_bit_17_swizzle(obj);
1909 if (obj->madv == I915_MADV_DONTNEED)
1912 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1913 struct page *page = sg_page_iter_page(&sg_iter);
1916 set_page_dirty(page);
1918 if (obj->madv == I915_MADV_WILLNEED)
1919 mark_page_accessed(page);
1921 page_cache_release(page);
1925 sg_free_table(obj->pages);
1930 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1932 const struct drm_i915_gem_object_ops *ops = obj->ops;
1934 if (obj->pages == NULL)
1937 if (obj->pages_pin_count)
1940 BUG_ON(i915_gem_obj_bound_any(obj));
1942 /* ->put_pages might need to allocate memory for the bit17 swizzle
1943 * array, hence protect them from being reaped by removing them from gtt
1945 list_del(&obj->global_list);
1947 ops->put_pages(obj);
1950 i915_gem_object_invalidate(obj);
1956 i915_gem_shrink(struct drm_i915_private *dev_priv,
1957 long target, unsigned flags)
1960 struct list_head *list;
1963 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
1964 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
1967 unsigned long count = 0;
1970 * As we may completely rewrite the (un)bound list whilst unbinding
1971 * (due to retiring requests) we have to strictly process only
1972 * one element of the list at the time, and recheck the list
1973 * on every iteration.
1975 * In particular, we must hold a reference whilst removing the
1976 * object as we may end up waiting for and/or retiring the objects.
1977 * This might release the final reference (held by the active list)
1978 * and result in the object being freed from under us. This is
1979 * similar to the precautions the eviction code must take whilst
1982 * Also note that although these lists do not hold a reference to
1983 * the object we can safely grab one here: The final object
1984 * unreferencing and the bound_list are both protected by the
1985 * dev->struct_mutex and so we won't ever be able to observe an
1986 * object on the bound_list with a reference count equals 0.
1988 for (phase = phases; phase->list; phase++) {
1989 struct list_head still_in_list;
1991 if ((flags & phase->bit) == 0)
1994 INIT_LIST_HEAD(&still_in_list);
1995 while (count < target && !list_empty(phase->list)) {
1996 struct drm_i915_gem_object *obj;
1997 struct i915_vma *vma, *v;
1999 obj = list_first_entry(phase->list,
2000 typeof(*obj), global_list);
2001 list_move_tail(&obj->global_list, &still_in_list);
2003 if (flags & I915_SHRINK_PURGEABLE &&
2004 !i915_gem_object_is_purgeable(obj))
2007 drm_gem_object_reference(&obj->base);
2009 /* For the unbound phase, this should be a no-op! */
2010 list_for_each_entry_safe(vma, v,
2011 &obj->vma_list, vma_link)
2012 if (i915_vma_unbind(vma))
2015 if (i915_gem_object_put_pages(obj) == 0)
2016 count += obj->base.size >> PAGE_SHIFT;
2018 drm_gem_object_unreference(&obj->base);
2020 list_splice(&still_in_list, phase->list);
2026 static unsigned long
2027 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2029 i915_gem_evict_everything(dev_priv->dev);
2030 return i915_gem_shrink(dev_priv, LONG_MAX,
2031 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2035 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2037 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2039 struct address_space *mapping;
2040 struct sg_table *st;
2041 struct scatterlist *sg;
2042 struct sg_page_iter sg_iter;
2044 unsigned long last_pfn = 0; /* suppress gcc warning */
2047 /* Assert that the object is not currently in any GPU domain. As it
2048 * wasn't in the GTT, there shouldn't be any way it could have been in
2051 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2052 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2054 st = kmalloc(sizeof(*st), GFP_KERNEL);
2058 page_count = obj->base.size / PAGE_SIZE;
2059 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2064 /* Get the list of pages out of our struct file. They'll be pinned
2065 * at this point until we release them.
2067 * Fail silently without starting the shrinker
2069 mapping = file_inode(obj->base.filp)->i_mapping;
2070 gfp = mapping_gfp_mask(mapping);
2071 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2072 gfp &= ~(__GFP_IO | __GFP_WAIT);
2075 for (i = 0; i < page_count; i++) {
2076 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2078 i915_gem_shrink(dev_priv,
2081 I915_SHRINK_UNBOUND |
2082 I915_SHRINK_PURGEABLE);
2083 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2086 /* We've tried hard to allocate the memory by reaping
2087 * our own buffer, now let the real VM do its job and
2088 * go down in flames if truly OOM.
2090 i915_gem_shrink_all(dev_priv);
2091 page = shmem_read_mapping_page(mapping, i);
2095 #ifdef CONFIG_SWIOTLB
2096 if (swiotlb_nr_tbl()) {
2098 sg_set_page(sg, page, PAGE_SIZE, 0);
2103 if (!i || page_to_pfn(page) != last_pfn + 1) {
2107 sg_set_page(sg, page, PAGE_SIZE, 0);
2109 sg->length += PAGE_SIZE;
2111 last_pfn = page_to_pfn(page);
2113 /* Check that the i965g/gm workaround works. */
2114 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2116 #ifdef CONFIG_SWIOTLB
2117 if (!swiotlb_nr_tbl())
2122 if (i915_gem_object_needs_bit17_swizzle(obj))
2123 i915_gem_object_do_bit_17_swizzle(obj);
2129 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2130 page_cache_release(sg_page_iter_page(&sg_iter));
2134 /* shmemfs first checks if there is enough memory to allocate the page
2135 * and reports ENOSPC should there be insufficient, along with the usual
2136 * ENOMEM for a genuine allocation failure.
2138 * We use ENOSPC in our driver to mean that we have run out of aperture
2139 * space and so want to translate the error from shmemfs back to our
2140 * usual understanding of ENOMEM.
2142 if (PTR_ERR(page) == -ENOSPC)
2145 return PTR_ERR(page);
2148 /* Ensure that the associated pages are gathered from the backing storage
2149 * and pinned into our object. i915_gem_object_get_pages() may be called
2150 * multiple times before they are released by a single call to
2151 * i915_gem_object_put_pages() - once the pages are no longer referenced
2152 * either as a result of memory pressure (reaping pages under the shrinker)
2153 * or as the object is itself released.
2156 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2158 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2159 const struct drm_i915_gem_object_ops *ops = obj->ops;
2165 if (obj->madv != I915_MADV_WILLNEED) {
2166 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2170 BUG_ON(obj->pages_pin_count);
2172 ret = ops->get_pages(obj);
2176 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2181 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2182 struct intel_engine_cs *ring)
2184 u32 seqno = intel_ring_get_seqno(ring);
2186 BUG_ON(ring == NULL);
2187 if (obj->ring != ring && obj->last_write_seqno) {
2188 /* Keep the seqno relative to the current ring */
2189 obj->last_write_seqno = seqno;
2193 /* Add a reference if we're newly entering the active list. */
2195 drm_gem_object_reference(&obj->base);
2199 list_move_tail(&obj->ring_list, &ring->active_list);
2201 obj->last_read_seqno = seqno;
2204 void i915_vma_move_to_active(struct i915_vma *vma,
2205 struct intel_engine_cs *ring)
2207 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2208 return i915_gem_object_move_to_active(vma->obj, ring);
2212 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2214 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2215 struct i915_address_space *vm;
2216 struct i915_vma *vma;
2218 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2219 BUG_ON(!obj->active);
2221 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2222 vma = i915_gem_obj_to_vma(obj, vm);
2223 if (vma && !list_empty(&vma->mm_list))
2224 list_move_tail(&vma->mm_list, &vm->inactive_list);
2227 intel_fb_obj_flush(obj, true);
2229 list_del_init(&obj->ring_list);
2232 obj->last_read_seqno = 0;
2233 obj->last_write_seqno = 0;
2234 obj->base.write_domain = 0;
2236 obj->last_fenced_seqno = 0;
2239 drm_gem_object_unreference(&obj->base);
2241 WARN_ON(i915_verify_lists(dev));
2245 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2247 struct intel_engine_cs *ring = obj->ring;
2252 if (i915_seqno_passed(ring->get_seqno(ring, true),
2253 obj->last_read_seqno))
2254 i915_gem_object_move_to_inactive(obj);
2258 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2261 struct intel_engine_cs *ring;
2264 /* Carefully retire all requests without writing to the rings */
2265 for_each_ring(ring, dev_priv, i) {
2266 ret = intel_ring_idle(ring);
2270 i915_gem_retire_requests(dev);
2272 /* Finally reset hw state */
2273 for_each_ring(ring, dev_priv, i) {
2274 intel_ring_init_seqno(ring, seqno);
2276 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2277 ring->semaphore.sync_seqno[j] = 0;
2283 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2285 struct drm_i915_private *dev_priv = dev->dev_private;
2291 /* HWS page needs to be set less than what we
2292 * will inject to ring
2294 ret = i915_gem_init_seqno(dev, seqno - 1);
2298 /* Carefully set the last_seqno value so that wrap
2299 * detection still works
2301 dev_priv->next_seqno = seqno;
2302 dev_priv->last_seqno = seqno - 1;
2303 if (dev_priv->last_seqno == 0)
2304 dev_priv->last_seqno--;
2310 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2314 /* reserve 0 for non-seqno */
2315 if (dev_priv->next_seqno == 0) {
2316 int ret = i915_gem_init_seqno(dev, 0);
2320 dev_priv->next_seqno = 1;
2323 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2327 int __i915_add_request(struct intel_engine_cs *ring,
2328 struct drm_file *file,
2329 struct drm_i915_gem_object *obj,
2332 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2333 struct drm_i915_gem_request *request;
2334 struct intel_ringbuffer *ringbuf;
2335 u32 request_ring_position, request_start;
2338 request = ring->preallocated_lazy_request;
2339 if (WARN_ON(request == NULL))
2342 if (i915.enable_execlists) {
2343 struct intel_context *ctx = request->ctx;
2344 ringbuf = ctx->engine[ring->id].ringbuf;
2346 ringbuf = ring->buffer;
2348 request_start = intel_ring_get_tail(ringbuf);
2350 * Emit any outstanding flushes - execbuf can fail to emit the flush
2351 * after having emitted the batchbuffer command. Hence we need to fix
2352 * things up similar to emitting the lazy request. The difference here
2353 * is that the flush _must_ happen before the next request, no matter
2356 if (i915.enable_execlists) {
2357 ret = logical_ring_flush_all_caches(ringbuf);
2361 ret = intel_ring_flush_all_caches(ring);
2366 /* Record the position of the start of the request so that
2367 * should we detect the updated seqno part-way through the
2368 * GPU processing the request, we never over-estimate the
2369 * position of the head.
2371 request_ring_position = intel_ring_get_tail(ringbuf);
2373 if (i915.enable_execlists) {
2374 ret = ring->emit_request(ringbuf);
2378 ret = ring->add_request(ring);
2383 request->seqno = intel_ring_get_seqno(ring);
2384 request->ring = ring;
2385 request->head = request_start;
2386 request->tail = request_ring_position;
2388 /* Whilst this request exists, batch_obj will be on the
2389 * active_list, and so will hold the active reference. Only when this
2390 * request is retired will the the batch_obj be moved onto the
2391 * inactive_list and lose its active reference. Hence we do not need
2392 * to explicitly hold another reference here.
2394 request->batch_obj = obj;
2396 if (!i915.enable_execlists) {
2397 /* Hold a reference to the current context so that we can inspect
2398 * it later in case a hangcheck error event fires.
2400 request->ctx = ring->last_context;
2402 i915_gem_context_reference(request->ctx);
2405 request->emitted_jiffies = jiffies;
2406 list_add_tail(&request->list, &ring->request_list);
2407 request->file_priv = NULL;
2410 struct drm_i915_file_private *file_priv = file->driver_priv;
2412 spin_lock(&file_priv->mm.lock);
2413 request->file_priv = file_priv;
2414 list_add_tail(&request->client_list,
2415 &file_priv->mm.request_list);
2416 spin_unlock(&file_priv->mm.lock);
2419 trace_i915_gem_request_add(ring, request->seqno);
2420 ring->outstanding_lazy_seqno = 0;
2421 ring->preallocated_lazy_request = NULL;
2423 if (!dev_priv->ums.mm_suspended) {
2424 i915_queue_hangcheck(ring->dev);
2426 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2427 queue_delayed_work(dev_priv->wq,
2428 &dev_priv->mm.retire_work,
2429 round_jiffies_up_relative(HZ));
2430 intel_mark_busy(dev_priv->dev);
2434 *out_seqno = request->seqno;
2439 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2441 struct drm_i915_file_private *file_priv = request->file_priv;
2446 spin_lock(&file_priv->mm.lock);
2447 list_del(&request->client_list);
2448 request->file_priv = NULL;
2449 spin_unlock(&file_priv->mm.lock);
2452 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2453 const struct intel_context *ctx)
2455 unsigned long elapsed;
2457 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2459 if (ctx->hang_stats.banned)
2462 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2463 if (!i915_gem_context_is_default(ctx)) {
2464 DRM_DEBUG("context hanging too fast, banning!\n");
2466 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2467 if (i915_stop_ring_allow_warn(dev_priv))
2468 DRM_ERROR("gpu hanging too fast, banning!\n");
2476 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2477 struct intel_context *ctx,
2480 struct i915_ctx_hang_stats *hs;
2485 hs = &ctx->hang_stats;
2488 hs->banned = i915_context_is_banned(dev_priv, ctx);
2490 hs->guilty_ts = get_seconds();
2492 hs->batch_pending++;
2496 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2498 list_del(&request->list);
2499 i915_gem_request_remove_from_client(request);
2502 i915_gem_context_unreference(request->ctx);
2507 struct drm_i915_gem_request *
2508 i915_gem_find_active_request(struct intel_engine_cs *ring)
2510 struct drm_i915_gem_request *request;
2511 u32 completed_seqno;
2513 completed_seqno = ring->get_seqno(ring, false);
2515 list_for_each_entry(request, &ring->request_list, list) {
2516 if (i915_seqno_passed(completed_seqno, request->seqno))
2525 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2526 struct intel_engine_cs *ring)
2528 struct drm_i915_gem_request *request;
2531 request = i915_gem_find_active_request(ring);
2533 if (request == NULL)
2536 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2538 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2540 list_for_each_entry_continue(request, &ring->request_list, list)
2541 i915_set_reset_status(dev_priv, request->ctx, false);
2544 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2545 struct intel_engine_cs *ring)
2547 while (!list_empty(&ring->active_list)) {
2548 struct drm_i915_gem_object *obj;
2550 obj = list_first_entry(&ring->active_list,
2551 struct drm_i915_gem_object,
2554 i915_gem_object_move_to_inactive(obj);
2558 * We must free the requests after all the corresponding objects have
2559 * been moved off active lists. Which is the same order as the normal
2560 * retire_requests function does. This is important if object hold
2561 * implicit references on things like e.g. ppgtt address spaces through
2564 while (!list_empty(&ring->request_list)) {
2565 struct drm_i915_gem_request *request;
2567 request = list_first_entry(&ring->request_list,
2568 struct drm_i915_gem_request,
2571 i915_gem_free_request(request);
2574 while (!list_empty(&ring->execlist_queue)) {
2575 struct intel_ctx_submit_request *submit_req;
2577 submit_req = list_first_entry(&ring->execlist_queue,
2578 struct intel_ctx_submit_request,
2580 list_del(&submit_req->execlist_link);
2581 intel_runtime_pm_put(dev_priv);
2582 i915_gem_context_unreference(submit_req->ctx);
2586 /* These may not have been flush before the reset, do so now */
2587 kfree(ring->preallocated_lazy_request);
2588 ring->preallocated_lazy_request = NULL;
2589 ring->outstanding_lazy_seqno = 0;
2592 void i915_gem_restore_fences(struct drm_device *dev)
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2597 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2598 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2601 * Commit delayed tiling changes if we have an object still
2602 * attached to the fence, otherwise just clear the fence.
2605 i915_gem_object_update_fence(reg->obj, reg,
2606 reg->obj->tiling_mode);
2608 i915_gem_write_fence(dev, i, NULL);
2613 void i915_gem_reset(struct drm_device *dev)
2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 struct intel_engine_cs *ring;
2620 * Before we free the objects from the requests, we need to inspect
2621 * them for finding the guilty party. As the requests only borrow
2622 * their reference to the objects, the inspection must be done first.
2624 for_each_ring(ring, dev_priv, i)
2625 i915_gem_reset_ring_status(dev_priv, ring);
2627 for_each_ring(ring, dev_priv, i)
2628 i915_gem_reset_ring_cleanup(dev_priv, ring);
2630 i915_gem_context_reset(dev);
2632 i915_gem_restore_fences(dev);
2636 * This function clears the request list as sequence numbers are passed.
2639 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2643 if (list_empty(&ring->request_list))
2646 WARN_ON(i915_verify_lists(ring->dev));
2648 seqno = ring->get_seqno(ring, true);
2650 /* Move any buffers on the active list that are no longer referenced
2651 * by the ringbuffer to the flushing/inactive lists as appropriate,
2652 * before we free the context associated with the requests.
2654 while (!list_empty(&ring->active_list)) {
2655 struct drm_i915_gem_object *obj;
2657 obj = list_first_entry(&ring->active_list,
2658 struct drm_i915_gem_object,
2661 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2664 i915_gem_object_move_to_inactive(obj);
2668 while (!list_empty(&ring->request_list)) {
2669 struct drm_i915_gem_request *request;
2670 struct intel_ringbuffer *ringbuf;
2672 request = list_first_entry(&ring->request_list,
2673 struct drm_i915_gem_request,
2676 if (!i915_seqno_passed(seqno, request->seqno))
2679 trace_i915_gem_request_retire(ring, request->seqno);
2681 /* This is one of the few common intersection points
2682 * between legacy ringbuffer submission and execlists:
2683 * we need to tell them apart in order to find the correct
2684 * ringbuffer to which the request belongs to.
2686 if (i915.enable_execlists) {
2687 struct intel_context *ctx = request->ctx;
2688 ringbuf = ctx->engine[ring->id].ringbuf;
2690 ringbuf = ring->buffer;
2692 /* We know the GPU must have read the request to have
2693 * sent us the seqno + interrupt, so use the position
2694 * of tail of the request to update the last known position
2697 ringbuf->last_retired_head = request->tail;
2699 i915_gem_free_request(request);
2702 if (unlikely(ring->trace_irq_seqno &&
2703 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2704 ring->irq_put(ring);
2705 ring->trace_irq_seqno = 0;
2708 WARN_ON(i915_verify_lists(ring->dev));
2712 i915_gem_retire_requests(struct drm_device *dev)
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 struct intel_engine_cs *ring;
2719 for_each_ring(ring, dev_priv, i) {
2720 i915_gem_retire_requests_ring(ring);
2721 idle &= list_empty(&ring->request_list);
2725 mod_delayed_work(dev_priv->wq,
2726 &dev_priv->mm.idle_work,
2727 msecs_to_jiffies(100));
2733 i915_gem_retire_work_handler(struct work_struct *work)
2735 struct drm_i915_private *dev_priv =
2736 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2737 struct drm_device *dev = dev_priv->dev;
2740 /* Come back later if the device is busy... */
2742 if (mutex_trylock(&dev->struct_mutex)) {
2743 idle = i915_gem_retire_requests(dev);
2744 mutex_unlock(&dev->struct_mutex);
2747 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2748 round_jiffies_up_relative(HZ));
2752 i915_gem_idle_work_handler(struct work_struct *work)
2754 struct drm_i915_private *dev_priv =
2755 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2757 intel_mark_idle(dev_priv->dev);
2761 * Ensures that an object will eventually get non-busy by flushing any required
2762 * write domains, emitting any outstanding lazy request and retiring and
2763 * completed requests.
2766 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2771 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2775 i915_gem_retire_requests_ring(obj->ring);
2782 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2783 * @DRM_IOCTL_ARGS: standard ioctl arguments
2785 * Returns 0 if successful, else an error is returned with the remaining time in
2786 * the timeout parameter.
2787 * -ETIME: object is still busy after timeout
2788 * -ERESTARTSYS: signal interrupted the wait
2789 * -ENONENT: object doesn't exist
2790 * Also possible, but rare:
2791 * -EAGAIN: GPU wedged
2793 * -ENODEV: Internal IRQ fail
2794 * -E?: The add request failed
2796 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2797 * non-zero timeout parameter the wait ioctl will wait for the given number of
2798 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2799 * without holding struct_mutex the object may become re-busied before this
2800 * function completes. A similar but shorter * race condition exists in the busy
2804 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2806 struct drm_i915_private *dev_priv = dev->dev_private;
2807 struct drm_i915_gem_wait *args = data;
2808 struct drm_i915_gem_object *obj;
2809 struct intel_engine_cs *ring = NULL;
2810 unsigned reset_counter;
2814 if (args->flags != 0)
2817 ret = i915_mutex_lock_interruptible(dev);
2821 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2822 if (&obj->base == NULL) {
2823 mutex_unlock(&dev->struct_mutex);
2827 /* Need to make sure the object gets inactive eventually. */
2828 ret = i915_gem_object_flush_active(obj);
2833 seqno = obj->last_read_seqno;
2840 /* Do this after OLR check to make sure we make forward progress polling
2841 * on this IOCTL with a timeout <=0 (like busy ioctl)
2843 if (args->timeout_ns <= 0) {
2848 drm_gem_object_unreference(&obj->base);
2849 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2850 mutex_unlock(&dev->struct_mutex);
2852 return __i915_wait_seqno(ring, seqno, reset_counter, true,
2853 &args->timeout_ns, file->driver_priv);
2856 drm_gem_object_unreference(&obj->base);
2857 mutex_unlock(&dev->struct_mutex);
2862 * i915_gem_object_sync - sync an object to a ring.
2864 * @obj: object which may be in use on another ring.
2865 * @to: ring we wish to use the object on. May be NULL.
2867 * This code is meant to abstract object synchronization with the GPU.
2868 * Calling with NULL implies synchronizing the object with the CPU
2869 * rather than a particular GPU ring.
2871 * Returns 0 if successful, else propagates up the lower layer error.
2874 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2875 struct intel_engine_cs *to)
2877 struct intel_engine_cs *from = obj->ring;
2881 if (from == NULL || to == from)
2884 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2885 return i915_gem_object_wait_rendering(obj, false);
2887 idx = intel_ring_sync_index(from, to);
2889 seqno = obj->last_read_seqno;
2890 /* Optimization: Avoid semaphore sync when we are sure we already
2891 * waited for an object with higher seqno */
2892 if (seqno <= from->semaphore.sync_seqno[idx])
2895 ret = i915_gem_check_olr(obj->ring, seqno);
2899 trace_i915_gem_ring_sync_to(from, to, seqno);
2900 ret = to->semaphore.sync_to(to, from, seqno);
2902 /* We use last_read_seqno because sync_to()
2903 * might have just caused seqno wrap under
2906 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2911 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2913 u32 old_write_domain, old_read_domains;
2915 /* Force a pagefault for domain tracking on next user access */
2916 i915_gem_release_mmap(obj);
2918 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2921 /* Wait for any direct GTT access to complete */
2924 old_read_domains = obj->base.read_domains;
2925 old_write_domain = obj->base.write_domain;
2927 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2928 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2930 trace_i915_gem_object_change_domain(obj,
2935 int i915_vma_unbind(struct i915_vma *vma)
2937 struct drm_i915_gem_object *obj = vma->obj;
2938 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2941 if (list_empty(&vma->vma_link))
2944 if (!drm_mm_node_allocated(&vma->node)) {
2945 i915_gem_vma_destroy(vma);
2952 BUG_ON(obj->pages == NULL);
2954 ret = i915_gem_object_finish_gpu(obj);
2957 /* Continue on if we fail due to EIO, the GPU is hung so we
2958 * should be safe and we need to cleanup or else we might
2959 * cause memory corruption through use-after-free.
2962 /* Throw away the active reference before moving to the unbound list */
2963 i915_gem_object_retire(obj);
2965 if (i915_is_ggtt(vma->vm)) {
2966 i915_gem_object_finish_gtt(obj);
2968 /* release the fence reg _after_ flushing */
2969 ret = i915_gem_object_put_fence(obj);
2974 trace_i915_vma_unbind(vma);
2976 vma->unbind_vma(vma);
2978 list_del_init(&vma->mm_list);
2979 if (i915_is_ggtt(vma->vm))
2980 obj->map_and_fenceable = false;
2982 drm_mm_remove_node(&vma->node);
2983 i915_gem_vma_destroy(vma);
2985 /* Since the unbound list is global, only move to that list if
2986 * no more VMAs exist. */
2987 if (list_empty(&obj->vma_list)) {
2988 i915_gem_gtt_finish_object(obj);
2989 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2992 /* And finally now the object is completely decoupled from this vma,
2993 * we can drop its hold on the backing storage and allow it to be
2994 * reaped by the shrinker.
2996 i915_gem_object_unpin_pages(obj);
3001 int i915_gpu_idle(struct drm_device *dev)
3003 struct drm_i915_private *dev_priv = dev->dev_private;
3004 struct intel_engine_cs *ring;
3007 /* Flush everything onto the inactive list. */
3008 for_each_ring(ring, dev_priv, i) {
3009 if (!i915.enable_execlists) {
3010 ret = i915_switch_context(ring, ring->default_context);
3015 ret = intel_ring_idle(ring);
3023 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3024 struct drm_i915_gem_object *obj)
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3028 int fence_pitch_shift;
3030 if (INTEL_INFO(dev)->gen >= 6) {
3031 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3032 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3034 fence_reg = FENCE_REG_965_0;
3035 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3038 fence_reg += reg * 8;
3040 /* To w/a incoherency with non-atomic 64-bit register updates,
3041 * we split the 64-bit update into two 32-bit writes. In order
3042 * for a partial fence not to be evaluated between writes, we
3043 * precede the update with write to turn off the fence register,
3044 * and only enable the fence as the last step.
3046 * For extra levels of paranoia, we make sure each step lands
3047 * before applying the next step.
3049 I915_WRITE(fence_reg, 0);
3050 POSTING_READ(fence_reg);
3053 u32 size = i915_gem_obj_ggtt_size(obj);
3056 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3058 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3059 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3060 if (obj->tiling_mode == I915_TILING_Y)
3061 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3062 val |= I965_FENCE_REG_VALID;
3064 I915_WRITE(fence_reg + 4, val >> 32);
3065 POSTING_READ(fence_reg + 4);
3067 I915_WRITE(fence_reg + 0, val);
3068 POSTING_READ(fence_reg);
3070 I915_WRITE(fence_reg + 4, 0);
3071 POSTING_READ(fence_reg + 4);
3075 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3076 struct drm_i915_gem_object *obj)
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3082 u32 size = i915_gem_obj_ggtt_size(obj);
3086 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3087 (size & -size) != size ||
3088 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3089 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3090 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3092 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3097 /* Note: pitch better be a power of two tile widths */
3098 pitch_val = obj->stride / tile_width;
3099 pitch_val = ffs(pitch_val) - 1;
3101 val = i915_gem_obj_ggtt_offset(obj);
3102 if (obj->tiling_mode == I915_TILING_Y)
3103 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3104 val |= I915_FENCE_SIZE_BITS(size);
3105 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3106 val |= I830_FENCE_REG_VALID;
3111 reg = FENCE_REG_830_0 + reg * 4;
3113 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3115 I915_WRITE(reg, val);
3119 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3120 struct drm_i915_gem_object *obj)
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3126 u32 size = i915_gem_obj_ggtt_size(obj);
3129 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3130 (size & -size) != size ||
3131 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3132 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3133 i915_gem_obj_ggtt_offset(obj), size);
3135 pitch_val = obj->stride / 128;
3136 pitch_val = ffs(pitch_val) - 1;
3138 val = i915_gem_obj_ggtt_offset(obj);
3139 if (obj->tiling_mode == I915_TILING_Y)
3140 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3141 val |= I830_FENCE_SIZE_BITS(size);
3142 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3143 val |= I830_FENCE_REG_VALID;
3147 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3148 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3151 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3153 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3156 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3157 struct drm_i915_gem_object *obj)
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3161 /* Ensure that all CPU reads are completed before installing a fence
3162 * and all writes before removing the fence.
3164 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3167 WARN(obj && (!obj->stride || !obj->tiling_mode),
3168 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3169 obj->stride, obj->tiling_mode);
3171 switch (INTEL_INFO(dev)->gen) {
3177 case 4: i965_write_fence_reg(dev, reg, obj); break;
3178 case 3: i915_write_fence_reg(dev, reg, obj); break;
3179 case 2: i830_write_fence_reg(dev, reg, obj); break;
3183 /* And similarly be paranoid that no direct access to this region
3184 * is reordered to before the fence is installed.
3186 if (i915_gem_object_needs_mb(obj))
3190 static inline int fence_number(struct drm_i915_private *dev_priv,
3191 struct drm_i915_fence_reg *fence)
3193 return fence - dev_priv->fence_regs;
3196 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3197 struct drm_i915_fence_reg *fence,
3200 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3201 int reg = fence_number(dev_priv, fence);
3203 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3206 obj->fence_reg = reg;
3208 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3210 obj->fence_reg = I915_FENCE_REG_NONE;
3212 list_del_init(&fence->lru_list);
3214 obj->fence_dirty = false;
3218 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3220 if (obj->last_fenced_seqno) {
3221 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3225 obj->last_fenced_seqno = 0;
3232 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3234 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3235 struct drm_i915_fence_reg *fence;
3238 ret = i915_gem_object_wait_fence(obj);
3242 if (obj->fence_reg == I915_FENCE_REG_NONE)
3245 fence = &dev_priv->fence_regs[obj->fence_reg];
3247 if (WARN_ON(fence->pin_count))
3250 i915_gem_object_fence_lost(obj);
3251 i915_gem_object_update_fence(obj, fence, false);
3256 static struct drm_i915_fence_reg *
3257 i915_find_fence_reg(struct drm_device *dev)
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 struct drm_i915_fence_reg *reg, *avail;
3263 /* First try to find a free reg */
3265 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3266 reg = &dev_priv->fence_regs[i];
3270 if (!reg->pin_count)
3277 /* None available, try to steal one or wait for a user to finish */
3278 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3286 /* Wait for completion of pending flips which consume fences */
3287 if (intel_has_pending_fb_unpin(dev))
3288 return ERR_PTR(-EAGAIN);
3290 return ERR_PTR(-EDEADLK);
3294 * i915_gem_object_get_fence - set up fencing for an object
3295 * @obj: object to map through a fence reg
3297 * When mapping objects through the GTT, userspace wants to be able to write
3298 * to them without having to worry about swizzling if the object is tiled.
3299 * This function walks the fence regs looking for a free one for @obj,
3300 * stealing one if it can't find any.
3302 * It then sets up the reg based on the object's properties: address, pitch
3303 * and tiling format.
3305 * For an untiled surface, this removes any existing fence.
3308 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3310 struct drm_device *dev = obj->base.dev;
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 bool enable = obj->tiling_mode != I915_TILING_NONE;
3313 struct drm_i915_fence_reg *reg;
3316 /* Have we updated the tiling parameters upon the object and so
3317 * will need to serialise the write to the associated fence register?
3319 if (obj->fence_dirty) {
3320 ret = i915_gem_object_wait_fence(obj);
3325 /* Just update our place in the LRU if our fence is getting reused. */
3326 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3327 reg = &dev_priv->fence_regs[obj->fence_reg];
3328 if (!obj->fence_dirty) {
3329 list_move_tail(®->lru_list,
3330 &dev_priv->mm.fence_list);
3333 } else if (enable) {
3334 if (WARN_ON(!obj->map_and_fenceable))
3337 reg = i915_find_fence_reg(dev);
3339 return PTR_ERR(reg);
3342 struct drm_i915_gem_object *old = reg->obj;
3344 ret = i915_gem_object_wait_fence(old);
3348 i915_gem_object_fence_lost(old);
3353 i915_gem_object_update_fence(obj, reg, enable);
3358 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3359 unsigned long cache_level)
3361 struct drm_mm_node *gtt_space = &vma->node;
3362 struct drm_mm_node *other;
3365 * On some machines we have to be careful when putting differing types
3366 * of snoopable memory together to avoid the prefetcher crossing memory
3367 * domains and dying. During vm initialisation, we decide whether or not
3368 * these constraints apply and set the drm_mm.color_adjust
3371 if (vma->vm->mm.color_adjust == NULL)
3374 if (!drm_mm_node_allocated(gtt_space))
3377 if (list_empty(>t_space->node_list))
3380 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3381 if (other->allocated && !other->hole_follows && other->color != cache_level)
3384 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3385 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3392 * Finds free space in the GTT aperture and binds the object there.
3394 static struct i915_vma *
3395 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3396 struct i915_address_space *vm,
3400 struct drm_device *dev = obj->base.dev;
3401 struct drm_i915_private *dev_priv = dev->dev_private;
3402 u32 size, fence_size, fence_alignment, unfenced_alignment;
3403 unsigned long start =
3404 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3406 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3407 struct i915_vma *vma;
3410 fence_size = i915_gem_get_gtt_size(dev,
3413 fence_alignment = i915_gem_get_gtt_alignment(dev,
3415 obj->tiling_mode, true);
3416 unfenced_alignment =
3417 i915_gem_get_gtt_alignment(dev,
3419 obj->tiling_mode, false);
3422 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3424 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3425 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3426 return ERR_PTR(-EINVAL);
3429 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3431 /* If the object is bigger than the entire aperture, reject it early
3432 * before evicting everything in a vain attempt to find space.
3434 if (obj->base.size > end) {
3435 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3437 flags & PIN_MAPPABLE ? "mappable" : "total",
3439 return ERR_PTR(-E2BIG);
3442 ret = i915_gem_object_get_pages(obj);
3444 return ERR_PTR(ret);
3446 i915_gem_object_pin_pages(obj);
3448 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3453 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3457 DRM_MM_SEARCH_DEFAULT,
3458 DRM_MM_CREATE_DEFAULT);
3460 ret = i915_gem_evict_something(dev, vm, size, alignment,
3469 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3471 goto err_remove_node;
3474 ret = i915_gem_gtt_prepare_object(obj);
3476 goto err_remove_node;
3478 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3479 list_add_tail(&vma->mm_list, &vm->inactive_list);
3481 trace_i915_vma_bind(vma, flags);
3482 vma->bind_vma(vma, obj->cache_level,
3483 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3488 drm_mm_remove_node(&vma->node);
3490 i915_gem_vma_destroy(vma);
3493 i915_gem_object_unpin_pages(obj);
3498 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3501 /* If we don't have a page list set up, then we're not pinned
3502 * to GPU, and we can ignore the cache flush because it'll happen
3503 * again at bind time.
3505 if (obj->pages == NULL)
3509 * Stolen memory is always coherent with the GPU as it is explicitly
3510 * marked as wc by the system, or the system is cache-coherent.
3515 /* If the GPU is snooping the contents of the CPU cache,
3516 * we do not need to manually clear the CPU cache lines. However,
3517 * the caches are only snooped when the render cache is
3518 * flushed/invalidated. As we always have to emit invalidations
3519 * and flushes when moving into and out of the RENDER domain, correct
3520 * snooping behaviour occurs naturally as the result of our domain
3523 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3526 trace_i915_gem_object_clflush(obj);
3527 drm_clflush_sg(obj->pages);
3532 /** Flushes the GTT write domain for the object if it's dirty. */
3534 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3536 uint32_t old_write_domain;
3538 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3541 /* No actual flushing is required for the GTT write domain. Writes
3542 * to it immediately go to main memory as far as we know, so there's
3543 * no chipset flush. It also doesn't land in render cache.
3545 * However, we do have to enforce the order so that all writes through
3546 * the GTT land before any writes to the device, such as updates to
3551 old_write_domain = obj->base.write_domain;
3552 obj->base.write_domain = 0;
3554 intel_fb_obj_flush(obj, false);
3556 trace_i915_gem_object_change_domain(obj,
3557 obj->base.read_domains,
3561 /** Flushes the CPU write domain for the object if it's dirty. */
3563 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3566 uint32_t old_write_domain;
3568 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3571 if (i915_gem_clflush_object(obj, force))
3572 i915_gem_chipset_flush(obj->base.dev);
3574 old_write_domain = obj->base.write_domain;
3575 obj->base.write_domain = 0;
3577 intel_fb_obj_flush(obj, false);
3579 trace_i915_gem_object_change_domain(obj,
3580 obj->base.read_domains,
3585 * Moves a single object to the GTT read, and possibly write domain.
3587 * This function returns when the move is complete, including waiting on
3591 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3593 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3594 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3595 uint32_t old_write_domain, old_read_domains;
3598 /* Not valid to be called on unbound objects. */
3602 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3605 ret = i915_gem_object_wait_rendering(obj, !write);
3609 i915_gem_object_retire(obj);
3610 i915_gem_object_flush_cpu_write_domain(obj, false);
3612 /* Serialise direct access to this object with the barriers for
3613 * coherent writes from the GPU, by effectively invalidating the
3614 * GTT domain upon first access.
3616 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3619 old_write_domain = obj->base.write_domain;
3620 old_read_domains = obj->base.read_domains;
3622 /* It should now be out of any other write domains, and we can update
3623 * the domain values for our changes.
3625 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3626 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3628 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3629 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3634 intel_fb_obj_invalidate(obj, NULL);
3636 trace_i915_gem_object_change_domain(obj,
3640 /* And bump the LRU for this access */
3641 if (i915_gem_object_is_inactive(obj))
3642 list_move_tail(&vma->mm_list,
3643 &dev_priv->gtt.base.inactive_list);
3648 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3649 enum i915_cache_level cache_level)
3651 struct drm_device *dev = obj->base.dev;
3652 struct i915_vma *vma, *next;
3655 if (obj->cache_level == cache_level)
3658 if (i915_gem_obj_is_pinned(obj)) {
3659 DRM_DEBUG("can not change the cache level of pinned objects\n");
3663 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3664 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3665 ret = i915_vma_unbind(vma);
3671 if (i915_gem_obj_bound_any(obj)) {
3672 ret = i915_gem_object_finish_gpu(obj);
3676 i915_gem_object_finish_gtt(obj);
3678 /* Before SandyBridge, you could not use tiling or fence
3679 * registers with snooped memory, so relinquish any fences
3680 * currently pointing to our region in the aperture.
3682 if (INTEL_INFO(dev)->gen < 6) {
3683 ret = i915_gem_object_put_fence(obj);
3688 list_for_each_entry(vma, &obj->vma_list, vma_link)
3689 if (drm_mm_node_allocated(&vma->node))
3690 vma->bind_vma(vma, cache_level,
3691 vma->bound & GLOBAL_BIND);
3694 list_for_each_entry(vma, &obj->vma_list, vma_link)
3695 vma->node.color = cache_level;
3696 obj->cache_level = cache_level;
3698 if (cpu_write_needs_clflush(obj)) {
3699 u32 old_read_domains, old_write_domain;
3701 /* If we're coming from LLC cached, then we haven't
3702 * actually been tracking whether the data is in the
3703 * CPU cache or not, since we only allow one bit set
3704 * in obj->write_domain and have been skipping the clflushes.
3705 * Just set it to the CPU cache for now.
3707 i915_gem_object_retire(obj);
3708 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3710 old_read_domains = obj->base.read_domains;
3711 old_write_domain = obj->base.write_domain;
3713 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3714 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3716 trace_i915_gem_object_change_domain(obj,
3724 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3725 struct drm_file *file)
3727 struct drm_i915_gem_caching *args = data;
3728 struct drm_i915_gem_object *obj;
3731 ret = i915_mutex_lock_interruptible(dev);
3735 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3736 if (&obj->base == NULL) {
3741 switch (obj->cache_level) {
3742 case I915_CACHE_LLC:
3743 case I915_CACHE_L3_LLC:
3744 args->caching = I915_CACHING_CACHED;
3748 args->caching = I915_CACHING_DISPLAY;
3752 args->caching = I915_CACHING_NONE;
3756 drm_gem_object_unreference(&obj->base);
3758 mutex_unlock(&dev->struct_mutex);
3762 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3763 struct drm_file *file)
3765 struct drm_i915_gem_caching *args = data;
3766 struct drm_i915_gem_object *obj;
3767 enum i915_cache_level level;
3770 switch (args->caching) {
3771 case I915_CACHING_NONE:
3772 level = I915_CACHE_NONE;
3774 case I915_CACHING_CACHED:
3775 level = I915_CACHE_LLC;
3777 case I915_CACHING_DISPLAY:
3778 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3784 ret = i915_mutex_lock_interruptible(dev);
3788 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3789 if (&obj->base == NULL) {
3794 ret = i915_gem_object_set_cache_level(obj, level);
3796 drm_gem_object_unreference(&obj->base);
3798 mutex_unlock(&dev->struct_mutex);
3802 static bool is_pin_display(struct drm_i915_gem_object *obj)
3804 struct i915_vma *vma;
3806 vma = i915_gem_obj_to_ggtt(obj);
3810 /* There are 3 sources that pin objects:
3811 * 1. The display engine (scanouts, sprites, cursors);
3812 * 2. Reservations for execbuffer;
3815 * We can ignore reservations as we hold the struct_mutex and
3816 * are only called outside of the reservation path. The user
3817 * can only increment pin_count once, and so if after
3818 * subtracting the potential reference by the user, any pin_count
3819 * remains, it must be due to another use by the display engine.
3821 return vma->pin_count - !!obj->user_pin_count;
3825 * Prepare buffer for display plane (scanout, cursors, etc).
3826 * Can be called from an uninterruptible phase (modesetting) and allows
3827 * any flushes to be pipelined (for pageflips).
3830 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3832 struct intel_engine_cs *pipelined)
3834 u32 old_read_domains, old_write_domain;
3835 bool was_pin_display;
3838 if (pipelined != obj->ring) {
3839 ret = i915_gem_object_sync(obj, pipelined);
3844 /* Mark the pin_display early so that we account for the
3845 * display coherency whilst setting up the cache domains.
3847 was_pin_display = obj->pin_display;
3848 obj->pin_display = true;
3850 /* The display engine is not coherent with the LLC cache on gen6. As
3851 * a result, we make sure that the pinning that is about to occur is
3852 * done with uncached PTEs. This is lowest common denominator for all
3855 * However for gen6+, we could do better by using the GFDT bit instead
3856 * of uncaching, which would allow us to flush all the LLC-cached data
3857 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3859 ret = i915_gem_object_set_cache_level(obj,
3860 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3862 goto err_unpin_display;
3864 /* As the user may map the buffer once pinned in the display plane
3865 * (e.g. libkms for the bootup splash), we have to ensure that we
3866 * always use map_and_fenceable for all scanout buffers.
3868 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3870 goto err_unpin_display;
3872 i915_gem_object_flush_cpu_write_domain(obj, true);
3874 old_write_domain = obj->base.write_domain;
3875 old_read_domains = obj->base.read_domains;
3877 /* It should now be out of any other write domains, and we can update
3878 * the domain values for our changes.
3880 obj->base.write_domain = 0;
3881 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3883 trace_i915_gem_object_change_domain(obj,
3890 WARN_ON(was_pin_display != is_pin_display(obj));
3891 obj->pin_display = was_pin_display;
3896 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3898 i915_gem_object_ggtt_unpin(obj);
3899 obj->pin_display = is_pin_display(obj);
3903 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3907 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3910 ret = i915_gem_object_wait_rendering(obj, false);
3914 /* Ensure that we invalidate the GPU's caches and TLBs. */
3915 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3920 * Moves a single object to the CPU read, and possibly write domain.
3922 * This function returns when the move is complete, including waiting on
3926 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3928 uint32_t old_write_domain, old_read_domains;
3931 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3934 ret = i915_gem_object_wait_rendering(obj, !write);
3938 i915_gem_object_retire(obj);
3939 i915_gem_object_flush_gtt_write_domain(obj);
3941 old_write_domain = obj->base.write_domain;
3942 old_read_domains = obj->base.read_domains;
3944 /* Flush the CPU cache if it's still invalid. */
3945 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3946 i915_gem_clflush_object(obj, false);
3948 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3951 /* It should now be out of any other write domains, and we can update
3952 * the domain values for our changes.
3954 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3956 /* If we're writing through the CPU, then the GPU read domains will
3957 * need to be invalidated at next use.
3960 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3961 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3965 intel_fb_obj_invalidate(obj, NULL);
3967 trace_i915_gem_object_change_domain(obj,
3974 /* Throttle our rendering by waiting until the ring has completed our requests
3975 * emitted over 20 msec ago.
3977 * Note that if we were to use the current jiffies each time around the loop,
3978 * we wouldn't escape the function with any frames outstanding if the time to
3979 * render a frame was over 20ms.
3981 * This should get us reasonable parallelism between CPU and GPU but also
3982 * relatively low latency when blocking on a particular request to finish.
3985 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3987 struct drm_i915_private *dev_priv = dev->dev_private;
3988 struct drm_i915_file_private *file_priv = file->driver_priv;
3989 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3990 struct drm_i915_gem_request *request;
3991 struct intel_engine_cs *ring = NULL;
3992 unsigned reset_counter;
3996 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4000 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4004 spin_lock(&file_priv->mm.lock);
4005 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4006 if (time_after_eq(request->emitted_jiffies, recent_enough))
4009 ring = request->ring;
4010 seqno = request->seqno;
4012 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4013 spin_unlock(&file_priv->mm.lock);
4018 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4020 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4026 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4028 struct drm_i915_gem_object *obj = vma->obj;
4031 vma->node.start & (alignment - 1))
4034 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4037 if (flags & PIN_OFFSET_BIAS &&
4038 vma->node.start < (flags & PIN_OFFSET_MASK))
4045 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4046 struct i915_address_space *vm,
4050 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4051 struct i915_vma *vma;
4055 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4058 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4061 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4064 vma = i915_gem_obj_to_vma(obj, vm);
4066 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4069 if (i915_vma_misplaced(vma, alignment, flags)) {
4070 WARN(vma->pin_count,
4071 "bo is already pinned with incorrect alignment:"
4072 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4073 " obj->map_and_fenceable=%d\n",
4074 i915_gem_obj_offset(obj, vm), alignment,
4075 !!(flags & PIN_MAPPABLE),
4076 obj->map_and_fenceable);
4077 ret = i915_vma_unbind(vma);
4085 bound = vma ? vma->bound : 0;
4086 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4087 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4089 return PTR_ERR(vma);
4092 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4093 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4095 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4096 bool mappable, fenceable;
4097 u32 fence_size, fence_alignment;
4099 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4102 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4107 fenceable = (vma->node.size == fence_size &&
4108 (vma->node.start & (fence_alignment - 1)) == 0);
4110 mappable = (vma->node.start + obj->base.size <=
4111 dev_priv->gtt.mappable_end);
4113 obj->map_and_fenceable = mappable && fenceable;
4116 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4119 if (flags & PIN_MAPPABLE)
4120 obj->pin_mappable |= true;
4126 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4128 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4131 BUG_ON(vma->pin_count == 0);
4132 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4134 if (--vma->pin_count == 0)
4135 obj->pin_mappable = false;
4139 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4141 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4142 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4143 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4145 WARN_ON(!ggtt_vma ||
4146 dev_priv->fence_regs[obj->fence_reg].pin_count >
4147 ggtt_vma->pin_count);
4148 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4155 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4157 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4158 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4159 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4160 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4165 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4166 struct drm_file *file)
4168 struct drm_i915_gem_pin *args = data;
4169 struct drm_i915_gem_object *obj;
4172 if (INTEL_INFO(dev)->gen >= 6)
4175 ret = i915_mutex_lock_interruptible(dev);
4179 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4180 if (&obj->base == NULL) {
4185 if (obj->madv != I915_MADV_WILLNEED) {
4186 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4191 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4192 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4198 if (obj->user_pin_count == ULONG_MAX) {
4203 if (obj->user_pin_count == 0) {
4204 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4209 obj->user_pin_count++;
4210 obj->pin_filp = file;
4212 args->offset = i915_gem_obj_ggtt_offset(obj);
4214 drm_gem_object_unreference(&obj->base);
4216 mutex_unlock(&dev->struct_mutex);
4221 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4222 struct drm_file *file)
4224 struct drm_i915_gem_pin *args = data;
4225 struct drm_i915_gem_object *obj;
4228 ret = i915_mutex_lock_interruptible(dev);
4232 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4233 if (&obj->base == NULL) {
4238 if (obj->pin_filp != file) {
4239 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4244 obj->user_pin_count--;
4245 if (obj->user_pin_count == 0) {
4246 obj->pin_filp = NULL;
4247 i915_gem_object_ggtt_unpin(obj);
4251 drm_gem_object_unreference(&obj->base);
4253 mutex_unlock(&dev->struct_mutex);
4258 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4259 struct drm_file *file)
4261 struct drm_i915_gem_busy *args = data;
4262 struct drm_i915_gem_object *obj;
4265 ret = i915_mutex_lock_interruptible(dev);
4269 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4270 if (&obj->base == NULL) {
4275 /* Count all active objects as busy, even if they are currently not used
4276 * by the gpu. Users of this interface expect objects to eventually
4277 * become non-busy without any further actions, therefore emit any
4278 * necessary flushes here.
4280 ret = i915_gem_object_flush_active(obj);
4282 args->busy = obj->active;
4284 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4285 args->busy |= intel_ring_flag(obj->ring) << 16;
4288 drm_gem_object_unreference(&obj->base);
4290 mutex_unlock(&dev->struct_mutex);
4295 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4296 struct drm_file *file_priv)
4298 return i915_gem_ring_throttle(dev, file_priv);
4302 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4303 struct drm_file *file_priv)
4305 struct drm_i915_gem_madvise *args = data;
4306 struct drm_i915_gem_object *obj;
4309 switch (args->madv) {
4310 case I915_MADV_DONTNEED:
4311 case I915_MADV_WILLNEED:
4317 ret = i915_mutex_lock_interruptible(dev);
4321 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4322 if (&obj->base == NULL) {
4327 if (i915_gem_obj_is_pinned(obj)) {
4332 if (obj->madv != __I915_MADV_PURGED)
4333 obj->madv = args->madv;
4335 /* if the object is no longer attached, discard its backing storage */
4336 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4337 i915_gem_object_truncate(obj);
4339 args->retained = obj->madv != __I915_MADV_PURGED;
4342 drm_gem_object_unreference(&obj->base);
4344 mutex_unlock(&dev->struct_mutex);
4348 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4349 const struct drm_i915_gem_object_ops *ops)
4351 INIT_LIST_HEAD(&obj->global_list);
4352 INIT_LIST_HEAD(&obj->ring_list);
4353 INIT_LIST_HEAD(&obj->obj_exec_link);
4354 INIT_LIST_HEAD(&obj->vma_list);
4358 obj->fence_reg = I915_FENCE_REG_NONE;
4359 obj->madv = I915_MADV_WILLNEED;
4361 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4364 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4365 .get_pages = i915_gem_object_get_pages_gtt,
4366 .put_pages = i915_gem_object_put_pages_gtt,
4369 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4372 struct drm_i915_gem_object *obj;
4373 struct address_space *mapping;
4376 obj = i915_gem_object_alloc(dev);
4380 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4381 i915_gem_object_free(obj);
4385 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4386 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4387 /* 965gm cannot relocate objects above 4GiB. */
4388 mask &= ~__GFP_HIGHMEM;
4389 mask |= __GFP_DMA32;
4392 mapping = file_inode(obj->base.filp)->i_mapping;
4393 mapping_set_gfp_mask(mapping, mask);
4395 i915_gem_object_init(obj, &i915_gem_object_ops);
4397 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4398 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4401 /* On some devices, we can have the GPU use the LLC (the CPU
4402 * cache) for about a 10% performance improvement
4403 * compared to uncached. Graphics requests other than
4404 * display scanout are coherent with the CPU in
4405 * accessing this cache. This means in this mode we
4406 * don't need to clflush on the CPU side, and on the
4407 * GPU side we only need to flush internal caches to
4408 * get data visible to the CPU.
4410 * However, we maintain the display planes as UC, and so
4411 * need to rebind when first used as such.
4413 obj->cache_level = I915_CACHE_LLC;
4415 obj->cache_level = I915_CACHE_NONE;
4417 trace_i915_gem_object_create(obj);
4422 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4424 /* If we are the last user of the backing storage (be it shmemfs
4425 * pages or stolen etc), we know that the pages are going to be
4426 * immediately released. In this case, we can then skip copying
4427 * back the contents from the GPU.
4430 if (obj->madv != I915_MADV_WILLNEED)
4433 if (obj->base.filp == NULL)
4436 /* At first glance, this looks racy, but then again so would be
4437 * userspace racing mmap against close. However, the first external
4438 * reference to the filp can only be obtained through the
4439 * i915_gem_mmap_ioctl() which safeguards us against the user
4440 * acquiring such a reference whilst we are in the middle of
4441 * freeing the object.
4443 return atomic_long_read(&obj->base.filp->f_count) == 1;
4446 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4448 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4449 struct drm_device *dev = obj->base.dev;
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451 struct i915_vma *vma, *next;
4453 intel_runtime_pm_get(dev_priv);
4455 trace_i915_gem_object_destroy(obj);
4457 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4461 ret = i915_vma_unbind(vma);
4462 if (WARN_ON(ret == -ERESTARTSYS)) {
4463 bool was_interruptible;
4465 was_interruptible = dev_priv->mm.interruptible;
4466 dev_priv->mm.interruptible = false;
4468 WARN_ON(i915_vma_unbind(vma));
4470 dev_priv->mm.interruptible = was_interruptible;
4474 i915_gem_object_detach_phys(obj);
4476 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4477 * before progressing. */
4479 i915_gem_object_unpin_pages(obj);
4481 WARN_ON(obj->frontbuffer_bits);
4483 if (WARN_ON(obj->pages_pin_count))
4484 obj->pages_pin_count = 0;
4485 if (discard_backing_storage(obj))
4486 obj->madv = I915_MADV_DONTNEED;
4487 i915_gem_object_put_pages(obj);
4488 i915_gem_object_free_mmap_offset(obj);
4492 if (obj->base.import_attach)
4493 drm_prime_gem_destroy(&obj->base, NULL);
4495 if (obj->ops->release)
4496 obj->ops->release(obj);
4498 drm_gem_object_release(&obj->base);
4499 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4502 i915_gem_object_free(obj);
4504 intel_runtime_pm_put(dev_priv);
4507 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4508 struct i915_address_space *vm)
4510 struct i915_vma *vma;
4511 list_for_each_entry(vma, &obj->vma_list, vma_link)
4518 void i915_gem_vma_destroy(struct i915_vma *vma)
4520 struct i915_address_space *vm = NULL;
4521 WARN_ON(vma->node.allocated);
4523 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4524 if (!list_empty(&vma->exec_list))
4529 if (!i915_is_ggtt(vm))
4530 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4532 list_del(&vma->vma_link);
4538 i915_gem_stop_ringbuffers(struct drm_device *dev)
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 struct intel_engine_cs *ring;
4544 for_each_ring(ring, dev_priv, i)
4545 dev_priv->gt.stop_ring(ring);
4549 i915_gem_suspend(struct drm_device *dev)
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4554 mutex_lock(&dev->struct_mutex);
4555 if (dev_priv->ums.mm_suspended)
4558 ret = i915_gpu_idle(dev);
4562 i915_gem_retire_requests(dev);
4564 /* Under UMS, be paranoid and evict. */
4565 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4566 i915_gem_evict_everything(dev);
4568 i915_kernel_lost_context(dev);
4569 i915_gem_stop_ringbuffers(dev);
4571 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4572 * We need to replace this with a semaphore, or something.
4573 * And not confound ums.mm_suspended!
4575 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4577 mutex_unlock(&dev->struct_mutex);
4579 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4580 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4581 flush_delayed_work(&dev_priv->mm.idle_work);
4586 mutex_unlock(&dev->struct_mutex);
4590 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4592 struct drm_device *dev = ring->dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4595 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4598 if (!HAS_L3_DPF(dev) || !remap_info)
4601 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4606 * Note: We do not worry about the concurrent register cacheline hang
4607 * here because no other code should access these registers other than
4608 * at initialization time.
4610 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4611 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4612 intel_ring_emit(ring, reg_base + i);
4613 intel_ring_emit(ring, remap_info[i/4]);
4616 intel_ring_advance(ring);
4621 void i915_gem_init_swizzling(struct drm_device *dev)
4623 struct drm_i915_private *dev_priv = dev->dev_private;
4625 if (INTEL_INFO(dev)->gen < 5 ||
4626 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4629 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4630 DISP_TILE_SURFACE_SWIZZLING);
4635 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4637 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4638 else if (IS_GEN7(dev))
4639 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4640 else if (IS_GEN8(dev))
4641 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4647 intel_enable_blt(struct drm_device *dev)
4652 /* The blitter was dysfunctional on early prototypes */
4653 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4654 DRM_INFO("BLT not supported on this pre-production hardware;"
4655 " graphics performance will be degraded.\n");
4662 static void init_unused_ring(struct drm_device *dev, u32 base)
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4666 I915_WRITE(RING_CTL(base), 0);
4667 I915_WRITE(RING_HEAD(base), 0);
4668 I915_WRITE(RING_TAIL(base), 0);
4669 I915_WRITE(RING_START(base), 0);
4672 static void init_unused_rings(struct drm_device *dev)
4675 init_unused_ring(dev, PRB1_BASE);
4676 init_unused_ring(dev, SRB0_BASE);
4677 init_unused_ring(dev, SRB1_BASE);
4678 init_unused_ring(dev, SRB2_BASE);
4679 init_unused_ring(dev, SRB3_BASE);
4680 } else if (IS_GEN2(dev)) {
4681 init_unused_ring(dev, SRB0_BASE);
4682 init_unused_ring(dev, SRB1_BASE);
4683 } else if (IS_GEN3(dev)) {
4684 init_unused_ring(dev, PRB1_BASE);
4685 init_unused_ring(dev, PRB2_BASE);
4689 int i915_gem_init_rings(struct drm_device *dev)
4691 struct drm_i915_private *dev_priv = dev->dev_private;
4695 * At least 830 can leave some of the unused rings
4696 * "active" (ie. head != tail) after resume which
4697 * will prevent c3 entry. Makes sure all unused rings
4700 init_unused_rings(dev);
4702 ret = intel_init_render_ring_buffer(dev);
4707 ret = intel_init_bsd_ring_buffer(dev);
4709 goto cleanup_render_ring;
4712 if (intel_enable_blt(dev)) {
4713 ret = intel_init_blt_ring_buffer(dev);
4715 goto cleanup_bsd_ring;
4718 if (HAS_VEBOX(dev)) {
4719 ret = intel_init_vebox_ring_buffer(dev);
4721 goto cleanup_blt_ring;
4724 if (HAS_BSD2(dev)) {
4725 ret = intel_init_bsd2_ring_buffer(dev);
4727 goto cleanup_vebox_ring;
4730 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4732 goto cleanup_bsd2_ring;
4737 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4739 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4741 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4743 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4744 cleanup_render_ring:
4745 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4751 i915_gem_init_hw(struct drm_device *dev)
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4756 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4759 if (dev_priv->ellc_size)
4760 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4762 if (IS_HASWELL(dev))
4763 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4764 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4766 if (HAS_PCH_NOP(dev)) {
4767 if (IS_IVYBRIDGE(dev)) {
4768 u32 temp = I915_READ(GEN7_MSG_CTL);
4769 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4770 I915_WRITE(GEN7_MSG_CTL, temp);
4771 } else if (INTEL_INFO(dev)->gen >= 7) {
4772 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4773 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4774 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4778 i915_gem_init_swizzling(dev);
4780 ret = dev_priv->gt.init_rings(dev);
4784 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4785 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4788 * XXX: Contexts should only be initialized once. Doing a switch to the
4789 * default context switch however is something we'd like to do after
4790 * reset or thaw (the latter may not actually be necessary for HW, but
4791 * goes with our code better). Context switching requires rings (for
4792 * the do_switch), but before enabling PPGTT. So don't move this.
4794 ret = i915_gem_context_enable(dev_priv);
4795 if (ret && ret != -EIO) {
4796 DRM_ERROR("Context enable failed %d\n", ret);
4797 i915_gem_cleanup_ringbuffer(dev);
4802 ret = i915_ppgtt_init_hw(dev);
4803 if (ret && ret != -EIO) {
4804 DRM_ERROR("PPGTT enable failed %d\n", ret);
4805 i915_gem_cleanup_ringbuffer(dev);
4811 int i915_gem_init(struct drm_device *dev)
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4816 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4817 i915.enable_execlists);
4819 mutex_lock(&dev->struct_mutex);
4821 if (IS_VALLEYVIEW(dev)) {
4822 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4823 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4824 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4825 VLV_GTLC_ALLOWWAKEACK), 10))
4826 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4829 if (!i915.enable_execlists) {
4830 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4831 dev_priv->gt.init_rings = i915_gem_init_rings;
4832 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4833 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4835 dev_priv->gt.do_execbuf = intel_execlists_submission;
4836 dev_priv->gt.init_rings = intel_logical_rings_init;
4837 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4838 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4841 ret = i915_gem_init_userptr(dev);
4843 mutex_unlock(&dev->struct_mutex);
4847 i915_gem_init_global_gtt(dev);
4849 ret = i915_gem_context_init(dev);
4851 mutex_unlock(&dev->struct_mutex);
4855 ret = i915_gem_init_hw(dev);
4857 /* Allow ring initialisation to fail by marking the GPU as
4858 * wedged. But we only want to do this where the GPU is angry,
4859 * for all other failure, such as an allocation failure, bail.
4861 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4862 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4865 mutex_unlock(&dev->struct_mutex);
4867 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4868 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4869 dev_priv->dri1.allow_batchbuffer = 1;
4874 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877 struct intel_engine_cs *ring;
4880 for_each_ring(ring, dev_priv, i)
4881 dev_priv->gt.cleanup_ring(ring);
4885 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4886 struct drm_file *file_priv)
4888 struct drm_i915_private *dev_priv = dev->dev_private;
4891 if (drm_core_check_feature(dev, DRIVER_MODESET))
4894 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4895 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4896 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4899 mutex_lock(&dev->struct_mutex);
4900 dev_priv->ums.mm_suspended = 0;
4902 ret = i915_gem_init_hw(dev);
4904 mutex_unlock(&dev->struct_mutex);
4908 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4910 ret = drm_irq_install(dev, dev->pdev->irq);
4912 goto cleanup_ringbuffer;
4913 mutex_unlock(&dev->struct_mutex);
4918 i915_gem_cleanup_ringbuffer(dev);
4919 dev_priv->ums.mm_suspended = 1;
4920 mutex_unlock(&dev->struct_mutex);
4926 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4927 struct drm_file *file_priv)
4929 if (drm_core_check_feature(dev, DRIVER_MODESET))
4932 mutex_lock(&dev->struct_mutex);
4933 drm_irq_uninstall(dev);
4934 mutex_unlock(&dev->struct_mutex);
4936 return i915_gem_suspend(dev);
4940 i915_gem_lastclose(struct drm_device *dev)
4944 if (drm_core_check_feature(dev, DRIVER_MODESET))
4947 ret = i915_gem_suspend(dev);
4949 DRM_ERROR("failed to idle hardware: %d\n", ret);
4953 init_ring_lists(struct intel_engine_cs *ring)
4955 INIT_LIST_HEAD(&ring->active_list);
4956 INIT_LIST_HEAD(&ring->request_list);
4959 void i915_init_vm(struct drm_i915_private *dev_priv,
4960 struct i915_address_space *vm)
4962 if (!i915_is_ggtt(vm))
4963 drm_mm_init(&vm->mm, vm->start, vm->total);
4964 vm->dev = dev_priv->dev;
4965 INIT_LIST_HEAD(&vm->active_list);
4966 INIT_LIST_HEAD(&vm->inactive_list);
4967 INIT_LIST_HEAD(&vm->global_link);
4968 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4972 i915_gem_load(struct drm_device *dev)
4974 struct drm_i915_private *dev_priv = dev->dev_private;
4978 kmem_cache_create("i915_gem_object",
4979 sizeof(struct drm_i915_gem_object), 0,
4983 INIT_LIST_HEAD(&dev_priv->vm_list);
4984 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4986 INIT_LIST_HEAD(&dev_priv->context_list);
4987 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4988 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4989 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4990 for (i = 0; i < I915_NUM_RINGS; i++)
4991 init_ring_lists(&dev_priv->ring[i]);
4992 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4993 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4994 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4995 i915_gem_retire_work_handler);
4996 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4997 i915_gem_idle_work_handler);
4998 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5000 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5001 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5002 I915_WRITE(MI_ARB_STATE,
5003 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5006 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5008 /* Old X drivers will take 0-2 for front, back, depth buffers */
5009 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5010 dev_priv->fence_reg_start = 3;
5012 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5013 dev_priv->num_fence_regs = 32;
5014 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5015 dev_priv->num_fence_regs = 16;
5017 dev_priv->num_fence_regs = 8;
5019 /* Initialize fence registers to zero */
5020 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5021 i915_gem_restore_fences(dev);
5023 i915_gem_detect_bit_6_swizzle(dev);
5024 init_waitqueue_head(&dev_priv->pending_flip_queue);
5026 dev_priv->mm.interruptible = true;
5028 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5029 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5030 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5031 register_shrinker(&dev_priv->mm.shrinker);
5033 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5034 register_oom_notifier(&dev_priv->mm.oom_notifier);
5036 mutex_init(&dev_priv->fb_tracking.lock);
5039 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5041 struct drm_i915_file_private *file_priv = file->driver_priv;
5043 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5045 /* Clean up our request list when the client is going away, so that
5046 * later retire_requests won't dereference our soon-to-be-gone
5049 spin_lock(&file_priv->mm.lock);
5050 while (!list_empty(&file_priv->mm.request_list)) {
5051 struct drm_i915_gem_request *request;
5053 request = list_first_entry(&file_priv->mm.request_list,
5054 struct drm_i915_gem_request,
5056 list_del(&request->client_list);
5057 request->file_priv = NULL;
5059 spin_unlock(&file_priv->mm.lock);
5063 i915_gem_file_idle_work_handler(struct work_struct *work)
5065 struct drm_i915_file_private *file_priv =
5066 container_of(work, typeof(*file_priv), mm.idle_work.work);
5068 atomic_set(&file_priv->rps_wait_boost, false);
5071 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5073 struct drm_i915_file_private *file_priv;
5076 DRM_DEBUG_DRIVER("\n");
5078 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5082 file->driver_priv = file_priv;
5083 file_priv->dev_priv = dev->dev_private;
5084 file_priv->file = file;
5086 spin_lock_init(&file_priv->mm.lock);
5087 INIT_LIST_HEAD(&file_priv->mm.request_list);
5088 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5089 i915_gem_file_idle_work_handler);
5091 ret = i915_gem_context_open(dev, file);
5099 * i915_gem_track_fb - update frontbuffer tracking
5100 * old: current GEM buffer for the frontbuffer slots
5101 * new: new GEM buffer for the frontbuffer slots
5102 * frontbuffer_bits: bitmask of frontbuffer slots
5104 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5105 * from @old and setting them in @new. Both @old and @new can be NULL.
5107 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5108 struct drm_i915_gem_object *new,
5109 unsigned frontbuffer_bits)
5112 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5113 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5114 old->frontbuffer_bits &= ~frontbuffer_bits;
5118 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5119 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5120 new->frontbuffer_bits |= frontbuffer_bits;
5124 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5126 if (!mutex_is_locked(mutex))
5129 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5130 return mutex->owner == task;
5132 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5137 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5139 if (!mutex_trylock(&dev->struct_mutex)) {
5140 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5143 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5153 static int num_vma_bound(struct drm_i915_gem_object *obj)
5155 struct i915_vma *vma;
5158 list_for_each_entry(vma, &obj->vma_list, vma_link)
5159 if (drm_mm_node_allocated(&vma->node))
5165 static unsigned long
5166 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5168 struct drm_i915_private *dev_priv =
5169 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5170 struct drm_device *dev = dev_priv->dev;
5171 struct drm_i915_gem_object *obj;
5172 unsigned long count;
5175 if (!i915_gem_shrinker_lock(dev, &unlock))
5179 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5180 if (obj->pages_pin_count == 0)
5181 count += obj->base.size >> PAGE_SHIFT;
5183 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5184 if (!i915_gem_obj_is_pinned(obj) &&
5185 obj->pages_pin_count == num_vma_bound(obj))
5186 count += obj->base.size >> PAGE_SHIFT;
5190 mutex_unlock(&dev->struct_mutex);
5195 /* All the new VM stuff */
5196 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5197 struct i915_address_space *vm)
5199 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5200 struct i915_vma *vma;
5202 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5204 list_for_each_entry(vma, &o->vma_list, vma_link) {
5206 return vma->node.start;
5209 WARN(1, "%s vma for this object not found.\n",
5210 i915_is_ggtt(vm) ? "global" : "ppgtt");
5214 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5215 struct i915_address_space *vm)
5217 struct i915_vma *vma;
5219 list_for_each_entry(vma, &o->vma_list, vma_link)
5220 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5226 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5228 struct i915_vma *vma;
5230 list_for_each_entry(vma, &o->vma_list, vma_link)
5231 if (drm_mm_node_allocated(&vma->node))
5237 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5238 struct i915_address_space *vm)
5240 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5241 struct i915_vma *vma;
5243 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5245 BUG_ON(list_empty(&o->vma_list));
5247 list_for_each_entry(vma, &o->vma_list, vma_link)
5249 return vma->node.size;
5254 static unsigned long
5255 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5257 struct drm_i915_private *dev_priv =
5258 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5259 struct drm_device *dev = dev_priv->dev;
5260 unsigned long freed;
5263 if (!i915_gem_shrinker_lock(dev, &unlock))
5266 freed = i915_gem_shrink(dev_priv,
5269 I915_SHRINK_UNBOUND |
5270 I915_SHRINK_PURGEABLE);
5271 if (freed < sc->nr_to_scan)
5272 freed += i915_gem_shrink(dev_priv,
5273 sc->nr_to_scan - freed,
5275 I915_SHRINK_UNBOUND);
5277 mutex_unlock(&dev->struct_mutex);
5283 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5285 struct drm_i915_private *dev_priv =
5286 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5287 struct drm_device *dev = dev_priv->dev;
5288 struct drm_i915_gem_object *obj;
5289 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5290 unsigned long pinned, bound, unbound, freed_pages;
5291 bool was_interruptible;
5294 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5295 schedule_timeout_killable(1);
5296 if (fatal_signal_pending(current))
5300 pr_err("Unable to purge GPU memory due lock contention.\n");
5304 was_interruptible = dev_priv->mm.interruptible;
5305 dev_priv->mm.interruptible = false;
5307 freed_pages = i915_gem_shrink_all(dev_priv);
5309 dev_priv->mm.interruptible = was_interruptible;
5311 /* Because we may be allocating inside our own driver, we cannot
5312 * assert that there are no objects with pinned pages that are not
5313 * being pointed to by hardware.
5315 unbound = bound = pinned = 0;
5316 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5317 if (!obj->base.filp) /* not backed by a freeable object */
5320 if (obj->pages_pin_count)
5321 pinned += obj->base.size;
5323 unbound += obj->base.size;
5325 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5326 if (!obj->base.filp)
5329 if (obj->pages_pin_count)
5330 pinned += obj->base.size;
5332 bound += obj->base.size;
5336 mutex_unlock(&dev->struct_mutex);
5338 if (freed_pages || unbound || bound)
5339 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5340 freed_pages << PAGE_SHIFT, pinned);
5341 if (unbound || bound)
5342 pr_err("%lu and %lu bytes still available in the "
5343 "bound and unbound GPU page lists.\n",
5346 *(unsigned long *)ptr += freed_pages;
5350 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5352 struct i915_vma *vma;
5354 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5355 if (vma->vm != i915_obj_to_ggtt(obj))