1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170529"
84 #define DRIVER_TIMESTAMP 1496041258
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func, int line);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
125 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
127 uint_fixed_16_16_t fp;
135 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
137 return DIV_ROUND_UP(fp.val, 1 << 16);
140 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
145 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
146 uint_fixed_16_16_t min2)
148 uint_fixed_16_16_t min;
150 min.val = min(min1.val, min2.val);
154 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
155 uint_fixed_16_16_t max2)
157 uint_fixed_16_16_t max;
159 max.val = max(max1.val, max2.val);
163 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
164 uint_fixed_16_16_t d)
166 return DIV_ROUND_UP(val.val, d.val);
169 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
170 uint_fixed_16_16_t mul)
172 uint64_t intermediate_val;
175 intermediate_val = (uint64_t) val * mul.val;
176 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
177 WARN_ON(intermediate_val >> 32);
178 result = clamp_t(uint32_t, intermediate_val, 0, ~0);
182 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
183 uint_fixed_16_16_t mul)
185 uint64_t intermediate_val;
186 uint_fixed_16_16_t fp;
188 intermediate_val = (uint64_t) val.val * mul.val;
189 intermediate_val = intermediate_val >> 16;
190 WARN_ON(intermediate_val >> 32);
191 fp.val = clamp_t(uint32_t, intermediate_val, 0, ~0);
195 static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d)
197 uint_fixed_16_16_t fp, res;
199 fp = u32_to_fixed_16_16(val);
200 res.val = DIV_ROUND_UP(fp.val, d);
204 static inline uint_fixed_16_16_t fixed_16_16_div_u64(uint32_t val, uint32_t d)
206 uint_fixed_16_16_t res;
209 interm_val = (uint64_t)val << 16;
210 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
211 WARN_ON(interm_val >> 32);
212 res.val = (uint32_t) interm_val;
217 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
218 uint_fixed_16_16_t d)
222 interm_val = (uint64_t)val << 16;
223 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
224 WARN_ON(interm_val >> 32);
225 return clamp_t(uint32_t, interm_val, 0, ~0);
228 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
229 uint_fixed_16_16_t mul)
231 uint64_t intermediate_val;
232 uint_fixed_16_16_t fp;
234 intermediate_val = (uint64_t) val * mul.val;
235 WARN_ON(intermediate_val >> 32);
236 fp.val = (uint32_t) intermediate_val;
240 static inline const char *yesno(bool v)
242 return v ? "yes" : "no";
245 static inline const char *onoff(bool v)
247 return v ? "on" : "off";
250 static inline const char *enableddisabled(bool v)
252 return v ? "enabled" : "disabled";
261 I915_MAX_PIPES = _PIPE_EDP
263 #define pipe_name(p) ((p) + 'A')
275 static inline const char *transcoder_name(enum transcoder transcoder)
277 switch (transcoder) {
286 case TRANSCODER_DSI_A:
288 case TRANSCODER_DSI_C:
295 static inline bool transcoder_is_dsi(enum transcoder transcoder)
297 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
301 * Global legacy plane identifier. Valid only for primary/sprite
302 * planes on pre-g4x, and only for primary planes on g4x+.
309 #define plane_name(p) ((p) + 'A')
311 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
314 * Per-pipe plane identifier.
315 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
316 * number of planes per CRTC. Not all platforms really have this many planes,
317 * which means some arrays of size I915_MAX_PLANES may have unused entries
318 * between the topmost sprite plane and the cursor plane.
320 * This is expected to be passed to various register macros
321 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
332 #define for_each_plane_id_on_crtc(__crtc, __p) \
333 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
334 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
345 #define port_name(p) ((p) + 'A')
347 #define I915_NUM_PHYS_VLV 2
360 enum intel_display_power_domain {
364 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
365 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
366 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
367 POWER_DOMAIN_TRANSCODER_A,
368 POWER_DOMAIN_TRANSCODER_B,
369 POWER_DOMAIN_TRANSCODER_C,
370 POWER_DOMAIN_TRANSCODER_EDP,
371 POWER_DOMAIN_TRANSCODER_DSI_A,
372 POWER_DOMAIN_TRANSCODER_DSI_C,
373 POWER_DOMAIN_PORT_DDI_A_LANES,
374 POWER_DOMAIN_PORT_DDI_B_LANES,
375 POWER_DOMAIN_PORT_DDI_C_LANES,
376 POWER_DOMAIN_PORT_DDI_D_LANES,
377 POWER_DOMAIN_PORT_DDI_E_LANES,
378 POWER_DOMAIN_PORT_DDI_A_IO,
379 POWER_DOMAIN_PORT_DDI_B_IO,
380 POWER_DOMAIN_PORT_DDI_C_IO,
381 POWER_DOMAIN_PORT_DDI_D_IO,
382 POWER_DOMAIN_PORT_DDI_E_IO,
383 POWER_DOMAIN_PORT_DSI,
384 POWER_DOMAIN_PORT_CRT,
385 POWER_DOMAIN_PORT_OTHER,
394 POWER_DOMAIN_MODESET,
400 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
401 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
402 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
403 #define POWER_DOMAIN_TRANSCODER(tran) \
404 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
405 (tran) + POWER_DOMAIN_TRANSCODER_A)
409 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
421 #define for_each_hpd_pin(__pin) \
422 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
424 #define HPD_STORM_DEFAULT_THRESHOLD 5
426 struct i915_hotplug {
427 struct work_struct hotplug_work;
430 unsigned long last_jiffies;
435 HPD_MARK_DISABLED = 2
437 } stats[HPD_NUM_PINS];
439 struct delayed_work reenable_work;
441 struct intel_digital_port *irq_port[I915_MAX_PORTS];
444 struct work_struct dig_port_work;
446 struct work_struct poll_init_work;
449 unsigned int hpd_storm_threshold;
452 * if we get a HPD irq from DP and a HPD irq from non-DP
453 * the non-DP HPD could block the workqueue on a mode config
454 * mutex getting, that userspace may have taken. However
455 * userspace is waiting on the DP workqueue to run which is
456 * blocked behind the non-DP one.
458 struct workqueue_struct *dp_wq;
461 #define I915_GEM_GPU_DOMAINS \
462 (I915_GEM_DOMAIN_RENDER | \
463 I915_GEM_DOMAIN_SAMPLER | \
464 I915_GEM_DOMAIN_COMMAND | \
465 I915_GEM_DOMAIN_INSTRUCTION | \
466 I915_GEM_DOMAIN_VERTEX)
468 #define for_each_pipe(__dev_priv, __p) \
469 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
470 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
471 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
472 for_each_if ((__mask) & (1 << (__p)))
473 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
475 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
477 #define for_each_sprite(__dev_priv, __p, __s) \
479 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
482 #define for_each_port_masked(__port, __ports_mask) \
483 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
484 for_each_if ((__ports_mask) & (1 << (__port)))
486 #define for_each_crtc(dev, crtc) \
487 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
489 #define for_each_intel_plane(dev, intel_plane) \
490 list_for_each_entry(intel_plane, \
491 &(dev)->mode_config.plane_list, \
494 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
495 list_for_each_entry(intel_plane, \
496 &(dev)->mode_config.plane_list, \
498 for_each_if ((plane_mask) & \
499 (1 << drm_plane_index(&intel_plane->base)))
501 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
502 list_for_each_entry(intel_plane, \
503 &(dev)->mode_config.plane_list, \
505 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
507 #define for_each_intel_crtc(dev, intel_crtc) \
508 list_for_each_entry(intel_crtc, \
509 &(dev)->mode_config.crtc_list, \
512 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
513 list_for_each_entry(intel_crtc, \
514 &(dev)->mode_config.crtc_list, \
516 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
518 #define for_each_intel_encoder(dev, intel_encoder) \
519 list_for_each_entry(intel_encoder, \
520 &(dev)->mode_config.encoder_list, \
523 #define for_each_intel_connector_iter(intel_connector, iter) \
524 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
526 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
527 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
528 for_each_if ((intel_encoder)->base.crtc == (__crtc))
530 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
531 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
532 for_each_if ((intel_connector)->base.encoder == (__encoder))
534 #define for_each_power_domain(domain, mask) \
535 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
536 for_each_if (BIT_ULL(domain) & (mask))
538 #define for_each_power_well(__dev_priv, __power_well) \
539 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
540 (__power_well) - (__dev_priv)->power_domains.power_wells < \
541 (__dev_priv)->power_domains.power_well_count; \
544 #define for_each_power_well_rev(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
546 (__dev_priv)->power_domains.power_well_count - 1; \
547 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
550 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
551 for_each_power_well(__dev_priv, __power_well) \
552 for_each_if ((__power_well)->domains & (__domain_mask))
554 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
555 for_each_power_well_rev(__dev_priv, __power_well) \
556 for_each_if ((__power_well)->domains & (__domain_mask))
558 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
560 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
561 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
562 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
564 for_each_if (plane_state)
566 struct drm_i915_private;
567 struct i915_mm_struct;
568 struct i915_mmu_object;
570 struct drm_i915_file_private {
571 struct drm_i915_private *dev_priv;
572 struct drm_file *file;
576 struct list_head request_list;
577 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
578 * chosen to prevent the CPU getting more than a frame ahead of the GPU
579 * (when using lax throttling for the frontbuffer). We also use it to
580 * offer free GPU waitboosts for severely congested workloads.
582 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
584 struct idr context_idr;
586 struct intel_rps_client {
587 struct list_head link;
591 unsigned int bsd_engine;
593 /* Client can have a maximum of 3 contexts banned before
594 * it is denied of creating new contexts. As one context
595 * ban needs 4 consecutive hangs, and more if there is
596 * progress in between, this is a last resort stop gap measure
597 * to limit the badly behaving clients access to gpu.
599 #define I915_MAX_CLIENT_CONTEXT_BANS 3
603 /* Used by dp and fdi links */
604 struct intel_link_m_n {
612 void intel_link_compute_m_n(int bpp, int nlanes,
613 int pixel_clock, int link_clock,
614 struct intel_link_m_n *m_n);
616 /* Interface history:
619 * 1.2: Add Power Management
620 * 1.3: Add vblank support
621 * 1.4: Fix cmdbuffer path, add heap destroy
622 * 1.5: Add vblank pipe configuration
623 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
624 * - Support vertical blank on secondary display pipe
626 #define DRIVER_MAJOR 1
627 #define DRIVER_MINOR 6
628 #define DRIVER_PATCHLEVEL 0
630 struct opregion_header;
631 struct opregion_acpi;
632 struct opregion_swsci;
633 struct opregion_asle;
635 struct intel_opregion {
636 struct opregion_header *header;
637 struct opregion_acpi *acpi;
638 struct opregion_swsci *swsci;
639 u32 swsci_gbda_sub_functions;
640 u32 swsci_sbcb_sub_functions;
641 struct opregion_asle *asle;
646 struct work_struct asle_work;
648 #define OPREGION_SIZE (8*1024)
650 struct intel_overlay;
651 struct intel_overlay_error_state;
653 struct sdvo_device_mapping {
662 struct intel_connector;
663 struct intel_encoder;
664 struct intel_atomic_state;
665 struct intel_crtc_state;
666 struct intel_initial_plane_config;
670 struct intel_cdclk_state;
672 struct drm_i915_display_funcs {
673 void (*get_cdclk)(struct drm_i915_private *dev_priv,
674 struct intel_cdclk_state *cdclk_state);
675 void (*set_cdclk)(struct drm_i915_private *dev_priv,
676 const struct intel_cdclk_state *cdclk_state);
677 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
678 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
679 int (*compute_intermediate_wm)(struct drm_device *dev,
680 struct intel_crtc *intel_crtc,
681 struct intel_crtc_state *newstate);
682 void (*initial_watermarks)(struct intel_atomic_state *state,
683 struct intel_crtc_state *cstate);
684 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
685 struct intel_crtc_state *cstate);
686 void (*optimize_watermarks)(struct intel_atomic_state *state,
687 struct intel_crtc_state *cstate);
688 int (*compute_global_watermarks)(struct drm_atomic_state *state);
689 void (*update_wm)(struct intel_crtc *crtc);
690 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
691 /* Returns the active state of the crtc, and if the crtc is active,
692 * fills out the pipe-config with the hw state. */
693 bool (*get_pipe_config)(struct intel_crtc *,
694 struct intel_crtc_state *);
695 void (*get_initial_plane_config)(struct intel_crtc *,
696 struct intel_initial_plane_config *);
697 int (*crtc_compute_clock)(struct intel_crtc *crtc,
698 struct intel_crtc_state *crtc_state);
699 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
700 struct drm_atomic_state *old_state);
701 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
702 struct drm_atomic_state *old_state);
703 void (*update_crtcs)(struct drm_atomic_state *state,
704 unsigned int *crtc_vblank_mask);
705 void (*audio_codec_enable)(struct drm_connector *connector,
706 struct intel_encoder *encoder,
707 const struct drm_display_mode *adjusted_mode);
708 void (*audio_codec_disable)(struct intel_encoder *encoder);
709 void (*fdi_link_train)(struct intel_crtc *crtc,
710 const struct intel_crtc_state *crtc_state);
711 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
712 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
713 struct drm_framebuffer *fb,
714 struct drm_i915_gem_object *obj,
715 struct drm_i915_gem_request *req,
717 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
718 /* clock updates for mode set */
720 /* render clock increase/decrease */
721 /* display clock increase/decrease */
722 /* pll clock increase/decrease */
724 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
725 void (*load_luts)(struct drm_crtc_state *crtc_state);
728 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
729 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
730 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
733 struct work_struct work;
735 uint32_t *dmc_payload;
736 uint32_t dmc_fw_size;
739 i915_reg_t mmioaddr[8];
740 uint32_t mmiodata[8];
742 uint32_t allowed_dc_mask;
745 #define DEV_INFO_FOR_EACH_FLAG(func) \
748 func(is_alpha_support); \
749 /* Keep has_* in alphabetical order */ \
750 func(has_64bit_reloc); \
751 func(has_aliasing_ppgtt); \
756 func(has_fpga_dbg); \
757 func(has_full_ppgtt); \
758 func(has_full_48bit_ppgtt); \
759 func(has_gmbus_irq); \
760 func(has_gmch_display); \
766 func(has_logical_ring_contexts); \
768 func(has_pipe_cxsr); \
769 func(has_pooled_eu); \
773 func(has_resource_streamer); \
774 func(has_runtime_pm); \
776 func(unfenced_needs_alignment); \
777 func(cursor_needs_physical); \
778 func(hws_needs_physical); \
779 func(overlay_needs_physical); \
782 struct sseu_dev_info {
788 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
791 u8 has_subslice_pg:1;
795 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
797 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
800 /* Keep in gen based order, and chronological order within a gen */
801 enum intel_platform {
802 INTEL_PLATFORM_UNINITIALIZED = 0,
831 struct intel_device_info {
832 u32 display_mmio_offset;
835 u8 num_sprites[I915_MAX_PIPES];
836 u8 num_scalers[I915_MAX_PIPES];
839 enum intel_platform platform;
840 u8 ring_mask; /* Rings supported by the HW */
842 #define DEFINE_FLAG(name) u8 name:1
843 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
845 u16 ddb_size; /* in blocks */
846 /* Register offsets for the various display pipes and transcoders */
847 int pipe_offsets[I915_MAX_TRANSCODERS];
848 int trans_offsets[I915_MAX_TRANSCODERS];
849 int palette_offsets[I915_MAX_PIPES];
850 int cursor_offsets[I915_MAX_PIPES];
852 /* Slice/subslice/EU info */
853 struct sseu_dev_info sseu;
856 u16 degamma_lut_size;
861 struct intel_display_error_state;
863 struct i915_gpu_state {
866 struct timeval boottime;
867 struct timeval uptime;
869 struct drm_i915_private *i915;
879 struct intel_device_info device_info;
880 struct i915_params params;
882 /* Generic register state */
886 u32 gtier[4], ngtier;
890 u32 error; /* gen6+ */
891 u32 err_int; /* gen7 */
892 u32 fault_data0; /* gen8, gen9 */
893 u32 fault_data1; /* gen8, gen9 */
901 u64 fence[I915_MAX_NUM_FENCES];
902 struct intel_overlay_error_state *overlay;
903 struct intel_display_error_state *display;
904 struct drm_i915_error_object *semaphore;
905 struct drm_i915_error_object *guc_log;
907 struct drm_i915_error_engine {
909 /* Software tracked state */
912 unsigned long hangcheck_timestamp;
913 bool hangcheck_stalled;
914 enum intel_engine_hangcheck_action hangcheck_action;
915 struct i915_address_space *vm;
918 /* position of active request inside the ring */
919 u32 rq_head, rq_post, rq_tail;
921 /* our own tracking of ring head and tail */
944 u32 rc_psmi; /* sleep state */
945 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
946 struct intel_instdone instdone;
948 struct drm_i915_error_context {
949 char comm[TASK_COMM_LEN];
958 struct drm_i915_error_object {
964 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
966 struct drm_i915_error_object **user_bo;
969 struct drm_i915_error_object *wa_ctx;
971 struct drm_i915_error_request {
979 } *requests, execlist[2];
981 struct drm_i915_error_waiter {
982 char comm[TASK_COMM_LEN];
994 } engine[I915_NUM_ENGINES];
996 struct drm_i915_error_buffer {
999 u32 rseqno[I915_NUM_ENGINES], wseqno;
1003 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1010 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1011 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1012 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1015 enum i915_cache_level {
1016 I915_CACHE_NONE = 0,
1017 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1018 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1019 caches, eg sampler/render caches, and the
1020 large Last-Level-Cache. LLC is coherent with
1021 the CPU, but L3 is only visible to the GPU. */
1022 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1025 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1036 /* This is always the inner lock when overlapping with struct_mutex and
1037 * it's the outer lock when overlapping with stolen_lock. */
1040 unsigned int possible_framebuffer_bits;
1041 unsigned int busy_bits;
1042 unsigned int visible_pipes_mask;
1043 struct intel_crtc *crtc;
1045 struct drm_mm_node compressed_fb;
1046 struct drm_mm_node *compressed_llb;
1053 bool underrun_detected;
1054 struct work_struct underrun_work;
1056 struct intel_fbc_state_cache {
1057 struct i915_vma *vma;
1060 unsigned int mode_flags;
1061 uint32_t hsw_bdw_pixel_rate;
1065 unsigned int rotation;
1072 const struct drm_format_info *format;
1073 unsigned int stride;
1077 struct intel_fbc_reg_params {
1078 struct i915_vma *vma;
1083 unsigned int fence_y_offset;
1087 const struct drm_format_info *format;
1088 unsigned int stride;
1094 struct intel_fbc_work {
1096 u32 scheduled_vblank;
1097 struct work_struct work;
1100 const char *no_fbc_reason;
1104 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1105 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1106 * parsing for same resolution.
1108 enum drrs_refresh_rate_type {
1111 DRRS_MAX_RR, /* RR count */
1114 enum drrs_support_type {
1115 DRRS_NOT_SUPPORTED = 0,
1116 STATIC_DRRS_SUPPORT = 1,
1117 SEAMLESS_DRRS_SUPPORT = 2
1123 struct delayed_work work;
1124 struct intel_dp *dp;
1125 unsigned busy_frontbuffer_bits;
1126 enum drrs_refresh_rate_type refresh_rate_type;
1127 enum drrs_support_type type;
1134 struct intel_dp *enabled;
1136 struct delayed_work work;
1137 unsigned busy_frontbuffer_bits;
1139 bool aux_frame_sync;
1141 bool y_cord_support;
1142 bool colorimetry_support;
1147 PCH_NONE = 0, /* No PCH present */
1148 PCH_IBX, /* Ibexpeak PCH */
1149 PCH_CPT, /* Cougarpoint PCH */
1150 PCH_LPT, /* Lynxpoint PCH */
1151 PCH_SPT, /* Sunrisepoint PCH */
1152 PCH_KBP, /* Kabypoint PCH */
1153 PCH_CNP, /* Cannonpoint PCH */
1157 enum intel_sbi_destination {
1162 #define QUIRK_PIPEA_FORCE (1<<0)
1163 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1164 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1165 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1166 #define QUIRK_PIPEB_FORCE (1<<4)
1167 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1170 struct intel_fbc_work;
1172 struct intel_gmbus {
1173 struct i2c_adapter adapter;
1174 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1177 i915_reg_t gpio_reg;
1178 struct i2c_algo_bit_data bit_algo;
1179 struct drm_i915_private *dev_priv;
1182 struct i915_suspend_saved_registers {
1184 u32 saveFBC_CONTROL;
1185 u32 saveCACHE_MODE_0;
1186 u32 saveMI_ARB_STATE;
1190 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1191 u32 savePCH_PORT_HOTPLUG;
1195 struct vlv_s0ix_state {
1202 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1203 u32 media_max_req_count;
1204 u32 gfx_max_req_count;
1230 u32 rp_down_timeout;
1236 /* Display 1 CZ domain */
1241 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1243 /* GT SA CZ domain */
1250 /* Display 2 CZ domain */
1254 u32 clock_gate_dis2;
1257 struct intel_rps_ei {
1263 struct intel_gen6_power_mgmt {
1265 * work, interrupts_enabled and pm_iir are protected by
1266 * dev_priv->irq_lock
1268 struct work_struct work;
1269 bool interrupts_enabled;
1272 /* PM interrupt bits that should never be masked */
1275 /* Frequencies are stored in potentially platform dependent multiples.
1276 * In other words, *_freq needs to be multiplied by X to be interesting.
1277 * Soft limits are those which are used for the dynamic reclocking done
1278 * by the driver (raise frequencies under heavy loads, and lower for
1279 * lighter loads). Hard limits are those imposed by the hardware.
1281 * A distinction is made for overclocking, which is never enabled by
1282 * default, and is considered to be above the hard limit if it's
1285 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1286 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1287 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1288 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1289 u8 min_freq; /* AKA RPn. Minimum frequency */
1290 u8 boost_freq; /* Frequency to request when wait boosting */
1291 u8 idle_freq; /* Frequency to request when we are idle */
1292 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1293 u8 rp1_freq; /* "less than" RP0 power/freqency */
1294 u8 rp0_freq; /* Non-overclocked max frequency. */
1295 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1297 u8 up_threshold; /* Current %busy required to uplock */
1298 u8 down_threshold; /* Current %busy required to downclock */
1301 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1303 spinlock_t client_lock;
1304 struct list_head clients;
1308 struct delayed_work autoenable_work;
1311 /* manual wa residency calculations */
1312 struct intel_rps_ei ei;
1315 * Protects RPS/RC6 register access and PCU communication.
1316 * Must be taken after struct_mutex if nested. Note that
1317 * this lock may be held for long periods of time when
1318 * talking to hw - so only take it when talking to hw!
1320 struct mutex hw_lock;
1323 /* defined intel_pm.c */
1324 extern spinlock_t mchdev_lock;
1326 struct intel_ilk_power_mgmt {
1334 unsigned long last_time1;
1335 unsigned long chipset_power;
1338 unsigned long gfx_power;
1345 struct drm_i915_private;
1346 struct i915_power_well;
1348 struct i915_power_well_ops {
1350 * Synchronize the well's hw state to match the current sw state, for
1351 * example enable/disable it based on the current refcount. Called
1352 * during driver init and resume time, possibly after first calling
1353 * the enable/disable handlers.
1355 void (*sync_hw)(struct drm_i915_private *dev_priv,
1356 struct i915_power_well *power_well);
1358 * Enable the well and resources that depend on it (for example
1359 * interrupts located on the well). Called after the 0->1 refcount
1362 void (*enable)(struct drm_i915_private *dev_priv,
1363 struct i915_power_well *power_well);
1365 * Disable the well and resources that depend on it. Called after
1366 * the 1->0 refcount transition.
1368 void (*disable)(struct drm_i915_private *dev_priv,
1369 struct i915_power_well *power_well);
1370 /* Returns the hw enabled state. */
1371 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1372 struct i915_power_well *power_well);
1375 /* Power well structure for haswell */
1376 struct i915_power_well {
1379 /* power well enable/disable usage count */
1381 /* cached hw enabled state */
1384 /* unique identifier for this power well */
1387 * Arbitraty data associated with this power well. Platform and power
1391 const struct i915_power_well_ops *ops;
1394 struct i915_power_domains {
1396 * Power wells needed for initialization at driver init and suspend
1397 * time are on. They are kept on until after the first modeset.
1401 int power_well_count;
1404 int domain_use_count[POWER_DOMAIN_NUM];
1405 struct i915_power_well *power_wells;
1408 #define MAX_L3_SLICES 2
1409 struct intel_l3_parity {
1410 u32 *remap_info[MAX_L3_SLICES];
1411 struct work_struct error_work;
1415 struct i915_gem_mm {
1416 /** Memory allocator for GTT stolen memory */
1417 struct drm_mm stolen;
1418 /** Protects the usage of the GTT stolen memory allocator. This is
1419 * always the inner lock when overlapping with struct_mutex. */
1420 struct mutex stolen_lock;
1422 /** List of all objects in gtt_space. Used to restore gtt
1423 * mappings on resume */
1424 struct list_head bound_list;
1426 * List of objects which are not bound to the GTT (thus
1427 * are idle and not used by the GPU). These objects may or may
1428 * not actually have any pages attached.
1430 struct list_head unbound_list;
1432 /** List of all objects in gtt_space, currently mmaped by userspace.
1433 * All objects within this list must also be on bound_list.
1435 struct list_head userfault_list;
1438 * List of objects which are pending destruction.
1440 struct llist_head free_list;
1441 struct work_struct free_work;
1443 /** Usable portion of the GTT for GEM */
1444 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1446 /** PPGTT used for aliasing the PPGTT with the GTT */
1447 struct i915_hw_ppgtt *aliasing_ppgtt;
1449 struct notifier_block oom_notifier;
1450 struct notifier_block vmap_notifier;
1451 struct shrinker shrinker;
1453 /** LRU list of objects with fence regs on them. */
1454 struct list_head fence_list;
1456 u64 unordered_timeline;
1458 /* the indicator for dispatch video commands on two BSD rings */
1459 atomic_t bsd_engine_dispatch_index;
1461 /** Bit 6 swizzling required for X tiling */
1462 uint32_t bit_6_swizzle_x;
1463 /** Bit 6 swizzling required for Y tiling */
1464 uint32_t bit_6_swizzle_y;
1466 /* accounting, useful for userland debugging */
1467 spinlock_t object_stat_lock;
1472 struct drm_i915_error_state_buf {
1473 struct drm_i915_private *i915;
1482 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1483 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1485 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1486 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1488 struct i915_gpu_error {
1489 /* For hangcheck timer */
1490 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1491 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1493 struct delayed_work hangcheck_work;
1495 /* For reset and error_state handling. */
1497 /* Protected by the above dev->gpu_error.lock. */
1498 struct i915_gpu_state *first_error;
1500 unsigned long missed_irq_rings;
1503 * State variable controlling the reset flow and count
1505 * This is a counter which gets incremented when reset is triggered,
1507 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1508 * meaning that any waiters holding onto the struct_mutex should
1509 * relinquish the lock immediately in order for the reset to start.
1511 * If reset is not completed succesfully, the I915_WEDGE bit is
1512 * set meaning that hardware is terminally sour and there is no
1513 * recovery. All waiters on the reset_queue will be woken when
1516 * This counter is used by the wait_seqno code to notice that reset
1517 * event happened and it needs to restart the entire ioctl (since most
1518 * likely the seqno it waited for won't ever signal anytime soon).
1520 * This is important for lock-free wait paths, where no contended lock
1521 * naturally enforces the correct ordering between the bail-out of the
1522 * waiter and the gpu reset work code.
1524 unsigned long reset_count;
1527 * flags: Control various stages of the GPU reset
1529 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1530 * other users acquiring the struct_mutex. To do this we set the
1531 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1532 * and then check for that bit before acquiring the struct_mutex (in
1533 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1534 * secondary role in preventing two concurrent global reset attempts.
1536 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1537 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1538 * but it may be held by some long running waiter (that we cannot
1539 * interrupt without causing trouble). Once we are ready to do the GPU
1540 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1541 * they already hold the struct_mutex and want to participate they can
1542 * inspect the bit and do the reset directly, otherwise the worker
1543 * waits for the struct_mutex.
1545 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1546 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1547 * i915_gem_request_alloc(), this bit is checked and the sequence
1548 * aborted (with -EIO reported to userspace) if set.
1550 unsigned long flags;
1551 #define I915_RESET_BACKOFF 0
1552 #define I915_RESET_HANDOFF 1
1553 #define I915_WEDGED (BITS_PER_LONG - 1)
1556 * Waitqueue to signal when a hang is detected. Used to for waiters
1557 * to release the struct_mutex for the reset to procede.
1559 wait_queue_head_t wait_queue;
1562 * Waitqueue to signal when the reset has completed. Used by clients
1563 * that wait for dev_priv->mm.wedged to settle.
1565 wait_queue_head_t reset_queue;
1567 /* For missed irq/seqno simulation. */
1568 unsigned long test_irq_rings;
1571 enum modeset_restore {
1572 MODESET_ON_LID_OPEN,
1577 #define DP_AUX_A 0x40
1578 #define DP_AUX_B 0x10
1579 #define DP_AUX_C 0x20
1580 #define DP_AUX_D 0x30
1582 #define DDC_PIN_B 0x05
1583 #define DDC_PIN_C 0x04
1584 #define DDC_PIN_D 0x06
1586 struct ddi_vbt_port_info {
1588 * This is an index in the HDMI/DVI DDI buffer translation table.
1589 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1590 * populate this field.
1592 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1593 uint8_t hdmi_level_shift;
1595 uint8_t supports_dvi:1;
1596 uint8_t supports_hdmi:1;
1597 uint8_t supports_dp:1;
1598 uint8_t supports_edp:1;
1600 uint8_t alternate_aux_channel;
1601 uint8_t alternate_ddc_pin;
1603 uint8_t dp_boost_level;
1604 uint8_t hdmi_boost_level;
1607 enum psr_lines_to_wait {
1608 PSR_0_LINES_TO_WAIT = 0,
1610 PSR_4_LINES_TO_WAIT,
1614 struct intel_vbt_data {
1615 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1616 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1619 unsigned int int_tv_support:1;
1620 unsigned int lvds_dither:1;
1621 unsigned int lvds_vbt:1;
1622 unsigned int int_crt_support:1;
1623 unsigned int lvds_use_ssc:1;
1624 unsigned int display_clock_mode:1;
1625 unsigned int fdi_rx_polarity_inverted:1;
1626 unsigned int panel_type:4;
1628 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1630 enum drrs_support_type drrs_type;
1641 struct edp_power_seq pps;
1646 bool require_aux_wakeup;
1648 enum psr_lines_to_wait lines_to_wait;
1649 int tp1_wakeup_time;
1650 int tp2_tp3_wakeup_time;
1656 bool active_low_pwm;
1657 u8 min_brightness; /* min_brightness/255 of max */
1658 u8 controller; /* brightness controller number */
1659 enum intel_backlight_type type;
1665 struct mipi_config *config;
1666 struct mipi_pps_data *pps;
1670 const u8 *sequence[MIPI_SEQ_MAX];
1676 union child_device_config *child_dev;
1678 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1679 struct sdvo_device_mapping sdvo_mappings[2];
1682 enum intel_ddb_partitioning {
1684 INTEL_DDB_PART_5_6, /* IVB+ */
1687 struct intel_wm_level {
1695 struct ilk_wm_values {
1696 uint32_t wm_pipe[3];
1698 uint32_t wm_lp_spr[3];
1699 uint32_t wm_linetime[3];
1701 enum intel_ddb_partitioning partitioning;
1704 struct g4x_pipe_wm {
1705 uint16_t plane[I915_MAX_PLANES];
1715 struct vlv_wm_ddl_values {
1716 uint8_t plane[I915_MAX_PLANES];
1719 struct vlv_wm_values {
1720 struct g4x_pipe_wm pipe[3];
1721 struct g4x_sr_wm sr;
1722 struct vlv_wm_ddl_values ddl[3];
1727 struct g4x_wm_values {
1728 struct g4x_pipe_wm pipe[2];
1729 struct g4x_sr_wm sr;
1730 struct g4x_sr_wm hpll;
1736 struct skl_ddb_entry {
1737 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1740 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1742 return entry->end - entry->start;
1745 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1746 const struct skl_ddb_entry *e2)
1748 if (e1->start == e2->start && e1->end == e2->end)
1754 struct skl_ddb_allocation {
1755 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1756 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1759 struct skl_wm_values {
1760 unsigned dirty_pipes;
1761 struct skl_ddb_allocation ddb;
1764 struct skl_wm_level {
1766 uint16_t plane_res_b;
1767 uint8_t plane_res_l;
1771 * This struct helps tracking the state needed for runtime PM, which puts the
1772 * device in PCI D3 state. Notice that when this happens, nothing on the
1773 * graphics device works, even register access, so we don't get interrupts nor
1776 * Every piece of our code that needs to actually touch the hardware needs to
1777 * either call intel_runtime_pm_get or call intel_display_power_get with the
1778 * appropriate power domain.
1780 * Our driver uses the autosuspend delay feature, which means we'll only really
1781 * suspend if we stay with zero refcount for a certain amount of time. The
1782 * default value is currently very conservative (see intel_runtime_pm_enable), but
1783 * it can be changed with the standard runtime PM files from sysfs.
1785 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1786 * goes back to false exactly before we reenable the IRQs. We use this variable
1787 * to check if someone is trying to enable/disable IRQs while they're supposed
1788 * to be disabled. This shouldn't happen and we'll print some error messages in
1791 * For more, read the Documentation/power/runtime_pm.txt.
1793 struct i915_runtime_pm {
1794 atomic_t wakeref_count;
1799 enum intel_pipe_crc_source {
1800 INTEL_PIPE_CRC_SOURCE_NONE,
1801 INTEL_PIPE_CRC_SOURCE_PLANE1,
1802 INTEL_PIPE_CRC_SOURCE_PLANE2,
1803 INTEL_PIPE_CRC_SOURCE_PF,
1804 INTEL_PIPE_CRC_SOURCE_PIPE,
1805 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1806 INTEL_PIPE_CRC_SOURCE_TV,
1807 INTEL_PIPE_CRC_SOURCE_DP_B,
1808 INTEL_PIPE_CRC_SOURCE_DP_C,
1809 INTEL_PIPE_CRC_SOURCE_DP_D,
1810 INTEL_PIPE_CRC_SOURCE_AUTO,
1811 INTEL_PIPE_CRC_SOURCE_MAX,
1814 struct intel_pipe_crc_entry {
1819 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1820 struct intel_pipe_crc {
1822 bool opened; /* exclusive access to the result file */
1823 struct intel_pipe_crc_entry *entries;
1824 enum intel_pipe_crc_source source;
1826 wait_queue_head_t wq;
1830 struct i915_frontbuffer_tracking {
1834 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1841 struct i915_wa_reg {
1844 /* bitmask representing WA bits */
1849 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1850 * allowing it for RCS as we don't foresee any requirement of having
1851 * a whitelist for other engines. When it is really required for
1852 * other engines then the limit need to be increased.
1854 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1856 struct i915_workarounds {
1857 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1859 u32 hw_whitelist_count[I915_NUM_ENGINES];
1862 struct i915_virtual_gpu {
1866 /* used in computing the new watermarks state */
1867 struct intel_wm_config {
1868 unsigned int num_pipes_active;
1869 bool sprites_enabled;
1870 bool sprites_scaled;
1873 struct i915_oa_format {
1878 struct i915_oa_reg {
1883 struct i915_perf_stream;
1886 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1888 struct i915_perf_stream_ops {
1890 * @enable: Enables the collection of HW samples, either in response to
1891 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1892 * without `I915_PERF_FLAG_DISABLED`.
1894 void (*enable)(struct i915_perf_stream *stream);
1897 * @disable: Disables the collection of HW samples, either in response
1898 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1901 void (*disable)(struct i915_perf_stream *stream);
1904 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1905 * once there is something ready to read() for the stream
1907 void (*poll_wait)(struct i915_perf_stream *stream,
1912 * @wait_unlocked: For handling a blocking read, wait until there is
1913 * something to ready to read() for the stream. E.g. wait on the same
1914 * wait queue that would be passed to poll_wait().
1916 int (*wait_unlocked)(struct i915_perf_stream *stream);
1919 * @read: Copy buffered metrics as records to userspace
1920 * **buf**: the userspace, destination buffer
1921 * **count**: the number of bytes to copy, requested by userspace
1922 * **offset**: zero at the start of the read, updated as the read
1923 * proceeds, it represents how many bytes have been copied so far and
1924 * the buffer offset for copying the next record.
1926 * Copy as many buffered i915 perf samples and records for this stream
1927 * to userspace as will fit in the given buffer.
1929 * Only write complete records; returning -%ENOSPC if there isn't room
1930 * for a complete record.
1932 * Return any error condition that results in a short read such as
1933 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1934 * returning to userspace.
1936 int (*read)(struct i915_perf_stream *stream,
1942 * @destroy: Cleanup any stream specific resources.
1944 * The stream will always be disabled before this is called.
1946 void (*destroy)(struct i915_perf_stream *stream);
1950 * struct i915_perf_stream - state for a single open stream FD
1952 struct i915_perf_stream {
1954 * @dev_priv: i915 drm device
1956 struct drm_i915_private *dev_priv;
1959 * @link: Links the stream into ``&drm_i915_private->streams``
1961 struct list_head link;
1964 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1965 * properties given when opening a stream, representing the contents
1966 * of a single sample as read() by userspace.
1971 * @sample_size: Considering the configured contents of a sample
1972 * combined with the required header size, this is the total size
1973 * of a single sample record.
1978 * @ctx: %NULL if measuring system-wide across all contexts or a
1979 * specific context that is being monitored.
1981 struct i915_gem_context *ctx;
1984 * @enabled: Whether the stream is currently enabled, considering
1985 * whether the stream was opened in a disabled state and based
1986 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1991 * @ops: The callbacks providing the implementation of this specific
1992 * type of configured stream.
1994 const struct i915_perf_stream_ops *ops;
1998 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2000 struct i915_oa_ops {
2002 * @init_oa_buffer: Resets the head and tail pointers of the
2003 * circular buffer for periodic OA reports.
2005 * Called when first opening a stream for OA metrics, but also may be
2006 * called in response to an OA buffer overflow or other error
2009 * Note it may be necessary to clear the full OA buffer here as part of
2010 * maintaining the invariable that new reports must be written to
2011 * zeroed memory for us to be able to reliable detect if an expected
2012 * report has not yet landed in memory. (At least on Haswell the OA
2013 * buffer tail pointer is not synchronized with reports being visible
2016 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2019 * @enable_metric_set: Applies any MUX configuration to set up the
2020 * Boolean and Custom (B/C) counters that are part of the counter
2021 * reports being sampled. May apply system constraints such as
2022 * disabling EU clock gating as required.
2024 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2027 * @disable_metric_set: Remove system constraints associated with using
2030 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2033 * @oa_enable: Enable periodic sampling
2035 void (*oa_enable)(struct drm_i915_private *dev_priv);
2038 * @oa_disable: Disable periodic sampling
2040 void (*oa_disable)(struct drm_i915_private *dev_priv);
2043 * @read: Copy data from the circular OA buffer into a given userspace
2046 int (*read)(struct i915_perf_stream *stream,
2052 * @oa_buffer_check: Check for OA buffer data + update tail
2054 * This is either called via fops or the poll check hrtimer (atomic
2055 * ctx) without any locks taken.
2057 * It's safe to read OA config state here unlocked, assuming that this
2058 * is only called while the stream is enabled, while the global OA
2059 * configuration can't be modified.
2061 * Efficiency is more important than avoiding some false positives
2062 * here, which will be handled gracefully - likely resulting in an
2063 * %EAGAIN error for userspace.
2065 bool (*oa_buffer_check)(struct drm_i915_private *dev_priv);
2068 struct intel_cdclk_state {
2069 unsigned int cdclk, vco, ref;
2072 struct drm_i915_private {
2073 struct drm_device drm;
2075 struct kmem_cache *objects;
2076 struct kmem_cache *vmas;
2077 struct kmem_cache *requests;
2078 struct kmem_cache *dependencies;
2079 struct kmem_cache *priorities;
2081 const struct intel_device_info info;
2085 struct intel_uncore uncore;
2087 struct i915_virtual_gpu vgpu;
2089 struct intel_gvt *gvt;
2091 struct intel_huc huc;
2092 struct intel_guc guc;
2094 struct intel_csr csr;
2096 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2098 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2099 * controller on different i2c buses. */
2100 struct mutex gmbus_mutex;
2103 * Base address of the gmbus and gpio block.
2105 uint32_t gpio_mmio_base;
2107 /* MMIO base address for MIPI regs */
2108 uint32_t mipi_mmio_base;
2110 uint32_t psr_mmio_base;
2112 uint32_t pps_mmio_base;
2114 wait_queue_head_t gmbus_wait_queue;
2116 struct pci_dev *bridge_dev;
2117 struct i915_gem_context *kernel_context;
2118 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2119 struct i915_vma *semaphore;
2121 struct drm_dma_handle *status_page_dmah;
2122 struct resource mch_res;
2124 /* protects the irq masks */
2125 spinlock_t irq_lock;
2127 /* protects the mmio flip data */
2128 spinlock_t mmio_flip_lock;
2130 bool display_irqs_enabled;
2132 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2133 struct pm_qos_request pm_qos;
2135 /* Sideband mailbox protection */
2136 struct mutex sb_lock;
2138 /** Cached value of IMR to avoid reads in updating the bitfield */
2141 u32 de_irq_mask[I915_MAX_PIPES];
2148 u32 pipestat_irq_mask[I915_MAX_PIPES];
2150 struct i915_hotplug hotplug;
2151 struct intel_fbc fbc;
2152 struct i915_drrs drrs;
2153 struct intel_opregion opregion;
2154 struct intel_vbt_data vbt;
2156 bool preserve_bios_swizzle;
2159 struct intel_overlay *overlay;
2161 /* backlight registers and fields in struct intel_panel */
2162 struct mutex backlight_lock;
2165 bool no_aux_handshake;
2167 /* protects panel power sequencer state */
2168 struct mutex pps_mutex;
2170 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2171 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2173 unsigned int fsb_freq, mem_freq, is_ddr3;
2174 unsigned int skl_preferred_vco_freq;
2175 unsigned int max_cdclk_freq;
2177 unsigned int max_dotclk_freq;
2178 unsigned int rawclk_freq;
2179 unsigned int hpll_freq;
2180 unsigned int czclk_freq;
2184 * The current logical cdclk state.
2185 * See intel_atomic_state.cdclk.logical
2187 * For reading holding any crtc lock is sufficient,
2188 * for writing must hold all of them.
2190 struct intel_cdclk_state logical;
2192 * The current actual cdclk state.
2193 * See intel_atomic_state.cdclk.actual
2195 struct intel_cdclk_state actual;
2196 /* The current hardware cdclk state */
2197 struct intel_cdclk_state hw;
2201 * wq - Driver workqueue for GEM.
2203 * NOTE: Work items scheduled here are not allowed to grab any modeset
2204 * locks, for otherwise the flushing done in the pageflip code will
2205 * result in deadlocks.
2207 struct workqueue_struct *wq;
2209 /* Display functions */
2210 struct drm_i915_display_funcs display;
2212 /* PCH chipset type */
2213 enum intel_pch pch_type;
2214 unsigned short pch_id;
2216 unsigned long quirks;
2218 enum modeset_restore modeset_restore;
2219 struct mutex modeset_restore_lock;
2220 struct drm_atomic_state *modeset_restore_state;
2221 struct drm_modeset_acquire_ctx reset_ctx;
2223 struct list_head vm_list; /* Global list of all address spaces */
2224 struct i915_ggtt ggtt; /* VM representing the global address space */
2226 struct i915_gem_mm mm;
2227 DECLARE_HASHTABLE(mm_structs, 7);
2228 struct mutex mm_lock;
2230 /* The hw wants to have a stable context identifier for the lifetime
2231 * of the context (for OA, PASID, faults, etc). This is limited
2232 * in execlists to 21 bits.
2234 struct ida context_hw_ida;
2235 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2237 /* Kernel Modesetting */
2239 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2240 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2241 wait_queue_head_t pending_flip_queue;
2243 #ifdef CONFIG_DEBUG_FS
2244 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2247 /* dpll and cdclk state is protected by connection_mutex */
2248 int num_shared_dpll;
2249 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2250 const struct intel_dpll_mgr *dpll_mgr;
2253 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2254 * Must be global rather than per dpll, because on some platforms
2255 * plls share registers.
2257 struct mutex dpll_lock;
2259 unsigned int active_crtcs;
2260 unsigned int min_pixclk[I915_MAX_PIPES];
2262 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2264 struct i915_workarounds workarounds;
2266 struct i915_frontbuffer_tracking fb_tracking;
2268 struct intel_atomic_helper {
2269 struct llist_head free_list;
2270 struct work_struct free_work;
2275 bool mchbar_need_disable;
2277 struct intel_l3_parity l3_parity;
2279 /* Cannot be determined by PCIID. You must always read a register. */
2282 /* gen6+ rps state */
2283 struct intel_gen6_power_mgmt rps;
2285 /* ilk-only ips/rps state. Everything in here is protected by the global
2286 * mchdev_lock in intel_pm.c */
2287 struct intel_ilk_power_mgmt ips;
2289 struct i915_power_domains power_domains;
2291 struct i915_psr psr;
2293 struct i915_gpu_error gpu_error;
2295 struct drm_i915_gem_object *vlv_pctx;
2297 #ifdef CONFIG_DRM_FBDEV_EMULATION
2298 /* list of fbdev register on this device */
2299 struct intel_fbdev *fbdev;
2300 struct work_struct fbdev_suspend_work;
2303 struct drm_property *broadcast_rgb_property;
2304 struct drm_property *force_audio_property;
2306 /* hda/i915 audio component */
2307 struct i915_audio_component *audio_component;
2308 bool audio_component_registered;
2310 * av_mutex - mutex for audio/video sync
2313 struct mutex av_mutex;
2315 struct list_head context_list;
2319 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2320 u32 chv_phy_control;
2322 * Shadows for CHV DPLL_MD regs to keep the state
2323 * checker somewhat working in the presence hardware
2324 * crappiness (can't read out DPLL_MD for pipes B & C).
2326 u32 chv_dpll_md[I915_MAX_PIPES];
2330 bool suspended_to_idle;
2331 struct i915_suspend_saved_registers regfile;
2332 struct vlv_s0ix_state vlv_s0ix_state;
2335 I915_SAGV_UNKNOWN = 0,
2338 I915_SAGV_NOT_CONTROLLED
2343 * Raw watermark latency values:
2344 * in 0.1us units for WM0,
2345 * in 0.5us units for WM1+.
2348 uint16_t pri_latency[5];
2350 uint16_t spr_latency[5];
2352 uint16_t cur_latency[5];
2354 * Raw watermark memory latency values
2355 * for SKL for all 8 levels
2358 uint16_t skl_latency[8];
2360 /* current hardware state */
2362 struct ilk_wm_values hw;
2363 struct skl_wm_values skl_hw;
2364 struct vlv_wm_values vlv;
2365 struct g4x_wm_values g4x;
2371 * Should be held around atomic WM register writing; also
2372 * protects * intel_crtc->wm.active and
2373 * cstate->wm.need_postvbl_update.
2375 struct mutex wm_mutex;
2378 * Set during HW readout of watermarks/DDB. Some platforms
2379 * need to know when we're still using BIOS-provided values
2380 * (which we don't fully trust).
2382 bool distrust_bios_wm;
2385 struct i915_runtime_pm pm;
2390 struct kobject *metrics_kobj;
2391 struct ctl_table_header *sysctl_header;
2394 struct list_head streams;
2396 spinlock_t hook_lock;
2399 struct i915_perf_stream *exclusive_stream;
2401 u32 specific_ctx_id;
2403 struct hrtimer poll_check_timer;
2404 wait_queue_head_t poll_wq;
2408 * For rate limiting any notifications of spurious
2409 * invalid OA reports
2411 struct ratelimit_state spurious_report_rs;
2414 int period_exponent;
2418 const struct i915_oa_reg *mux_regs;
2420 const struct i915_oa_reg *b_counter_regs;
2421 int b_counter_regs_len;
2424 struct i915_vma *vma;
2430 * Locks reads and writes to all head/tail state
2432 * Consider: the head and tail pointer state
2433 * needs to be read consistently from a hrtimer
2434 * callback (atomic context) and read() fop
2435 * (user context) with tail pointer updates
2436 * happening in atomic context and head updates
2437 * in user context and the (unlikely)
2438 * possibility of read() errors needing to
2439 * reset all head/tail state.
2441 * Note: Contention or performance aren't
2442 * currently a significant concern here
2443 * considering the relatively low frequency of
2444 * hrtimer callbacks (5ms period) and that
2445 * reads typically only happen in response to a
2446 * hrtimer event and likely complete before the
2449 * Note: This lock is not held *while* reading
2450 * and copying data to userspace so the value
2451 * of head observed in htrimer callbacks won't
2452 * represent any partial consumption of data.
2454 spinlock_t ptr_lock;
2457 * One 'aging' tail pointer and one 'aged'
2458 * tail pointer ready to used for reading.
2460 * Initial values of 0xffffffff are invalid
2461 * and imply that an update is required
2462 * (and should be ignored by an attempted
2470 * Index for the aged tail ready to read()
2473 unsigned int aged_tail_idx;
2476 * A monotonic timestamp for when the current
2477 * aging tail pointer was read; used to
2478 * determine when it is old enough to trust.
2480 u64 aging_timestamp;
2483 * Although we can always read back the head
2484 * pointer register, we prefer to avoid
2485 * trusting the HW state, just to avoid any
2486 * risk that some hardware condition could
2487 * somehow bump the head pointer unpredictably
2488 * and cause us to forward the wrong OA buffer
2489 * data to userspace.
2494 u32 gen7_latched_oastatus1;
2496 struct i915_oa_ops ops;
2497 const struct i915_oa_format *oa_formats;
2502 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2504 void (*resume)(struct drm_i915_private *);
2505 void (*cleanup_engine)(struct intel_engine_cs *engine);
2507 struct list_head timelines;
2508 struct i915_gem_timeline global_timeline;
2509 u32 active_requests;
2512 * Is the GPU currently considered idle, or busy executing
2513 * userspace requests? Whilst idle, we allow runtime power
2514 * management to power down the hardware and display clocks.
2515 * In order to reduce the effect on performance, there
2516 * is a slight delay before we do so.
2521 * We leave the user IRQ off as much as possible,
2522 * but this means that requests will finish and never
2523 * be retired once the system goes idle. Set a timer to
2524 * fire periodically while the ring is running. When it
2525 * fires, go retire requests.
2527 struct delayed_work retire_work;
2530 * When we detect an idle GPU, we want to turn on
2531 * powersaving features. So once we see that there
2532 * are no more requests outstanding and no more
2533 * arrive within a small period of time, we fire
2534 * off the idle_work.
2536 struct delayed_work idle_work;
2538 ktime_t last_init_time;
2541 /* perform PHY state sanity checks? */
2542 bool chv_phy_assert[2];
2546 /* Used to save the pipe-to-encoder mapping for audio */
2547 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2549 /* necessary resource sharing with HDMI LPE audio driver. */
2551 struct platform_device *platdev;
2556 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2557 * will be rejected. Instead look for a better place.
2561 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2563 return container_of(dev, struct drm_i915_private, drm);
2566 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2568 return to_i915(dev_get_drvdata(kdev));
2571 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2573 return container_of(guc, struct drm_i915_private, guc);
2576 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2578 return container_of(huc, struct drm_i915_private, huc);
2581 /* Simple iterator over all initialised engines */
2582 #define for_each_engine(engine__, dev_priv__, id__) \
2584 (id__) < I915_NUM_ENGINES; \
2586 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2588 /* Iterator over subset of engines selected by mask */
2589 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2590 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2591 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2593 enum hdmi_force_audio {
2594 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2595 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2596 HDMI_AUDIO_AUTO, /* trust EDID */
2597 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2600 #define I915_GTT_OFFSET_NONE ((u32)-1)
2603 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2604 * considered to be the frontbuffer for the given plane interface-wise. This
2605 * doesn't mean that the hw necessarily already scans it out, but that any
2606 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2608 * We have one bit per pipe and per scanout plane type.
2610 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2611 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2612 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2613 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2614 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2615 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2616 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2617 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2618 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2619 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2620 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2621 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2624 * Optimised SGL iterator for GEM objects
2626 static __always_inline struct sgt_iter {
2627 struct scatterlist *sgp;
2634 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2635 struct sgt_iter s = { .sgp = sgl };
2638 s.max = s.curr = s.sgp->offset;
2639 s.max += s.sgp->length;
2641 s.dma = sg_dma_address(s.sgp);
2643 s.pfn = page_to_pfn(sg_page(s.sgp));
2649 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2652 if (unlikely(sg_is_chain(sg)))
2653 sg = sg_chain_ptr(sg);
2658 * __sg_next - return the next scatterlist entry in a list
2659 * @sg: The current sg entry
2662 * If the entry is the last, return NULL; otherwise, step to the next
2663 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2664 * otherwise just return the pointer to the current element.
2666 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2668 #ifdef CONFIG_DEBUG_SG
2669 BUG_ON(sg->sg_magic != SG_MAGIC);
2671 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2675 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2676 * @__dmap: DMA address (output)
2677 * @__iter: 'struct sgt_iter' (iterator state, internal)
2678 * @__sgt: sg_table to iterate over (input)
2680 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2681 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2682 ((__dmap) = (__iter).dma + (__iter).curr); \
2683 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2684 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2687 * for_each_sgt_page - iterate over the pages of the given sg_table
2688 * @__pp: page pointer (output)
2689 * @__iter: 'struct sgt_iter' (iterator state, internal)
2690 * @__sgt: sg_table to iterate over (input)
2692 #define for_each_sgt_page(__pp, __iter, __sgt) \
2693 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2694 ((__pp) = (__iter).pfn == 0 ? NULL : \
2695 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2696 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2697 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2699 static inline const struct intel_device_info *
2700 intel_info(const struct drm_i915_private *dev_priv)
2702 return &dev_priv->info;
2705 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2707 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2708 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2710 #define REVID_FOREVER 0xff
2711 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2713 #define GEN_FOREVER (0)
2715 * Returns true if Gen is in inclusive range [Start, End].
2717 * Use GEN_FOREVER for unbound start and or end.
2719 #define IS_GEN(dev_priv, s, e) ({ \
2720 unsigned int __s = (s), __e = (e); \
2721 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2722 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2723 if ((__s) != GEN_FOREVER) \
2725 if ((__e) == GEN_FOREVER) \
2726 __e = BITS_PER_LONG - 1; \
2729 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2733 * Return true if revision is in range [since,until] inclusive.
2735 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2737 #define IS_REVID(p, since, until) \
2738 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2740 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2741 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2742 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2743 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2744 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2745 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2746 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2747 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2748 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2749 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2750 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2751 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2752 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2753 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2754 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2755 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2756 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2757 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2758 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2759 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2760 INTEL_DEVID(dev_priv) == 0x0152 || \
2761 INTEL_DEVID(dev_priv) == 0x015a)
2762 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2763 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2764 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2765 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2766 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2767 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2768 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2769 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2770 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2771 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2772 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2773 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2774 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2775 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2776 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2777 /* ULX machines are also considered ULT. */
2778 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2779 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2780 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2781 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2782 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2783 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2784 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2785 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2786 /* ULX machines are also considered ULT. */
2787 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2788 INTEL_DEVID(dev_priv) == 0x0A1E)
2789 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2790 INTEL_DEVID(dev_priv) == 0x1913 || \
2791 INTEL_DEVID(dev_priv) == 0x1916 || \
2792 INTEL_DEVID(dev_priv) == 0x1921 || \
2793 INTEL_DEVID(dev_priv) == 0x1926)
2794 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2795 INTEL_DEVID(dev_priv) == 0x1915 || \
2796 INTEL_DEVID(dev_priv) == 0x191E)
2797 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2798 INTEL_DEVID(dev_priv) == 0x5913 || \
2799 INTEL_DEVID(dev_priv) == 0x5916 || \
2800 INTEL_DEVID(dev_priv) == 0x5921 || \
2801 INTEL_DEVID(dev_priv) == 0x5926)
2802 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2803 INTEL_DEVID(dev_priv) == 0x5915 || \
2804 INTEL_DEVID(dev_priv) == 0x591E)
2805 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2806 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2807 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2808 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2810 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2812 #define SKL_REVID_A0 0x0
2813 #define SKL_REVID_B0 0x1
2814 #define SKL_REVID_C0 0x2
2815 #define SKL_REVID_D0 0x3
2816 #define SKL_REVID_E0 0x4
2817 #define SKL_REVID_F0 0x5
2818 #define SKL_REVID_G0 0x6
2819 #define SKL_REVID_H0 0x7
2821 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2823 #define BXT_REVID_A0 0x0
2824 #define BXT_REVID_A1 0x1
2825 #define BXT_REVID_B0 0x3
2826 #define BXT_REVID_B_LAST 0x8
2827 #define BXT_REVID_C0 0x9
2829 #define IS_BXT_REVID(dev_priv, since, until) \
2830 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2832 #define KBL_REVID_A0 0x0
2833 #define KBL_REVID_B0 0x1
2834 #define KBL_REVID_C0 0x2
2835 #define KBL_REVID_D0 0x3
2836 #define KBL_REVID_E0 0x4
2838 #define IS_KBL_REVID(dev_priv, since, until) \
2839 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2841 #define GLK_REVID_A0 0x0
2842 #define GLK_REVID_A1 0x1
2844 #define IS_GLK_REVID(dev_priv, since, until) \
2845 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2848 * The genX designation typically refers to the render engine, so render
2849 * capability related checks should use IS_GEN, while display and other checks
2850 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2853 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2854 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2855 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2856 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2857 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2858 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2859 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2860 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2862 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2863 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2864 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2866 #define ENGINE_MASK(id) BIT(id)
2867 #define RENDER_RING ENGINE_MASK(RCS)
2868 #define BSD_RING ENGINE_MASK(VCS)
2869 #define BLT_RING ENGINE_MASK(BCS)
2870 #define VEBOX_RING ENGINE_MASK(VECS)
2871 #define BSD2_RING ENGINE_MASK(VCS2)
2872 #define ALL_ENGINES (~0)
2874 #define HAS_ENGINE(dev_priv, id) \
2875 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2877 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2878 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2879 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2880 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2882 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2883 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2884 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2885 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2886 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2888 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2890 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2891 ((dev_priv)->info.has_logical_ring_contexts)
2892 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2893 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2894 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2896 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2897 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2898 ((dev_priv)->info.overlay_needs_physical)
2900 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2901 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2903 /* WaRsDisableCoarsePowerGating:skl,bxt */
2904 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2905 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2908 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2909 * even when in MSI mode. This results in spurious interrupt warnings if the
2910 * legacy irq no. is shared with another device. The kernel then disables that
2911 * interrupt source and so prevents the other device from working properly.
2913 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2914 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2916 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2917 * rows, which changed the alignment requirements and fence programming.
2919 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2920 !(IS_I915G(dev_priv) || \
2921 IS_I915GM(dev_priv)))
2922 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2923 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2925 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2926 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2927 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2928 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2930 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2932 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2934 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2935 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2936 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2937 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2938 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2940 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2942 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2943 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2946 * For now, anything with a GuC requires uCode loading, and then supports
2947 * command submission once loaded. But these are logically independent
2948 * properties, so we have separate macros to test them.
2950 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2951 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2952 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2953 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2954 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2956 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2958 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2960 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2961 #define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
2962 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2963 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2964 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2965 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2966 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2967 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2968 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2969 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2970 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2971 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2972 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2973 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2974 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2976 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2977 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2978 #define HAS_PCH_CNP_LP(dev_priv) \
2979 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2980 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2981 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2982 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2983 #define HAS_PCH_LPT_LP(dev_priv) \
2984 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2985 #define HAS_PCH_LPT_H(dev_priv) \
2986 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2987 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2988 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2989 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2990 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2992 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2994 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2996 /* DPF == dynamic parity feature */
2997 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2998 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2999 2 : HAS_L3_DPF(dev_priv))
3001 #define GT_FREQUENCY_MULTIPLIER 50
3002 #define GEN9_FREQ_SCALER 3
3004 #include "i915_trace.h"
3006 static inline bool intel_vtd_active(void)
3008 #ifdef CONFIG_INTEL_IOMMU
3009 if (intel_iommu_gfx_mapped)
3015 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
3017 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
3021 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
3023 return IS_BROXTON(dev_priv) && intel_vtd_active();
3026 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
3029 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
3033 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
3034 const char *fmt, ...);
3036 #define i915_report_error(dev_priv, fmt, ...) \
3037 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3039 #ifdef CONFIG_COMPAT
3040 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
3043 #define i915_compat_ioctl NULL
3045 extern const struct dev_pm_ops i915_pm_ops;
3047 extern int i915_driver_load(struct pci_dev *pdev,
3048 const struct pci_device_id *ent);
3049 extern void i915_driver_unload(struct drm_device *dev);
3050 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3051 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3052 extern void i915_reset(struct drm_i915_private *dev_priv);
3053 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3054 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3055 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3056 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3057 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3058 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3059 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3060 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3062 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
3063 int intel_engines_init(struct drm_i915_private *dev_priv);
3065 /* intel_hotplug.c */
3066 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3067 u32 pin_mask, u32 long_mask);
3068 void intel_hpd_init(struct drm_i915_private *dev_priv);
3069 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3070 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3071 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3072 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3073 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3076 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3078 unsigned long delay;
3080 if (unlikely(!i915.enable_hangcheck))
3083 /* Don't continually defer the hangcheck so that it is always run at
3084 * least once after work has been scheduled on any ring. Otherwise,
3085 * we will ignore a hung ring if a second ring is kept busy.
3088 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3089 queue_delayed_work(system_long_wq,
3090 &dev_priv->gpu_error.hangcheck_work, delay);
3094 void i915_handle_error(struct drm_i915_private *dev_priv,
3096 const char *fmt, ...);
3098 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3099 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3100 int intel_irq_install(struct drm_i915_private *dev_priv);
3101 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3103 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3105 return dev_priv->gvt;
3108 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3110 return dev_priv->vgpu.active;
3114 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3118 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3121 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3122 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3123 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3126 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3127 uint32_t interrupt_mask,
3128 uint32_t enabled_irq_mask);
3130 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3132 ilk_update_display_irq(dev_priv, bits, bits);
3135 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3137 ilk_update_display_irq(dev_priv, bits, 0);
3139 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3141 uint32_t interrupt_mask,
3142 uint32_t enabled_irq_mask);
3143 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3144 enum pipe pipe, uint32_t bits)
3146 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3148 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3149 enum pipe pipe, uint32_t bits)
3151 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3153 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3154 uint32_t interrupt_mask,
3155 uint32_t enabled_irq_mask);
3157 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3159 ibx_display_interrupt_update(dev_priv, bits, bits);
3162 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3164 ibx_display_interrupt_update(dev_priv, bits, 0);
3168 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3169 struct drm_file *file_priv);
3170 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3171 struct drm_file *file_priv);
3172 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3173 struct drm_file *file_priv);
3174 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3175 struct drm_file *file_priv);
3176 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3177 struct drm_file *file_priv);
3178 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3179 struct drm_file *file_priv);
3180 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3181 struct drm_file *file_priv);
3182 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3183 struct drm_file *file_priv);
3184 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3185 struct drm_file *file_priv);
3186 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3187 struct drm_file *file_priv);
3188 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3189 struct drm_file *file);
3190 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3191 struct drm_file *file);
3192 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3193 struct drm_file *file_priv);
3194 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3195 struct drm_file *file_priv);
3196 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3197 struct drm_file *file_priv);
3198 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3199 struct drm_file *file_priv);
3200 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3201 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3202 struct drm_file *file);
3203 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3204 struct drm_file *file_priv);
3205 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3206 struct drm_file *file_priv);
3207 void i915_gem_sanitize(struct drm_i915_private *i915);
3208 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3209 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3210 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3211 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3212 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3214 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3215 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3216 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3217 const struct drm_i915_gem_object_ops *ops);
3218 struct drm_i915_gem_object *
3219 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3220 struct drm_i915_gem_object *
3221 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3222 const void *data, size_t size);
3223 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3224 void i915_gem_free_object(struct drm_gem_object *obj);
3226 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3228 /* A single pass should suffice to release all the freed objects (along
3229 * most call paths) , but be a little more paranoid in that freeing
3230 * the objects does take a little amount of time, during which the rcu
3231 * callbacks could have added new objects into the freed list, and
3232 * armed the work again.
3236 } while (flush_work(&i915->mm.free_work));
3239 struct i915_vma * __must_check
3240 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3241 const struct i915_ggtt_view *view,
3246 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3247 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3249 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3251 static inline int __sg_page_count(const struct scatterlist *sg)
3253 return sg->length >> PAGE_SHIFT;
3256 struct scatterlist *
3257 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3258 unsigned int n, unsigned int *offset);
3261 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3265 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3269 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3272 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3273 struct sg_table *pages);
3274 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3276 static inline int __must_check
3277 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3279 might_lock(&obj->mm.lock);
3281 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3284 return __i915_gem_object_get_pages(obj);
3288 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3290 GEM_BUG_ON(!obj->mm.pages);
3292 atomic_inc(&obj->mm.pages_pin_count);
3296 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3298 return atomic_read(&obj->mm.pages_pin_count);
3302 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3304 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3305 GEM_BUG_ON(!obj->mm.pages);
3307 atomic_dec(&obj->mm.pages_pin_count);
3311 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3313 __i915_gem_object_unpin_pages(obj);
3316 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3321 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3322 enum i915_mm_subclass subclass);
3323 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3325 enum i915_map_type {
3331 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3332 * @obj: the object to map into kernel address space
3333 * @type: the type of mapping, used to select pgprot_t
3335 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3336 * pages and then returns a contiguous mapping of the backing storage into
3337 * the kernel address space. Based on the @type of mapping, the PTE will be
3338 * set to either WriteBack or WriteCombine (via pgprot_t).
3340 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3341 * mapping is no longer required.
3343 * Returns the pointer through which to access the mapped object, or an
3344 * ERR_PTR() on error.
3346 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3347 enum i915_map_type type);
3350 * i915_gem_object_unpin_map - releases an earlier mapping
3351 * @obj: the object to unmap
3353 * After pinning the object and mapping its pages, once you are finished
3354 * with your access, call i915_gem_object_unpin_map() to release the pin
3355 * upon the mapping. Once the pin count reaches zero, that mapping may be
3358 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3360 i915_gem_object_unpin_pages(obj);
3363 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3364 unsigned int *needs_clflush);
3365 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3366 unsigned int *needs_clflush);
3367 #define CLFLUSH_BEFORE BIT(0)
3368 #define CLFLUSH_AFTER BIT(1)
3369 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3372 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3374 i915_gem_object_unpin_pages(obj);
3377 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3378 void i915_vma_move_to_active(struct i915_vma *vma,
3379 struct drm_i915_gem_request *req,
3380 unsigned int flags);
3381 int i915_gem_dumb_create(struct drm_file *file_priv,
3382 struct drm_device *dev,
3383 struct drm_mode_create_dumb *args);
3384 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3385 uint32_t handle, uint64_t *offset);
3386 int i915_gem_mmap_gtt_version(void);
3388 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3389 struct drm_i915_gem_object *new,
3390 unsigned frontbuffer_bits);
3392 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3394 struct drm_i915_gem_request *
3395 i915_gem_find_active_request(struct intel_engine_cs *engine);
3397 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3399 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3401 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3404 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3406 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3409 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3411 return unlikely(test_bit(I915_WEDGED, &error->flags));
3414 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3416 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3419 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3421 return READ_ONCE(error->reset_count);
3424 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3425 void i915_gem_reset(struct drm_i915_private *dev_priv);
3426 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3427 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3428 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3430 void i915_gem_init_mmio(struct drm_i915_private *i915);
3431 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3432 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3433 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3434 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3435 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3436 unsigned int flags);
3437 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3438 void i915_gem_resume(struct drm_i915_private *dev_priv);
3439 int i915_gem_fault(struct vm_fault *vmf);
3440 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3443 struct intel_rps_client *rps);
3444 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3447 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3450 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3452 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3454 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3455 struct i915_vma * __must_check
3456 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3458 const struct i915_ggtt_view *view);
3459 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3460 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3462 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3463 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3465 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3466 enum i915_cache_level cache_level);
3468 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3469 struct dma_buf *dma_buf);
3471 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3472 struct drm_gem_object *gem_obj, int flags);
3474 static inline struct i915_hw_ppgtt *
3475 i915_vm_to_ppgtt(struct i915_address_space *vm)
3477 return container_of(vm, struct i915_hw_ppgtt, base);
3480 /* i915_gem_fence_reg.c */
3481 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3482 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3484 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3485 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3487 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3488 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3489 struct sg_table *pages);
3490 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3491 struct sg_table *pages);
3493 static inline struct i915_gem_context *
3494 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3496 struct i915_gem_context *ctx;
3498 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3500 ctx = idr_find(&file_priv->context_idr, id);
3502 return ERR_PTR(-ENOENT);
3507 static inline struct i915_gem_context *
3508 i915_gem_context_get(struct i915_gem_context *ctx)
3510 kref_get(&ctx->ref);
3514 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3516 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3517 kref_put(&ctx->ref, i915_gem_context_free);
3520 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3522 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3524 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3528 static inline struct intel_timeline *
3529 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3530 struct intel_engine_cs *engine)
3532 struct i915_address_space *vm;
3534 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3535 return &vm->timeline.engine[engine->id];
3538 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3539 struct drm_file *file);
3541 /* i915_gem_evict.c */
3542 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3543 u64 min_size, u64 alignment,
3544 unsigned cache_level,
3547 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3548 struct drm_mm_node *node,
3549 unsigned int flags);
3550 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3552 /* belongs in i915_gem_gtt.h */
3553 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3556 if (INTEL_GEN(dev_priv) < 6)
3557 intel_gtt_chipset_flush();
3560 /* i915_gem_stolen.c */
3561 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3562 struct drm_mm_node *node, u64 size,
3563 unsigned alignment);
3564 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3565 struct drm_mm_node *node, u64 size,
3566 unsigned alignment, u64 start,
3568 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3569 struct drm_mm_node *node);
3570 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3571 void i915_gem_cleanup_stolen(struct drm_device *dev);
3572 struct drm_i915_gem_object *
3573 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3574 struct drm_i915_gem_object *
3575 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3580 /* i915_gem_internal.c */
3581 struct drm_i915_gem_object *
3582 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3585 /* i915_gem_shrinker.c */
3586 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3587 unsigned long target,
3589 #define I915_SHRINK_PURGEABLE 0x1
3590 #define I915_SHRINK_UNBOUND 0x2
3591 #define I915_SHRINK_BOUND 0x4
3592 #define I915_SHRINK_ACTIVE 0x8
3593 #define I915_SHRINK_VMAPS 0x10
3594 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3595 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3596 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3599 /* i915_gem_tiling.c */
3600 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3602 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3604 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3605 i915_gem_object_is_tiled(obj);
3608 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3609 unsigned int tiling, unsigned int stride);
3610 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3611 unsigned int tiling, unsigned int stride);
3613 /* i915_debugfs.c */
3614 #ifdef CONFIG_DEBUG_FS
3615 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3616 int i915_debugfs_connector_add(struct drm_connector *connector);
3617 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3619 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3620 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3622 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3625 /* i915_gpu_error.c */
3626 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3629 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3630 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3631 const struct i915_gpu_state *gpu);
3632 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3633 struct drm_i915_private *i915,
3634 size_t count, loff_t pos);
3635 static inline void i915_error_state_buf_release(
3636 struct drm_i915_error_state_buf *eb)
3641 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3642 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3644 const char *error_msg);
3646 static inline struct i915_gpu_state *
3647 i915_gpu_state_get(struct i915_gpu_state *gpu)
3649 kref_get(&gpu->ref);
3653 void __i915_gpu_state_free(struct kref *kref);
3654 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3657 kref_put(&gpu->ref, __i915_gpu_state_free);
3660 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3661 void i915_reset_error_state(struct drm_i915_private *i915);
3665 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3667 const char *error_msg)
3671 static inline struct i915_gpu_state *
3672 i915_first_error_state(struct drm_i915_private *i915)
3677 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3683 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3685 /* i915_cmd_parser.c */
3686 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3687 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3688 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3689 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3690 struct drm_i915_gem_object *batch_obj,
3691 struct drm_i915_gem_object *shadow_batch_obj,
3692 u32 batch_start_offset,
3697 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3698 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3699 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3700 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3702 /* i915_suspend.c */
3703 extern int i915_save_state(struct drm_i915_private *dev_priv);
3704 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3707 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3708 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3710 /* intel_lpe_audio.c */
3711 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3712 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3713 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3714 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3715 enum pipe pipe, enum port port,
3716 const void *eld, int ls_clock, bool dp_output);
3719 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3720 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3721 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3724 extern struct i2c_adapter *
3725 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3726 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3727 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3728 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3730 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3732 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3735 void intel_bios_init(struct drm_i915_private *dev_priv);
3736 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3737 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3738 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3739 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3740 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3741 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3742 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3743 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3745 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3749 /* intel_opregion.c */
3751 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3752 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3753 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3754 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3755 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3757 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3759 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3761 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3762 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3763 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3764 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3768 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3773 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3777 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3785 extern void intel_register_dsm_handler(void);
3786 extern void intel_unregister_dsm_handler(void);
3788 static inline void intel_register_dsm_handler(void) { return; }
3789 static inline void intel_unregister_dsm_handler(void) { return; }
3790 #endif /* CONFIG_ACPI */
3792 /* intel_device_info.c */
3793 static inline struct intel_device_info *
3794 mkwrite_device_info(struct drm_i915_private *dev_priv)
3796 return (struct intel_device_info *)&dev_priv->info;
3799 const char *intel_platform_name(enum intel_platform platform);
3800 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3801 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3804 extern void intel_modeset_init_hw(struct drm_device *dev);
3805 extern int intel_modeset_init(struct drm_device *dev);
3806 extern void intel_modeset_gem_init(struct drm_device *dev);
3807 extern void intel_modeset_cleanup(struct drm_device *dev);
3808 extern int intel_connector_register(struct drm_connector *);
3809 extern void intel_connector_unregister(struct drm_connector *);
3810 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3812 extern void intel_display_resume(struct drm_device *dev);
3813 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3814 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3815 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3816 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3817 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3818 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3821 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3822 struct drm_file *file);
3825 extern struct intel_overlay_error_state *
3826 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3827 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3828 struct intel_overlay_error_state *error);
3830 extern struct intel_display_error_state *
3831 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3832 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3833 struct intel_display_error_state *error);
3835 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3836 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3837 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3838 u32 reply_mask, u32 reply, int timeout_base_ms);
3840 /* intel_sideband.c */
3841 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3842 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3843 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3844 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3845 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3846 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3847 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3848 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3849 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3850 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3851 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3852 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3853 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3854 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3855 enum intel_sbi_destination destination);
3856 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3857 enum intel_sbi_destination destination);
3858 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3859 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3861 /* intel_dpio_phy.c */
3862 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3863 enum dpio_phy *phy, enum dpio_channel *ch);
3864 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3865 enum port port, u32 margin, u32 scale,
3866 u32 enable, u32 deemphasis);
3867 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3868 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3869 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3871 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3873 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3874 uint8_t lane_count);
3875 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3876 uint8_t lane_lat_optim_mask);
3877 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3879 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3880 u32 deemph_reg_value, u32 margin_reg_value,
3881 bool uniq_trans_scale);
3882 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3884 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3885 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3886 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3887 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3889 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3890 u32 demph_reg_value, u32 preemph_reg_value,
3891 u32 uniqtranscale_reg_value, u32 tx3_demph);
3892 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3893 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3894 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3896 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3897 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3898 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3899 const i915_reg_t reg);
3901 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3902 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3904 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3905 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3906 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3907 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3909 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3910 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3911 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3912 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3914 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3915 * will be implemented using 2 32-bit writes in an arbitrary order with
3916 * an arbitrary delay between them. This can cause the hardware to
3917 * act upon the intermediate value, possibly leading to corruption and
3918 * machine death. For this reason we do not support I915_WRITE64, or
3919 * dev_priv->uncore.funcs.mmio_writeq.
3921 * When reading a 64-bit value as two 32-bit values, the delay may cause
3922 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3923 * occasionally a 64-bit register does not actualy support a full readq
3924 * and must be read using two 32-bit reads.
3926 * You have been warned.
3928 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3930 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3931 u32 upper, lower, old_upper, loop = 0; \
3932 upper = I915_READ(upper_reg); \
3934 old_upper = upper; \
3935 lower = I915_READ(lower_reg); \
3936 upper = I915_READ(upper_reg); \
3937 } while (upper != old_upper && loop++ < 2); \
3938 (u64)upper << 32 | lower; })
3940 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3941 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3943 #define __raw_read(x, s) \
3944 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3947 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3950 #define __raw_write(x, s) \
3951 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3952 i915_reg_t reg, uint##x##_t val) \
3954 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3969 /* These are untraced mmio-accessors that are only valid to be used inside
3970 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3973 * Think twice, and think again, before using these.
3975 * As an example, these accessors can possibly be used between:
3977 * spin_lock_irq(&dev_priv->uncore.lock);
3978 * intel_uncore_forcewake_get__locked();
3982 * intel_uncore_forcewake_put__locked();
3983 * spin_unlock_irq(&dev_priv->uncore.lock);
3986 * Note: some registers may not need forcewake held, so
3987 * intel_uncore_forcewake_{get,put} can be omitted, see
3988 * intel_uncore_forcewake_for_reg().
3990 * Certain architectures will die if the same cacheline is concurrently accessed
3991 * by different clients (e.g. on Ivybridge). Access to registers should
3992 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3993 * a more localised lock guarding all access to that bank of registers.
3995 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3996 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3997 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3998 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4000 /* "Broadcast RGB" property */
4001 #define INTEL_BROADCAST_RGB_AUTO 0
4002 #define INTEL_BROADCAST_RGB_FULL 1
4003 #define INTEL_BROADCAST_RGB_LIMITED 2
4005 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4007 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4008 return VLV_VGACNTRL;
4009 else if (INTEL_GEN(dev_priv) >= 5)
4010 return CPU_VGACNTRL;
4015 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
4017 unsigned long j = msecs_to_jiffies(m);
4019 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4022 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4024 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4027 static inline unsigned long
4028 timespec_to_jiffies_timeout(const struct timespec *value)
4030 unsigned long j = timespec_to_jiffies(value);
4032 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4036 * If you need to wait X milliseconds between events A and B, but event B
4037 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4038 * when event A happened, then just before event B you call this function and
4039 * pass the timestamp as the first argument, and X as the second argument.
4042 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4044 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4047 * Don't re-read the value of "jiffies" every time since it may change
4048 * behind our back and break the math.
4050 tmp_jiffies = jiffies;
4051 target_jiffies = timestamp_jiffies +
4052 msecs_to_jiffies_timeout(to_wait_ms);
4054 if (time_after(target_jiffies, tmp_jiffies)) {
4055 remaining_jiffies = target_jiffies - tmp_jiffies;
4056 while (remaining_jiffies)
4058 schedule_timeout_uninterruptible(remaining_jiffies);
4063 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4065 struct intel_engine_cs *engine = req->engine;
4068 /* Note that the engine may have wrapped around the seqno, and
4069 * so our request->global_seqno will be ahead of the hardware,
4070 * even though it completed the request before wrapping. We catch
4071 * this by kicking all the waiters before resetting the seqno
4072 * in hardware, and also signal the fence.
4074 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4077 /* The request was dequeued before we were awoken. We check after
4078 * inspecting the hw to confirm that this was the same request
4079 * that generated the HWS update. The memory barriers within
4080 * the request execution are sufficient to ensure that a check
4081 * after reading the value from hw matches this request.
4083 seqno = i915_gem_request_global_seqno(req);
4087 /* Before we do the heavier coherent read of the seqno,
4088 * check the value (hopefully) in the CPU cacheline.
4090 if (__i915_gem_request_completed(req, seqno))
4093 /* Ensure our read of the seqno is coherent so that we
4094 * do not "miss an interrupt" (i.e. if this is the last
4095 * request and the seqno write from the GPU is not visible
4096 * by the time the interrupt fires, we will see that the
4097 * request is incomplete and go back to sleep awaiting
4098 * another interrupt that will never come.)
4100 * Strictly, we only need to do this once after an interrupt,
4101 * but it is easier and safer to do it every time the waiter
4104 if (engine->irq_seqno_barrier &&
4105 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4106 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4108 /* The ordering of irq_posted versus applying the barrier
4109 * is crucial. The clearing of the current irq_posted must
4110 * be visible before we perform the barrier operation,
4111 * such that if a subsequent interrupt arrives, irq_posted
4112 * is reasserted and our task rewoken (which causes us to
4113 * do another __i915_request_irq_complete() immediately
4114 * and reapply the barrier). Conversely, if the clear
4115 * occurs after the barrier, then an interrupt that arrived
4116 * whilst we waited on the barrier would not trigger a
4117 * barrier on the next pass, and the read may not see the
4120 engine->irq_seqno_barrier(engine);
4122 /* If we consume the irq, but we are no longer the bottom-half,
4123 * the real bottom-half may not have serialised their own
4124 * seqno check with the irq-barrier (i.e. may have inspected
4125 * the seqno before we believe it coherent since they see
4126 * irq_posted == false but we are still running).
4128 spin_lock_irq(&b->irq_lock);
4129 if (b->irq_wait && b->irq_wait->tsk != current)
4130 /* Note that if the bottom-half is changed as we
4131 * are sending the wake-up, the new bottom-half will
4132 * be woken by whomever made the change. We only have
4133 * to worry about when we steal the irq-posted for
4136 wake_up_process(b->irq_wait->tsk);
4137 spin_unlock_irq(&b->irq_lock);
4139 if (__i915_gem_request_completed(req, seqno))
4146 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4147 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4149 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4150 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4151 * perform the operation. To check beforehand, pass in the parameters to
4152 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4153 * you only need to pass in the minor offsets, page-aligned pointers are
4156 * For just checking for SSE4.1, in the foreknowledge that the future use
4157 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4159 #define i915_can_memcpy_from_wc(dst, src, len) \
4160 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4162 #define i915_has_memcpy_from_wc() \
4163 i915_memcpy_from_wc(NULL, NULL, 0)
4166 int remap_io_mapping(struct vm_area_struct *vma,
4167 unsigned long addr, unsigned long pfn, unsigned long size,
4168 struct io_mapping *iomap);
4170 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4172 return (obj->cache_level != I915_CACHE_NONE ||
4173 HAS_LLC(to_i915(obj->base.dev)));