1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <asm/hypervisor.h>
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <linux/backlight.h>
42 #include <linux/hash.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/mm_types.h>
46 #include <linux/perf_event.h>
47 #include <linux/pm_qos.h>
48 #include <linux/dma-resv.h>
49 #include <linux/shmem_fs.h>
50 #include <linux/stackdepot.h>
51 #include <linux/xarray.h>
53 #include <drm/intel-gtt.h>
54 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
55 #include <drm/drm_gem.h>
56 #include <drm/drm_auth.h>
57 #include <drm/drm_cache.h>
58 #include <drm/drm_util.h>
59 #include <drm/drm_dsc.h>
60 #include <drm/drm_atomic.h>
61 #include <drm/drm_connector.h>
62 #include <drm/i915_mei_hdcp_interface.h>
64 #include "i915_params.h"
66 #include "i915_utils.h"
68 #include "display/intel_bios.h"
69 #include "display/intel_display.h"
70 #include "display/intel_display_power.h"
71 #include "display/intel_dpll_mgr.h"
72 #include "display/intel_dsb.h"
73 #include "display/intel_frontbuffer.h"
74 #include "display/intel_global_state.h"
75 #include "display/intel_gmbus.h"
76 #include "display/intel_opregion.h"
78 #include "gem/i915_gem_context_types.h"
79 #include "gem/i915_gem_shrinker.h"
80 #include "gem/i915_gem_stolen.h"
82 #include "gt/intel_engine.h"
83 #include "gt/intel_gt_types.h"
84 #include "gt/intel_region_lmem.h"
85 #include "gt/intel_workarounds.h"
86 #include "gt/uc/intel_uc.h"
88 #include "intel_device_info.h"
89 #include "intel_memory_region.h"
90 #include "intel_pch.h"
91 #include "intel_runtime_pm.h"
92 #include "intel_step.h"
93 #include "intel_uncore.h"
94 #include "intel_wakeref.h"
95 #include "intel_wopcm.h"
98 #include "i915_gem_gtt.h"
99 #include "i915_gpu_error.h"
100 #include "i915_perf_types.h"
101 #include "i915_request.h"
102 #include "i915_scheduler.h"
103 #include "gt/intel_timeline.h"
104 #include "i915_vma.h"
105 #include "i915_irq.h"
108 /* General customization:
111 #define DRIVER_NAME "i915"
112 #define DRIVER_DESC "Intel Graphics"
113 #define DRIVER_DATE "20201103"
114 #define DRIVER_TIMESTAMP 1604406085
116 struct drm_i915_gem_object;
120 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
139 #define for_each_hpd_pin(__pin) \
140 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
142 /* Threshold == 5 for long IRQs, 50 for short */
143 #define HPD_STORM_DEFAULT_THRESHOLD 50
145 struct i915_hotplug {
146 struct delayed_work hotplug_work;
148 const u32 *hpd, *pch_hpd;
151 unsigned long last_jiffies;
156 HPD_MARK_DISABLED = 2
158 } stats[HPD_NUM_PINS];
161 struct delayed_work reenable_work;
165 struct work_struct dig_port_work;
167 struct work_struct poll_init_work;
170 unsigned int hpd_storm_threshold;
171 /* Whether or not to count short HPD IRQs in HPD storms */
172 u8 hpd_short_storm_enabled;
175 * if we get a HPD irq from DP and a HPD irq from non-DP
176 * the non-DP HPD could block the workqueue on a mode config
177 * mutex getting, that userspace may have taken. However
178 * userspace is waiting on the DP workqueue to run which is
179 * blocked behind the non-DP one.
181 struct workqueue_struct *dp_wq;
184 #define I915_GEM_GPU_DOMAINS \
185 (I915_GEM_DOMAIN_RENDER | \
186 I915_GEM_DOMAIN_SAMPLER | \
187 I915_GEM_DOMAIN_COMMAND | \
188 I915_GEM_DOMAIN_INSTRUCTION | \
189 I915_GEM_DOMAIN_VERTEX)
191 struct drm_i915_private;
192 struct i915_mm_struct;
193 struct i915_mmu_object;
195 struct drm_i915_file_private {
196 struct drm_i915_private *dev_priv;
199 struct drm_file *file;
203 struct xarray context_xa;
206 unsigned int bsd_engine;
209 * Every context ban increments per client ban score. Also
210 * hangs in short succession increments ban score. If ban threshold
211 * is reached, client is considered banned and submitting more work
212 * will fail. This is a stop gap measure to limit the badly behaving
213 * clients access to gpu. Note that unbannable contexts never increment
214 * the client ban score.
216 #define I915_CLIENT_SCORE_HANG_FAST 1
217 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
218 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
219 #define I915_CLIENT_SCORE_BANNED 9
220 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
222 unsigned long hang_timestamp;
225 /* Interface history:
228 * 1.2: Add Power Management
229 * 1.3: Add vblank support
230 * 1.4: Fix cmdbuffer path, add heap destroy
231 * 1.5: Add vblank pipe configuration
232 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
233 * - Support vertical blank on secondary display pipe
235 #define DRIVER_MAJOR 1
236 #define DRIVER_MINOR 6
237 #define DRIVER_PATCHLEVEL 0
239 struct intel_overlay;
240 struct intel_overlay_error_state;
242 struct sdvo_device_mapping {
251 struct intel_connector;
252 struct intel_encoder;
253 struct intel_atomic_state;
254 struct intel_cdclk_config;
255 struct intel_cdclk_state;
256 struct intel_cdclk_vals;
257 struct intel_initial_plane_config;
262 struct drm_i915_display_funcs {
263 void (*get_cdclk)(struct drm_i915_private *dev_priv,
264 struct intel_cdclk_config *cdclk_config);
265 void (*set_cdclk)(struct drm_i915_private *dev_priv,
266 const struct intel_cdclk_config *cdclk_config,
268 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
269 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
270 enum i9xx_plane_id i9xx_plane);
271 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
272 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
273 void (*initial_watermarks)(struct intel_atomic_state *state,
274 struct intel_crtc *crtc);
275 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
276 struct intel_crtc *crtc);
277 void (*optimize_watermarks)(struct intel_atomic_state *state,
278 struct intel_crtc *crtc);
279 int (*compute_global_watermarks)(struct intel_atomic_state *state);
280 void (*update_wm)(struct intel_crtc *crtc);
281 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
282 u8 (*calc_voltage_level)(int cdclk);
283 /* Returns the active state of the crtc, and if the crtc is active,
284 * fills out the pipe-config with the hw state. */
285 bool (*get_pipe_config)(struct intel_crtc *,
286 struct intel_crtc_state *);
287 void (*get_initial_plane_config)(struct intel_crtc *,
288 struct intel_initial_plane_config *);
289 int (*crtc_compute_clock)(struct intel_crtc *crtc,
290 struct intel_crtc_state *crtc_state);
291 void (*crtc_enable)(struct intel_atomic_state *state,
292 struct intel_crtc *crtc);
293 void (*crtc_disable)(struct intel_atomic_state *state,
294 struct intel_crtc *crtc);
295 void (*commit_modeset_enables)(struct intel_atomic_state *state);
296 void (*commit_modeset_disables)(struct intel_atomic_state *state);
297 void (*audio_codec_enable)(struct intel_encoder *encoder,
298 const struct intel_crtc_state *crtc_state,
299 const struct drm_connector_state *conn_state);
300 void (*audio_codec_disable)(struct intel_encoder *encoder,
301 const struct intel_crtc_state *old_crtc_state,
302 const struct drm_connector_state *old_conn_state);
303 void (*fdi_link_train)(struct intel_crtc *crtc,
304 const struct intel_crtc_state *crtc_state);
305 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
306 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
307 /* clock updates for mode set */
309 /* render clock increase/decrease */
310 /* display clock increase/decrease */
311 /* pll clock increase/decrease */
313 int (*color_check)(struct intel_crtc_state *crtc_state);
315 * Program double buffered color management registers during
316 * vblank evasion. The registers should then latch during the
317 * next vblank start, alongside any other double buffered registers
318 * involved with the same commit.
320 void (*color_commit)(const struct intel_crtc_state *crtc_state);
322 * Load LUTs (and other single buffered color management
323 * registers). Will (hopefully) be called during the vblank
324 * following the latching of any double buffered registers
325 * involved with the same commit.
327 void (*load_luts)(const struct intel_crtc_state *crtc_state);
328 void (*read_luts)(struct intel_crtc_state *crtc_state);
332 struct work_struct work;
334 u32 required_version;
335 u32 max_fw_size; /* bytes */
337 u32 dmc_fw_size; /* dwords */
340 i915_reg_t mmioaddr[20];
345 intel_wakeref_t wakeref;
348 enum i915_cache_level {
350 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
351 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
352 caches, eg sampler/render caches, and the
353 large Last-Level-Cache. LLC is coherent with
354 the CPU, but L3 is only visible to the GPU. */
355 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
361 /* This is always the inner lock when overlapping with struct_mutex and
362 * it's the outer lock when overlapping with stolen_lock. */
365 unsigned int possible_framebuffer_bits;
366 unsigned int busy_bits;
367 struct intel_crtc *crtc;
369 struct drm_mm_node compressed_fb;
370 struct drm_mm_node *compressed_llb;
378 bool underrun_detected;
379 struct work_struct underrun_work;
382 * Due to the atomic rules we can't access some structures without the
383 * appropriate locking, so we cache information here in order to avoid
386 struct intel_fbc_state_cache {
388 unsigned int mode_flags;
389 u32 hsw_bdw_pixel_rate;
393 unsigned int rotation;
398 * Display surface base address adjustement for
399 * pageflips. Note that on gen4+ this only adjusts up
400 * to a tile, offsets within a tile are handled in
401 * the hw itself (with the TILEOFF register).
406 u16 pixel_blend_mode;
410 const struct drm_format_info *format;
415 unsigned int fence_y_offset;
416 u16 gen9_wa_cfb_stride;
423 * This structure contains everything that's relevant to program the
424 * hardware registers. When we want to figure out if we need to disable
425 * and re-enable FBC for a new configuration we just check if there's
426 * something different in the struct. The genx_fbc_activate functions
427 * are supposed to read from it in order to program the registers.
429 struct intel_fbc_reg_params {
432 enum i9xx_plane_id i9xx_plane;
436 const struct drm_format_info *format;
442 unsigned int fence_y_offset;
443 u16 gen9_wa_cfb_stride;
449 const char *no_fbc_reason;
453 * HIGH_RR is the highest eDP panel refresh rate read from EDID
454 * LOW_RR is the lowest eDP panel refresh rate found from EDID
455 * parsing for same resolution.
457 enum drrs_refresh_rate_type {
460 DRRS_MAX_RR, /* RR count */
463 enum drrs_support_type {
464 DRRS_NOT_SUPPORTED = 0,
465 STATIC_DRRS_SUPPORT = 1,
466 SEAMLESS_DRRS_SUPPORT = 2
472 struct delayed_work work;
474 unsigned busy_frontbuffer_bits;
475 enum drrs_refresh_rate_type refresh_rate_type;
476 enum drrs_support_type type;
479 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
480 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
481 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
482 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
483 #define QUIRK_INCREASE_T12_DELAY (1<<6)
484 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
487 struct intel_fbc_work;
490 struct i2c_adapter adapter;
491 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
495 struct i2c_algo_bit_data bit_algo;
496 struct drm_i915_private *dev_priv;
499 struct i915_suspend_saved_registers {
507 struct vlv_s0ix_state;
509 #define MAX_L3_SLICES 2
510 struct intel_l3_parity {
511 u32 *remap_info[MAX_L3_SLICES];
512 struct work_struct error_work;
517 /** Memory allocator for GTT stolen memory */
518 struct drm_mm stolen;
519 /** Protects the usage of the GTT stolen memory allocator. This is
520 * always the inner lock when overlapping with struct_mutex. */
521 struct mutex stolen_lock;
523 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
527 * List of objects which are purgeable.
529 struct list_head purge_list;
532 * List of objects which have allocated pages and are shrinkable.
534 struct list_head shrink_list;
537 * List of objects which are pending destruction.
539 struct llist_head free_list;
540 struct work_struct free_work;
542 * Count of objects pending destructions. Used to skip needlessly
543 * waiting on an RCU barrier if no objects are waiting to be freed.
548 * tmpfs instance used for shmem backed objects
550 struct vfsmount *gemfs;
552 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
554 struct notifier_block oom_notifier;
555 struct notifier_block vmap_notifier;
556 struct shrinker shrinker;
558 #ifdef CONFIG_MMU_NOTIFIER
560 * notifier_lock for mmu notifiers, memory may not be allocated
561 * while holding this lock.
563 spinlock_t notifier_lock;
566 /* shrinker accounting, also useful for userland debugging */
571 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
573 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
576 static inline unsigned long
577 i915_fence_timeout(const struct drm_i915_private *i915)
579 return i915_fence_context_timeout(i915, U64_MAX);
582 /* Amount of SAGV/QGV points, BSpec precisely defines this */
583 #define I915_NUM_QGV_POINTS 8
585 struct ddi_vbt_port_info {
586 /* Non-NULL if port present. */
587 struct intel_bios_encoder_data *devdata;
591 /* This is an index in the HDMI/DVI DDI buffer translation table. */
593 u8 hdmi_level_shift_set:1;
595 u8 alternate_aux_channel;
596 u8 alternate_ddc_pin;
598 int dp_max_link_rate; /* 0 for not limited by VBT */
601 enum psr_lines_to_wait {
602 PSR_0_LINES_TO_WAIT = 0,
608 struct intel_vbt_data {
612 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
613 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
616 unsigned int int_tv_support:1;
617 unsigned int lvds_dither:1;
618 unsigned int int_crt_support:1;
619 unsigned int lvds_use_ssc:1;
620 unsigned int int_lvds_support:1;
621 unsigned int display_clock_mode:1;
622 unsigned int fdi_rx_polarity_inverted:1;
623 unsigned int panel_type:4;
625 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
626 enum drm_panel_orientation orientation;
628 enum drrs_support_type drrs_type;
638 struct edp_power_seq pps;
645 bool require_aux_wakeup;
647 enum psr_lines_to_wait lines_to_wait;
648 int tp1_wakeup_time_us;
649 int tp2_tp3_wakeup_time_us;
650 int psr2_tp2_tp3_wakeup_time_us;
657 u8 min_brightness; /* min_brightness/255 of max */
658 u8 controller; /* brightness controller number */
659 enum intel_backlight_type type;
665 struct mipi_config *config;
666 struct mipi_pps_data *pps;
672 const u8 *sequence[MIPI_SEQ_MAX];
673 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
674 enum drm_panel_orientation orientation;
679 struct list_head display_devices;
681 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
682 struct sdvo_device_mapping sdvo_mappings[2];
685 enum intel_ddb_partitioning {
687 INTEL_DDB_PART_5_6, /* IVB+ */
690 struct ilk_wm_values {
695 enum intel_ddb_partitioning partitioning;
699 u16 plane[I915_MAX_PLANES];
709 struct vlv_wm_ddl_values {
710 u8 plane[I915_MAX_PLANES];
713 struct vlv_wm_values {
714 struct g4x_pipe_wm pipe[3];
716 struct vlv_wm_ddl_values ddl[3];
721 struct g4x_wm_values {
722 struct g4x_pipe_wm pipe[2];
724 struct g4x_sr_wm hpll;
730 struct skl_ddb_entry {
731 u16 start, end; /* in number of blocks, 'end' is exclusive */
734 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
736 return entry->end - entry->start;
739 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
740 const struct skl_ddb_entry *e2)
742 if (e1->start == e2->start && e1->end == e2->end)
748 struct i915_frontbuffer_tracking {
752 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
759 struct i915_virtual_gpu {
760 struct mutex lock; /* serialises sending of g2v_notify command pkts */
765 struct intel_cdclk_config {
766 unsigned int cdclk, vco, ref, bypass;
770 struct i915_selftest_stash {
774 struct drm_i915_private {
775 struct drm_device drm;
777 /* FIXME: Device release actions should all be moved to drmm_ */
780 /* i915 device parameters */
781 struct i915_params params;
783 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
784 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
785 struct intel_driver_caps caps;
788 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
789 * end of stolen which we can optionally use to create GEM objects
790 * backed by stolen memory. Note that stolen_usable_size tells us
791 * exactly how much of this we are actually allowed to use, given that
792 * some portion of it is in fact reserved for use by hardware functions.
796 * Reseved portion of Data Stolen Memory
798 struct resource dsm_reserved;
801 * Stolen memory is segmented in hardware with different portions
802 * offlimits to certain functions.
804 * The drm_mm is initialised to the total accessible range, as found
805 * from the PCI config. On Broadwell+, this is further restricted to
806 * avoid the first page! The upper end of stolen memory is reserved for
807 * hardware functions and similarly removed from the accessible range.
809 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
811 struct intel_uncore uncore;
812 struct intel_uncore_mmio_debug mmio_debug;
814 struct i915_virtual_gpu vgpu;
816 struct intel_gvt *gvt;
818 struct intel_wopcm wopcm;
820 struct intel_csr csr;
822 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
824 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
825 * controller on different i2c buses. */
826 struct mutex gmbus_mutex;
829 * Base address of where the gmbus and gpio blocks are located (either
830 * on PCH or on SoC for platforms without PCH).
834 u32 hsw_psr_mmio_adjust;
836 /* MMIO base address for MIPI regs */
841 wait_queue_head_t gmbus_wait_queue;
843 struct pci_dev *bridge_dev;
845 struct rb_root uabi_engines;
847 struct resource mch_res;
849 /* protects the irq masks */
852 bool display_irqs_enabled;
854 /* Sideband mailbox protection */
855 struct mutex sb_lock;
856 struct pm_qos_request sb_qos;
858 /** Cached value of IMR to avoid reads in updating the bitfield */
861 u32 de_irq_mask[I915_MAX_PIPES];
863 u32 pipestat_irq_mask[I915_MAX_PIPES];
865 struct i915_hotplug hotplug;
866 struct intel_fbc fbc;
867 struct i915_drrs drrs;
868 struct intel_opregion opregion;
869 struct intel_vbt_data vbt;
871 bool preserve_bios_swizzle;
874 struct intel_overlay *overlay;
876 /* backlight registers and fields in struct intel_panel */
877 struct mutex backlight_lock;
879 /* protects panel power sequencer state */
880 struct mutex pps_mutex;
882 unsigned int fsb_freq, mem_freq, is_ddr3;
883 unsigned int skl_preferred_vco_freq;
884 unsigned int max_cdclk_freq;
886 unsigned int max_dotclk_freq;
887 unsigned int hpll_freq;
888 unsigned int fdi_pll_freq;
889 unsigned int czclk_freq;
892 /* The current hardware cdclk configuration */
893 struct intel_cdclk_config hw;
895 /* cdclk, divider, and ratio table from bspec */
896 const struct intel_cdclk_vals *table;
898 struct intel_global_obj obj;
902 /* The current hardware dbuf configuration */
905 struct intel_global_obj obj;
909 * wq - Driver workqueue for GEM.
911 * NOTE: Work items scheduled here are not allowed to grab any modeset
912 * locks, for otherwise the flushing done in the pageflip code will
913 * result in deadlocks.
915 struct workqueue_struct *wq;
917 /* ordered wq for modesets */
918 struct workqueue_struct *modeset_wq;
919 /* unbound hipri wq for page flips/plane updates */
920 struct workqueue_struct *flip_wq;
922 /* Display functions */
923 struct drm_i915_display_funcs display;
925 /* PCH chipset type */
926 enum intel_pch pch_type;
927 unsigned short pch_id;
929 unsigned long quirks;
931 struct drm_atomic_state *modeset_restore_state;
932 struct drm_modeset_acquire_ctx reset_ctx;
934 struct i915_ggtt ggtt; /* VM representing the global address space */
936 struct i915_gem_mm mm;
938 /* Kernel Modesetting */
940 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
941 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
944 * dpll and cdclk state is protected by connection_mutex
945 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
946 * Must be global rather than per dpll, because on some platforms plls
953 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
954 const struct intel_dpll_mgr *mgr;
962 struct list_head global_obj_list;
965 * For reading active_pipes holding any crtc lock is
966 * sufficient, for writing must hold all of them.
970 struct i915_wa_list gt_wa_list;
972 struct i915_frontbuffer_tracking fb_tracking;
974 struct intel_atomic_helper {
975 struct llist_head free_list;
976 struct work_struct free_work;
979 bool mchbar_need_disable;
981 struct intel_l3_parity l3_parity;
984 * HTI (aka HDPORT) state read during initial hw readout. Most
985 * platforms don't have HTI, so this will just stay 0. Those that do
986 * will use this later to figure out which PLLs and PHYs are unavailable
993 * Cannot be determined by PCIID. You must always read a register.
997 struct i915_power_domains power_domains;
999 struct i915_gpu_error gpu_error;
1001 struct drm_i915_gem_object *vlv_pctx;
1003 /* list of fbdev register on this device */
1004 struct intel_fbdev *fbdev;
1005 struct work_struct fbdev_suspend_work;
1007 struct drm_property *broadcast_rgb_property;
1008 struct drm_property *force_audio_property;
1010 /* hda/i915 audio component */
1011 struct i915_audio_component *audio_component;
1012 bool audio_component_registered;
1014 * av_mutex - mutex for audio/video sync
1017 struct mutex av_mutex;
1018 int audio_power_refcount;
1019 u32 audio_freq_cntrl;
1023 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1024 u32 chv_phy_control;
1026 * Shadows for CHV DPLL_MD regs to keep the state
1027 * checker somewhat working in the presence hardware
1028 * crappiness (can't read out DPLL_MD for pipes B & C).
1030 u32 chv_dpll_md[I915_MAX_PIPES];
1034 bool power_domains_suspended;
1035 struct i915_suspend_saved_registers regfile;
1036 struct vlv_s0ix_state *vlv_s0ix_state;
1039 I915_SAGV_UNKNOWN = 0,
1042 I915_SAGV_NOT_CONTROLLED
1045 u32 sagv_block_time_us;
1049 * Raw watermark latency values:
1050 * in 0.1us units for WM0,
1051 * in 0.5us units for WM1+.
1060 * Raw watermark memory latency values
1061 * for SKL for all 8 levels
1066 /* current hardware state */
1068 struct ilk_wm_values hw;
1069 struct vlv_wm_values vlv;
1070 struct g4x_wm_values g4x;
1076 * Should be held around atomic WM register writing; also
1077 * protects * intel_crtc->wm.active and
1078 * crtc_state->wm.need_postvbl_update.
1080 struct mutex wm_mutex;
1084 bool wm_lv_0_adjust_needed;
1086 bool symmetric_memory;
1087 enum intel_dram_type {
1099 struct intel_bw_info {
1100 /* for each QGV point */
1101 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1106 struct intel_global_obj bw_obj;
1108 struct intel_runtime_pm runtime_pm;
1110 struct i915_perf perf;
1112 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1116 struct i915_gem_contexts {
1117 spinlock_t lock; /* locks list */
1118 struct list_head list;
1122 * We replace the local file with a global mappings as the
1123 * backing storage for the mmap is on the device and not
1124 * on the struct file, and we do not want to prolong the
1125 * lifetime of the local fd. To minimise the number of
1126 * anonymous inodes we create, we use a global singleton to
1127 * share the global mapping.
1129 struct file *mmap_singleton;
1132 u8 framestart_delay;
1136 /* For i915gm/i945gm vblank irq workaround */
1139 /* perform PHY state sanity checks? */
1140 bool chv_phy_assert[2];
1144 /* Used to save the pipe-to-encoder mapping for audio */
1145 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1147 /* necessary resource sharing with HDMI LPE audio driver. */
1149 struct platform_device *platdev;
1153 struct i915_pmu pmu;
1155 struct i915_hdcp_comp_master *hdcp_master;
1156 bool hdcp_comp_added;
1158 /* Mutex to protect the above hdcp component related values. */
1159 struct mutex hdcp_comp_mutex;
1161 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1164 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1165 * will be rejected. Instead look for a better place.
1169 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1171 return container_of(dev, struct drm_i915_private, drm);
1174 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1176 return dev_get_drvdata(kdev);
1179 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1181 return pci_get_drvdata(pdev);
1184 /* Simple iterator over all initialised engines */
1185 #define for_each_engine(engine__, dev_priv__, id__) \
1187 (id__) < I915_NUM_ENGINES; \
1189 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1191 /* Iterator over subset of engines selected by mask */
1192 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1193 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1195 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1198 #define rb_to_uabi_engine(rb) \
1199 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1201 #define for_each_uabi_engine(engine__, i915__) \
1202 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1204 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1206 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1207 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1208 (engine__) && (engine__)->uabi_class == (class__); \
1209 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1211 #define I915_GTT_OFFSET_NONE ((u32)-1)
1214 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1215 * considered to be the frontbuffer for the given plane interface-wise. This
1216 * doesn't mean that the hw necessarily already scans it out, but that any
1217 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1219 * We have one bit per pipe and per scanout plane type.
1221 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1222 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1223 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1224 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1225 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1227 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1228 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1229 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1230 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1231 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1233 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1234 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1235 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1237 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1238 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1240 #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.version)
1241 #define IS_DISPLAY_RANGE(i915, from, until) \
1242 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1243 #define IS_DISPLAY_VER(i915, v) (DISPLAY_VER(i915) == (v))
1245 #define REVID_FOREVER 0xff
1246 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
1248 #define INTEL_GEN_MASK(s, e) ( \
1249 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1250 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1251 GENMASK((e) - 1, (s) - 1))
1253 /* Returns true if Gen is in inclusive range [Start, End] */
1254 #define IS_GEN_RANGE(dev_priv, s, e) \
1255 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1257 #define IS_GEN(dev_priv, n) \
1258 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1259 INTEL_INFO(dev_priv)->gen == (n))
1261 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1264 * Return true if revision is in range [since,until] inclusive.
1266 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1268 #define IS_REVID(p, since, until) \
1269 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1271 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1272 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1274 #define IS_DISPLAY_STEP(__i915, since, until) \
1275 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1276 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
1278 #define IS_GT_STEP(__i915, since, until) \
1279 (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1280 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
1282 static __always_inline unsigned int
1283 __platform_mask_index(const struct intel_runtime_info *info,
1284 enum intel_platform p)
1286 const unsigned int pbits =
1287 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1289 /* Expand the platform_mask array if this fails. */
1290 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1291 pbits * ARRAY_SIZE(info->platform_mask));
1296 static __always_inline unsigned int
1297 __platform_mask_bit(const struct intel_runtime_info *info,
1298 enum intel_platform p)
1300 const unsigned int pbits =
1301 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1303 return p % pbits + INTEL_SUBPLATFORM_BITS;
1307 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1309 const unsigned int pi = __platform_mask_index(info, p);
1311 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1314 static __always_inline bool
1315 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1317 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1318 const unsigned int pi = __platform_mask_index(info, p);
1319 const unsigned int pb = __platform_mask_bit(info, p);
1321 BUILD_BUG_ON(!__builtin_constant_p(p));
1323 return info->platform_mask[pi] & BIT(pb);
1326 static __always_inline bool
1327 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1328 enum intel_platform p, unsigned int s)
1330 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1331 const unsigned int pi = __platform_mask_index(info, p);
1332 const unsigned int pb = __platform_mask_bit(info, p);
1333 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1334 const u32 mask = info->platform_mask[pi];
1336 BUILD_BUG_ON(!__builtin_constant_p(p));
1337 BUILD_BUG_ON(!__builtin_constant_p(s));
1338 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1340 /* Shift and test on the MSB position so sign flag can be used. */
1341 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1344 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1345 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1347 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1348 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1349 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1350 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1351 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1352 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1353 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1354 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1355 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1356 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1357 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1358 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1359 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1360 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1361 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1362 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1363 #define IS_IRONLAKE_M(dev_priv) \
1364 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1365 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1366 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1367 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1368 INTEL_INFO(dev_priv)->gt == 1)
1369 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1370 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1371 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1372 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1373 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1374 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1375 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1376 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1377 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1378 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1379 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1380 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1381 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1382 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1383 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1384 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1385 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
1386 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1387 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1388 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1389 #define IS_BDW_ULT(dev_priv) \
1390 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1391 #define IS_BDW_ULX(dev_priv) \
1392 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1393 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1394 INTEL_INFO(dev_priv)->gt == 3)
1395 #define IS_HSW_ULT(dev_priv) \
1396 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1397 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1398 INTEL_INFO(dev_priv)->gt == 3)
1399 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1400 INTEL_INFO(dev_priv)->gt == 1)
1401 /* ULX machines are also considered ULT. */
1402 #define IS_HSW_ULX(dev_priv) \
1403 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1404 #define IS_SKL_ULT(dev_priv) \
1405 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1406 #define IS_SKL_ULX(dev_priv) \
1407 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1408 #define IS_KBL_ULT(dev_priv) \
1409 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1410 #define IS_KBL_ULX(dev_priv) \
1411 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1412 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1413 INTEL_INFO(dev_priv)->gt == 2)
1414 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1415 INTEL_INFO(dev_priv)->gt == 3)
1416 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1417 INTEL_INFO(dev_priv)->gt == 4)
1418 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1419 INTEL_INFO(dev_priv)->gt == 2)
1420 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1421 INTEL_INFO(dev_priv)->gt == 3)
1422 #define IS_CFL_ULT(dev_priv) \
1423 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1424 #define IS_CFL_ULX(dev_priv) \
1425 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1426 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1427 INTEL_INFO(dev_priv)->gt == 2)
1428 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1429 INTEL_INFO(dev_priv)->gt == 3)
1431 #define IS_CML_ULT(dev_priv) \
1432 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1433 #define IS_CML_ULX(dev_priv) \
1434 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1435 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
1436 INTEL_INFO(dev_priv)->gt == 2)
1438 #define IS_CNL_WITH_PORT_F(dev_priv) \
1439 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1440 #define IS_ICL_WITH_PORT_F(dev_priv) \
1441 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1443 #define IS_TGL_U(dev_priv) \
1444 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1446 #define IS_TGL_Y(dev_priv) \
1447 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1449 #define SKL_REVID_A0 0x0
1450 #define SKL_REVID_B0 0x1
1451 #define SKL_REVID_C0 0x2
1452 #define SKL_REVID_D0 0x3
1453 #define SKL_REVID_E0 0x4
1454 #define SKL_REVID_F0 0x5
1455 #define SKL_REVID_G0 0x6
1456 #define SKL_REVID_H0 0x7
1458 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1460 #define BXT_REVID_A0 0x0
1461 #define BXT_REVID_A1 0x1
1462 #define BXT_REVID_B0 0x3
1463 #define BXT_REVID_B_LAST 0x8
1464 #define BXT_REVID_C0 0x9
1466 #define IS_BXT_REVID(dev_priv, since, until) \
1467 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1469 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1470 (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1471 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1472 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1474 #define GLK_REVID_A0 0x0
1475 #define GLK_REVID_A1 0x1
1476 #define GLK_REVID_A2 0x2
1477 #define GLK_REVID_B0 0x3
1479 #define IS_GLK_REVID(dev_priv, since, until) \
1480 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1482 #define CNL_REVID_A0 0x0
1483 #define CNL_REVID_B0 0x1
1484 #define CNL_REVID_C0 0x2
1486 #define IS_CNL_REVID(p, since, until) \
1487 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1489 #define ICL_REVID_A0 0x0
1490 #define ICL_REVID_A2 0x1
1491 #define ICL_REVID_B0 0x3
1492 #define ICL_REVID_B2 0x4
1493 #define ICL_REVID_C0 0x5
1495 #define IS_ICL_REVID(p, since, until) \
1496 (IS_ICELAKE(p) && IS_REVID(p, since, until))
1498 #define EHL_REVID_A0 0x0
1499 #define EHL_REVID_B0 0x1
1501 #define IS_JSL_EHL_REVID(p, since, until) \
1502 (IS_JSL_EHL(p) && IS_REVID(p, since, until))
1504 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1505 (IS_TIGERLAKE(__i915) && \
1506 IS_DISPLAY_STEP(__i915, since, until))
1508 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1509 ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1510 IS_GT_STEP(__i915, since, until))
1512 #define IS_TGL_GT_STEP(__i915, since, until) \
1513 (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1514 IS_GT_STEP(__i915, since, until))
1516 #define RKL_REVID_A0 0x0
1517 #define RKL_REVID_B0 0x1
1518 #define RKL_REVID_C0 0x4
1520 #define IS_RKL_REVID(p, since, until) \
1521 (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
1523 #define DG1_REVID_A0 0x0
1524 #define DG1_REVID_B0 0x1
1526 #define IS_DG1_REVID(p, since, until) \
1527 (IS_DG1(p) && IS_REVID(p, since, until))
1529 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1530 (IS_ALDERLAKE_S(__i915) && \
1531 IS_DISPLAY_STEP(__i915, since, until))
1533 #define IS_ADLS_GT_STEP(__i915, since, until) \
1534 (IS_ALDERLAKE_S(__i915) && \
1535 IS_GT_STEP(__i915, since, until))
1537 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1538 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1539 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1541 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1542 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1544 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
1545 unsigned int first__ = (first); \
1546 unsigned int count__ = (count); \
1547 ((gt)->info.engine_mask & \
1548 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1550 #define VDBOX_MASK(gt) \
1551 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1552 #define VEBOX_MASK(gt) \
1553 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1556 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1557 * All later gens can run the final buffer from the ppgtt
1559 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1561 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1562 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1563 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1564 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1565 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
1567 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1569 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1570 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1571 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1572 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1574 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1576 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1578 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1579 #define HAS_PPGTT(dev_priv) \
1580 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1581 #define HAS_FULL_PPGTT(dev_priv) \
1582 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1584 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1585 GEM_BUG_ON((sizes) == 0); \
1586 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1589 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1590 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1591 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1593 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1594 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1596 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1597 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1599 /* WaRsDisableCoarsePowerGating:skl,cnl */
1600 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1601 (IS_CANNONLAKE(dev_priv) || \
1602 IS_SKL_GT3(dev_priv) || \
1603 IS_SKL_GT4(dev_priv))
1605 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1606 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1607 IS_GEMINILAKE(dev_priv) || \
1608 IS_KABYLAKE(dev_priv))
1610 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1611 * rows, which changed the alignment requirements and fence programming.
1613 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1614 !(IS_I915G(dev_priv) || \
1615 IS_I915GM(dev_priv)))
1616 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1617 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1619 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1620 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1621 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1623 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1625 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1627 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1628 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1629 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1630 #define HAS_PSR_HW_TRACKING(dev_priv) \
1631 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1632 #define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12)
1633 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1635 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1636 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1637 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1639 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1641 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
1643 #define HAS_MSO(i915) (INTEL_GEN(i915) >= 12)
1645 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1646 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1648 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1650 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1651 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1653 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1655 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1657 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1660 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1662 #define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10))
1664 /* DPF == dynamic parity feature */
1665 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1666 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1667 2 : HAS_L3_DPF(dev_priv))
1669 #define GT_FREQUENCY_MULTIPLIER 50
1670 #define GEN9_FREQ_SCALER 3
1672 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1674 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1676 #define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
1678 /* Only valid when HAS_DISPLAY() is true */
1679 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1680 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1682 static inline bool run_as_guest(void)
1684 return !hypervisor_is_type(X86_HYPER_NATIVE);
1687 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1688 IS_ALDERLAKE_S(dev_priv))
1690 static inline bool intel_vtd_active(void)
1692 #ifdef CONFIG_INTEL_IOMMU
1693 if (intel_iommu_gfx_mapped)
1697 /* Running as a guest, we assume the host is enforcing VT'd */
1698 return run_as_guest();
1701 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1703 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1707 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1709 return IS_BROXTON(dev_priv) && intel_vtd_active();
1713 extern const struct dev_pm_ops i915_pm_ops;
1715 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1716 void i915_driver_remove(struct drm_i915_private *i915);
1717 void i915_driver_shutdown(struct drm_i915_private *i915);
1719 int i915_resume_switcheroo(struct drm_i915_private *i915);
1720 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1722 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1723 struct drm_file *file_priv);
1726 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1727 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1728 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1729 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1731 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1733 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1736 * A single pass should suffice to release all the freed objects (along
1737 * most call paths) , but be a little more paranoid in that freeing
1738 * the objects does take a little amount of time, during which the rcu
1739 * callbacks could have added new objects into the freed list, and
1740 * armed the work again.
1742 while (atomic_read(&i915->mm.free_count)) {
1743 flush_work(&i915->mm.free_work);
1748 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1751 * Similar to objects above (see i915_gem_drain_freed-objects), in
1752 * general we have workers that are armed by RCU and then rearm
1753 * themselves in their callbacks. To be paranoid, we need to
1754 * drain the workqueue a second time after waiting for the RCU
1755 * grace period so that we catch work queued via RCU from the first
1756 * pass. As neither drain_workqueue() nor flush_workqueue() report
1757 * a result, we make an assumption that we only don't require more
1758 * than 3 passes to catch all _recursive_ RCU delayed work.
1763 flush_workqueue(i915->wq);
1765 i915_gem_drain_freed_objects(i915);
1767 drain_workqueue(i915->wq);
1770 struct i915_vma * __must_check
1771 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1772 struct i915_gem_ww_ctx *ww,
1773 const struct i915_ggtt_view *view,
1774 u64 size, u64 alignment, u64 flags);
1776 static inline struct i915_vma * __must_check
1777 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1778 const struct i915_ggtt_view *view,
1779 u64 size, u64 alignment, u64 flags)
1781 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1784 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1785 unsigned long flags);
1786 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1787 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1788 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1790 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1792 int i915_gem_dumb_create(struct drm_file *file_priv,
1793 struct drm_device *dev,
1794 struct drm_mode_create_dumb *args);
1796 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1798 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1800 return atomic_read(&error->reset_count);
1803 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1804 const struct intel_engine_cs *engine)
1806 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1809 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1810 void i915_gem_driver_register(struct drm_i915_private *i915);
1811 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1812 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1813 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1814 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1815 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1816 void i915_gem_resume(struct drm_i915_private *dev_priv);
1818 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1820 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1821 enum i915_cache_level cache_level);
1823 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1824 struct dma_buf *dma_buf);
1826 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1828 static inline struct i915_gem_context *
1829 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1831 return xa_load(&file_priv->context_xa, id);
1834 static inline struct i915_gem_context *
1835 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1837 struct i915_gem_context *ctx;
1840 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1841 if (ctx && !kref_get_unless_zero(&ctx->ref))
1848 /* i915_gem_evict.c */
1849 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1850 u64 min_size, u64 alignment,
1851 unsigned long color,
1854 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1855 struct drm_mm_node *node,
1856 unsigned int flags);
1857 int i915_gem_evict_vm(struct i915_address_space *vm);
1859 /* i915_gem_internal.c */
1860 struct drm_i915_gem_object *
1861 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1864 /* i915_gem_tiling.c */
1865 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1867 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1869 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1870 i915_gem_object_is_tiled(obj);
1873 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1874 unsigned int tiling, unsigned int stride);
1875 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1876 unsigned int tiling, unsigned int stride);
1878 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1880 /* i915_cmd_parser.c */
1881 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1882 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1883 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1884 unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
1887 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1888 struct i915_vma *batch,
1889 unsigned long batch_offset,
1890 unsigned long batch_length,
1891 struct i915_vma *shadow,
1892 unsigned long *jump_whitelist,
1894 const void *batch_map);
1895 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1897 /* intel_device_info.c */
1898 static inline struct intel_device_info *
1899 mkwrite_device_info(struct drm_i915_private *dev_priv)
1901 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1904 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1905 struct drm_file *file);
1908 int remap_io_sg(struct vm_area_struct *vma,
1909 unsigned long addr, unsigned long size,
1910 struct scatterlist *sgl, resource_size_t iobase);
1912 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1914 if (INTEL_GEN(i915) >= 10)
1915 return CNL_HWS_CSB_WRITE_INDEX;
1917 return I915_HWS_CSB_WRITE_INDEX;
1920 static inline enum i915_map_type
1921 i915_coherent_map_type(struct drm_i915_private *i915)
1923 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;