1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170529"
84 #define DRIVER_TIMESTAMP 1496041258
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func, int line);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
125 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
127 uint_fixed_16_16_t fp;
135 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
137 return DIV_ROUND_UP(fp.val, 1 << 16);
140 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
145 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
146 uint_fixed_16_16_t min2)
148 uint_fixed_16_16_t min;
150 min.val = min(min1.val, min2.val);
154 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
155 uint_fixed_16_16_t max2)
157 uint_fixed_16_16_t max;
159 max.val = max(max1.val, max2.val);
163 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
164 uint_fixed_16_16_t d)
166 return DIV_ROUND_UP(val.val, d.val);
169 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
170 uint_fixed_16_16_t mul)
172 uint64_t intermediate_val;
175 intermediate_val = (uint64_t) val * mul.val;
176 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
177 WARN_ON(intermediate_val >> 32);
178 result = clamp_t(uint32_t, intermediate_val, 0, ~0);
182 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
183 uint_fixed_16_16_t mul)
185 uint64_t intermediate_val;
186 uint_fixed_16_16_t fp;
188 intermediate_val = (uint64_t) val.val * mul.val;
189 intermediate_val = intermediate_val >> 16;
190 WARN_ON(intermediate_val >> 32);
191 fp.val = clamp_t(uint32_t, intermediate_val, 0, ~0);
195 static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d)
197 uint_fixed_16_16_t fp, res;
199 fp = u32_to_fixed_16_16(val);
200 res.val = DIV_ROUND_UP(fp.val, d);
204 static inline uint_fixed_16_16_t fixed_16_16_div_u64(uint32_t val, uint32_t d)
206 uint_fixed_16_16_t res;
209 interm_val = (uint64_t)val << 16;
210 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
211 WARN_ON(interm_val >> 32);
212 res.val = (uint32_t) interm_val;
217 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
218 uint_fixed_16_16_t d)
222 interm_val = (uint64_t)val << 16;
223 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
224 WARN_ON(interm_val >> 32);
225 return clamp_t(uint32_t, interm_val, 0, ~0);
228 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
229 uint_fixed_16_16_t mul)
231 uint64_t intermediate_val;
232 uint_fixed_16_16_t fp;
234 intermediate_val = (uint64_t) val * mul.val;
235 WARN_ON(intermediate_val >> 32);
236 fp.val = (uint32_t) intermediate_val;
240 static inline const char *yesno(bool v)
242 return v ? "yes" : "no";
245 static inline const char *onoff(bool v)
247 return v ? "on" : "off";
250 static inline const char *enableddisabled(bool v)
252 return v ? "enabled" : "disabled";
261 I915_MAX_PIPES = _PIPE_EDP
263 #define pipe_name(p) ((p) + 'A')
275 static inline const char *transcoder_name(enum transcoder transcoder)
277 switch (transcoder) {
286 case TRANSCODER_DSI_A:
288 case TRANSCODER_DSI_C:
295 static inline bool transcoder_is_dsi(enum transcoder transcoder)
297 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
301 * Global legacy plane identifier. Valid only for primary/sprite
302 * planes on pre-g4x, and only for primary planes on g4x+.
309 #define plane_name(p) ((p) + 'A')
311 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
314 * Per-pipe plane identifier.
315 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
316 * number of planes per CRTC. Not all platforms really have this many planes,
317 * which means some arrays of size I915_MAX_PLANES may have unused entries
318 * between the topmost sprite plane and the cursor plane.
320 * This is expected to be passed to various register macros
321 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
332 #define for_each_plane_id_on_crtc(__crtc, __p) \
333 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
334 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
345 #define port_name(p) ((p) + 'A')
347 #define I915_NUM_PHYS_VLV 2
360 enum intel_display_power_domain {
364 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
365 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
366 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
367 POWER_DOMAIN_TRANSCODER_A,
368 POWER_DOMAIN_TRANSCODER_B,
369 POWER_DOMAIN_TRANSCODER_C,
370 POWER_DOMAIN_TRANSCODER_EDP,
371 POWER_DOMAIN_TRANSCODER_DSI_A,
372 POWER_DOMAIN_TRANSCODER_DSI_C,
373 POWER_DOMAIN_PORT_DDI_A_LANES,
374 POWER_DOMAIN_PORT_DDI_B_LANES,
375 POWER_DOMAIN_PORT_DDI_C_LANES,
376 POWER_DOMAIN_PORT_DDI_D_LANES,
377 POWER_DOMAIN_PORT_DDI_E_LANES,
378 POWER_DOMAIN_PORT_DDI_A_IO,
379 POWER_DOMAIN_PORT_DDI_B_IO,
380 POWER_DOMAIN_PORT_DDI_C_IO,
381 POWER_DOMAIN_PORT_DDI_D_IO,
382 POWER_DOMAIN_PORT_DDI_E_IO,
383 POWER_DOMAIN_PORT_DSI,
384 POWER_DOMAIN_PORT_CRT,
385 POWER_DOMAIN_PORT_OTHER,
394 POWER_DOMAIN_MODESET,
400 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
401 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
402 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
403 #define POWER_DOMAIN_TRANSCODER(tran) \
404 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
405 (tran) + POWER_DOMAIN_TRANSCODER_A)
409 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
421 #define for_each_hpd_pin(__pin) \
422 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
424 #define HPD_STORM_DEFAULT_THRESHOLD 5
426 struct i915_hotplug {
427 struct work_struct hotplug_work;
430 unsigned long last_jiffies;
435 HPD_MARK_DISABLED = 2
437 } stats[HPD_NUM_PINS];
439 struct delayed_work reenable_work;
441 struct intel_digital_port *irq_port[I915_MAX_PORTS];
444 struct work_struct dig_port_work;
446 struct work_struct poll_init_work;
449 unsigned int hpd_storm_threshold;
452 * if we get a HPD irq from DP and a HPD irq from non-DP
453 * the non-DP HPD could block the workqueue on a mode config
454 * mutex getting, that userspace may have taken. However
455 * userspace is waiting on the DP workqueue to run which is
456 * blocked behind the non-DP one.
458 struct workqueue_struct *dp_wq;
461 #define I915_GEM_GPU_DOMAINS \
462 (I915_GEM_DOMAIN_RENDER | \
463 I915_GEM_DOMAIN_SAMPLER | \
464 I915_GEM_DOMAIN_COMMAND | \
465 I915_GEM_DOMAIN_INSTRUCTION | \
466 I915_GEM_DOMAIN_VERTEX)
468 #define for_each_pipe(__dev_priv, __p) \
469 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
470 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
471 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
472 for_each_if ((__mask) & (1 << (__p)))
473 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
475 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
477 #define for_each_sprite(__dev_priv, __p, __s) \
479 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
482 #define for_each_port_masked(__port, __ports_mask) \
483 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
484 for_each_if ((__ports_mask) & (1 << (__port)))
486 #define for_each_crtc(dev, crtc) \
487 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
489 #define for_each_intel_plane(dev, intel_plane) \
490 list_for_each_entry(intel_plane, \
491 &(dev)->mode_config.plane_list, \
494 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
495 list_for_each_entry(intel_plane, \
496 &(dev)->mode_config.plane_list, \
498 for_each_if ((plane_mask) & \
499 (1 << drm_plane_index(&intel_plane->base)))
501 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
502 list_for_each_entry(intel_plane, \
503 &(dev)->mode_config.plane_list, \
505 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
507 #define for_each_intel_crtc(dev, intel_crtc) \
508 list_for_each_entry(intel_crtc, \
509 &(dev)->mode_config.crtc_list, \
512 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
513 list_for_each_entry(intel_crtc, \
514 &(dev)->mode_config.crtc_list, \
516 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
518 #define for_each_intel_encoder(dev, intel_encoder) \
519 list_for_each_entry(intel_encoder, \
520 &(dev)->mode_config.encoder_list, \
523 #define for_each_intel_connector_iter(intel_connector, iter) \
524 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
526 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
527 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
528 for_each_if ((intel_encoder)->base.crtc == (__crtc))
530 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
531 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
532 for_each_if ((intel_connector)->base.encoder == (__encoder))
534 #define for_each_power_domain(domain, mask) \
535 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
536 for_each_if (BIT_ULL(domain) & (mask))
538 #define for_each_power_well(__dev_priv, __power_well) \
539 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
540 (__power_well) - (__dev_priv)->power_domains.power_wells < \
541 (__dev_priv)->power_domains.power_well_count; \
544 #define for_each_power_well_rev(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
546 (__dev_priv)->power_domains.power_well_count - 1; \
547 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
550 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
551 for_each_power_well(__dev_priv, __power_well) \
552 for_each_if ((__power_well)->domains & (__domain_mask))
554 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
555 for_each_power_well_rev(__dev_priv, __power_well) \
556 for_each_if ((__power_well)->domains & (__domain_mask))
558 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
560 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
561 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
562 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
564 for_each_if (plane_state)
566 struct drm_i915_private;
567 struct i915_mm_struct;
568 struct i915_mmu_object;
570 struct drm_i915_file_private {
571 struct drm_i915_private *dev_priv;
572 struct drm_file *file;
576 struct list_head request_list;
577 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
578 * chosen to prevent the CPU getting more than a frame ahead of the GPU
579 * (when using lax throttling for the frontbuffer). We also use it to
580 * offer free GPU waitboosts for severely congested workloads.
582 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
584 struct idr context_idr;
586 struct intel_rps_client {
587 struct list_head link;
591 unsigned int bsd_engine;
593 /* Client can have a maximum of 3 contexts banned before
594 * it is denied of creating new contexts. As one context
595 * ban needs 4 consecutive hangs, and more if there is
596 * progress in between, this is a last resort stop gap measure
597 * to limit the badly behaving clients access to gpu.
599 #define I915_MAX_CLIENT_CONTEXT_BANS 3
603 /* Used by dp and fdi links */
604 struct intel_link_m_n {
612 void intel_link_compute_m_n(int bpp, int nlanes,
613 int pixel_clock, int link_clock,
614 struct intel_link_m_n *m_n);
616 /* Interface history:
619 * 1.2: Add Power Management
620 * 1.3: Add vblank support
621 * 1.4: Fix cmdbuffer path, add heap destroy
622 * 1.5: Add vblank pipe configuration
623 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
624 * - Support vertical blank on secondary display pipe
626 #define DRIVER_MAJOR 1
627 #define DRIVER_MINOR 6
628 #define DRIVER_PATCHLEVEL 0
630 struct opregion_header;
631 struct opregion_acpi;
632 struct opregion_swsci;
633 struct opregion_asle;
635 struct intel_opregion {
636 struct opregion_header *header;
637 struct opregion_acpi *acpi;
638 struct opregion_swsci *swsci;
639 u32 swsci_gbda_sub_functions;
640 u32 swsci_sbcb_sub_functions;
641 struct opregion_asle *asle;
646 struct work_struct asle_work;
648 #define OPREGION_SIZE (8*1024)
650 struct intel_overlay;
651 struct intel_overlay_error_state;
653 struct sdvo_device_mapping {
662 struct intel_connector;
663 struct intel_encoder;
664 struct intel_atomic_state;
665 struct intel_crtc_state;
666 struct intel_initial_plane_config;
670 struct intel_cdclk_state;
672 struct drm_i915_display_funcs {
673 void (*get_cdclk)(struct drm_i915_private *dev_priv,
674 struct intel_cdclk_state *cdclk_state);
675 void (*set_cdclk)(struct drm_i915_private *dev_priv,
676 const struct intel_cdclk_state *cdclk_state);
677 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
678 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
679 int (*compute_intermediate_wm)(struct drm_device *dev,
680 struct intel_crtc *intel_crtc,
681 struct intel_crtc_state *newstate);
682 void (*initial_watermarks)(struct intel_atomic_state *state,
683 struct intel_crtc_state *cstate);
684 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
685 struct intel_crtc_state *cstate);
686 void (*optimize_watermarks)(struct intel_atomic_state *state,
687 struct intel_crtc_state *cstate);
688 int (*compute_global_watermarks)(struct drm_atomic_state *state);
689 void (*update_wm)(struct intel_crtc *crtc);
690 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
691 /* Returns the active state of the crtc, and if the crtc is active,
692 * fills out the pipe-config with the hw state. */
693 bool (*get_pipe_config)(struct intel_crtc *,
694 struct intel_crtc_state *);
695 void (*get_initial_plane_config)(struct intel_crtc *,
696 struct intel_initial_plane_config *);
697 int (*crtc_compute_clock)(struct intel_crtc *crtc,
698 struct intel_crtc_state *crtc_state);
699 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
700 struct drm_atomic_state *old_state);
701 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
702 struct drm_atomic_state *old_state);
703 void (*update_crtcs)(struct drm_atomic_state *state,
704 unsigned int *crtc_vblank_mask);
705 void (*audio_codec_enable)(struct drm_connector *connector,
706 struct intel_encoder *encoder,
707 const struct drm_display_mode *adjusted_mode);
708 void (*audio_codec_disable)(struct intel_encoder *encoder);
709 void (*fdi_link_train)(struct intel_crtc *crtc,
710 const struct intel_crtc_state *crtc_state);
711 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
712 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
713 struct drm_framebuffer *fb,
714 struct drm_i915_gem_object *obj,
715 struct drm_i915_gem_request *req,
717 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
718 /* clock updates for mode set */
720 /* render clock increase/decrease */
721 /* display clock increase/decrease */
722 /* pll clock increase/decrease */
724 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
725 void (*load_luts)(struct drm_crtc_state *crtc_state);
728 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
729 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
730 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
733 struct work_struct work;
735 uint32_t *dmc_payload;
736 uint32_t dmc_fw_size;
739 i915_reg_t mmioaddr[8];
740 uint32_t mmiodata[8];
742 uint32_t allowed_dc_mask;
745 #define DEV_INFO_FOR_EACH_FLAG(func) \
748 func(is_alpha_support); \
749 /* Keep has_* in alphabetical order */ \
750 func(has_64bit_reloc); \
751 func(has_aliasing_ppgtt); \
756 func(has_fpga_dbg); \
757 func(has_full_ppgtt); \
758 func(has_full_48bit_ppgtt); \
759 func(has_gmbus_irq); \
760 func(has_gmch_display); \
766 func(has_logical_ring_contexts); \
768 func(has_pipe_cxsr); \
769 func(has_pooled_eu); \
773 func(has_resource_streamer); \
774 func(has_runtime_pm); \
776 func(unfenced_needs_alignment); \
777 func(cursor_needs_physical); \
778 func(hws_needs_physical); \
779 func(overlay_needs_physical); \
782 struct sseu_dev_info {
788 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
791 u8 has_subslice_pg:1;
795 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
797 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
800 /* Keep in gen based order, and chronological order within a gen */
801 enum intel_platform {
802 INTEL_PLATFORM_UNINITIALIZED = 0,
833 struct intel_device_info {
834 u32 display_mmio_offset;
837 u8 num_sprites[I915_MAX_PIPES];
838 u8 num_scalers[I915_MAX_PIPES];
841 enum intel_platform platform;
842 u8 ring_mask; /* Rings supported by the HW */
844 #define DEFINE_FLAG(name) u8 name:1
845 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
847 u16 ddb_size; /* in blocks */
848 /* Register offsets for the various display pipes and transcoders */
849 int pipe_offsets[I915_MAX_TRANSCODERS];
850 int trans_offsets[I915_MAX_TRANSCODERS];
851 int palette_offsets[I915_MAX_PIPES];
852 int cursor_offsets[I915_MAX_PIPES];
854 /* Slice/subslice/EU info */
855 struct sseu_dev_info sseu;
858 u16 degamma_lut_size;
863 struct intel_display_error_state;
865 struct i915_gpu_state {
868 struct timeval boottime;
869 struct timeval uptime;
871 struct drm_i915_private *i915;
881 struct intel_device_info device_info;
882 struct i915_params params;
884 /* Generic register state */
888 u32 gtier[4], ngtier;
892 u32 error; /* gen6+ */
893 u32 err_int; /* gen7 */
894 u32 fault_data0; /* gen8, gen9 */
895 u32 fault_data1; /* gen8, gen9 */
903 u64 fence[I915_MAX_NUM_FENCES];
904 struct intel_overlay_error_state *overlay;
905 struct intel_display_error_state *display;
906 struct drm_i915_error_object *semaphore;
907 struct drm_i915_error_object *guc_log;
909 struct drm_i915_error_engine {
911 /* Software tracked state */
914 unsigned long hangcheck_timestamp;
915 bool hangcheck_stalled;
916 enum intel_engine_hangcheck_action hangcheck_action;
917 struct i915_address_space *vm;
920 /* position of active request inside the ring */
921 u32 rq_head, rq_post, rq_tail;
923 /* our own tracking of ring head and tail */
946 u32 rc_psmi; /* sleep state */
947 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
948 struct intel_instdone instdone;
950 struct drm_i915_error_context {
951 char comm[TASK_COMM_LEN];
960 struct drm_i915_error_object {
966 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
968 struct drm_i915_error_object **user_bo;
971 struct drm_i915_error_object *wa_ctx;
973 struct drm_i915_error_request {
981 } *requests, execlist[2];
983 struct drm_i915_error_waiter {
984 char comm[TASK_COMM_LEN];
996 } engine[I915_NUM_ENGINES];
998 struct drm_i915_error_buffer {
1001 u32 rseqno[I915_NUM_ENGINES], wseqno;
1005 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1012 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1013 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1014 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1017 enum i915_cache_level {
1018 I915_CACHE_NONE = 0,
1019 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1020 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1021 caches, eg sampler/render caches, and the
1022 large Last-Level-Cache. LLC is coherent with
1023 the CPU, but L3 is only visible to the GPU. */
1024 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1027 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1038 /* This is always the inner lock when overlapping with struct_mutex and
1039 * it's the outer lock when overlapping with stolen_lock. */
1042 unsigned int possible_framebuffer_bits;
1043 unsigned int busy_bits;
1044 unsigned int visible_pipes_mask;
1045 struct intel_crtc *crtc;
1047 struct drm_mm_node compressed_fb;
1048 struct drm_mm_node *compressed_llb;
1055 bool underrun_detected;
1056 struct work_struct underrun_work;
1058 struct intel_fbc_state_cache {
1059 struct i915_vma *vma;
1062 unsigned int mode_flags;
1063 uint32_t hsw_bdw_pixel_rate;
1067 unsigned int rotation;
1074 const struct drm_format_info *format;
1075 unsigned int stride;
1079 struct intel_fbc_reg_params {
1080 struct i915_vma *vma;
1085 unsigned int fence_y_offset;
1089 const struct drm_format_info *format;
1090 unsigned int stride;
1096 struct intel_fbc_work {
1098 u32 scheduled_vblank;
1099 struct work_struct work;
1102 const char *no_fbc_reason;
1106 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1107 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1108 * parsing for same resolution.
1110 enum drrs_refresh_rate_type {
1113 DRRS_MAX_RR, /* RR count */
1116 enum drrs_support_type {
1117 DRRS_NOT_SUPPORTED = 0,
1118 STATIC_DRRS_SUPPORT = 1,
1119 SEAMLESS_DRRS_SUPPORT = 2
1125 struct delayed_work work;
1126 struct intel_dp *dp;
1127 unsigned busy_frontbuffer_bits;
1128 enum drrs_refresh_rate_type refresh_rate_type;
1129 enum drrs_support_type type;
1136 struct intel_dp *enabled;
1138 struct delayed_work work;
1139 unsigned busy_frontbuffer_bits;
1141 bool aux_frame_sync;
1143 bool y_cord_support;
1144 bool colorimetry_support;
1149 PCH_NONE = 0, /* No PCH present */
1150 PCH_IBX, /* Ibexpeak PCH */
1151 PCH_CPT, /* Cougarpoint PCH */
1152 PCH_LPT, /* Lynxpoint PCH */
1153 PCH_SPT, /* Sunrisepoint PCH */
1154 PCH_KBP, /* Kabypoint PCH */
1155 PCH_CNP, /* Cannonpoint PCH */
1159 enum intel_sbi_destination {
1164 #define QUIRK_PIPEA_FORCE (1<<0)
1165 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1166 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1167 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1168 #define QUIRK_PIPEB_FORCE (1<<4)
1169 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1172 struct intel_fbc_work;
1174 struct intel_gmbus {
1175 struct i2c_adapter adapter;
1176 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1179 i915_reg_t gpio_reg;
1180 struct i2c_algo_bit_data bit_algo;
1181 struct drm_i915_private *dev_priv;
1184 struct i915_suspend_saved_registers {
1186 u32 saveFBC_CONTROL;
1187 u32 saveCACHE_MODE_0;
1188 u32 saveMI_ARB_STATE;
1192 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1193 u32 savePCH_PORT_HOTPLUG;
1197 struct vlv_s0ix_state {
1204 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1205 u32 media_max_req_count;
1206 u32 gfx_max_req_count;
1232 u32 rp_down_timeout;
1238 /* Display 1 CZ domain */
1243 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1245 /* GT SA CZ domain */
1252 /* Display 2 CZ domain */
1256 u32 clock_gate_dis2;
1259 struct intel_rps_ei {
1265 struct intel_gen6_power_mgmt {
1267 * work, interrupts_enabled and pm_iir are protected by
1268 * dev_priv->irq_lock
1270 struct work_struct work;
1271 bool interrupts_enabled;
1274 /* PM interrupt bits that should never be masked */
1277 /* Frequencies are stored in potentially platform dependent multiples.
1278 * In other words, *_freq needs to be multiplied by X to be interesting.
1279 * Soft limits are those which are used for the dynamic reclocking done
1280 * by the driver (raise frequencies under heavy loads, and lower for
1281 * lighter loads). Hard limits are those imposed by the hardware.
1283 * A distinction is made for overclocking, which is never enabled by
1284 * default, and is considered to be above the hard limit if it's
1287 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1288 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1289 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1290 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1291 u8 min_freq; /* AKA RPn. Minimum frequency */
1292 u8 boost_freq; /* Frequency to request when wait boosting */
1293 u8 idle_freq; /* Frequency to request when we are idle */
1294 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1295 u8 rp1_freq; /* "less than" RP0 power/freqency */
1296 u8 rp0_freq; /* Non-overclocked max frequency. */
1297 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1299 u8 up_threshold; /* Current %busy required to uplock */
1300 u8 down_threshold; /* Current %busy required to downclock */
1303 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1305 spinlock_t client_lock;
1306 struct list_head clients;
1310 struct delayed_work autoenable_work;
1313 /* manual wa residency calculations */
1314 struct intel_rps_ei ei;
1317 * Protects RPS/RC6 register access and PCU communication.
1318 * Must be taken after struct_mutex if nested. Note that
1319 * this lock may be held for long periods of time when
1320 * talking to hw - so only take it when talking to hw!
1322 struct mutex hw_lock;
1325 /* defined intel_pm.c */
1326 extern spinlock_t mchdev_lock;
1328 struct intel_ilk_power_mgmt {
1336 unsigned long last_time1;
1337 unsigned long chipset_power;
1340 unsigned long gfx_power;
1347 struct drm_i915_private;
1348 struct i915_power_well;
1350 struct i915_power_well_ops {
1352 * Synchronize the well's hw state to match the current sw state, for
1353 * example enable/disable it based on the current refcount. Called
1354 * during driver init and resume time, possibly after first calling
1355 * the enable/disable handlers.
1357 void (*sync_hw)(struct drm_i915_private *dev_priv,
1358 struct i915_power_well *power_well);
1360 * Enable the well and resources that depend on it (for example
1361 * interrupts located on the well). Called after the 0->1 refcount
1364 void (*enable)(struct drm_i915_private *dev_priv,
1365 struct i915_power_well *power_well);
1367 * Disable the well and resources that depend on it. Called after
1368 * the 1->0 refcount transition.
1370 void (*disable)(struct drm_i915_private *dev_priv,
1371 struct i915_power_well *power_well);
1372 /* Returns the hw enabled state. */
1373 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1374 struct i915_power_well *power_well);
1377 /* Power well structure for haswell */
1378 struct i915_power_well {
1381 /* power well enable/disable usage count */
1383 /* cached hw enabled state */
1386 /* unique identifier for this power well */
1389 * Arbitraty data associated with this power well. Platform and power
1393 const struct i915_power_well_ops *ops;
1396 struct i915_power_domains {
1398 * Power wells needed for initialization at driver init and suspend
1399 * time are on. They are kept on until after the first modeset.
1403 int power_well_count;
1406 int domain_use_count[POWER_DOMAIN_NUM];
1407 struct i915_power_well *power_wells;
1410 #define MAX_L3_SLICES 2
1411 struct intel_l3_parity {
1412 u32 *remap_info[MAX_L3_SLICES];
1413 struct work_struct error_work;
1417 struct i915_gem_mm {
1418 /** Memory allocator for GTT stolen memory */
1419 struct drm_mm stolen;
1420 /** Protects the usage of the GTT stolen memory allocator. This is
1421 * always the inner lock when overlapping with struct_mutex. */
1422 struct mutex stolen_lock;
1424 /** List of all objects in gtt_space. Used to restore gtt
1425 * mappings on resume */
1426 struct list_head bound_list;
1428 * List of objects which are not bound to the GTT (thus
1429 * are idle and not used by the GPU). These objects may or may
1430 * not actually have any pages attached.
1432 struct list_head unbound_list;
1434 /** List of all objects in gtt_space, currently mmaped by userspace.
1435 * All objects within this list must also be on bound_list.
1437 struct list_head userfault_list;
1440 * List of objects which are pending destruction.
1442 struct llist_head free_list;
1443 struct work_struct free_work;
1445 /** Usable portion of the GTT for GEM */
1446 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1448 /** PPGTT used for aliasing the PPGTT with the GTT */
1449 struct i915_hw_ppgtt *aliasing_ppgtt;
1451 struct notifier_block oom_notifier;
1452 struct notifier_block vmap_notifier;
1453 struct shrinker shrinker;
1455 /** LRU list of objects with fence regs on them. */
1456 struct list_head fence_list;
1458 u64 unordered_timeline;
1460 /* the indicator for dispatch video commands on two BSD rings */
1461 atomic_t bsd_engine_dispatch_index;
1463 /** Bit 6 swizzling required for X tiling */
1464 uint32_t bit_6_swizzle_x;
1465 /** Bit 6 swizzling required for Y tiling */
1466 uint32_t bit_6_swizzle_y;
1468 /* accounting, useful for userland debugging */
1469 spinlock_t object_stat_lock;
1474 struct drm_i915_error_state_buf {
1475 struct drm_i915_private *i915;
1484 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1485 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1487 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1488 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1490 struct i915_gpu_error {
1491 /* For hangcheck timer */
1492 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1493 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1495 struct delayed_work hangcheck_work;
1497 /* For reset and error_state handling. */
1499 /* Protected by the above dev->gpu_error.lock. */
1500 struct i915_gpu_state *first_error;
1502 unsigned long missed_irq_rings;
1505 * State variable controlling the reset flow and count
1507 * This is a counter which gets incremented when reset is triggered,
1509 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1510 * meaning that any waiters holding onto the struct_mutex should
1511 * relinquish the lock immediately in order for the reset to start.
1513 * If reset is not completed succesfully, the I915_WEDGE bit is
1514 * set meaning that hardware is terminally sour and there is no
1515 * recovery. All waiters on the reset_queue will be woken when
1518 * This counter is used by the wait_seqno code to notice that reset
1519 * event happened and it needs to restart the entire ioctl (since most
1520 * likely the seqno it waited for won't ever signal anytime soon).
1522 * This is important for lock-free wait paths, where no contended lock
1523 * naturally enforces the correct ordering between the bail-out of the
1524 * waiter and the gpu reset work code.
1526 unsigned long reset_count;
1529 * flags: Control various stages of the GPU reset
1531 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1532 * other users acquiring the struct_mutex. To do this we set the
1533 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1534 * and then check for that bit before acquiring the struct_mutex (in
1535 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1536 * secondary role in preventing two concurrent global reset attempts.
1538 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1539 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1540 * but it may be held by some long running waiter (that we cannot
1541 * interrupt without causing trouble). Once we are ready to do the GPU
1542 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1543 * they already hold the struct_mutex and want to participate they can
1544 * inspect the bit and do the reset directly, otherwise the worker
1545 * waits for the struct_mutex.
1547 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1548 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1549 * i915_gem_request_alloc(), this bit is checked and the sequence
1550 * aborted (with -EIO reported to userspace) if set.
1552 unsigned long flags;
1553 #define I915_RESET_BACKOFF 0
1554 #define I915_RESET_HANDOFF 1
1555 #define I915_WEDGED (BITS_PER_LONG - 1)
1558 * Waitqueue to signal when a hang is detected. Used to for waiters
1559 * to release the struct_mutex for the reset to procede.
1561 wait_queue_head_t wait_queue;
1564 * Waitqueue to signal when the reset has completed. Used by clients
1565 * that wait for dev_priv->mm.wedged to settle.
1567 wait_queue_head_t reset_queue;
1569 /* For missed irq/seqno simulation. */
1570 unsigned long test_irq_rings;
1573 enum modeset_restore {
1574 MODESET_ON_LID_OPEN,
1579 #define DP_AUX_A 0x40
1580 #define DP_AUX_B 0x10
1581 #define DP_AUX_C 0x20
1582 #define DP_AUX_D 0x30
1584 #define DDC_PIN_B 0x05
1585 #define DDC_PIN_C 0x04
1586 #define DDC_PIN_D 0x06
1588 struct ddi_vbt_port_info {
1590 * This is an index in the HDMI/DVI DDI buffer translation table.
1591 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1592 * populate this field.
1594 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1595 uint8_t hdmi_level_shift;
1597 uint8_t supports_dvi:1;
1598 uint8_t supports_hdmi:1;
1599 uint8_t supports_dp:1;
1600 uint8_t supports_edp:1;
1602 uint8_t alternate_aux_channel;
1603 uint8_t alternate_ddc_pin;
1605 uint8_t dp_boost_level;
1606 uint8_t hdmi_boost_level;
1609 enum psr_lines_to_wait {
1610 PSR_0_LINES_TO_WAIT = 0,
1612 PSR_4_LINES_TO_WAIT,
1616 struct intel_vbt_data {
1617 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1618 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1621 unsigned int int_tv_support:1;
1622 unsigned int lvds_dither:1;
1623 unsigned int lvds_vbt:1;
1624 unsigned int int_crt_support:1;
1625 unsigned int lvds_use_ssc:1;
1626 unsigned int display_clock_mode:1;
1627 unsigned int fdi_rx_polarity_inverted:1;
1628 unsigned int panel_type:4;
1630 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1632 enum drrs_support_type drrs_type;
1643 struct edp_power_seq pps;
1648 bool require_aux_wakeup;
1650 enum psr_lines_to_wait lines_to_wait;
1651 int tp1_wakeup_time;
1652 int tp2_tp3_wakeup_time;
1658 bool active_low_pwm;
1659 u8 min_brightness; /* min_brightness/255 of max */
1660 u8 controller; /* brightness controller number */
1661 enum intel_backlight_type type;
1667 struct mipi_config *config;
1668 struct mipi_pps_data *pps;
1672 const u8 *sequence[MIPI_SEQ_MAX];
1678 union child_device_config *child_dev;
1680 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1681 struct sdvo_device_mapping sdvo_mappings[2];
1684 enum intel_ddb_partitioning {
1686 INTEL_DDB_PART_5_6, /* IVB+ */
1689 struct intel_wm_level {
1697 struct ilk_wm_values {
1698 uint32_t wm_pipe[3];
1700 uint32_t wm_lp_spr[3];
1701 uint32_t wm_linetime[3];
1703 enum intel_ddb_partitioning partitioning;
1706 struct g4x_pipe_wm {
1707 uint16_t plane[I915_MAX_PLANES];
1717 struct vlv_wm_ddl_values {
1718 uint8_t plane[I915_MAX_PLANES];
1721 struct vlv_wm_values {
1722 struct g4x_pipe_wm pipe[3];
1723 struct g4x_sr_wm sr;
1724 struct vlv_wm_ddl_values ddl[3];
1729 struct g4x_wm_values {
1730 struct g4x_pipe_wm pipe[2];
1731 struct g4x_sr_wm sr;
1732 struct g4x_sr_wm hpll;
1738 struct skl_ddb_entry {
1739 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1742 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1744 return entry->end - entry->start;
1747 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1748 const struct skl_ddb_entry *e2)
1750 if (e1->start == e2->start && e1->end == e2->end)
1756 struct skl_ddb_allocation {
1757 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1758 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1761 struct skl_wm_values {
1762 unsigned dirty_pipes;
1763 struct skl_ddb_allocation ddb;
1766 struct skl_wm_level {
1768 uint16_t plane_res_b;
1769 uint8_t plane_res_l;
1773 * This struct helps tracking the state needed for runtime PM, which puts the
1774 * device in PCI D3 state. Notice that when this happens, nothing on the
1775 * graphics device works, even register access, so we don't get interrupts nor
1778 * Every piece of our code that needs to actually touch the hardware needs to
1779 * either call intel_runtime_pm_get or call intel_display_power_get with the
1780 * appropriate power domain.
1782 * Our driver uses the autosuspend delay feature, which means we'll only really
1783 * suspend if we stay with zero refcount for a certain amount of time. The
1784 * default value is currently very conservative (see intel_runtime_pm_enable), but
1785 * it can be changed with the standard runtime PM files from sysfs.
1787 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1788 * goes back to false exactly before we reenable the IRQs. We use this variable
1789 * to check if someone is trying to enable/disable IRQs while they're supposed
1790 * to be disabled. This shouldn't happen and we'll print some error messages in
1793 * For more, read the Documentation/power/runtime_pm.txt.
1795 struct i915_runtime_pm {
1796 atomic_t wakeref_count;
1801 enum intel_pipe_crc_source {
1802 INTEL_PIPE_CRC_SOURCE_NONE,
1803 INTEL_PIPE_CRC_SOURCE_PLANE1,
1804 INTEL_PIPE_CRC_SOURCE_PLANE2,
1805 INTEL_PIPE_CRC_SOURCE_PF,
1806 INTEL_PIPE_CRC_SOURCE_PIPE,
1807 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1808 INTEL_PIPE_CRC_SOURCE_TV,
1809 INTEL_PIPE_CRC_SOURCE_DP_B,
1810 INTEL_PIPE_CRC_SOURCE_DP_C,
1811 INTEL_PIPE_CRC_SOURCE_DP_D,
1812 INTEL_PIPE_CRC_SOURCE_AUTO,
1813 INTEL_PIPE_CRC_SOURCE_MAX,
1816 struct intel_pipe_crc_entry {
1821 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1822 struct intel_pipe_crc {
1824 bool opened; /* exclusive access to the result file */
1825 struct intel_pipe_crc_entry *entries;
1826 enum intel_pipe_crc_source source;
1828 wait_queue_head_t wq;
1832 struct i915_frontbuffer_tracking {
1836 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1843 struct i915_wa_reg {
1846 /* bitmask representing WA bits */
1851 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1852 * allowing it for RCS as we don't foresee any requirement of having
1853 * a whitelist for other engines. When it is really required for
1854 * other engines then the limit need to be increased.
1856 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1858 struct i915_workarounds {
1859 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1861 u32 hw_whitelist_count[I915_NUM_ENGINES];
1864 struct i915_virtual_gpu {
1868 /* used in computing the new watermarks state */
1869 struct intel_wm_config {
1870 unsigned int num_pipes_active;
1871 bool sprites_enabled;
1872 bool sprites_scaled;
1875 struct i915_oa_format {
1880 struct i915_oa_reg {
1885 struct i915_perf_stream;
1888 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1890 struct i915_perf_stream_ops {
1892 * @enable: Enables the collection of HW samples, either in response to
1893 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1894 * without `I915_PERF_FLAG_DISABLED`.
1896 void (*enable)(struct i915_perf_stream *stream);
1899 * @disable: Disables the collection of HW samples, either in response
1900 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1903 void (*disable)(struct i915_perf_stream *stream);
1906 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1907 * once there is something ready to read() for the stream
1909 void (*poll_wait)(struct i915_perf_stream *stream,
1914 * @wait_unlocked: For handling a blocking read, wait until there is
1915 * something to ready to read() for the stream. E.g. wait on the same
1916 * wait queue that would be passed to poll_wait().
1918 int (*wait_unlocked)(struct i915_perf_stream *stream);
1921 * @read: Copy buffered metrics as records to userspace
1922 * **buf**: the userspace, destination buffer
1923 * **count**: the number of bytes to copy, requested by userspace
1924 * **offset**: zero at the start of the read, updated as the read
1925 * proceeds, it represents how many bytes have been copied so far and
1926 * the buffer offset for copying the next record.
1928 * Copy as many buffered i915 perf samples and records for this stream
1929 * to userspace as will fit in the given buffer.
1931 * Only write complete records; returning -%ENOSPC if there isn't room
1932 * for a complete record.
1934 * Return any error condition that results in a short read such as
1935 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1936 * returning to userspace.
1938 int (*read)(struct i915_perf_stream *stream,
1944 * @destroy: Cleanup any stream specific resources.
1946 * The stream will always be disabled before this is called.
1948 void (*destroy)(struct i915_perf_stream *stream);
1952 * struct i915_perf_stream - state for a single open stream FD
1954 struct i915_perf_stream {
1956 * @dev_priv: i915 drm device
1958 struct drm_i915_private *dev_priv;
1961 * @link: Links the stream into ``&drm_i915_private->streams``
1963 struct list_head link;
1966 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1967 * properties given when opening a stream, representing the contents
1968 * of a single sample as read() by userspace.
1973 * @sample_size: Considering the configured contents of a sample
1974 * combined with the required header size, this is the total size
1975 * of a single sample record.
1980 * @ctx: %NULL if measuring system-wide across all contexts or a
1981 * specific context that is being monitored.
1983 struct i915_gem_context *ctx;
1986 * @enabled: Whether the stream is currently enabled, considering
1987 * whether the stream was opened in a disabled state and based
1988 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1993 * @ops: The callbacks providing the implementation of this specific
1994 * type of configured stream.
1996 const struct i915_perf_stream_ops *ops;
2000 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2002 struct i915_oa_ops {
2004 * @init_oa_buffer: Resets the head and tail pointers of the
2005 * circular buffer for periodic OA reports.
2007 * Called when first opening a stream for OA metrics, but also may be
2008 * called in response to an OA buffer overflow or other error
2011 * Note it may be necessary to clear the full OA buffer here as part of
2012 * maintaining the invariable that new reports must be written to
2013 * zeroed memory for us to be able to reliable detect if an expected
2014 * report has not yet landed in memory. (At least on Haswell the OA
2015 * buffer tail pointer is not synchronized with reports being visible
2018 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2021 * @enable_metric_set: Applies any MUX configuration to set up the
2022 * Boolean and Custom (B/C) counters that are part of the counter
2023 * reports being sampled. May apply system constraints such as
2024 * disabling EU clock gating as required.
2026 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2029 * @disable_metric_set: Remove system constraints associated with using
2032 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2035 * @oa_enable: Enable periodic sampling
2037 void (*oa_enable)(struct drm_i915_private *dev_priv);
2040 * @oa_disable: Disable periodic sampling
2042 void (*oa_disable)(struct drm_i915_private *dev_priv);
2045 * @read: Copy data from the circular OA buffer into a given userspace
2048 int (*read)(struct i915_perf_stream *stream,
2054 * @oa_buffer_check: Check for OA buffer data + update tail
2056 * This is either called via fops or the poll check hrtimer (atomic
2057 * ctx) without any locks taken.
2059 * It's safe to read OA config state here unlocked, assuming that this
2060 * is only called while the stream is enabled, while the global OA
2061 * configuration can't be modified.
2063 * Efficiency is more important than avoiding some false positives
2064 * here, which will be handled gracefully - likely resulting in an
2065 * %EAGAIN error for userspace.
2067 bool (*oa_buffer_check)(struct drm_i915_private *dev_priv);
2070 struct intel_cdclk_state {
2071 unsigned int cdclk, vco, ref;
2074 struct drm_i915_private {
2075 struct drm_device drm;
2077 struct kmem_cache *objects;
2078 struct kmem_cache *vmas;
2079 struct kmem_cache *requests;
2080 struct kmem_cache *dependencies;
2081 struct kmem_cache *priorities;
2083 const struct intel_device_info info;
2087 struct intel_uncore uncore;
2089 struct i915_virtual_gpu vgpu;
2091 struct intel_gvt *gvt;
2093 struct intel_huc huc;
2094 struct intel_guc guc;
2096 struct intel_csr csr;
2098 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2100 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2101 * controller on different i2c buses. */
2102 struct mutex gmbus_mutex;
2105 * Base address of the gmbus and gpio block.
2107 uint32_t gpio_mmio_base;
2109 /* MMIO base address for MIPI regs */
2110 uint32_t mipi_mmio_base;
2112 uint32_t psr_mmio_base;
2114 uint32_t pps_mmio_base;
2116 wait_queue_head_t gmbus_wait_queue;
2118 struct pci_dev *bridge_dev;
2119 struct i915_gem_context *kernel_context;
2120 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2121 struct i915_vma *semaphore;
2123 struct drm_dma_handle *status_page_dmah;
2124 struct resource mch_res;
2126 /* protects the irq masks */
2127 spinlock_t irq_lock;
2129 /* protects the mmio flip data */
2130 spinlock_t mmio_flip_lock;
2132 bool display_irqs_enabled;
2134 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2135 struct pm_qos_request pm_qos;
2137 /* Sideband mailbox protection */
2138 struct mutex sb_lock;
2140 /** Cached value of IMR to avoid reads in updating the bitfield */
2143 u32 de_irq_mask[I915_MAX_PIPES];
2150 u32 pipestat_irq_mask[I915_MAX_PIPES];
2152 struct i915_hotplug hotplug;
2153 struct intel_fbc fbc;
2154 struct i915_drrs drrs;
2155 struct intel_opregion opregion;
2156 struct intel_vbt_data vbt;
2158 bool preserve_bios_swizzle;
2161 struct intel_overlay *overlay;
2163 /* backlight registers and fields in struct intel_panel */
2164 struct mutex backlight_lock;
2167 bool no_aux_handshake;
2169 /* protects panel power sequencer state */
2170 struct mutex pps_mutex;
2172 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2173 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2175 unsigned int fsb_freq, mem_freq, is_ddr3;
2176 unsigned int skl_preferred_vco_freq;
2177 unsigned int max_cdclk_freq;
2179 unsigned int max_dotclk_freq;
2180 unsigned int rawclk_freq;
2181 unsigned int hpll_freq;
2182 unsigned int czclk_freq;
2186 * The current logical cdclk state.
2187 * See intel_atomic_state.cdclk.logical
2189 * For reading holding any crtc lock is sufficient,
2190 * for writing must hold all of them.
2192 struct intel_cdclk_state logical;
2194 * The current actual cdclk state.
2195 * See intel_atomic_state.cdclk.actual
2197 struct intel_cdclk_state actual;
2198 /* The current hardware cdclk state */
2199 struct intel_cdclk_state hw;
2203 * wq - Driver workqueue for GEM.
2205 * NOTE: Work items scheduled here are not allowed to grab any modeset
2206 * locks, for otherwise the flushing done in the pageflip code will
2207 * result in deadlocks.
2209 struct workqueue_struct *wq;
2211 /* Display functions */
2212 struct drm_i915_display_funcs display;
2214 /* PCH chipset type */
2215 enum intel_pch pch_type;
2216 unsigned short pch_id;
2218 unsigned long quirks;
2220 enum modeset_restore modeset_restore;
2221 struct mutex modeset_restore_lock;
2222 struct drm_atomic_state *modeset_restore_state;
2223 struct drm_modeset_acquire_ctx reset_ctx;
2225 struct list_head vm_list; /* Global list of all address spaces */
2226 struct i915_ggtt ggtt; /* VM representing the global address space */
2228 struct i915_gem_mm mm;
2229 DECLARE_HASHTABLE(mm_structs, 7);
2230 struct mutex mm_lock;
2232 /* The hw wants to have a stable context identifier for the lifetime
2233 * of the context (for OA, PASID, faults, etc). This is limited
2234 * in execlists to 21 bits.
2236 struct ida context_hw_ida;
2237 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2239 /* Kernel Modesetting */
2241 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2242 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2243 wait_queue_head_t pending_flip_queue;
2245 #ifdef CONFIG_DEBUG_FS
2246 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2249 /* dpll and cdclk state is protected by connection_mutex */
2250 int num_shared_dpll;
2251 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2252 const struct intel_dpll_mgr *dpll_mgr;
2255 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2256 * Must be global rather than per dpll, because on some platforms
2257 * plls share registers.
2259 struct mutex dpll_lock;
2261 unsigned int active_crtcs;
2262 unsigned int min_pixclk[I915_MAX_PIPES];
2264 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2266 struct i915_workarounds workarounds;
2268 struct i915_frontbuffer_tracking fb_tracking;
2270 struct intel_atomic_helper {
2271 struct llist_head free_list;
2272 struct work_struct free_work;
2277 bool mchbar_need_disable;
2279 struct intel_l3_parity l3_parity;
2281 /* Cannot be determined by PCIID. You must always read a register. */
2284 /* gen6+ rps state */
2285 struct intel_gen6_power_mgmt rps;
2287 /* ilk-only ips/rps state. Everything in here is protected by the global
2288 * mchdev_lock in intel_pm.c */
2289 struct intel_ilk_power_mgmt ips;
2291 struct i915_power_domains power_domains;
2293 struct i915_psr psr;
2295 struct i915_gpu_error gpu_error;
2297 struct drm_i915_gem_object *vlv_pctx;
2299 #ifdef CONFIG_DRM_FBDEV_EMULATION
2300 /* list of fbdev register on this device */
2301 struct intel_fbdev *fbdev;
2302 struct work_struct fbdev_suspend_work;
2305 struct drm_property *broadcast_rgb_property;
2306 struct drm_property *force_audio_property;
2308 /* hda/i915 audio component */
2309 struct i915_audio_component *audio_component;
2310 bool audio_component_registered;
2312 * av_mutex - mutex for audio/video sync
2315 struct mutex av_mutex;
2317 struct list_head context_list;
2321 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2322 u32 chv_phy_control;
2324 * Shadows for CHV DPLL_MD regs to keep the state
2325 * checker somewhat working in the presence hardware
2326 * crappiness (can't read out DPLL_MD for pipes B & C).
2328 u32 chv_dpll_md[I915_MAX_PIPES];
2332 bool suspended_to_idle;
2333 struct i915_suspend_saved_registers regfile;
2334 struct vlv_s0ix_state vlv_s0ix_state;
2337 I915_SAGV_UNKNOWN = 0,
2340 I915_SAGV_NOT_CONTROLLED
2345 * Raw watermark latency values:
2346 * in 0.1us units for WM0,
2347 * in 0.5us units for WM1+.
2350 uint16_t pri_latency[5];
2352 uint16_t spr_latency[5];
2354 uint16_t cur_latency[5];
2356 * Raw watermark memory latency values
2357 * for SKL for all 8 levels
2360 uint16_t skl_latency[8];
2362 /* current hardware state */
2364 struct ilk_wm_values hw;
2365 struct skl_wm_values skl_hw;
2366 struct vlv_wm_values vlv;
2367 struct g4x_wm_values g4x;
2373 * Should be held around atomic WM register writing; also
2374 * protects * intel_crtc->wm.active and
2375 * cstate->wm.need_postvbl_update.
2377 struct mutex wm_mutex;
2380 * Set during HW readout of watermarks/DDB. Some platforms
2381 * need to know when we're still using BIOS-provided values
2382 * (which we don't fully trust).
2384 bool distrust_bios_wm;
2387 struct i915_runtime_pm pm;
2392 struct kobject *metrics_kobj;
2393 struct ctl_table_header *sysctl_header;
2396 struct list_head streams;
2398 spinlock_t hook_lock;
2401 struct i915_perf_stream *exclusive_stream;
2403 u32 specific_ctx_id;
2405 struct hrtimer poll_check_timer;
2406 wait_queue_head_t poll_wq;
2410 * For rate limiting any notifications of spurious
2411 * invalid OA reports
2413 struct ratelimit_state spurious_report_rs;
2416 int period_exponent;
2420 const struct i915_oa_reg *mux_regs;
2422 const struct i915_oa_reg *b_counter_regs;
2423 int b_counter_regs_len;
2426 struct i915_vma *vma;
2432 * Locks reads and writes to all head/tail state
2434 * Consider: the head and tail pointer state
2435 * needs to be read consistently from a hrtimer
2436 * callback (atomic context) and read() fop
2437 * (user context) with tail pointer updates
2438 * happening in atomic context and head updates
2439 * in user context and the (unlikely)
2440 * possibility of read() errors needing to
2441 * reset all head/tail state.
2443 * Note: Contention or performance aren't
2444 * currently a significant concern here
2445 * considering the relatively low frequency of
2446 * hrtimer callbacks (5ms period) and that
2447 * reads typically only happen in response to a
2448 * hrtimer event and likely complete before the
2451 * Note: This lock is not held *while* reading
2452 * and copying data to userspace so the value
2453 * of head observed in htrimer callbacks won't
2454 * represent any partial consumption of data.
2456 spinlock_t ptr_lock;
2459 * One 'aging' tail pointer and one 'aged'
2460 * tail pointer ready to used for reading.
2462 * Initial values of 0xffffffff are invalid
2463 * and imply that an update is required
2464 * (and should be ignored by an attempted
2472 * Index for the aged tail ready to read()
2475 unsigned int aged_tail_idx;
2478 * A monotonic timestamp for when the current
2479 * aging tail pointer was read; used to
2480 * determine when it is old enough to trust.
2482 u64 aging_timestamp;
2485 * Although we can always read back the head
2486 * pointer register, we prefer to avoid
2487 * trusting the HW state, just to avoid any
2488 * risk that some hardware condition could
2489 * somehow bump the head pointer unpredictably
2490 * and cause us to forward the wrong OA buffer
2491 * data to userspace.
2496 u32 gen7_latched_oastatus1;
2498 struct i915_oa_ops ops;
2499 const struct i915_oa_format *oa_formats;
2504 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2506 void (*resume)(struct drm_i915_private *);
2507 void (*cleanup_engine)(struct intel_engine_cs *engine);
2509 struct list_head timelines;
2510 struct i915_gem_timeline global_timeline;
2511 u32 active_requests;
2514 * Is the GPU currently considered idle, or busy executing
2515 * userspace requests? Whilst idle, we allow runtime power
2516 * management to power down the hardware and display clocks.
2517 * In order to reduce the effect on performance, there
2518 * is a slight delay before we do so.
2523 * We leave the user IRQ off as much as possible,
2524 * but this means that requests will finish and never
2525 * be retired once the system goes idle. Set a timer to
2526 * fire periodically while the ring is running. When it
2527 * fires, go retire requests.
2529 struct delayed_work retire_work;
2532 * When we detect an idle GPU, we want to turn on
2533 * powersaving features. So once we see that there
2534 * are no more requests outstanding and no more
2535 * arrive within a small period of time, we fire
2536 * off the idle_work.
2538 struct delayed_work idle_work;
2540 ktime_t last_init_time;
2543 /* perform PHY state sanity checks? */
2544 bool chv_phy_assert[2];
2548 /* Used to save the pipe-to-encoder mapping for audio */
2549 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2551 /* necessary resource sharing with HDMI LPE audio driver. */
2553 struct platform_device *platdev;
2558 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2559 * will be rejected. Instead look for a better place.
2563 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2565 return container_of(dev, struct drm_i915_private, drm);
2568 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2570 return to_i915(dev_get_drvdata(kdev));
2573 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2575 return container_of(guc, struct drm_i915_private, guc);
2578 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2580 return container_of(huc, struct drm_i915_private, huc);
2583 /* Simple iterator over all initialised engines */
2584 #define for_each_engine(engine__, dev_priv__, id__) \
2586 (id__) < I915_NUM_ENGINES; \
2588 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2590 /* Iterator over subset of engines selected by mask */
2591 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2592 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2593 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2595 enum hdmi_force_audio {
2596 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2597 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2598 HDMI_AUDIO_AUTO, /* trust EDID */
2599 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2602 #define I915_GTT_OFFSET_NONE ((u32)-1)
2605 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2606 * considered to be the frontbuffer for the given plane interface-wise. This
2607 * doesn't mean that the hw necessarily already scans it out, but that any
2608 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2610 * We have one bit per pipe and per scanout plane type.
2612 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2613 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2614 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2615 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2616 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2617 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2618 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2619 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2620 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2621 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2622 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2623 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2626 * Optimised SGL iterator for GEM objects
2628 static __always_inline struct sgt_iter {
2629 struct scatterlist *sgp;
2636 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2637 struct sgt_iter s = { .sgp = sgl };
2640 s.max = s.curr = s.sgp->offset;
2641 s.max += s.sgp->length;
2643 s.dma = sg_dma_address(s.sgp);
2645 s.pfn = page_to_pfn(sg_page(s.sgp));
2651 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2654 if (unlikely(sg_is_chain(sg)))
2655 sg = sg_chain_ptr(sg);
2660 * __sg_next - return the next scatterlist entry in a list
2661 * @sg: The current sg entry
2664 * If the entry is the last, return NULL; otherwise, step to the next
2665 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2666 * otherwise just return the pointer to the current element.
2668 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2670 #ifdef CONFIG_DEBUG_SG
2671 BUG_ON(sg->sg_magic != SG_MAGIC);
2673 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2677 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2678 * @__dmap: DMA address (output)
2679 * @__iter: 'struct sgt_iter' (iterator state, internal)
2680 * @__sgt: sg_table to iterate over (input)
2682 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2683 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2684 ((__dmap) = (__iter).dma + (__iter).curr); \
2685 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2686 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2689 * for_each_sgt_page - iterate over the pages of the given sg_table
2690 * @__pp: page pointer (output)
2691 * @__iter: 'struct sgt_iter' (iterator state, internal)
2692 * @__sgt: sg_table to iterate over (input)
2694 #define for_each_sgt_page(__pp, __iter, __sgt) \
2695 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2696 ((__pp) = (__iter).pfn == 0 ? NULL : \
2697 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2698 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2699 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2701 static inline const struct intel_device_info *
2702 intel_info(const struct drm_i915_private *dev_priv)
2704 return &dev_priv->info;
2707 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2709 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2710 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2712 #define REVID_FOREVER 0xff
2713 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2715 #define GEN_FOREVER (0)
2717 * Returns true if Gen is in inclusive range [Start, End].
2719 * Use GEN_FOREVER for unbound start and or end.
2721 #define IS_GEN(dev_priv, s, e) ({ \
2722 unsigned int __s = (s), __e = (e); \
2723 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2724 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2725 if ((__s) != GEN_FOREVER) \
2727 if ((__e) == GEN_FOREVER) \
2728 __e = BITS_PER_LONG - 1; \
2731 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2735 * Return true if revision is in range [since,until] inclusive.
2737 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2739 #define IS_REVID(p, since, until) \
2740 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2742 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2743 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2744 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2745 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2746 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2747 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2748 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2749 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2750 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2751 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2752 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2753 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2754 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2755 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2756 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2757 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2758 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2759 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2760 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2761 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2762 INTEL_DEVID(dev_priv) == 0x0152 || \
2763 INTEL_DEVID(dev_priv) == 0x015a)
2764 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2765 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2766 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2767 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2768 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2769 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2770 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2771 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2772 #define IS_COFFEELAKE(dev_priv) ((dev_priv)->info.platform == INTEL_COFFEELAKE)
2773 #define IS_CANNONLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_CANNONLAKE)
2774 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2775 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2776 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2777 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2778 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2779 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2780 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2781 /* ULX machines are also considered ULT. */
2782 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2783 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2784 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2785 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2786 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2787 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2788 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2789 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2790 /* ULX machines are also considered ULT. */
2791 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2792 INTEL_DEVID(dev_priv) == 0x0A1E)
2793 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2794 INTEL_DEVID(dev_priv) == 0x1913 || \
2795 INTEL_DEVID(dev_priv) == 0x1916 || \
2796 INTEL_DEVID(dev_priv) == 0x1921 || \
2797 INTEL_DEVID(dev_priv) == 0x1926)
2798 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2799 INTEL_DEVID(dev_priv) == 0x1915 || \
2800 INTEL_DEVID(dev_priv) == 0x191E)
2801 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2802 INTEL_DEVID(dev_priv) == 0x5913 || \
2803 INTEL_DEVID(dev_priv) == 0x5916 || \
2804 INTEL_DEVID(dev_priv) == 0x5921 || \
2805 INTEL_DEVID(dev_priv) == 0x5926)
2806 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2807 INTEL_DEVID(dev_priv) == 0x5915 || \
2808 INTEL_DEVID(dev_priv) == 0x591E)
2809 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2810 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2811 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2812 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2813 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2814 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2816 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2818 #define SKL_REVID_A0 0x0
2819 #define SKL_REVID_B0 0x1
2820 #define SKL_REVID_C0 0x2
2821 #define SKL_REVID_D0 0x3
2822 #define SKL_REVID_E0 0x4
2823 #define SKL_REVID_F0 0x5
2824 #define SKL_REVID_G0 0x6
2825 #define SKL_REVID_H0 0x7
2827 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2829 #define BXT_REVID_A0 0x0
2830 #define BXT_REVID_A1 0x1
2831 #define BXT_REVID_B0 0x3
2832 #define BXT_REVID_B_LAST 0x8
2833 #define BXT_REVID_C0 0x9
2835 #define IS_BXT_REVID(dev_priv, since, until) \
2836 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2838 #define KBL_REVID_A0 0x0
2839 #define KBL_REVID_B0 0x1
2840 #define KBL_REVID_C0 0x2
2841 #define KBL_REVID_D0 0x3
2842 #define KBL_REVID_E0 0x4
2844 #define IS_KBL_REVID(dev_priv, since, until) \
2845 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2847 #define GLK_REVID_A0 0x0
2848 #define GLK_REVID_A1 0x1
2850 #define IS_GLK_REVID(dev_priv, since, until) \
2851 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2853 #define CNL_REVID_A0 0x0
2854 #define CNL_REVID_B0 0x1
2856 #define IS_CNL_REVID(p, since, until) \
2857 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2860 * The genX designation typically refers to the render engine, so render
2861 * capability related checks should use IS_GEN, while display and other checks
2862 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2865 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2866 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2867 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2868 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2869 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2870 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2871 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2872 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2873 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2875 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2876 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2877 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2879 #define ENGINE_MASK(id) BIT(id)
2880 #define RENDER_RING ENGINE_MASK(RCS)
2881 #define BSD_RING ENGINE_MASK(VCS)
2882 #define BLT_RING ENGINE_MASK(BCS)
2883 #define VEBOX_RING ENGINE_MASK(VECS)
2884 #define BSD2_RING ENGINE_MASK(VCS2)
2885 #define ALL_ENGINES (~0)
2887 #define HAS_ENGINE(dev_priv, id) \
2888 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2890 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2891 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2892 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2893 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2895 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2896 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2897 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2898 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2899 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2901 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2903 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2904 ((dev_priv)->info.has_logical_ring_contexts)
2905 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2906 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2907 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2909 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2910 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2911 ((dev_priv)->info.overlay_needs_physical)
2913 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2914 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2916 /* WaRsDisableCoarsePowerGating:skl,bxt */
2917 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2918 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2921 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2922 * even when in MSI mode. This results in spurious interrupt warnings if the
2923 * legacy irq no. is shared with another device. The kernel then disables that
2924 * interrupt source and so prevents the other device from working properly.
2926 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2927 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2929 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2930 * rows, which changed the alignment requirements and fence programming.
2932 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2933 !(IS_I915G(dev_priv) || \
2934 IS_I915GM(dev_priv)))
2935 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2936 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2938 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2939 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2940 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2941 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2943 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2945 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2947 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2948 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2949 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2950 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2951 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2953 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2955 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2956 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2959 * For now, anything with a GuC requires uCode loading, and then supports
2960 * command submission once loaded. But these are logically independent
2961 * properties, so we have separate macros to test them.
2963 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2964 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2965 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2966 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2967 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2969 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2971 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2973 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2974 #define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
2975 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2976 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2977 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2978 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2979 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2980 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2981 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2982 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2983 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2984 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2985 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2986 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2987 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2989 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2990 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2991 #define HAS_PCH_CNP_LP(dev_priv) \
2992 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2993 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2994 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2995 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2996 #define HAS_PCH_LPT_LP(dev_priv) \
2997 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2998 #define HAS_PCH_LPT_H(dev_priv) \
2999 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
3000 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3001 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3002 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3003 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3005 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3007 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3009 /* DPF == dynamic parity feature */
3010 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3011 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3012 2 : HAS_L3_DPF(dev_priv))
3014 #define GT_FREQUENCY_MULTIPLIER 50
3015 #define GEN9_FREQ_SCALER 3
3017 #include "i915_trace.h"
3019 static inline bool intel_vtd_active(void)
3021 #ifdef CONFIG_INTEL_IOMMU
3022 if (intel_iommu_gfx_mapped)
3028 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
3030 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
3034 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
3036 return IS_BROXTON(dev_priv) && intel_vtd_active();
3039 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
3042 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
3046 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
3047 const char *fmt, ...);
3049 #define i915_report_error(dev_priv, fmt, ...) \
3050 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3052 #ifdef CONFIG_COMPAT
3053 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
3056 #define i915_compat_ioctl NULL
3058 extern const struct dev_pm_ops i915_pm_ops;
3060 extern int i915_driver_load(struct pci_dev *pdev,
3061 const struct pci_device_id *ent);
3062 extern void i915_driver_unload(struct drm_device *dev);
3063 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3064 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3065 extern void i915_reset(struct drm_i915_private *dev_priv);
3066 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3067 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3068 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3069 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3070 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3071 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3072 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3073 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3075 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
3076 int intel_engines_init(struct drm_i915_private *dev_priv);
3078 /* intel_hotplug.c */
3079 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3080 u32 pin_mask, u32 long_mask);
3081 void intel_hpd_init(struct drm_i915_private *dev_priv);
3082 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3083 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3084 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3085 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3086 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3089 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3091 unsigned long delay;
3093 if (unlikely(!i915.enable_hangcheck))
3096 /* Don't continually defer the hangcheck so that it is always run at
3097 * least once after work has been scheduled on any ring. Otherwise,
3098 * we will ignore a hung ring if a second ring is kept busy.
3101 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3102 queue_delayed_work(system_long_wq,
3103 &dev_priv->gpu_error.hangcheck_work, delay);
3107 void i915_handle_error(struct drm_i915_private *dev_priv,
3109 const char *fmt, ...);
3111 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3112 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3113 int intel_irq_install(struct drm_i915_private *dev_priv);
3114 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3116 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3118 return dev_priv->gvt;
3121 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3123 return dev_priv->vgpu.active;
3127 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3131 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3134 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3135 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3136 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3139 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3140 uint32_t interrupt_mask,
3141 uint32_t enabled_irq_mask);
3143 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3145 ilk_update_display_irq(dev_priv, bits, bits);
3148 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3150 ilk_update_display_irq(dev_priv, bits, 0);
3152 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3154 uint32_t interrupt_mask,
3155 uint32_t enabled_irq_mask);
3156 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3157 enum pipe pipe, uint32_t bits)
3159 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3161 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3162 enum pipe pipe, uint32_t bits)
3164 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3166 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3167 uint32_t interrupt_mask,
3168 uint32_t enabled_irq_mask);
3170 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3172 ibx_display_interrupt_update(dev_priv, bits, bits);
3175 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3177 ibx_display_interrupt_update(dev_priv, bits, 0);
3181 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3182 struct drm_file *file_priv);
3183 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3184 struct drm_file *file_priv);
3185 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3186 struct drm_file *file_priv);
3187 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3188 struct drm_file *file_priv);
3189 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3190 struct drm_file *file_priv);
3191 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3192 struct drm_file *file_priv);
3193 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3194 struct drm_file *file_priv);
3195 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3196 struct drm_file *file_priv);
3197 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3198 struct drm_file *file_priv);
3199 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3200 struct drm_file *file_priv);
3201 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3202 struct drm_file *file);
3203 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3204 struct drm_file *file);
3205 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3206 struct drm_file *file_priv);
3207 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3208 struct drm_file *file_priv);
3209 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3210 struct drm_file *file_priv);
3211 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3212 struct drm_file *file_priv);
3213 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3214 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3215 struct drm_file *file);
3216 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3217 struct drm_file *file_priv);
3218 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3219 struct drm_file *file_priv);
3220 void i915_gem_sanitize(struct drm_i915_private *i915);
3221 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3222 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3223 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3224 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3225 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3227 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3228 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3229 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3230 const struct drm_i915_gem_object_ops *ops);
3231 struct drm_i915_gem_object *
3232 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3233 struct drm_i915_gem_object *
3234 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3235 const void *data, size_t size);
3236 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3237 void i915_gem_free_object(struct drm_gem_object *obj);
3239 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3241 /* A single pass should suffice to release all the freed objects (along
3242 * most call paths) , but be a little more paranoid in that freeing
3243 * the objects does take a little amount of time, during which the rcu
3244 * callbacks could have added new objects into the freed list, and
3245 * armed the work again.
3249 } while (flush_work(&i915->mm.free_work));
3252 struct i915_vma * __must_check
3253 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3254 const struct i915_ggtt_view *view,
3259 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3260 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3262 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3264 static inline int __sg_page_count(const struct scatterlist *sg)
3266 return sg->length >> PAGE_SHIFT;
3269 struct scatterlist *
3270 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3271 unsigned int n, unsigned int *offset);
3274 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3278 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3282 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3285 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3286 struct sg_table *pages);
3287 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3289 static inline int __must_check
3290 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3292 might_lock(&obj->mm.lock);
3294 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3297 return __i915_gem_object_get_pages(obj);
3301 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3303 GEM_BUG_ON(!obj->mm.pages);
3305 atomic_inc(&obj->mm.pages_pin_count);
3309 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3311 return atomic_read(&obj->mm.pages_pin_count);
3315 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3317 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3318 GEM_BUG_ON(!obj->mm.pages);
3320 atomic_dec(&obj->mm.pages_pin_count);
3324 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3326 __i915_gem_object_unpin_pages(obj);
3329 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3334 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3335 enum i915_mm_subclass subclass);
3336 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3338 enum i915_map_type {
3344 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3345 * @obj: the object to map into kernel address space
3346 * @type: the type of mapping, used to select pgprot_t
3348 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3349 * pages and then returns a contiguous mapping of the backing storage into
3350 * the kernel address space. Based on the @type of mapping, the PTE will be
3351 * set to either WriteBack or WriteCombine (via pgprot_t).
3353 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3354 * mapping is no longer required.
3356 * Returns the pointer through which to access the mapped object, or an
3357 * ERR_PTR() on error.
3359 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3360 enum i915_map_type type);
3363 * i915_gem_object_unpin_map - releases an earlier mapping
3364 * @obj: the object to unmap
3366 * After pinning the object and mapping its pages, once you are finished
3367 * with your access, call i915_gem_object_unpin_map() to release the pin
3368 * upon the mapping. Once the pin count reaches zero, that mapping may be
3371 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3373 i915_gem_object_unpin_pages(obj);
3376 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3377 unsigned int *needs_clflush);
3378 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3379 unsigned int *needs_clflush);
3380 #define CLFLUSH_BEFORE BIT(0)
3381 #define CLFLUSH_AFTER BIT(1)
3382 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3385 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3387 i915_gem_object_unpin_pages(obj);
3390 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3391 void i915_vma_move_to_active(struct i915_vma *vma,
3392 struct drm_i915_gem_request *req,
3393 unsigned int flags);
3394 int i915_gem_dumb_create(struct drm_file *file_priv,
3395 struct drm_device *dev,
3396 struct drm_mode_create_dumb *args);
3397 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3398 uint32_t handle, uint64_t *offset);
3399 int i915_gem_mmap_gtt_version(void);
3401 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3402 struct drm_i915_gem_object *new,
3403 unsigned frontbuffer_bits);
3405 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3407 struct drm_i915_gem_request *
3408 i915_gem_find_active_request(struct intel_engine_cs *engine);
3410 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3412 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3414 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3417 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3419 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3422 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3424 return unlikely(test_bit(I915_WEDGED, &error->flags));
3427 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3429 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3432 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3434 return READ_ONCE(error->reset_count);
3437 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3438 void i915_gem_reset(struct drm_i915_private *dev_priv);
3439 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3440 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3441 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3443 void i915_gem_init_mmio(struct drm_i915_private *i915);
3444 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3445 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3446 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3447 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3448 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3449 unsigned int flags);
3450 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3451 void i915_gem_resume(struct drm_i915_private *dev_priv);
3452 int i915_gem_fault(struct vm_fault *vmf);
3453 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3456 struct intel_rps_client *rps);
3457 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3460 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3463 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3465 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3467 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3468 struct i915_vma * __must_check
3469 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3471 const struct i915_ggtt_view *view);
3472 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3473 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3475 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3476 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3478 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3479 enum i915_cache_level cache_level);
3481 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3482 struct dma_buf *dma_buf);
3484 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3485 struct drm_gem_object *gem_obj, int flags);
3487 static inline struct i915_hw_ppgtt *
3488 i915_vm_to_ppgtt(struct i915_address_space *vm)
3490 return container_of(vm, struct i915_hw_ppgtt, base);
3493 /* i915_gem_fence_reg.c */
3494 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3495 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3497 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3498 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3500 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3501 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3502 struct sg_table *pages);
3503 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3504 struct sg_table *pages);
3506 static inline struct i915_gem_context *
3507 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3509 struct i915_gem_context *ctx;
3511 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3513 ctx = idr_find(&file_priv->context_idr, id);
3515 return ERR_PTR(-ENOENT);
3520 static inline struct i915_gem_context *
3521 i915_gem_context_get(struct i915_gem_context *ctx)
3523 kref_get(&ctx->ref);
3527 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3529 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3530 kref_put(&ctx->ref, i915_gem_context_free);
3533 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3535 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3537 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3541 static inline struct intel_timeline *
3542 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3543 struct intel_engine_cs *engine)
3545 struct i915_address_space *vm;
3547 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3548 return &vm->timeline.engine[engine->id];
3551 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3552 struct drm_file *file);
3554 /* i915_gem_evict.c */
3555 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3556 u64 min_size, u64 alignment,
3557 unsigned cache_level,
3560 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3561 struct drm_mm_node *node,
3562 unsigned int flags);
3563 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3565 /* belongs in i915_gem_gtt.h */
3566 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3569 if (INTEL_GEN(dev_priv) < 6)
3570 intel_gtt_chipset_flush();
3573 /* i915_gem_stolen.c */
3574 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3575 struct drm_mm_node *node, u64 size,
3576 unsigned alignment);
3577 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3578 struct drm_mm_node *node, u64 size,
3579 unsigned alignment, u64 start,
3581 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3582 struct drm_mm_node *node);
3583 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3584 void i915_gem_cleanup_stolen(struct drm_device *dev);
3585 struct drm_i915_gem_object *
3586 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3587 struct drm_i915_gem_object *
3588 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3593 /* i915_gem_internal.c */
3594 struct drm_i915_gem_object *
3595 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3598 /* i915_gem_shrinker.c */
3599 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3600 unsigned long target,
3602 #define I915_SHRINK_PURGEABLE 0x1
3603 #define I915_SHRINK_UNBOUND 0x2
3604 #define I915_SHRINK_BOUND 0x4
3605 #define I915_SHRINK_ACTIVE 0x8
3606 #define I915_SHRINK_VMAPS 0x10
3607 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3608 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3609 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3612 /* i915_gem_tiling.c */
3613 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3615 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3617 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3618 i915_gem_object_is_tiled(obj);
3621 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3622 unsigned int tiling, unsigned int stride);
3623 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3624 unsigned int tiling, unsigned int stride);
3626 /* i915_debugfs.c */
3627 #ifdef CONFIG_DEBUG_FS
3628 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3629 int i915_debugfs_connector_add(struct drm_connector *connector);
3630 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3632 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3633 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3635 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3638 /* i915_gpu_error.c */
3639 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3642 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3643 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3644 const struct i915_gpu_state *gpu);
3645 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3646 struct drm_i915_private *i915,
3647 size_t count, loff_t pos);
3648 static inline void i915_error_state_buf_release(
3649 struct drm_i915_error_state_buf *eb)
3654 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3655 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3657 const char *error_msg);
3659 static inline struct i915_gpu_state *
3660 i915_gpu_state_get(struct i915_gpu_state *gpu)
3662 kref_get(&gpu->ref);
3666 void __i915_gpu_state_free(struct kref *kref);
3667 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3670 kref_put(&gpu->ref, __i915_gpu_state_free);
3673 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3674 void i915_reset_error_state(struct drm_i915_private *i915);
3678 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3680 const char *error_msg)
3684 static inline struct i915_gpu_state *
3685 i915_first_error_state(struct drm_i915_private *i915)
3690 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3696 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3698 /* i915_cmd_parser.c */
3699 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3700 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3701 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3702 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3703 struct drm_i915_gem_object *batch_obj,
3704 struct drm_i915_gem_object *shadow_batch_obj,
3705 u32 batch_start_offset,
3710 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3711 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3712 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3713 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3715 /* i915_suspend.c */
3716 extern int i915_save_state(struct drm_i915_private *dev_priv);
3717 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3720 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3721 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3723 /* intel_lpe_audio.c */
3724 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3725 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3726 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3727 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3728 enum pipe pipe, enum port port,
3729 const void *eld, int ls_clock, bool dp_output);
3732 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3733 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3734 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3737 extern struct i2c_adapter *
3738 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3739 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3740 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3741 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3743 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3745 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3748 void intel_bios_init(struct drm_i915_private *dev_priv);
3749 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3750 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3751 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3752 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3753 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3754 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3755 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3756 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3758 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3762 /* intel_opregion.c */
3764 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3765 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3766 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3767 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3768 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3770 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3772 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3774 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3775 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3776 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3777 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3781 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3786 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3790 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3798 extern void intel_register_dsm_handler(void);
3799 extern void intel_unregister_dsm_handler(void);
3801 static inline void intel_register_dsm_handler(void) { return; }
3802 static inline void intel_unregister_dsm_handler(void) { return; }
3803 #endif /* CONFIG_ACPI */
3805 /* intel_device_info.c */
3806 static inline struct intel_device_info *
3807 mkwrite_device_info(struct drm_i915_private *dev_priv)
3809 return (struct intel_device_info *)&dev_priv->info;
3812 const char *intel_platform_name(enum intel_platform platform);
3813 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3814 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3817 extern void intel_modeset_init_hw(struct drm_device *dev);
3818 extern int intel_modeset_init(struct drm_device *dev);
3819 extern void intel_modeset_gem_init(struct drm_device *dev);
3820 extern void intel_modeset_cleanup(struct drm_device *dev);
3821 extern int intel_connector_register(struct drm_connector *);
3822 extern void intel_connector_unregister(struct drm_connector *);
3823 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3825 extern void intel_display_resume(struct drm_device *dev);
3826 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3827 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3828 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3829 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3830 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3831 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3834 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3835 struct drm_file *file);
3838 extern struct intel_overlay_error_state *
3839 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3840 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3841 struct intel_overlay_error_state *error);
3843 extern struct intel_display_error_state *
3844 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3845 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3846 struct intel_display_error_state *error);
3848 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3849 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3850 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3851 u32 reply_mask, u32 reply, int timeout_base_ms);
3853 /* intel_sideband.c */
3854 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3855 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3856 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3857 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3858 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3859 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3860 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3861 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3862 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3863 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3864 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3865 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3866 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3867 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3868 enum intel_sbi_destination destination);
3869 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3870 enum intel_sbi_destination destination);
3871 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3872 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3874 /* intel_dpio_phy.c */
3875 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3876 enum dpio_phy *phy, enum dpio_channel *ch);
3877 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3878 enum port port, u32 margin, u32 scale,
3879 u32 enable, u32 deemphasis);
3880 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3881 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3882 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3884 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3886 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3887 uint8_t lane_count);
3888 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3889 uint8_t lane_lat_optim_mask);
3890 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3892 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3893 u32 deemph_reg_value, u32 margin_reg_value,
3894 bool uniq_trans_scale);
3895 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3897 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3898 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3899 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3900 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3902 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3903 u32 demph_reg_value, u32 preemph_reg_value,
3904 u32 uniqtranscale_reg_value, u32 tx3_demph);
3905 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3906 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3907 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3909 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3910 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3911 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3912 const i915_reg_t reg);
3914 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3915 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3917 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3918 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3919 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3920 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3922 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3923 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3924 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3925 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3927 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3928 * will be implemented using 2 32-bit writes in an arbitrary order with
3929 * an arbitrary delay between them. This can cause the hardware to
3930 * act upon the intermediate value, possibly leading to corruption and
3931 * machine death. For this reason we do not support I915_WRITE64, or
3932 * dev_priv->uncore.funcs.mmio_writeq.
3934 * When reading a 64-bit value as two 32-bit values, the delay may cause
3935 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3936 * occasionally a 64-bit register does not actualy support a full readq
3937 * and must be read using two 32-bit reads.
3939 * You have been warned.
3941 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3943 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3944 u32 upper, lower, old_upper, loop = 0; \
3945 upper = I915_READ(upper_reg); \
3947 old_upper = upper; \
3948 lower = I915_READ(lower_reg); \
3949 upper = I915_READ(upper_reg); \
3950 } while (upper != old_upper && loop++ < 2); \
3951 (u64)upper << 32 | lower; })
3953 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3954 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3956 #define __raw_read(x, s) \
3957 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3960 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3963 #define __raw_write(x, s) \
3964 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3965 i915_reg_t reg, uint##x##_t val) \
3967 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3982 /* These are untraced mmio-accessors that are only valid to be used inside
3983 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3986 * Think twice, and think again, before using these.
3988 * As an example, these accessors can possibly be used between:
3990 * spin_lock_irq(&dev_priv->uncore.lock);
3991 * intel_uncore_forcewake_get__locked();
3995 * intel_uncore_forcewake_put__locked();
3996 * spin_unlock_irq(&dev_priv->uncore.lock);
3999 * Note: some registers may not need forcewake held, so
4000 * intel_uncore_forcewake_{get,put} can be omitted, see
4001 * intel_uncore_forcewake_for_reg().
4003 * Certain architectures will die if the same cacheline is concurrently accessed
4004 * by different clients (e.g. on Ivybridge). Access to registers should
4005 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4006 * a more localised lock guarding all access to that bank of registers.
4008 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4009 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4010 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4011 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4013 /* "Broadcast RGB" property */
4014 #define INTEL_BROADCAST_RGB_AUTO 0
4015 #define INTEL_BROADCAST_RGB_FULL 1
4016 #define INTEL_BROADCAST_RGB_LIMITED 2
4018 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4020 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4021 return VLV_VGACNTRL;
4022 else if (INTEL_GEN(dev_priv) >= 5)
4023 return CPU_VGACNTRL;
4028 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
4030 unsigned long j = msecs_to_jiffies(m);
4032 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4035 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4037 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4040 static inline unsigned long
4041 timespec_to_jiffies_timeout(const struct timespec *value)
4043 unsigned long j = timespec_to_jiffies(value);
4045 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4049 * If you need to wait X milliseconds between events A and B, but event B
4050 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4051 * when event A happened, then just before event B you call this function and
4052 * pass the timestamp as the first argument, and X as the second argument.
4055 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4057 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4060 * Don't re-read the value of "jiffies" every time since it may change
4061 * behind our back and break the math.
4063 tmp_jiffies = jiffies;
4064 target_jiffies = timestamp_jiffies +
4065 msecs_to_jiffies_timeout(to_wait_ms);
4067 if (time_after(target_jiffies, tmp_jiffies)) {
4068 remaining_jiffies = target_jiffies - tmp_jiffies;
4069 while (remaining_jiffies)
4071 schedule_timeout_uninterruptible(remaining_jiffies);
4076 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4078 struct intel_engine_cs *engine = req->engine;
4081 /* Note that the engine may have wrapped around the seqno, and
4082 * so our request->global_seqno will be ahead of the hardware,
4083 * even though it completed the request before wrapping. We catch
4084 * this by kicking all the waiters before resetting the seqno
4085 * in hardware, and also signal the fence.
4087 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4090 /* The request was dequeued before we were awoken. We check after
4091 * inspecting the hw to confirm that this was the same request
4092 * that generated the HWS update. The memory barriers within
4093 * the request execution are sufficient to ensure that a check
4094 * after reading the value from hw matches this request.
4096 seqno = i915_gem_request_global_seqno(req);
4100 /* Before we do the heavier coherent read of the seqno,
4101 * check the value (hopefully) in the CPU cacheline.
4103 if (__i915_gem_request_completed(req, seqno))
4106 /* Ensure our read of the seqno is coherent so that we
4107 * do not "miss an interrupt" (i.e. if this is the last
4108 * request and the seqno write from the GPU is not visible
4109 * by the time the interrupt fires, we will see that the
4110 * request is incomplete and go back to sleep awaiting
4111 * another interrupt that will never come.)
4113 * Strictly, we only need to do this once after an interrupt,
4114 * but it is easier and safer to do it every time the waiter
4117 if (engine->irq_seqno_barrier &&
4118 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4119 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4121 /* The ordering of irq_posted versus applying the barrier
4122 * is crucial. The clearing of the current irq_posted must
4123 * be visible before we perform the barrier operation,
4124 * such that if a subsequent interrupt arrives, irq_posted
4125 * is reasserted and our task rewoken (which causes us to
4126 * do another __i915_request_irq_complete() immediately
4127 * and reapply the barrier). Conversely, if the clear
4128 * occurs after the barrier, then an interrupt that arrived
4129 * whilst we waited on the barrier would not trigger a
4130 * barrier on the next pass, and the read may not see the
4133 engine->irq_seqno_barrier(engine);
4135 /* If we consume the irq, but we are no longer the bottom-half,
4136 * the real bottom-half may not have serialised their own
4137 * seqno check with the irq-barrier (i.e. may have inspected
4138 * the seqno before we believe it coherent since they see
4139 * irq_posted == false but we are still running).
4141 spin_lock_irq(&b->irq_lock);
4142 if (b->irq_wait && b->irq_wait->tsk != current)
4143 /* Note that if the bottom-half is changed as we
4144 * are sending the wake-up, the new bottom-half will
4145 * be woken by whomever made the change. We only have
4146 * to worry about when we steal the irq-posted for
4149 wake_up_process(b->irq_wait->tsk);
4150 spin_unlock_irq(&b->irq_lock);
4152 if (__i915_gem_request_completed(req, seqno))
4159 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4160 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4162 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4163 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4164 * perform the operation. To check beforehand, pass in the parameters to
4165 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4166 * you only need to pass in the minor offsets, page-aligned pointers are
4169 * For just checking for SSE4.1, in the foreknowledge that the future use
4170 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4172 #define i915_can_memcpy_from_wc(dst, src, len) \
4173 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4175 #define i915_has_memcpy_from_wc() \
4176 i915_memcpy_from_wc(NULL, NULL, 0)
4179 int remap_io_mapping(struct vm_area_struct *vma,
4180 unsigned long addr, unsigned long pfn, unsigned long size,
4181 struct io_mapping *iomap);
4183 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4185 return (obj->cache_level != I915_CACHE_NONE ||
4186 HAS_LLC(to_i915(obj->base.dev)));