1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/dma-resv.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
49 #include <linux/xarray.h>
51 #include <drm/intel-gtt.h>
52 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
53 #include <drm/drm_gem.h>
54 #include <drm/drm_auth.h>
55 #include <drm/drm_cache.h>
56 #include <drm/drm_util.h>
57 #include <drm/drm_dsc.h>
58 #include <drm/drm_atomic.h>
59 #include <drm/drm_connector.h>
60 #include <drm/i915_mei_hdcp_interface.h>
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "display/intel_bios.h"
67 #include "display/intel_display.h"
68 #include "display/intel_display_power.h"
69 #include "display/intel_dpll_mgr.h"
70 #include "display/intel_dsb.h"
71 #include "display/intel_frontbuffer.h"
72 #include "display/intel_global_state.h"
73 #include "display/intel_gmbus.h"
74 #include "display/intel_opregion.h"
76 #include "gem/i915_gem_context_types.h"
77 #include "gem/i915_gem_shrinker.h"
78 #include "gem/i915_gem_stolen.h"
80 #include "gt/intel_lrc.h"
81 #include "gt/intel_engine.h"
82 #include "gt/intel_gt_types.h"
83 #include "gt/intel_workarounds.h"
84 #include "gt/uc/intel_uc.h"
86 #include "intel_device_info.h"
87 #include "intel_pch.h"
88 #include "intel_runtime_pm.h"
89 #include "intel_memory_region.h"
90 #include "intel_uncore.h"
91 #include "intel_wakeref.h"
92 #include "intel_wopcm.h"
95 #include "i915_gem_gtt.h"
96 #include "i915_gpu_error.h"
97 #include "i915_perf_types.h"
98 #include "i915_request.h"
99 #include "i915_scheduler.h"
100 #include "gt/intel_timeline.h"
101 #include "i915_vma.h"
102 #include "i915_irq.h"
104 #include "intel_region_lmem.h"
106 /* General customization:
109 #define DRIVER_NAME "i915"
110 #define DRIVER_DESC "Intel Graphics"
111 #define DRIVER_DATE "20200515"
112 #define DRIVER_TIMESTAMP 1589543364
114 struct drm_i915_gem_object;
117 * The code assumes that the hpd_pins below have consecutive values and
118 * starting with HPD_PORT_A, the HPD pin associated with any port can be
119 * retrieved by adding the corresponding port (or phy) enum value to
120 * HPD_PORT_A in most cases. For example:
121 * HPD_PORT_C = HPD_PORT_A + PHY_C - PHY_A
125 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
142 #define for_each_hpd_pin(__pin) \
143 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
145 /* Threshold == 5 for long IRQs, 50 for short */
146 #define HPD_STORM_DEFAULT_THRESHOLD 50
148 struct i915_hotplug {
149 struct delayed_work hotplug_work;
151 const u32 *hpd, *pch_hpd;
154 unsigned long last_jiffies;
159 HPD_MARK_DISABLED = 2
161 } stats[HPD_NUM_PINS];
164 struct delayed_work reenable_work;
168 struct work_struct dig_port_work;
170 struct work_struct poll_init_work;
173 unsigned int hpd_storm_threshold;
174 /* Whether or not to count short HPD IRQs in HPD storms */
175 u8 hpd_short_storm_enabled;
178 * if we get a HPD irq from DP and a HPD irq from non-DP
179 * the non-DP HPD could block the workqueue on a mode config
180 * mutex getting, that userspace may have taken. However
181 * userspace is waiting on the DP workqueue to run which is
182 * blocked behind the non-DP one.
184 struct workqueue_struct *dp_wq;
187 #define I915_GEM_GPU_DOMAINS \
188 (I915_GEM_DOMAIN_RENDER | \
189 I915_GEM_DOMAIN_SAMPLER | \
190 I915_GEM_DOMAIN_COMMAND | \
191 I915_GEM_DOMAIN_INSTRUCTION | \
192 I915_GEM_DOMAIN_VERTEX)
194 struct drm_i915_private;
195 struct i915_mm_struct;
196 struct i915_mmu_object;
198 struct drm_i915_file_private {
199 struct drm_i915_private *dev_priv;
202 struct drm_file *file;
208 struct list_head request_list;
211 struct xarray context_xa;
214 unsigned int bsd_engine;
217 * Every context ban increments per client ban score. Also
218 * hangs in short succession increments ban score. If ban threshold
219 * is reached, client is considered banned and submitting more work
220 * will fail. This is a stop gap measure to limit the badly behaving
221 * clients access to gpu. Note that unbannable contexts never increment
222 * the client ban score.
224 #define I915_CLIENT_SCORE_HANG_FAST 1
225 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
226 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
227 #define I915_CLIENT_SCORE_BANNED 9
228 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
230 unsigned long hang_timestamp;
233 /* Interface history:
236 * 1.2: Add Power Management
237 * 1.3: Add vblank support
238 * 1.4: Fix cmdbuffer path, add heap destroy
239 * 1.5: Add vblank pipe configuration
240 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
241 * - Support vertical blank on secondary display pipe
243 #define DRIVER_MAJOR 1
244 #define DRIVER_MINOR 6
245 #define DRIVER_PATCHLEVEL 0
247 struct intel_overlay;
248 struct intel_overlay_error_state;
250 struct sdvo_device_mapping {
259 struct intel_connector;
260 struct intel_encoder;
261 struct intel_atomic_state;
262 struct intel_cdclk_config;
263 struct intel_cdclk_state;
264 struct intel_cdclk_vals;
265 struct intel_initial_plane_config;
270 struct drm_i915_display_funcs {
271 void (*get_cdclk)(struct drm_i915_private *dev_priv,
272 struct intel_cdclk_config *cdclk_config);
273 void (*set_cdclk)(struct drm_i915_private *dev_priv,
274 const struct intel_cdclk_config *cdclk_config,
276 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
277 enum i9xx_plane_id i9xx_plane);
278 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
279 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
280 void (*initial_watermarks)(struct intel_atomic_state *state,
281 struct intel_crtc *crtc);
282 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
283 struct intel_crtc *crtc);
284 void (*optimize_watermarks)(struct intel_atomic_state *state,
285 struct intel_crtc *crtc);
286 int (*compute_global_watermarks)(struct intel_atomic_state *state);
287 void (*update_wm)(struct intel_crtc *crtc);
288 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
289 u8 (*calc_voltage_level)(int cdclk);
290 /* Returns the active state of the crtc, and if the crtc is active,
291 * fills out the pipe-config with the hw state. */
292 bool (*get_pipe_config)(struct intel_crtc *,
293 struct intel_crtc_state *);
294 void (*get_initial_plane_config)(struct intel_crtc *,
295 struct intel_initial_plane_config *);
296 int (*crtc_compute_clock)(struct intel_crtc *crtc,
297 struct intel_crtc_state *crtc_state);
298 void (*crtc_enable)(struct intel_atomic_state *state,
299 struct intel_crtc *crtc);
300 void (*crtc_disable)(struct intel_atomic_state *state,
301 struct intel_crtc *crtc);
302 void (*commit_modeset_enables)(struct intel_atomic_state *state);
303 void (*commit_modeset_disables)(struct intel_atomic_state *state);
304 void (*audio_codec_enable)(struct intel_encoder *encoder,
305 const struct intel_crtc_state *crtc_state,
306 const struct drm_connector_state *conn_state);
307 void (*audio_codec_disable)(struct intel_encoder *encoder,
308 const struct intel_crtc_state *old_crtc_state,
309 const struct drm_connector_state *old_conn_state);
310 void (*fdi_link_train)(struct intel_crtc *crtc,
311 const struct intel_crtc_state *crtc_state);
312 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
313 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
314 /* clock updates for mode set */
316 /* render clock increase/decrease */
317 /* display clock increase/decrease */
318 /* pll clock increase/decrease */
320 int (*color_check)(struct intel_crtc_state *crtc_state);
322 * Program double buffered color management registers during
323 * vblank evasion. The registers should then latch during the
324 * next vblank start, alongside any other double buffered registers
325 * involved with the same commit.
327 void (*color_commit)(const struct intel_crtc_state *crtc_state);
329 * Load LUTs (and other single buffered color management
330 * registers). Will (hopefully) be called during the vblank
331 * following the latching of any double buffered registers
332 * involved with the same commit.
334 void (*load_luts)(const struct intel_crtc_state *crtc_state);
335 void (*read_luts)(struct intel_crtc_state *crtc_state);
339 struct work_struct work;
341 u32 required_version;
342 u32 max_fw_size; /* bytes */
344 u32 dmc_fw_size; /* dwords */
347 i915_reg_t mmioaddr[20];
352 intel_wakeref_t wakeref;
355 enum i915_cache_level {
357 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
358 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
359 caches, eg sampler/render caches, and the
360 large Last-Level-Cache. LLC is coherent with
361 the CPU, but L3 is only visible to the GPU. */
362 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
365 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
368 /* This is always the inner lock when overlapping with struct_mutex and
369 * it's the outer lock when overlapping with stolen_lock. */
372 unsigned int possible_framebuffer_bits;
373 unsigned int busy_bits;
374 struct intel_crtc *crtc;
376 struct drm_mm_node compressed_fb;
377 struct drm_mm_node *compressed_llb;
385 bool underrun_detected;
386 struct work_struct underrun_work;
389 * Due to the atomic rules we can't access some structures without the
390 * appropriate locking, so we cache information here in order to avoid
393 struct intel_fbc_state_cache {
395 unsigned int mode_flags;
396 u32 hsw_bdw_pixel_rate;
400 unsigned int rotation;
405 * Display surface base address adjustement for
406 * pageflips. Note that on gen4+ this only adjusts up
407 * to a tile, offsets within a tile are handled in
408 * the hw itself (with the TILEOFF register).
415 u16 pixel_blend_mode;
419 const struct drm_format_info *format;
423 u16 gen9_wa_cfb_stride;
428 * This structure contains everything that's relevant to program the
429 * hardware registers. When we want to figure out if we need to disable
430 * and re-enable FBC for a new configuration we just check if there's
431 * something different in the struct. The genx_fbc_activate functions
432 * are supposed to read from it in order to program the registers.
434 struct intel_fbc_reg_params {
437 enum i9xx_plane_id i9xx_plane;
438 unsigned int fence_y_offset;
442 const struct drm_format_info *format;
447 u16 gen9_wa_cfb_stride;
452 const char *no_fbc_reason;
456 * HIGH_RR is the highest eDP panel refresh rate read from EDID
457 * LOW_RR is the lowest eDP panel refresh rate found from EDID
458 * parsing for same resolution.
460 enum drrs_refresh_rate_type {
463 DRRS_MAX_RR, /* RR count */
466 enum drrs_support_type {
467 DRRS_NOT_SUPPORTED = 0,
468 STATIC_DRRS_SUPPORT = 1,
469 SEAMLESS_DRRS_SUPPORT = 2
475 struct delayed_work work;
477 unsigned busy_frontbuffer_bits;
478 enum drrs_refresh_rate_type refresh_rate_type;
479 enum drrs_support_type type;
485 #define I915_PSR_DEBUG_MODE_MASK 0x0f
486 #define I915_PSR_DEBUG_DEFAULT 0x00
487 #define I915_PSR_DEBUG_DISABLE 0x01
488 #define I915_PSR_DEBUG_ENABLE 0x02
489 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
490 #define I915_PSR_DEBUG_IRQ 0x10
497 enum transcoder transcoder;
499 struct work_struct work;
500 unsigned busy_frontbuffer_bits;
501 bool sink_psr2_support;
503 bool colorimetry_support;
505 u8 sink_sync_latency;
506 ktime_t last_entry_attempt;
508 bool sink_not_reliable;
510 u16 su_x_granularity;
512 u32 dc3co_exit_delay;
513 struct delayed_work dc3co_work;
514 bool force_mode_changed;
515 struct drm_dp_vsc_sdp vsc;
518 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
519 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
520 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
521 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
522 #define QUIRK_INCREASE_T12_DELAY (1<<6)
523 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
526 struct intel_fbc_work;
529 struct i2c_adapter adapter;
530 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
534 struct i2c_algo_bit_data bit_algo;
535 struct drm_i915_private *dev_priv;
538 struct i915_suspend_saved_registers {
541 u32 saveCACHE_MODE_0;
542 u32 saveMI_ARB_STATE;
546 u32 savePCH_PORT_HOTPLUG;
550 struct vlv_s0ix_state;
552 #define MAX_L3_SLICES 2
553 struct intel_l3_parity {
554 u32 *remap_info[MAX_L3_SLICES];
555 struct work_struct error_work;
560 /** Memory allocator for GTT stolen memory */
561 struct drm_mm stolen;
562 /** Protects the usage of the GTT stolen memory allocator. This is
563 * always the inner lock when overlapping with struct_mutex. */
564 struct mutex stolen_lock;
566 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
570 * List of objects which are purgeable.
572 struct list_head purge_list;
575 * List of objects which have allocated pages and are shrinkable.
577 struct list_head shrink_list;
580 * List of objects which are pending destruction.
582 struct llist_head free_list;
583 struct work_struct free_work;
585 * Count of objects pending destructions. Used to skip needlessly
586 * waiting on an RCU barrier if no objects are waiting to be freed.
591 * Small stash of WC pages
593 struct pagestash wc_stash;
596 * tmpfs instance used for shmem backed objects
598 struct vfsmount *gemfs;
600 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
602 struct notifier_block oom_notifier;
603 struct notifier_block vmap_notifier;
604 struct shrinker shrinker;
607 * Workqueue to fault in userptr pages, flushed by the execbuf
608 * when required but otherwise left to userspace to try again
611 struct workqueue_struct *userptr_wq;
613 /* shrinker accounting, also useful for userland debugging */
618 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
620 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
623 static inline unsigned long
624 i915_fence_timeout(const struct drm_i915_private *i915)
626 return i915_fence_context_timeout(i915, U64_MAX);
629 /* Amount of SAGV/QGV points, BSpec precisely defines this */
630 #define I915_NUM_QGV_POINTS 8
632 struct ddi_vbt_port_info {
633 /* Non-NULL if port present. */
634 const struct child_device_config *child;
638 /* This is an index in the HDMI/DVI DDI buffer translation table. */
640 u8 hdmi_level_shift_set:1;
646 u8 supports_typec_usb:1;
649 u8 alternate_aux_channel;
650 u8 alternate_ddc_pin;
654 int dp_max_link_rate; /* 0 for not limited by VBT */
657 enum psr_lines_to_wait {
658 PSR_0_LINES_TO_WAIT = 0,
664 struct intel_vbt_data {
665 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
666 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
669 unsigned int int_tv_support:1;
670 unsigned int lvds_dither:1;
671 unsigned int int_crt_support:1;
672 unsigned int lvds_use_ssc:1;
673 unsigned int int_lvds_support:1;
674 unsigned int display_clock_mode:1;
675 unsigned int fdi_rx_polarity_inverted:1;
676 unsigned int panel_type:4;
678 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
679 enum drm_panel_orientation orientation;
681 enum drrs_support_type drrs_type;
691 struct edp_power_seq pps;
697 bool require_aux_wakeup;
699 enum psr_lines_to_wait lines_to_wait;
700 int tp1_wakeup_time_us;
701 int tp2_tp3_wakeup_time_us;
702 int psr2_tp2_tp3_wakeup_time_us;
709 u8 min_brightness; /* min_brightness/255 of max */
710 u8 controller; /* brightness controller number */
711 enum intel_backlight_type type;
717 struct mipi_config *config;
718 struct mipi_pps_data *pps;
724 const u8 *sequence[MIPI_SEQ_MAX];
725 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
726 enum drm_panel_orientation orientation;
731 struct list_head display_devices;
733 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
734 struct sdvo_device_mapping sdvo_mappings[2];
737 enum intel_ddb_partitioning {
739 INTEL_DDB_PART_5_6, /* IVB+ */
742 struct ilk_wm_values {
747 enum intel_ddb_partitioning partitioning;
751 u16 plane[I915_MAX_PLANES];
761 struct vlv_wm_ddl_values {
762 u8 plane[I915_MAX_PLANES];
765 struct vlv_wm_values {
766 struct g4x_pipe_wm pipe[3];
768 struct vlv_wm_ddl_values ddl[3];
773 struct g4x_wm_values {
774 struct g4x_pipe_wm pipe[2];
776 struct g4x_sr_wm hpll;
782 struct skl_ddb_entry {
783 u16 start, end; /* in number of blocks, 'end' is exclusive */
786 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
788 return entry->end - entry->start;
791 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
792 const struct skl_ddb_entry *e2)
794 if (e1->start == e2->start && e1->end == e2->end)
800 struct i915_frontbuffer_tracking {
804 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
811 struct i915_virtual_gpu {
812 struct mutex lock; /* serialises sending of g2v_notify command pkts */
817 struct intel_cdclk_config {
818 unsigned int cdclk, vco, ref, bypass;
822 struct i915_selftest_stash {
826 struct drm_i915_private {
827 struct drm_device drm;
829 /* FIXME: Device release actions should all be moved to drmm_ */
832 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
833 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
834 struct intel_driver_caps caps;
837 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
838 * end of stolen which we can optionally use to create GEM objects
839 * backed by stolen memory. Note that stolen_usable_size tells us
840 * exactly how much of this we are actually allowed to use, given that
841 * some portion of it is in fact reserved for use by hardware functions.
845 * Reseved portion of Data Stolen Memory
847 struct resource dsm_reserved;
850 * Stolen memory is segmented in hardware with different portions
851 * offlimits to certain functions.
853 * The drm_mm is initialised to the total accessible range, as found
854 * from the PCI config. On Broadwell+, this is further restricted to
855 * avoid the first page! The upper end of stolen memory is reserved for
856 * hardware functions and similarly removed from the accessible range.
858 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
860 struct intel_uncore uncore;
861 struct intel_uncore_mmio_debug mmio_debug;
863 struct i915_virtual_gpu vgpu;
865 struct intel_gvt *gvt;
867 struct intel_wopcm wopcm;
869 struct intel_csr csr;
871 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
873 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
874 * controller on different i2c buses. */
875 struct mutex gmbus_mutex;
878 * Base address of where the gmbus and gpio blocks are located (either
879 * on PCH or on SoC for platforms without PCH).
883 u32 hsw_psr_mmio_adjust;
885 /* MMIO base address for MIPI regs */
890 wait_queue_head_t gmbus_wait_queue;
892 struct pci_dev *bridge_dev;
894 struct rb_root uabi_engines;
896 struct resource mch_res;
898 /* protects the irq masks */
901 bool display_irqs_enabled;
903 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
904 struct pm_qos_request pm_qos;
906 /* Sideband mailbox protection */
907 struct mutex sb_lock;
908 struct pm_qos_request sb_qos;
910 /** Cached value of IMR to avoid reads in updating the bitfield */
913 u32 de_irq_mask[I915_MAX_PIPES];
915 u32 pipestat_irq_mask[I915_MAX_PIPES];
917 struct i915_hotplug hotplug;
918 struct intel_fbc fbc;
919 struct i915_drrs drrs;
920 struct intel_opregion opregion;
921 struct intel_vbt_data vbt;
923 bool preserve_bios_swizzle;
926 struct intel_overlay *overlay;
928 /* backlight registers and fields in struct intel_panel */
929 struct mutex backlight_lock;
931 /* protects panel power sequencer state */
932 struct mutex pps_mutex;
934 unsigned int fsb_freq, mem_freq, is_ddr3;
935 unsigned int skl_preferred_vco_freq;
936 unsigned int max_cdclk_freq;
938 unsigned int max_dotclk_freq;
939 unsigned int hpll_freq;
940 unsigned int fdi_pll_freq;
941 unsigned int czclk_freq;
944 /* The current hardware cdclk configuration */
945 struct intel_cdclk_config hw;
947 /* cdclk, divider, and ratio table from bspec */
948 const struct intel_cdclk_vals *table;
950 struct intel_global_obj obj;
954 * wq - Driver workqueue for GEM.
956 * NOTE: Work items scheduled here are not allowed to grab any modeset
957 * locks, for otherwise the flushing done in the pageflip code will
958 * result in deadlocks.
960 struct workqueue_struct *wq;
962 /* ordered wq for modesets */
963 struct workqueue_struct *modeset_wq;
964 /* unbound hipri wq for page flips/plane updates */
965 struct workqueue_struct *flip_wq;
967 /* Display functions */
968 struct drm_i915_display_funcs display;
970 /* PCH chipset type */
971 enum intel_pch pch_type;
972 unsigned short pch_id;
974 unsigned long quirks;
976 struct drm_atomic_state *modeset_restore_state;
977 struct drm_modeset_acquire_ctx reset_ctx;
979 struct i915_ggtt ggtt; /* VM representing the global address space */
981 struct i915_gem_mm mm;
982 DECLARE_HASHTABLE(mm_structs, 7);
983 struct mutex mm_lock;
985 /* Kernel Modesetting */
987 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
988 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
991 * dpll and cdclk state is protected by connection_mutex
992 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
993 * Must be global rather than per dpll, because on some platforms plls
1000 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1001 const struct intel_dpll_mgr *mgr;
1009 struct list_head global_obj_list;
1012 * For reading active_pipes holding any crtc lock is
1013 * sufficient, for writing must hold all of them.
1017 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1019 struct i915_wa_list gt_wa_list;
1021 struct i915_frontbuffer_tracking fb_tracking;
1023 struct intel_atomic_helper {
1024 struct llist_head free_list;
1025 struct work_struct free_work;
1028 bool mchbar_need_disable;
1030 struct intel_l3_parity l3_parity;
1034 * Cannot be determined by PCIID. You must always read a register.
1038 struct i915_power_domains power_domains;
1040 struct i915_psr psr;
1042 struct i915_gpu_error gpu_error;
1044 struct drm_i915_gem_object *vlv_pctx;
1046 /* list of fbdev register on this device */
1047 struct intel_fbdev *fbdev;
1048 struct work_struct fbdev_suspend_work;
1050 struct drm_property *broadcast_rgb_property;
1051 struct drm_property *force_audio_property;
1053 /* hda/i915 audio component */
1054 struct i915_audio_component *audio_component;
1055 bool audio_component_registered;
1057 * av_mutex - mutex for audio/video sync
1060 struct mutex av_mutex;
1061 int audio_power_refcount;
1062 u32 audio_freq_cntrl;
1066 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1067 u32 chv_phy_control;
1069 * Shadows for CHV DPLL_MD regs to keep the state
1070 * checker somewhat working in the presence hardware
1071 * crappiness (can't read out DPLL_MD for pipes B & C).
1073 u32 chv_dpll_md[I915_MAX_PIPES];
1077 bool power_domains_suspended;
1078 struct i915_suspend_saved_registers regfile;
1079 struct vlv_s0ix_state *vlv_s0ix_state;
1082 I915_SAGV_UNKNOWN = 0,
1085 I915_SAGV_NOT_CONTROLLED
1088 u32 sagv_block_time_us;
1092 * Raw watermark latency values:
1093 * in 0.1us units for WM0,
1094 * in 0.5us units for WM1+.
1103 * Raw watermark memory latency values
1104 * for SKL for all 8 levels
1109 /* current hardware state */
1111 struct ilk_wm_values hw;
1112 struct vlv_wm_values vlv;
1113 struct g4x_wm_values g4x;
1119 * Should be held around atomic WM register writing; also
1120 * protects * intel_crtc->wm.active and
1121 * crtc_state->wm.need_postvbl_update.
1123 struct mutex wm_mutex;
1126 * Set during HW readout of watermarks/DDB. Some platforms
1127 * need to know when we're still using BIOS-provided values
1128 * (which we don't fully trust).
1130 bool distrust_bios_wm;
1133 u8 enabled_dbuf_slices_mask; /* GEN11 has configurable 2 slices */
1141 bool symmetric_memory;
1142 enum intel_dram_type {
1151 struct intel_bw_info {
1152 /* for each QGV point */
1153 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1158 struct intel_global_obj bw_obj;
1160 struct intel_runtime_pm runtime_pm;
1162 struct i915_perf perf;
1164 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1168 struct i915_gem_contexts {
1169 spinlock_t lock; /* locks list */
1170 struct list_head list;
1172 struct llist_head free_list;
1173 struct work_struct free_work;
1177 * We replace the local file with a global mappings as the
1178 * backing storage for the mmap is on the device and not
1179 * on the struct file, and we do not want to prolong the
1180 * lifetime of the local fd. To minimise the number of
1181 * anonymous inodes we create, we use a global singleton to
1182 * share the global mapping.
1184 struct file *mmap_singleton;
1189 /* For i915gm/i945gm vblank irq workaround */
1192 /* perform PHY state sanity checks? */
1193 bool chv_phy_assert[2];
1197 /* Used to save the pipe-to-encoder mapping for audio */
1198 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1200 /* necessary resource sharing with HDMI LPE audio driver. */
1202 struct platform_device *platdev;
1206 struct i915_pmu pmu;
1208 struct i915_hdcp_comp_master *hdcp_master;
1209 bool hdcp_comp_added;
1211 /* Mutex to protect the above hdcp component related values. */
1212 struct mutex hdcp_comp_mutex;
1214 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1217 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1218 * will be rejected. Instead look for a better place.
1222 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1224 return container_of(dev, struct drm_i915_private, drm);
1227 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1229 return dev_get_drvdata(kdev);
1232 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1234 return pci_get_drvdata(pdev);
1237 /* Simple iterator over all initialised engines */
1238 #define for_each_engine(engine__, dev_priv__, id__) \
1240 (id__) < I915_NUM_ENGINES; \
1242 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1244 /* Iterator over subset of engines selected by mask */
1245 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1246 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1248 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1251 #define rb_to_uabi_engine(rb) \
1252 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1254 #define for_each_uabi_engine(engine__, i915__) \
1255 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1257 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1259 #define I915_GTT_OFFSET_NONE ((u32)-1)
1262 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1263 * considered to be the frontbuffer for the given plane interface-wise. This
1264 * doesn't mean that the hw necessarily already scans it out, but that any
1265 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1267 * We have one bit per pipe and per scanout plane type.
1269 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1270 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1271 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1272 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1273 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1275 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1276 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1277 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1278 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1279 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1281 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1282 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1283 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1285 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1286 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1288 #define REVID_FOREVER 0xff
1289 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
1291 #define INTEL_GEN_MASK(s, e) ( \
1292 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1293 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1294 GENMASK((e) - 1, (s) - 1))
1296 /* Returns true if Gen is in inclusive range [Start, End] */
1297 #define IS_GEN_RANGE(dev_priv, s, e) \
1298 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1300 #define IS_GEN(dev_priv, n) \
1301 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1302 INTEL_INFO(dev_priv)->gen == (n))
1304 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1307 * Return true if revision is in range [since,until] inclusive.
1309 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1311 #define IS_REVID(p, since, until) \
1312 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1314 static __always_inline unsigned int
1315 __platform_mask_index(const struct intel_runtime_info *info,
1316 enum intel_platform p)
1318 const unsigned int pbits =
1319 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1321 /* Expand the platform_mask array if this fails. */
1322 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1323 pbits * ARRAY_SIZE(info->platform_mask));
1328 static __always_inline unsigned int
1329 __platform_mask_bit(const struct intel_runtime_info *info,
1330 enum intel_platform p)
1332 const unsigned int pbits =
1333 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1335 return p % pbits + INTEL_SUBPLATFORM_BITS;
1339 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1341 const unsigned int pi = __platform_mask_index(info, p);
1343 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1346 static __always_inline bool
1347 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1349 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1350 const unsigned int pi = __platform_mask_index(info, p);
1351 const unsigned int pb = __platform_mask_bit(info, p);
1353 BUILD_BUG_ON(!__builtin_constant_p(p));
1355 return info->platform_mask[pi] & BIT(pb);
1358 static __always_inline bool
1359 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1360 enum intel_platform p, unsigned int s)
1362 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1363 const unsigned int pi = __platform_mask_index(info, p);
1364 const unsigned int pb = __platform_mask_bit(info, p);
1365 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1366 const u32 mask = info->platform_mask[pi];
1368 BUILD_BUG_ON(!__builtin_constant_p(p));
1369 BUILD_BUG_ON(!__builtin_constant_p(s));
1370 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1372 /* Shift and test on the MSB position so sign flag can be used. */
1373 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1376 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1377 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1379 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1380 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1381 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1382 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1383 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1384 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1385 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1386 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1387 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1388 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1389 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1390 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1391 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1392 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1393 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1394 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1395 #define IS_IRONLAKE_M(dev_priv) \
1396 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1397 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1398 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1399 INTEL_INFO(dev_priv)->gt == 1)
1400 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1401 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1402 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1403 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1404 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1405 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1406 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1407 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1408 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1409 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1410 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1411 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1412 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1413 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1414 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1415 #define IS_BDW_ULT(dev_priv) \
1416 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1417 #define IS_BDW_ULX(dev_priv) \
1418 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1419 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1420 INTEL_INFO(dev_priv)->gt == 3)
1421 #define IS_HSW_ULT(dev_priv) \
1422 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1423 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1424 INTEL_INFO(dev_priv)->gt == 3)
1425 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1426 INTEL_INFO(dev_priv)->gt == 1)
1427 /* ULX machines are also considered ULT. */
1428 #define IS_HSW_ULX(dev_priv) \
1429 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1430 #define IS_SKL_ULT(dev_priv) \
1431 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1432 #define IS_SKL_ULX(dev_priv) \
1433 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1434 #define IS_KBL_ULT(dev_priv) \
1435 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1436 #define IS_KBL_ULX(dev_priv) \
1437 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1438 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1439 INTEL_INFO(dev_priv)->gt == 2)
1440 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1441 INTEL_INFO(dev_priv)->gt == 3)
1442 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1443 INTEL_INFO(dev_priv)->gt == 4)
1444 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1445 INTEL_INFO(dev_priv)->gt == 2)
1446 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1447 INTEL_INFO(dev_priv)->gt == 3)
1448 #define IS_CFL_ULT(dev_priv) \
1449 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1450 #define IS_CFL_ULX(dev_priv) \
1451 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1452 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1453 INTEL_INFO(dev_priv)->gt == 2)
1454 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1455 INTEL_INFO(dev_priv)->gt == 3)
1456 #define IS_CNL_WITH_PORT_F(dev_priv) \
1457 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1458 #define IS_ICL_WITH_PORT_F(dev_priv) \
1459 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1461 #define SKL_REVID_A0 0x0
1462 #define SKL_REVID_B0 0x1
1463 #define SKL_REVID_C0 0x2
1464 #define SKL_REVID_D0 0x3
1465 #define SKL_REVID_E0 0x4
1466 #define SKL_REVID_F0 0x5
1467 #define SKL_REVID_G0 0x6
1468 #define SKL_REVID_H0 0x7
1470 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1472 #define BXT_REVID_A0 0x0
1473 #define BXT_REVID_A1 0x1
1474 #define BXT_REVID_B0 0x3
1475 #define BXT_REVID_B_LAST 0x8
1476 #define BXT_REVID_C0 0x9
1478 #define IS_BXT_REVID(dev_priv, since, until) \
1479 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1481 #define KBL_REVID_A0 0x0
1482 #define KBL_REVID_B0 0x1
1483 #define KBL_REVID_C0 0x2
1484 #define KBL_REVID_D0 0x3
1485 #define KBL_REVID_E0 0x4
1487 #define IS_KBL_REVID(dev_priv, since, until) \
1488 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1490 #define GLK_REVID_A0 0x0
1491 #define GLK_REVID_A1 0x1
1492 #define GLK_REVID_A2 0x2
1493 #define GLK_REVID_B0 0x3
1495 #define IS_GLK_REVID(dev_priv, since, until) \
1496 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1498 #define CNL_REVID_A0 0x0
1499 #define CNL_REVID_B0 0x1
1500 #define CNL_REVID_C0 0x2
1502 #define IS_CNL_REVID(p, since, until) \
1503 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1505 #define ICL_REVID_A0 0x0
1506 #define ICL_REVID_A2 0x1
1507 #define ICL_REVID_B0 0x3
1508 #define ICL_REVID_B2 0x4
1509 #define ICL_REVID_C0 0x5
1511 #define IS_ICL_REVID(p, since, until) \
1512 (IS_ICELAKE(p) && IS_REVID(p, since, until))
1514 #define EHL_REVID_A0 0x0
1516 #define IS_EHL_REVID(p, since, until) \
1517 (IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))
1519 #define TGL_REVID_A0 0x0
1520 #define TGL_REVID_B0 0x1
1521 #define TGL_REVID_C0 0x2
1523 #define IS_TGL_REVID(p, since, until) \
1524 (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1526 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1527 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1528 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1530 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1532 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
1533 unsigned int first__ = (first); \
1534 unsigned int count__ = (count); \
1535 (INTEL_INFO(dev_priv)->engine_mask & \
1536 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1538 #define VDBOX_MASK(dev_priv) \
1539 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1540 #define VEBOX_MASK(dev_priv) \
1541 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1544 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1545 * All later gens can run the final buffer from the ppgtt
1547 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1549 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1550 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1551 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1552 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1553 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
1554 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1556 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1558 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1559 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1560 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1561 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1562 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1563 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1565 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1567 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1568 #define HAS_PPGTT(dev_priv) \
1569 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1570 #define HAS_FULL_PPGTT(dev_priv) \
1571 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1573 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1574 GEM_BUG_ON((sizes) == 0); \
1575 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1578 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1579 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1580 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1582 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1583 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1585 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1586 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1588 /* WaRsDisableCoarsePowerGating:skl,cnl */
1589 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1590 (IS_CANNONLAKE(dev_priv) || \
1591 IS_SKL_GT3(dev_priv) || \
1592 IS_SKL_GT4(dev_priv))
1594 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1595 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1596 IS_GEMINILAKE(dev_priv) || \
1597 IS_KABYLAKE(dev_priv))
1599 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1600 * rows, which changed the alignment requirements and fence programming.
1602 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1603 !(IS_I915G(dev_priv) || \
1604 IS_I915GM(dev_priv)))
1605 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1606 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1608 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1609 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1610 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1612 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1614 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1616 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1617 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1618 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1619 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1621 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1622 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1623 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1625 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1627 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
1629 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1630 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1632 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1634 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1635 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1637 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1639 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1641 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1644 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1646 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1648 /* DPF == dynamic parity feature */
1649 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1650 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1651 2 : HAS_L3_DPF(dev_priv))
1653 #define GT_FREQUENCY_MULTIPLIER 50
1654 #define GEN9_FREQ_SCALER 3
1656 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1658 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1660 /* Only valid when HAS_DISPLAY() is true */
1661 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1663 static inline bool intel_vtd_active(void)
1665 #ifdef CONFIG_INTEL_IOMMU
1666 if (intel_iommu_gfx_mapped)
1672 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1674 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1678 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1680 return IS_BROXTON(dev_priv) && intel_vtd_active();
1684 extern const struct dev_pm_ops i915_pm_ops;
1686 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1687 void i915_driver_remove(struct drm_i915_private *i915);
1689 int i915_resume_switcheroo(struct drm_i915_private *i915);
1690 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1692 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1693 struct drm_file *file_priv);
1696 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1697 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1698 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1699 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1700 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1701 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1703 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1705 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1708 * A single pass should suffice to release all the freed objects (along
1709 * most call paths) , but be a little more paranoid in that freeing
1710 * the objects does take a little amount of time, during which the rcu
1711 * callbacks could have added new objects into the freed list, and
1712 * armed the work again.
1714 while (atomic_read(&i915->mm.free_count)) {
1715 flush_work(&i915->mm.free_work);
1720 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1723 * Similar to objects above (see i915_gem_drain_freed-objects), in
1724 * general we have workers that are armed by RCU and then rearm
1725 * themselves in their callbacks. To be paranoid, we need to
1726 * drain the workqueue a second time after waiting for the RCU
1727 * grace period so that we catch work queued via RCU from the first
1728 * pass. As neither drain_workqueue() nor flush_workqueue() report
1729 * a result, we make an assumption that we only don't require more
1730 * than 3 passes to catch all _recursive_ RCU delayed work.
1735 flush_workqueue(i915->wq);
1737 i915_gem_drain_freed_objects(i915);
1739 drain_workqueue(i915->wq);
1742 struct i915_vma * __must_check
1743 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1744 const struct i915_ggtt_view *view,
1749 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1750 unsigned long flags);
1751 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1752 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1753 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1755 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1757 int i915_gem_dumb_create(struct drm_file *file_priv,
1758 struct drm_device *dev,
1759 struct drm_mode_create_dumb *args);
1761 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1763 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1765 return atomic_read(&error->reset_count);
1768 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1769 const struct intel_engine_cs *engine)
1771 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1774 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1775 void i915_gem_driver_register(struct drm_i915_private *i915);
1776 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1777 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1778 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1779 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1780 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1781 void i915_gem_resume(struct drm_i915_private *dev_priv);
1783 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1784 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1786 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1787 enum i915_cache_level cache_level);
1789 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1790 struct dma_buf *dma_buf);
1792 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1794 static inline struct i915_gem_context *
1795 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1797 return xa_load(&file_priv->context_xa, id);
1800 static inline struct i915_gem_context *
1801 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1803 struct i915_gem_context *ctx;
1806 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1807 if (ctx && !kref_get_unless_zero(&ctx->ref))
1814 /* i915_gem_evict.c */
1815 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1816 u64 min_size, u64 alignment,
1817 unsigned long color,
1820 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1821 struct drm_mm_node *node,
1822 unsigned int flags);
1823 int i915_gem_evict_vm(struct i915_address_space *vm);
1825 /* i915_gem_internal.c */
1826 struct drm_i915_gem_object *
1827 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1830 /* i915_gem_tiling.c */
1831 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1833 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1835 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1836 i915_gem_object_is_tiled(obj);
1839 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1840 unsigned int tiling, unsigned int stride);
1841 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1842 unsigned int tiling, unsigned int stride);
1844 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1846 /* i915_cmd_parser.c */
1847 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1848 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1849 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1850 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1851 struct i915_vma *batch,
1854 struct i915_vma *shadow,
1856 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1858 /* intel_device_info.c */
1859 static inline struct intel_device_info *
1860 mkwrite_device_info(struct drm_i915_private *dev_priv)
1862 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1865 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1866 struct drm_file *file);
1868 #define __I915_REG_OP(op__, dev_priv__, ...) \
1869 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1871 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
1872 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1874 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
1876 /* These are untraced mmio-accessors that are only valid to be used inside
1877 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1880 * Think twice, and think again, before using these.
1882 * As an example, these accessors can possibly be used between:
1884 * spin_lock_irq(&dev_priv->uncore.lock);
1885 * intel_uncore_forcewake_get__locked();
1889 * intel_uncore_forcewake_put__locked();
1890 * spin_unlock_irq(&dev_priv->uncore.lock);
1893 * Note: some registers may not need forcewake held, so
1894 * intel_uncore_forcewake_{get,put} can be omitted, see
1895 * intel_uncore_forcewake_for_reg().
1897 * Certain architectures will die if the same cacheline is concurrently accessed
1898 * by different clients (e.g. on Ivybridge). Access to registers should
1899 * therefore generally be serialised, by either the dev_priv->uncore.lock or
1900 * a more localised lock guarding all access to that bank of registers.
1902 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
1903 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
1906 int remap_io_mapping(struct vm_area_struct *vma,
1907 unsigned long addr, unsigned long pfn, unsigned long size,
1908 struct io_mapping *iomap);
1909 int remap_io_sg(struct vm_area_struct *vma,
1910 unsigned long addr, unsigned long size,
1911 struct scatterlist *sgl, resource_size_t iobase);
1913 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1915 if (INTEL_GEN(i915) >= 10)
1916 return CNL_HWS_CSB_WRITE_INDEX;
1918 return I915_HWS_CSB_WRITE_INDEX;
1921 static inline enum i915_map_type
1922 i915_coherent_map_type(struct drm_i915_private *i915)
1924 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1927 static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val)
1929 return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
1933 static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val)
1935 return div_u64(val * 1000000000,
1936 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);