1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150522"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define for_each_hpd_pin(__pin) \
221 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
223 struct i915_hotplug {
224 struct work_struct hotplug_work;
227 unsigned long last_jiffies;
232 HPD_MARK_DISABLED = 2
234 } stats[HPD_NUM_PINS];
236 struct delayed_work reenable_work;
238 struct intel_digital_port *irq_port[I915_MAX_PORTS];
241 struct work_struct dig_port_work;
244 * if we get a HPD irq from DP and a HPD irq from non-DP
245 * the non-DP HPD could block the workqueue on a mode config
246 * mutex getting, that userspace may have taken. However
247 * userspace is waiting on the DP workqueue to run which is
248 * blocked behind the non-DP one.
250 struct workqueue_struct *dp_wq;
253 #define I915_GEM_GPU_DOMAINS \
254 (I915_GEM_DOMAIN_RENDER | \
255 I915_GEM_DOMAIN_SAMPLER | \
256 I915_GEM_DOMAIN_COMMAND | \
257 I915_GEM_DOMAIN_INSTRUCTION | \
258 I915_GEM_DOMAIN_VERTEX)
260 #define for_each_pipe(__dev_priv, __p) \
261 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
262 #define for_each_plane(__dev_priv, __pipe, __p) \
264 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
266 #define for_each_sprite(__dev_priv, __p, __s) \
268 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
271 #define for_each_crtc(dev, crtc) \
272 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
274 #define for_each_intel_plane(dev, intel_plane) \
275 list_for_each_entry(intel_plane, \
276 &dev->mode_config.plane_list, \
279 #define for_each_intel_crtc(dev, intel_crtc) \
280 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
282 #define for_each_intel_encoder(dev, intel_encoder) \
283 list_for_each_entry(intel_encoder, \
284 &(dev)->mode_config.encoder_list, \
287 #define for_each_intel_connector(dev, intel_connector) \
288 list_for_each_entry(intel_connector, \
289 &dev->mode_config.connector_list, \
292 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
293 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
294 if ((intel_encoder)->base.crtc == (__crtc))
296 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
297 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
298 if ((intel_connector)->base.encoder == (__encoder))
300 #define for_each_power_domain(domain, mask) \
301 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
302 if ((1 << (domain)) & (mask))
304 struct drm_i915_private;
305 struct i915_mm_struct;
306 struct i915_mmu_object;
308 struct drm_i915_file_private {
309 struct drm_i915_private *dev_priv;
310 struct drm_file *file;
314 struct list_head request_list;
315 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
316 * chosen to prevent the CPU getting more than a frame ahead of the GPU
317 * (when using lax throttling for the frontbuffer). We also use it to
318 * offer free GPU waitboosts for severely congested workloads.
320 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
322 struct idr context_idr;
324 struct intel_rps_client {
325 struct list_head link;
329 struct intel_engine_cs *bsd_ring;
333 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
334 /* real shared dpll ids must be >= 0 */
335 DPLL_ID_PCH_PLL_A = 0,
336 DPLL_ID_PCH_PLL_B = 1,
341 DPLL_ID_SKL_DPLL1 = 0,
342 DPLL_ID_SKL_DPLL2 = 1,
343 DPLL_ID_SKL_DPLL3 = 2,
345 #define I915_NUM_PLLS 3
347 struct intel_dpll_hw_state {
359 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
360 * lower part of ctrl1 and they get shifted into position when writing
361 * the register. This allows us to easily compare the state to share
365 /* HDMI only, 0 when used for DP */
366 uint32_t cfgcr1, cfgcr2;
369 uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
372 struct intel_shared_dpll_config {
373 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
374 struct intel_dpll_hw_state hw_state;
377 struct intel_shared_dpll {
378 struct intel_shared_dpll_config config;
379 struct intel_shared_dpll_config *new_config;
381 int active; /* count of number of active CRTCs (i.e. DPMS on) */
382 bool on; /* is the PLL actually active? Disabled during modeset */
384 /* should match the index in the dev_priv->shared_dplls array */
385 enum intel_dpll_id id;
386 /* The mode_set hook is optional and should be used together with the
387 * intel_prepare_shared_dpll function. */
388 void (*mode_set)(struct drm_i915_private *dev_priv,
389 struct intel_shared_dpll *pll);
390 void (*enable)(struct drm_i915_private *dev_priv,
391 struct intel_shared_dpll *pll);
392 void (*disable)(struct drm_i915_private *dev_priv,
393 struct intel_shared_dpll *pll);
394 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
395 struct intel_shared_dpll *pll,
396 struct intel_dpll_hw_state *hw_state);
404 /* Used by dp and fdi links */
405 struct intel_link_m_n {
413 void intel_link_compute_m_n(int bpp, int nlanes,
414 int pixel_clock, int link_clock,
415 struct intel_link_m_n *m_n);
417 /* Interface history:
420 * 1.2: Add Power Management
421 * 1.3: Add vblank support
422 * 1.4: Fix cmdbuffer path, add heap destroy
423 * 1.5: Add vblank pipe configuration
424 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
425 * - Support vertical blank on secondary display pipe
427 #define DRIVER_MAJOR 1
428 #define DRIVER_MINOR 6
429 #define DRIVER_PATCHLEVEL 0
431 #define WATCH_LISTS 0
433 struct opregion_header;
434 struct opregion_acpi;
435 struct opregion_swsci;
436 struct opregion_asle;
438 struct intel_opregion {
439 struct opregion_header __iomem *header;
440 struct opregion_acpi __iomem *acpi;
441 struct opregion_swsci __iomem *swsci;
442 u32 swsci_gbda_sub_functions;
443 u32 swsci_sbcb_sub_functions;
444 struct opregion_asle __iomem *asle;
446 u32 __iomem *lid_state;
447 struct work_struct asle_work;
449 #define OPREGION_SIZE (8*1024)
451 struct intel_overlay;
452 struct intel_overlay_error_state;
454 #define I915_FENCE_REG_NONE -1
455 #define I915_MAX_NUM_FENCES 32
456 /* 32 fences + sign bit for FENCE_REG_NONE */
457 #define I915_MAX_NUM_FENCE_BITS 6
459 struct drm_i915_fence_reg {
460 struct list_head lru_list;
461 struct drm_i915_gem_object *obj;
465 struct sdvo_device_mapping {
474 struct intel_display_error_state;
476 struct drm_i915_error_state {
484 /* Generic register state */
492 u32 error; /* gen6+ */
493 u32 err_int; /* gen7 */
494 u32 fault_data0; /* gen8, gen9 */
495 u32 fault_data1; /* gen8, gen9 */
501 u32 extra_instdone[I915_NUM_INSTDONE_REG];
502 u64 fence[I915_MAX_NUM_FENCES];
503 struct intel_overlay_error_state *overlay;
504 struct intel_display_error_state *display;
505 struct drm_i915_error_object *semaphore_obj;
507 struct drm_i915_error_ring {
509 /* Software tracked state */
512 enum intel_ring_hangcheck_action hangcheck_action;
515 /* our own tracking of ring head and tail */
519 u32 semaphore_seqno[I915_NUM_RINGS - 1];
538 u32 rc_psmi; /* sleep state */
539 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
541 struct drm_i915_error_object {
545 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
547 struct drm_i915_error_request {
562 char comm[TASK_COMM_LEN];
563 } ring[I915_NUM_RINGS];
565 struct drm_i915_error_buffer {
568 u32 rseqno[I915_NUM_RINGS], wseqno;
572 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
580 } **active_bo, **pinned_bo;
582 u32 *active_bo_count, *pinned_bo_count;
586 struct intel_connector;
587 struct intel_encoder;
588 struct intel_crtc_state;
589 struct intel_initial_plane_config;
594 struct drm_i915_display_funcs {
595 bool (*fbc_enabled)(struct drm_device *dev);
596 void (*enable_fbc)(struct drm_crtc *crtc);
597 void (*disable_fbc)(struct drm_device *dev);
598 int (*get_display_clock_speed)(struct drm_device *dev);
599 int (*get_fifo_size)(struct drm_device *dev, int plane);
601 * find_dpll() - Find the best values for the PLL
602 * @limit: limits for the PLL
603 * @crtc: current CRTC
604 * @target: target frequency in kHz
605 * @refclk: reference clock frequency in kHz
606 * @match_clock: if provided, @best_clock P divider must
607 * match the P divider from @match_clock
608 * used for LVDS downclocking
609 * @best_clock: best PLL values found
611 * Returns true on success, false on failure.
613 bool (*find_dpll)(const struct intel_limit *limit,
614 struct intel_crtc_state *crtc_state,
615 int target, int refclk,
616 struct dpll *match_clock,
617 struct dpll *best_clock);
618 void (*update_wm)(struct drm_crtc *crtc);
619 void (*update_sprite_wm)(struct drm_plane *plane,
620 struct drm_crtc *crtc,
621 uint32_t sprite_width, uint32_t sprite_height,
622 int pixel_size, bool enable, bool scaled);
623 void (*modeset_global_resources)(struct drm_atomic_state *state);
624 /* Returns the active state of the crtc, and if the crtc is active,
625 * fills out the pipe-config with the hw state. */
626 bool (*get_pipe_config)(struct intel_crtc *,
627 struct intel_crtc_state *);
628 void (*get_initial_plane_config)(struct intel_crtc *,
629 struct intel_initial_plane_config *);
630 int (*crtc_compute_clock)(struct intel_crtc *crtc,
631 struct intel_crtc_state *crtc_state);
632 void (*crtc_enable)(struct drm_crtc *crtc);
633 void (*crtc_disable)(struct drm_crtc *crtc);
634 void (*off)(struct drm_crtc *crtc);
635 void (*audio_codec_enable)(struct drm_connector *connector,
636 struct intel_encoder *encoder,
637 struct drm_display_mode *mode);
638 void (*audio_codec_disable)(struct intel_encoder *encoder);
639 void (*fdi_link_train)(struct drm_crtc *crtc);
640 void (*init_clock_gating)(struct drm_device *dev);
641 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
642 struct drm_framebuffer *fb,
643 struct drm_i915_gem_object *obj,
644 struct intel_engine_cs *ring,
646 void (*update_primary_plane)(struct drm_crtc *crtc,
647 struct drm_framebuffer *fb,
649 void (*hpd_irq_setup)(struct drm_device *dev);
650 /* clock updates for mode set */
652 /* render clock increase/decrease */
653 /* display clock increase/decrease */
654 /* pll clock increase/decrease */
656 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
657 uint32_t (*get_backlight)(struct intel_connector *connector);
658 void (*set_backlight)(struct intel_connector *connector,
660 void (*disable_backlight)(struct intel_connector *connector);
661 void (*enable_backlight)(struct intel_connector *connector);
664 enum forcewake_domain_id {
665 FW_DOMAIN_ID_RENDER = 0,
666 FW_DOMAIN_ID_BLITTER,
672 enum forcewake_domains {
673 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
674 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
675 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
676 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
681 struct intel_uncore_funcs {
682 void (*force_wake_get)(struct drm_i915_private *dev_priv,
683 enum forcewake_domains domains);
684 void (*force_wake_put)(struct drm_i915_private *dev_priv,
685 enum forcewake_domains domains);
687 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
688 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
689 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
690 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
692 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
693 uint8_t val, bool trace);
694 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
695 uint16_t val, bool trace);
696 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
697 uint32_t val, bool trace);
698 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
699 uint64_t val, bool trace);
702 struct intel_uncore {
703 spinlock_t lock; /** lock is also taken in irq contexts. */
705 struct intel_uncore_funcs funcs;
708 enum forcewake_domains fw_domains;
710 struct intel_uncore_forcewake_domain {
711 struct drm_i915_private *i915;
712 enum forcewake_domain_id id;
714 struct timer_list timer;
721 } fw_domain[FW_DOMAIN_ID_COUNT];
724 /* Iterate over initialised fw domains */
725 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
726 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
727 (i__) < FW_DOMAIN_ID_COUNT; \
728 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
729 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
731 #define for_each_fw_domain(domain__, dev_priv__, i__) \
732 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
735 FW_UNINITIALIZED = 0,
743 uint32_t dmc_fw_size;
745 uint32_t mmioaddr[8];
746 uint32_t mmiodata[8];
747 enum csr_state state;
750 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
751 func(is_mobile) sep \
754 func(is_i945gm) sep \
756 func(need_gfx_hws) sep \
758 func(is_pineview) sep \
759 func(is_broadwater) sep \
760 func(is_crestline) sep \
761 func(is_ivybridge) sep \
762 func(is_valleyview) sep \
763 func(is_haswell) sep \
764 func(is_skylake) sep \
765 func(is_preliminary) sep \
767 func(has_pipe_cxsr) sep \
768 func(has_hotplug) sep \
769 func(cursor_needs_physical) sep \
770 func(has_overlay) sep \
771 func(overlay_needs_physical) sep \
772 func(supports_tv) sep \
777 #define DEFINE_FLAG(name) u8 name:1
778 #define SEP_SEMICOLON ;
780 struct intel_device_info {
781 u32 display_mmio_offset;
784 u8 num_sprites[I915_MAX_PIPES];
786 u8 ring_mask; /* Rings supported by the HW */
787 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
788 /* Register offsets for the various display pipes and transcoders */
789 int pipe_offsets[I915_MAX_TRANSCODERS];
790 int trans_offsets[I915_MAX_TRANSCODERS];
791 int palette_offsets[I915_MAX_PIPES];
792 int cursor_offsets[I915_MAX_PIPES];
794 /* Slice/subslice/EU info */
797 u8 subslice_per_slice;
800 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
803 u8 has_subslice_pg:1;
810 enum i915_cache_level {
812 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
813 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
814 caches, eg sampler/render caches, and the
815 large Last-Level-Cache. LLC is coherent with
816 the CPU, but L3 is only visible to the GPU. */
817 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
820 struct i915_ctx_hang_stats {
821 /* This context had batch pending when hang was declared */
822 unsigned batch_pending;
824 /* This context had batch active when hang was declared */
825 unsigned batch_active;
827 /* Time when this context was last blamed for a GPU reset */
828 unsigned long guilty_ts;
830 /* If the contexts causes a second GPU hang within this time,
831 * it is permanently banned from submitting any more work.
833 unsigned long ban_period_seconds;
835 /* This context is banned to submit more work */
839 /* This must match up with the value previously used for execbuf2.rsvd1. */
840 #define DEFAULT_CONTEXT_HANDLE 0
842 #define CONTEXT_NO_ZEROMAP (1<<0)
844 * struct intel_context - as the name implies, represents a context.
845 * @ref: reference count.
846 * @user_handle: userspace tracking identity for this context.
847 * @remap_slice: l3 row remapping information.
848 * @flags: context specific flags:
849 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
850 * @file_priv: filp associated with this context (NULL for global default
852 * @hang_stats: information about the role of this context in possible GPU
854 * @ppgtt: virtual memory space used by this context.
855 * @legacy_hw_ctx: render context backing object and whether it is correctly
856 * initialized (legacy ring submission mechanism only).
857 * @link: link in the global list of contexts.
859 * Contexts are memory images used by the hardware to store copies of their
862 struct intel_context {
867 struct drm_i915_file_private *file_priv;
868 struct i915_ctx_hang_stats hang_stats;
869 struct i915_hw_ppgtt *ppgtt;
871 /* Legacy ring buffer submission */
873 struct drm_i915_gem_object *rcs_state;
878 bool rcs_initialized;
880 struct drm_i915_gem_object *state;
881 struct intel_ringbuffer *ringbuf;
883 } engine[I915_NUM_RINGS];
885 struct list_head link;
896 unsigned long uncompressed_size;
899 unsigned int possible_framebuffer_bits;
900 unsigned int busy_bits;
901 struct intel_crtc *crtc;
904 struct drm_mm_node compressed_fb;
905 struct drm_mm_node *compressed_llb;
909 /* Tracks whether the HW is actually enabled, not whether the feature is
913 struct intel_fbc_work {
914 struct delayed_work work;
915 struct drm_crtc *crtc;
916 struct drm_framebuffer *fb;
920 FBC_OK, /* FBC is enabled */
921 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
922 FBC_NO_OUTPUT, /* no outputs enabled to compress */
923 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
924 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
925 FBC_MODE_TOO_LARGE, /* mode too large for compression */
926 FBC_BAD_PLANE, /* fbc not supported on plane */
927 FBC_NOT_TILED, /* buffer not tiled */
928 FBC_MULTIPLE_PIPES, /* more than one pipe active */
930 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
935 * HIGH_RR is the highest eDP panel refresh rate read from EDID
936 * LOW_RR is the lowest eDP panel refresh rate found from EDID
937 * parsing for same resolution.
939 enum drrs_refresh_rate_type {
942 DRRS_MAX_RR, /* RR count */
945 enum drrs_support_type {
946 DRRS_NOT_SUPPORTED = 0,
947 STATIC_DRRS_SUPPORT = 1,
948 SEAMLESS_DRRS_SUPPORT = 2
954 struct delayed_work work;
956 unsigned busy_frontbuffer_bits;
957 enum drrs_refresh_rate_type refresh_rate_type;
958 enum drrs_support_type type;
965 struct intel_dp *enabled;
967 struct delayed_work work;
968 unsigned busy_frontbuffer_bits;
974 PCH_NONE = 0, /* No PCH present */
975 PCH_IBX, /* Ibexpeak PCH */
976 PCH_CPT, /* Cougarpoint PCH */
977 PCH_LPT, /* Lynxpoint PCH */
978 PCH_SPT, /* Sunrisepoint PCH */
982 enum intel_sbi_destination {
987 #define QUIRK_PIPEA_FORCE (1<<0)
988 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
989 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
990 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
991 #define QUIRK_PIPEB_FORCE (1<<4)
992 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
995 struct intel_fbc_work;
998 struct i2c_adapter adapter;
1002 struct i2c_algo_bit_data bit_algo;
1003 struct drm_i915_private *dev_priv;
1006 struct i915_suspend_saved_registers {
1009 u32 savePP_ON_DELAYS;
1010 u32 savePP_OFF_DELAYS;
1015 u32 saveFBC_CONTROL;
1016 u32 saveCACHE_MODE_0;
1017 u32 saveMI_ARB_STATE;
1021 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1022 u32 savePCH_PORT_HOTPLUG;
1026 struct vlv_s0ix_state {
1033 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1034 u32 media_max_req_count;
1035 u32 gfx_max_req_count;
1061 u32 rp_down_timeout;
1067 /* Display 1 CZ domain */
1072 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1074 /* GT SA CZ domain */
1081 /* Display 2 CZ domain */
1085 u32 clock_gate_dis2;
1088 struct intel_rps_ei {
1094 struct intel_gen6_power_mgmt {
1096 * work, interrupts_enabled and pm_iir are protected by
1097 * dev_priv->irq_lock
1099 struct work_struct work;
1100 bool interrupts_enabled;
1103 /* Frequencies are stored in potentially platform dependent multiples.
1104 * In other words, *_freq needs to be multiplied by X to be interesting.
1105 * Soft limits are those which are used for the dynamic reclocking done
1106 * by the driver (raise frequencies under heavy loads, and lower for
1107 * lighter loads). Hard limits are those imposed by the hardware.
1109 * A distinction is made for overclocking, which is never enabled by
1110 * default, and is considered to be above the hard limit if it's
1113 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1114 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1115 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1116 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1117 u8 min_freq; /* AKA RPn. Minimum frequency */
1118 u8 idle_freq; /* Frequency to request when we are idle */
1119 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1120 u8 rp1_freq; /* "less than" RP0 power/freqency */
1121 u8 rp0_freq; /* Non-overclocked max frequency. */
1124 u8 up_threshold; /* Current %busy required to uplock */
1125 u8 down_threshold; /* Current %busy required to downclock */
1128 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1130 spinlock_t client_lock;
1131 struct list_head clients;
1135 struct delayed_work delayed_resume_work;
1138 struct intel_rps_client semaphores, mmioflips;
1140 /* manual wa residency calculations */
1141 struct intel_rps_ei up_ei, down_ei;
1144 * Protects RPS/RC6 register access and PCU communication.
1145 * Must be taken after struct_mutex if nested. Note that
1146 * this lock may be held for long periods of time when
1147 * talking to hw - so only take it when talking to hw!
1149 struct mutex hw_lock;
1152 /* defined intel_pm.c */
1153 extern spinlock_t mchdev_lock;
1155 struct intel_ilk_power_mgmt {
1163 unsigned long last_time1;
1164 unsigned long chipset_power;
1167 unsigned long gfx_power;
1174 struct drm_i915_private;
1175 struct i915_power_well;
1177 struct i915_power_well_ops {
1179 * Synchronize the well's hw state to match the current sw state, for
1180 * example enable/disable it based on the current refcount. Called
1181 * during driver init and resume time, possibly after first calling
1182 * the enable/disable handlers.
1184 void (*sync_hw)(struct drm_i915_private *dev_priv,
1185 struct i915_power_well *power_well);
1187 * Enable the well and resources that depend on it (for example
1188 * interrupts located on the well). Called after the 0->1 refcount
1191 void (*enable)(struct drm_i915_private *dev_priv,
1192 struct i915_power_well *power_well);
1194 * Disable the well and resources that depend on it. Called after
1195 * the 1->0 refcount transition.
1197 void (*disable)(struct drm_i915_private *dev_priv,
1198 struct i915_power_well *power_well);
1199 /* Returns the hw enabled state. */
1200 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1201 struct i915_power_well *power_well);
1204 /* Power well structure for haswell */
1205 struct i915_power_well {
1208 /* power well enable/disable usage count */
1210 /* cached hw enabled state */
1212 unsigned long domains;
1214 const struct i915_power_well_ops *ops;
1217 struct i915_power_domains {
1219 * Power wells needed for initialization at driver init and suspend
1220 * time are on. They are kept on until after the first modeset.
1224 int power_well_count;
1227 int domain_use_count[POWER_DOMAIN_NUM];
1228 struct i915_power_well *power_wells;
1231 #define MAX_L3_SLICES 2
1232 struct intel_l3_parity {
1233 u32 *remap_info[MAX_L3_SLICES];
1234 struct work_struct error_work;
1238 struct i915_gem_mm {
1239 /** Memory allocator for GTT stolen memory */
1240 struct drm_mm stolen;
1241 /** List of all objects in gtt_space. Used to restore gtt
1242 * mappings on resume */
1243 struct list_head bound_list;
1245 * List of objects which are not bound to the GTT (thus
1246 * are idle and not used by the GPU) but still have
1247 * (presumably uncached) pages still attached.
1249 struct list_head unbound_list;
1251 /** Usable portion of the GTT for GEM */
1252 unsigned long stolen_base; /* limited to low memory (32-bit) */
1254 /** PPGTT used for aliasing the PPGTT with the GTT */
1255 struct i915_hw_ppgtt *aliasing_ppgtt;
1257 struct notifier_block oom_notifier;
1258 struct shrinker shrinker;
1259 bool shrinker_no_lock_stealing;
1261 /** LRU list of objects with fence regs on them. */
1262 struct list_head fence_list;
1265 * We leave the user IRQ off as much as possible,
1266 * but this means that requests will finish and never
1267 * be retired once the system goes idle. Set a timer to
1268 * fire periodically while the ring is running. When it
1269 * fires, go retire requests.
1271 struct delayed_work retire_work;
1274 * When we detect an idle GPU, we want to turn on
1275 * powersaving features. So once we see that there
1276 * are no more requests outstanding and no more
1277 * arrive within a small period of time, we fire
1278 * off the idle_work.
1280 struct delayed_work idle_work;
1283 * Are we in a non-interruptible section of code like
1289 * Is the GPU currently considered idle, or busy executing userspace
1290 * requests? Whilst idle, we attempt to power down the hardware and
1291 * display clocks. In order to reduce the effect on performance, there
1292 * is a slight delay before we do so.
1296 /* the indicator for dispatch video commands on two BSD rings */
1297 int bsd_ring_dispatch_index;
1299 /** Bit 6 swizzling required for X tiling */
1300 uint32_t bit_6_swizzle_x;
1301 /** Bit 6 swizzling required for Y tiling */
1302 uint32_t bit_6_swizzle_y;
1304 /* accounting, useful for userland debugging */
1305 spinlock_t object_stat_lock;
1306 size_t object_memory;
1310 struct drm_i915_error_state_buf {
1311 struct drm_i915_private *i915;
1320 struct i915_error_state_file_priv {
1321 struct drm_device *dev;
1322 struct drm_i915_error_state *error;
1325 struct i915_gpu_error {
1326 /* For hangcheck timer */
1327 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1328 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1329 /* Hang gpu twice in this window and your context gets banned */
1330 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1332 struct workqueue_struct *hangcheck_wq;
1333 struct delayed_work hangcheck_work;
1335 /* For reset and error_state handling. */
1337 /* Protected by the above dev->gpu_error.lock. */
1338 struct drm_i915_error_state *first_error;
1340 unsigned long missed_irq_rings;
1343 * State variable controlling the reset flow and count
1345 * This is a counter which gets incremented when reset is triggered,
1346 * and again when reset has been handled. So odd values (lowest bit set)
1347 * means that reset is in progress and even values that
1348 * (reset_counter >> 1):th reset was successfully completed.
1350 * If reset is not completed succesfully, the I915_WEDGE bit is
1351 * set meaning that hardware is terminally sour and there is no
1352 * recovery. All waiters on the reset_queue will be woken when
1355 * This counter is used by the wait_seqno code to notice that reset
1356 * event happened and it needs to restart the entire ioctl (since most
1357 * likely the seqno it waited for won't ever signal anytime soon).
1359 * This is important for lock-free wait paths, where no contended lock
1360 * naturally enforces the correct ordering between the bail-out of the
1361 * waiter and the gpu reset work code.
1363 atomic_t reset_counter;
1365 #define I915_RESET_IN_PROGRESS_FLAG 1
1366 #define I915_WEDGED (1 << 31)
1369 * Waitqueue to signal when the reset has completed. Used by clients
1370 * that wait for dev_priv->mm.wedged to settle.
1372 wait_queue_head_t reset_queue;
1374 /* Userspace knobs for gpu hang simulation;
1375 * combines both a ring mask, and extra flags
1378 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1379 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1381 /* For missed irq/seqno simulation. */
1382 unsigned int test_irq_rings;
1384 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1385 bool reload_in_reset;
1388 enum modeset_restore {
1389 MODESET_ON_LID_OPEN,
1394 struct ddi_vbt_port_info {
1396 * This is an index in the HDMI/DVI DDI buffer translation table.
1397 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1398 * populate this field.
1400 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1401 uint8_t hdmi_level_shift;
1403 uint8_t supports_dvi:1;
1404 uint8_t supports_hdmi:1;
1405 uint8_t supports_dp:1;
1408 enum psr_lines_to_wait {
1409 PSR_0_LINES_TO_WAIT = 0,
1411 PSR_4_LINES_TO_WAIT,
1415 struct intel_vbt_data {
1416 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1417 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1420 unsigned int int_tv_support:1;
1421 unsigned int lvds_dither:1;
1422 unsigned int lvds_vbt:1;
1423 unsigned int int_crt_support:1;
1424 unsigned int lvds_use_ssc:1;
1425 unsigned int display_clock_mode:1;
1426 unsigned int fdi_rx_polarity_inverted:1;
1427 unsigned int has_mipi:1;
1429 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1431 enum drrs_support_type drrs_type;
1436 int edp_preemphasis;
1438 bool edp_initialized;
1441 struct edp_power_seq edp_pps;
1445 bool require_aux_wakeup;
1447 enum psr_lines_to_wait lines_to_wait;
1448 int tp1_wakeup_time;
1449 int tp2_tp3_wakeup_time;
1455 bool active_low_pwm;
1456 u8 min_brightness; /* min_brightness/255 of max */
1463 struct mipi_config *config;
1464 struct mipi_pps_data *pps;
1468 u8 *sequence[MIPI_SEQ_MAX];
1474 union child_device_config *child_dev;
1476 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1479 enum intel_ddb_partitioning {
1481 INTEL_DDB_PART_5_6, /* IVB+ */
1484 struct intel_wm_level {
1492 struct ilk_wm_values {
1493 uint32_t wm_pipe[3];
1495 uint32_t wm_lp_spr[3];
1496 uint32_t wm_linetime[3];
1498 enum intel_ddb_partitioning partitioning;
1501 struct vlv_wm_values {
1520 struct skl_ddb_entry {
1521 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1524 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1526 return entry->end - entry->start;
1529 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1530 const struct skl_ddb_entry *e2)
1532 if (e1->start == e2->start && e1->end == e2->end)
1538 struct skl_ddb_allocation {
1539 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1540 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1541 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1542 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1545 struct skl_wm_values {
1546 bool dirty[I915_MAX_PIPES];
1547 struct skl_ddb_allocation ddb;
1548 uint32_t wm_linetime[I915_MAX_PIPES];
1549 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1550 uint32_t cursor[I915_MAX_PIPES][8];
1551 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1552 uint32_t cursor_trans[I915_MAX_PIPES];
1555 struct skl_wm_level {
1556 bool plane_en[I915_MAX_PLANES];
1558 uint16_t plane_res_b[I915_MAX_PLANES];
1559 uint8_t plane_res_l[I915_MAX_PLANES];
1560 uint16_t cursor_res_b;
1561 uint8_t cursor_res_l;
1565 * This struct helps tracking the state needed for runtime PM, which puts the
1566 * device in PCI D3 state. Notice that when this happens, nothing on the
1567 * graphics device works, even register access, so we don't get interrupts nor
1570 * Every piece of our code that needs to actually touch the hardware needs to
1571 * either call intel_runtime_pm_get or call intel_display_power_get with the
1572 * appropriate power domain.
1574 * Our driver uses the autosuspend delay feature, which means we'll only really
1575 * suspend if we stay with zero refcount for a certain amount of time. The
1576 * default value is currently very conservative (see intel_runtime_pm_enable), but
1577 * it can be changed with the standard runtime PM files from sysfs.
1579 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1580 * goes back to false exactly before we reenable the IRQs. We use this variable
1581 * to check if someone is trying to enable/disable IRQs while they're supposed
1582 * to be disabled. This shouldn't happen and we'll print some error messages in
1585 * For more, read the Documentation/power/runtime_pm.txt.
1587 struct i915_runtime_pm {
1592 enum intel_pipe_crc_source {
1593 INTEL_PIPE_CRC_SOURCE_NONE,
1594 INTEL_PIPE_CRC_SOURCE_PLANE1,
1595 INTEL_PIPE_CRC_SOURCE_PLANE2,
1596 INTEL_PIPE_CRC_SOURCE_PF,
1597 INTEL_PIPE_CRC_SOURCE_PIPE,
1598 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1599 INTEL_PIPE_CRC_SOURCE_TV,
1600 INTEL_PIPE_CRC_SOURCE_DP_B,
1601 INTEL_PIPE_CRC_SOURCE_DP_C,
1602 INTEL_PIPE_CRC_SOURCE_DP_D,
1603 INTEL_PIPE_CRC_SOURCE_AUTO,
1604 INTEL_PIPE_CRC_SOURCE_MAX,
1607 struct intel_pipe_crc_entry {
1612 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1613 struct intel_pipe_crc {
1615 bool opened; /* exclusive access to the result file */
1616 struct intel_pipe_crc_entry *entries;
1617 enum intel_pipe_crc_source source;
1619 wait_queue_head_t wq;
1622 struct i915_frontbuffer_tracking {
1626 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1633 struct i915_wa_reg {
1636 /* bitmask representing WA bits */
1640 #define I915_MAX_WA_REGS 16
1642 struct i915_workarounds {
1643 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1647 struct i915_virtual_gpu {
1651 struct drm_i915_private {
1652 struct drm_device *dev;
1653 struct kmem_cache *objects;
1654 struct kmem_cache *vmas;
1655 struct kmem_cache *requests;
1657 const struct intel_device_info info;
1659 int relative_constants_mode;
1663 struct intel_uncore uncore;
1665 struct i915_virtual_gpu vgpu;
1667 struct intel_csr csr;
1669 /* Display CSR-related protection */
1670 struct mutex csr_lock;
1672 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1674 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1675 * controller on different i2c buses. */
1676 struct mutex gmbus_mutex;
1679 * Base address of the gmbus and gpio block.
1681 uint32_t gpio_mmio_base;
1683 /* MMIO base address for MIPI regs */
1684 uint32_t mipi_mmio_base;
1686 wait_queue_head_t gmbus_wait_queue;
1688 struct pci_dev *bridge_dev;
1689 struct intel_engine_cs ring[I915_NUM_RINGS];
1690 struct drm_i915_gem_object *semaphore_obj;
1691 uint32_t last_seqno, next_seqno;
1693 struct drm_dma_handle *status_page_dmah;
1694 struct resource mch_res;
1696 /* protects the irq masks */
1697 spinlock_t irq_lock;
1699 /* protects the mmio flip data */
1700 spinlock_t mmio_flip_lock;
1702 bool display_irqs_enabled;
1704 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1705 struct pm_qos_request pm_qos;
1707 /* Sideband mailbox protection */
1708 struct mutex sb_lock;
1710 /** Cached value of IMR to avoid reads in updating the bitfield */
1713 u32 de_irq_mask[I915_MAX_PIPES];
1718 u32 pipestat_irq_mask[I915_MAX_PIPES];
1720 struct i915_hotplug hotplug;
1721 struct i915_fbc fbc;
1722 struct i915_drrs drrs;
1723 struct intel_opregion opregion;
1724 struct intel_vbt_data vbt;
1726 bool preserve_bios_swizzle;
1729 struct intel_overlay *overlay;
1731 /* backlight registers and fields in struct intel_panel */
1732 struct mutex backlight_lock;
1735 bool no_aux_handshake;
1737 /* protects panel power sequencer state */
1738 struct mutex pps_mutex;
1740 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1741 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1742 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1744 unsigned int fsb_freq, mem_freq, is_ddr3;
1745 unsigned int skl_boot_cdclk;
1746 unsigned int cdclk_freq;
1747 unsigned int hpll_freq;
1750 * wq - Driver workqueue for GEM.
1752 * NOTE: Work items scheduled here are not allowed to grab any modeset
1753 * locks, for otherwise the flushing done in the pageflip code will
1754 * result in deadlocks.
1756 struct workqueue_struct *wq;
1758 /* Display functions */
1759 struct drm_i915_display_funcs display;
1761 /* PCH chipset type */
1762 enum intel_pch pch_type;
1763 unsigned short pch_id;
1765 unsigned long quirks;
1767 enum modeset_restore modeset_restore;
1768 struct mutex modeset_restore_lock;
1770 struct list_head vm_list; /* Global list of all address spaces */
1771 struct i915_gtt gtt; /* VM representing the global address space */
1773 struct i915_gem_mm mm;
1774 DECLARE_HASHTABLE(mm_structs, 7);
1775 struct mutex mm_lock;
1777 /* Kernel Modesetting */
1779 struct sdvo_device_mapping sdvo_mappings[2];
1781 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1782 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1783 wait_queue_head_t pending_flip_queue;
1785 #ifdef CONFIG_DEBUG_FS
1786 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1789 int num_shared_dpll;
1790 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1791 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1793 struct i915_workarounds workarounds;
1795 /* Reclocking support */
1796 bool render_reclock_avail;
1797 bool lvds_downclock_avail;
1798 /* indicates the reduced downclock for LVDS*/
1801 struct i915_frontbuffer_tracking fb_tracking;
1805 bool mchbar_need_disable;
1807 struct intel_l3_parity l3_parity;
1809 /* Cannot be determined by PCIID. You must always read a register. */
1812 /* gen6+ rps state */
1813 struct intel_gen6_power_mgmt rps;
1815 /* ilk-only ips/rps state. Everything in here is protected by the global
1816 * mchdev_lock in intel_pm.c */
1817 struct intel_ilk_power_mgmt ips;
1819 struct i915_power_domains power_domains;
1821 struct i915_psr psr;
1823 struct i915_gpu_error gpu_error;
1825 struct drm_i915_gem_object *vlv_pctx;
1827 #ifdef CONFIG_DRM_I915_FBDEV
1828 /* list of fbdev register on this device */
1829 struct intel_fbdev *fbdev;
1830 struct work_struct fbdev_suspend_work;
1833 struct drm_property *broadcast_rgb_property;
1834 struct drm_property *force_audio_property;
1836 /* hda/i915 audio component */
1837 bool audio_component_registered;
1839 uint32_t hw_context_size;
1840 struct list_head context_list;
1844 u32 chv_phy_control;
1847 struct i915_suspend_saved_registers regfile;
1848 struct vlv_s0ix_state vlv_s0ix_state;
1852 * Raw watermark latency values:
1853 * in 0.1us units for WM0,
1854 * in 0.5us units for WM1+.
1857 uint16_t pri_latency[5];
1859 uint16_t spr_latency[5];
1861 uint16_t cur_latency[5];
1863 * Raw watermark memory latency values
1864 * for SKL for all 8 levels
1867 uint16_t skl_latency[8];
1870 * The skl_wm_values structure is a bit too big for stack
1871 * allocation, so we keep the staging struct where we store
1872 * intermediate results here instead.
1874 struct skl_wm_values skl_results;
1876 /* current hardware state */
1878 struct ilk_wm_values hw;
1879 struct skl_wm_values skl_hw;
1880 struct vlv_wm_values vlv;
1884 struct i915_runtime_pm pm;
1886 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1888 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1889 struct intel_engine_cs *ring,
1890 struct intel_context *ctx,
1891 struct drm_i915_gem_execbuffer2 *args,
1892 struct list_head *vmas,
1893 struct drm_i915_gem_object *batch_obj,
1894 u64 exec_start, u32 flags);
1895 int (*init_rings)(struct drm_device *dev);
1896 void (*cleanup_ring)(struct intel_engine_cs *ring);
1897 void (*stop_ring)(struct intel_engine_cs *ring);
1900 bool edp_low_vswing;
1903 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1904 * will be rejected. Instead look for a better place.
1908 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1910 return dev->dev_private;
1913 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1915 return to_i915(dev_get_drvdata(dev));
1918 /* Iterate over initialised rings */
1919 #define for_each_ring(ring__, dev_priv__, i__) \
1920 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1921 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1923 enum hdmi_force_audio {
1924 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1925 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1926 HDMI_AUDIO_AUTO, /* trust EDID */
1927 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1930 #define I915_GTT_OFFSET_NONE ((u32)-1)
1932 struct drm_i915_gem_object_ops {
1933 /* Interface between the GEM object and its backing storage.
1934 * get_pages() is called once prior to the use of the associated set
1935 * of pages before to binding them into the GTT, and put_pages() is
1936 * called after we no longer need them. As we expect there to be
1937 * associated cost with migrating pages between the backing storage
1938 * and making them available for the GPU (e.g. clflush), we may hold
1939 * onto the pages after they are no longer referenced by the GPU
1940 * in case they may be used again shortly (for example migrating the
1941 * pages to a different memory domain within the GTT). put_pages()
1942 * will therefore most likely be called when the object itself is
1943 * being released or under memory pressure (where we attempt to
1944 * reap pages for the shrinker).
1946 int (*get_pages)(struct drm_i915_gem_object *);
1947 void (*put_pages)(struct drm_i915_gem_object *);
1948 int (*dmabuf_export)(struct drm_i915_gem_object *);
1949 void (*release)(struct drm_i915_gem_object *);
1953 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1954 * considered to be the frontbuffer for the given plane interface-vise. This
1955 * doesn't mean that the hw necessarily already scans it out, but that any
1956 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1958 * We have one bit per pipe and per scanout plane type.
1960 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1961 #define INTEL_FRONTBUFFER_BITS \
1962 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1963 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1964 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1965 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1966 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1967 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1968 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1969 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1970 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1971 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1972 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1974 struct drm_i915_gem_object {
1975 struct drm_gem_object base;
1977 const struct drm_i915_gem_object_ops *ops;
1979 /** List of VMAs backed by this object */
1980 struct list_head vma_list;
1982 /** Stolen memory for this object, instead of being backed by shmem. */
1983 struct drm_mm_node *stolen;
1984 struct list_head global_list;
1986 struct list_head ring_list[I915_NUM_RINGS];
1987 /** Used in execbuf to temporarily hold a ref */
1988 struct list_head obj_exec_link;
1990 struct list_head batch_pool_link;
1993 * This is set if the object is on the active lists (has pending
1994 * rendering and so a non-zero seqno), and is not set if it i s on
1995 * inactive (ready to be unbound) list.
1997 unsigned int active:I915_NUM_RINGS;
2000 * This is set if the object has been written to since last bound
2003 unsigned int dirty:1;
2006 * Fence register bits (if any) for this object. Will be set
2007 * as needed when mapped into the GTT.
2008 * Protected by dev->struct_mutex.
2010 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2013 * Advice: are the backing pages purgeable?
2015 unsigned int madv:2;
2018 * Current tiling mode for the object.
2020 unsigned int tiling_mode:2;
2022 * Whether the tiling parameters for the currently associated fence
2023 * register have changed. Note that for the purposes of tracking
2024 * tiling changes we also treat the unfenced register, the register
2025 * slot that the object occupies whilst it executes a fenced
2026 * command (such as BLT on gen2/3), as a "fence".
2028 unsigned int fence_dirty:1;
2031 * Is the object at the current location in the gtt mappable and
2032 * fenceable? Used to avoid costly recalculations.
2034 unsigned int map_and_fenceable:1;
2037 * Whether the current gtt mapping needs to be mappable (and isn't just
2038 * mappable by accident). Track pin and fault separate for a more
2039 * accurate mappable working set.
2041 unsigned int fault_mappable:1;
2044 * Is the object to be mapped as read-only to the GPU
2045 * Only honoured if hardware has relevant pte bit
2047 unsigned long gt_ro:1;
2048 unsigned int cache_level:3;
2049 unsigned int cache_dirty:1;
2051 unsigned int has_dma_mapping:1;
2053 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2055 unsigned int pin_display;
2057 struct sg_table *pages;
2058 int pages_pin_count;
2060 struct scatterlist *sg;
2064 /* prime dma-buf support */
2065 void *dma_buf_vmapping;
2068 /** Breadcrumb of last rendering to the buffer.
2069 * There can only be one writer, but we allow for multiple readers.
2070 * If there is a writer that necessarily implies that all other
2071 * read requests are complete - but we may only be lazily clearing
2072 * the read requests. A read request is naturally the most recent
2073 * request on a ring, so we may have two different write and read
2074 * requests on one ring where the write request is older than the
2075 * read request. This allows for the CPU to read from an active
2076 * buffer by only waiting for the write to complete.
2078 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2079 struct drm_i915_gem_request *last_write_req;
2080 /** Breadcrumb of last fenced GPU access to the buffer. */
2081 struct drm_i915_gem_request *last_fenced_req;
2083 /** Current tiling stride for the object, if it's tiled. */
2086 /** References from framebuffers, locks out tiling changes. */
2087 unsigned long framebuffer_references;
2089 /** Record of address bit 17 of each page at last unbind. */
2090 unsigned long *bit_17;
2093 /** for phy allocated objects */
2094 struct drm_dma_handle *phys_handle;
2096 struct i915_gem_userptr {
2098 unsigned read_only :1;
2099 unsigned workers :4;
2100 #define I915_GEM_USERPTR_MAX_WORKERS 15
2102 struct i915_mm_struct *mm;
2103 struct i915_mmu_object *mmu_object;
2104 struct work_struct *work;
2108 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2110 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2111 struct drm_i915_gem_object *new,
2112 unsigned frontbuffer_bits);
2115 * Request queue structure.
2117 * The request queue allows us to note sequence numbers that have been emitted
2118 * and may be associated with active buffers to be retired.
2120 * By keeping this list, we can avoid having to do questionable sequence
2121 * number comparisons on buffer last_read|write_seqno. It also allows an
2122 * emission time to be associated with the request for tracking how far ahead
2123 * of the GPU the submission is.
2125 * The requests are reference counted, so upon creation they should have an
2126 * initial reference taken using kref_init
2128 struct drm_i915_gem_request {
2131 /** On Which ring this request was generated */
2132 struct drm_i915_private *i915;
2133 struct intel_engine_cs *ring;
2135 /** GEM sequence number associated with this request. */
2138 /** Position in the ringbuffer of the start of the request */
2142 * Position in the ringbuffer of the start of the postfix.
2143 * This is required to calculate the maximum available ringbuffer
2144 * space without overwriting the postfix.
2148 /** Position in the ringbuffer of the end of the whole request */
2152 * Context and ring buffer related to this request
2153 * Contexts are refcounted, so when this request is associated with a
2154 * context, we must increment the context's refcount, to guarantee that
2155 * it persists while any request is linked to it. Requests themselves
2156 * are also refcounted, so the request will only be freed when the last
2157 * reference to it is dismissed, and the code in
2158 * i915_gem_request_free() will then decrement the refcount on the
2161 struct intel_context *ctx;
2162 struct intel_ringbuffer *ringbuf;
2164 /** Batch buffer related to this request if any */
2165 struct drm_i915_gem_object *batch_obj;
2167 /** Time at which this request was emitted, in jiffies. */
2168 unsigned long emitted_jiffies;
2170 /** global list entry for this request */
2171 struct list_head list;
2173 struct drm_i915_file_private *file_priv;
2174 /** file_priv list entry for this request */
2175 struct list_head client_list;
2177 /** process identifier submitting this request */
2181 * The ELSP only accepts two elements at a time, so we queue
2182 * context/tail pairs on a given queue (ring->execlist_queue) until the
2183 * hardware is available. The queue serves a double purpose: we also use
2184 * it to keep track of the up to 2 contexts currently in the hardware
2185 * (usually one in execution and the other queued up by the GPU): We
2186 * only remove elements from the head of the queue when the hardware
2187 * informs us that an element has been completed.
2189 * All accesses to the queue are mediated by a spinlock
2190 * (ring->execlist_lock).
2193 /** Execlist link in the submission queue.*/
2194 struct list_head execlist_link;
2196 /** Execlists no. of times this request has been sent to the ELSP */
2201 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2202 struct intel_context *ctx);
2203 void i915_gem_request_free(struct kref *req_ref);
2205 static inline uint32_t
2206 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2208 return req ? req->seqno : 0;
2211 static inline struct intel_engine_cs *
2212 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2214 return req ? req->ring : NULL;
2217 static inline struct drm_i915_gem_request *
2218 i915_gem_request_reference(struct drm_i915_gem_request *req)
2221 kref_get(&req->ref);
2226 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2228 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2229 kref_put(&req->ref, i915_gem_request_free);
2233 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2235 struct drm_device *dev;
2240 dev = req->ring->dev;
2241 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2242 mutex_unlock(&dev->struct_mutex);
2245 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2246 struct drm_i915_gem_request *src)
2249 i915_gem_request_reference(src);
2252 i915_gem_request_unreference(*pdst);
2258 * XXX: i915_gem_request_completed should be here but currently needs the
2259 * definition of i915_seqno_passed() which is below. It will be moved in
2260 * a later patch when the call to i915_seqno_passed() is obsoleted...
2264 * A command that requires special handling by the command parser.
2266 struct drm_i915_cmd_descriptor {
2268 * Flags describing how the command parser processes the command.
2270 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2271 * a length mask if not set
2272 * CMD_DESC_SKIP: The command is allowed but does not follow the
2273 * standard length encoding for the opcode range in
2275 * CMD_DESC_REJECT: The command is never allowed
2276 * CMD_DESC_REGISTER: The command should be checked against the
2277 * register whitelist for the appropriate ring
2278 * CMD_DESC_MASTER: The command is allowed if the submitting process
2282 #define CMD_DESC_FIXED (1<<0)
2283 #define CMD_DESC_SKIP (1<<1)
2284 #define CMD_DESC_REJECT (1<<2)
2285 #define CMD_DESC_REGISTER (1<<3)
2286 #define CMD_DESC_BITMASK (1<<4)
2287 #define CMD_DESC_MASTER (1<<5)
2290 * The command's unique identification bits and the bitmask to get them.
2291 * This isn't strictly the opcode field as defined in the spec and may
2292 * also include type, subtype, and/or subop fields.
2300 * The command's length. The command is either fixed length (i.e. does
2301 * not include a length field) or has a length field mask. The flag
2302 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2303 * a length mask. All command entries in a command table must include
2304 * length information.
2312 * Describes where to find a register address in the command to check
2313 * against the ring's register whitelist. Only valid if flags has the
2314 * CMD_DESC_REGISTER bit set.
2321 #define MAX_CMD_DESC_BITMASKS 3
2323 * Describes command checks where a particular dword is masked and
2324 * compared against an expected value. If the command does not match
2325 * the expected value, the parser rejects it. Only valid if flags has
2326 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2329 * If the check specifies a non-zero condition_mask then the parser
2330 * only performs the check when the bits specified by condition_mask
2337 u32 condition_offset;
2339 } bits[MAX_CMD_DESC_BITMASKS];
2343 * A table of commands requiring special handling by the command parser.
2345 * Each ring has an array of tables. Each table consists of an array of command
2346 * descriptors, which must be sorted with command opcodes in ascending order.
2348 struct drm_i915_cmd_table {
2349 const struct drm_i915_cmd_descriptor *table;
2353 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2354 #define __I915__(p) ({ \
2355 struct drm_i915_private *__p; \
2356 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2357 __p = (struct drm_i915_private *)p; \
2358 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2359 __p = to_i915((struct drm_device *)p); \
2364 #define INTEL_INFO(p) (&__I915__(p)->info)
2365 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2366 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2368 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2369 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2370 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2371 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2372 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2373 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2374 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2375 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2376 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2377 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2378 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2379 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2380 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2381 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2382 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2383 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2384 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2385 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2386 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2387 INTEL_DEVID(dev) == 0x0152 || \
2388 INTEL_DEVID(dev) == 0x015a)
2389 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2390 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2391 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2392 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2393 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2394 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2395 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2396 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2397 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2398 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2399 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2400 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2401 (INTEL_DEVID(dev) & 0xf) == 0xe))
2402 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2403 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2404 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2405 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2406 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2407 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2408 /* ULX machines are also considered ULT. */
2409 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2410 INTEL_DEVID(dev) == 0x0A1E)
2411 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2413 #define SKL_REVID_A0 (0x0)
2414 #define SKL_REVID_B0 (0x1)
2415 #define SKL_REVID_C0 (0x2)
2416 #define SKL_REVID_D0 (0x3)
2417 #define SKL_REVID_E0 (0x4)
2418 #define SKL_REVID_F0 (0x5)
2420 #define BXT_REVID_A0 (0x0)
2421 #define BXT_REVID_B0 (0x3)
2422 #define BXT_REVID_C0 (0x6)
2425 * The genX designation typically refers to the render engine, so render
2426 * capability related checks should use IS_GEN, while display and other checks
2427 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2430 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2431 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2432 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2433 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2434 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2435 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2436 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2437 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2439 #define RENDER_RING (1<<RCS)
2440 #define BSD_RING (1<<VCS)
2441 #define BLT_RING (1<<BCS)
2442 #define VEBOX_RING (1<<VECS)
2443 #define BSD2_RING (1<<VCS2)
2444 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2445 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2446 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2447 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2448 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2449 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2450 __I915__(dev)->ellc_size)
2451 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2453 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2454 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2455 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2456 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2458 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2459 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2461 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2462 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2464 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2465 * even when in MSI mode. This results in spurious interrupt warnings if the
2466 * legacy irq no. is shared with another device. The kernel then disables that
2467 * interrupt source and so prevents the other device from working properly.
2469 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2470 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2472 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2473 * rows, which changed the alignment requirements and fence programming.
2475 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2477 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2478 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2479 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2480 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2481 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2483 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2484 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2485 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2487 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2489 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2490 INTEL_INFO(dev)->gen >= 9)
2492 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2493 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2494 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2495 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2497 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2498 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2500 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2501 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2503 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2505 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2506 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2507 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2508 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2509 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2510 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2511 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2512 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2514 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2515 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2516 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2517 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2518 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2519 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2520 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2522 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2524 /* DPF == dynamic parity feature */
2525 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2526 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2528 #define GT_FREQUENCY_MULTIPLIER 50
2529 #define GEN9_FREQ_SCALER 3
2531 #include "i915_trace.h"
2533 extern const struct drm_ioctl_desc i915_ioctls[];
2534 extern int i915_max_ioctl;
2536 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2537 extern int i915_resume_legacy(struct drm_device *dev);
2540 struct i915_params {
2542 int panel_ignore_lid;
2544 unsigned int lvds_downclock;
2545 int lvds_channel_mode;
2547 int vbt_sdvo_panel_type;
2551 int enable_execlists;
2553 unsigned int preliminary_hw_support;
2554 int disable_power_well;
2556 int invert_brightness;
2557 int enable_cmd_parser;
2558 /* leave bools at the end to not create holes */
2559 bool enable_hangcheck;
2561 bool prefault_disable;
2562 bool load_detect_test;
2564 bool disable_display;
2565 bool disable_vtd_wa;
2568 bool verbose_state_checks;
2569 bool nuclear_pageflip;
2572 extern struct i915_params i915 __read_mostly;
2575 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2576 extern int i915_driver_unload(struct drm_device *);
2577 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2578 extern void i915_driver_lastclose(struct drm_device * dev);
2579 extern void i915_driver_preclose(struct drm_device *dev,
2580 struct drm_file *file);
2581 extern void i915_driver_postclose(struct drm_device *dev,
2582 struct drm_file *file);
2583 extern int i915_driver_device_is_agp(struct drm_device * dev);
2584 #ifdef CONFIG_COMPAT
2585 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2588 extern int intel_gpu_reset(struct drm_device *dev);
2589 extern int i915_reset(struct drm_device *dev);
2590 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2591 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2592 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2593 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2594 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2595 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2596 void i915_firmware_load_error_print(const char *fw_path, int err);
2599 void i915_queue_hangcheck(struct drm_device *dev);
2601 void i915_handle_error(struct drm_device *dev, bool wedged,
2602 const char *fmt, ...);
2604 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2605 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2606 int intel_irq_install(struct drm_i915_private *dev_priv);
2607 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2609 extern void intel_uncore_sanitize(struct drm_device *dev);
2610 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2611 bool restore_forcewake);
2612 extern void intel_uncore_init(struct drm_device *dev);
2613 extern void intel_uncore_check_errors(struct drm_device *dev);
2614 extern void intel_uncore_fini(struct drm_device *dev);
2615 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2616 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2617 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2618 enum forcewake_domains domains);
2619 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2620 enum forcewake_domains domains);
2621 /* Like above but the caller must manage the uncore.lock itself.
2622 * Must be used with I915_READ_FW and friends.
2624 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2625 enum forcewake_domains domains);
2626 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2627 enum forcewake_domains domains);
2628 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2629 static inline bool intel_vgpu_active(struct drm_device *dev)
2631 return to_i915(dev)->vgpu.active;
2635 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2639 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2642 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2643 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2645 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2647 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2648 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2649 uint32_t interrupt_mask,
2650 uint32_t enabled_irq_mask);
2651 #define ibx_enable_display_interrupt(dev_priv, bits) \
2652 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2653 #define ibx_disable_display_interrupt(dev_priv, bits) \
2654 ibx_display_interrupt_update((dev_priv), (bits), 0)
2657 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2658 struct drm_file *file_priv);
2659 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2660 struct drm_file *file_priv);
2661 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2662 struct drm_file *file_priv);
2663 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2664 struct drm_file *file_priv);
2665 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2666 struct drm_file *file_priv);
2667 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2668 struct drm_file *file_priv);
2669 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2670 struct drm_file *file_priv);
2671 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2672 struct intel_engine_cs *ring);
2673 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2674 struct drm_file *file,
2675 struct intel_engine_cs *ring,
2676 struct drm_i915_gem_object *obj);
2677 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2678 struct drm_file *file,
2679 struct intel_engine_cs *ring,
2680 struct intel_context *ctx,
2681 struct drm_i915_gem_execbuffer2 *args,
2682 struct list_head *vmas,
2683 struct drm_i915_gem_object *batch_obj,
2684 u64 exec_start, u32 flags);
2685 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2686 struct drm_file *file_priv);
2687 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2688 struct drm_file *file_priv);
2689 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2690 struct drm_file *file_priv);
2691 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2692 struct drm_file *file);
2693 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2694 struct drm_file *file);
2695 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2696 struct drm_file *file_priv);
2697 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2698 struct drm_file *file_priv);
2699 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2700 struct drm_file *file_priv);
2701 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2702 struct drm_file *file_priv);
2703 int i915_gem_init_userptr(struct drm_device *dev);
2704 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2705 struct drm_file *file);
2706 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2707 struct drm_file *file_priv);
2708 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2709 struct drm_file *file_priv);
2710 void i915_gem_load(struct drm_device *dev);
2711 void *i915_gem_object_alloc(struct drm_device *dev);
2712 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2713 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2714 const struct drm_i915_gem_object_ops *ops);
2715 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2717 void i915_init_vm(struct drm_i915_private *dev_priv,
2718 struct i915_address_space *vm);
2719 void i915_gem_free_object(struct drm_gem_object *obj);
2720 void i915_gem_vma_destroy(struct i915_vma *vma);
2722 /* Flags used by pin/bind&friends. */
2723 #define PIN_MAPPABLE (1<<0)
2724 #define PIN_NONBLOCK (1<<1)
2725 #define PIN_GLOBAL (1<<2)
2726 #define PIN_OFFSET_BIAS (1<<3)
2727 #define PIN_USER (1<<4)
2728 #define PIN_UPDATE (1<<5)
2729 #define PIN_OFFSET_MASK (~4095)
2731 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2732 struct i915_address_space *vm,
2736 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2737 const struct i915_ggtt_view *view,
2741 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2743 int __must_check i915_vma_unbind(struct i915_vma *vma);
2744 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2745 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2746 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2748 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2749 int *needs_clflush);
2751 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2753 static inline int __sg_page_count(struct scatterlist *sg)
2755 return sg->length >> PAGE_SHIFT;
2758 static inline struct page *
2759 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2761 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2764 if (n < obj->get_page.last) {
2765 obj->get_page.sg = obj->pages->sgl;
2766 obj->get_page.last = 0;
2769 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2770 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2771 if (unlikely(sg_is_chain(obj->get_page.sg)))
2772 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2775 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2778 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2780 BUG_ON(obj->pages == NULL);
2781 obj->pages_pin_count++;
2783 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2785 BUG_ON(obj->pages_pin_count == 0);
2786 obj->pages_pin_count--;
2789 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2790 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2791 struct intel_engine_cs *to);
2792 void i915_vma_move_to_active(struct i915_vma *vma,
2793 struct intel_engine_cs *ring);
2794 int i915_gem_dumb_create(struct drm_file *file_priv,
2795 struct drm_device *dev,
2796 struct drm_mode_create_dumb *args);
2797 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2798 uint32_t handle, uint64_t *offset);
2800 * Returns true if seq1 is later than seq2.
2803 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2805 return (int32_t)(seq1 - seq2) >= 0;
2808 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2809 bool lazy_coherency)
2813 BUG_ON(req == NULL);
2815 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2817 return i915_seqno_passed(seqno, req->seqno);
2820 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2821 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2822 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2823 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2825 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2826 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2828 struct drm_i915_gem_request *
2829 i915_gem_find_active_request(struct intel_engine_cs *ring);
2831 bool i915_gem_retire_requests(struct drm_device *dev);
2832 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2833 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2834 bool interruptible);
2835 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2837 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2839 return unlikely(atomic_read(&error->reset_counter)
2840 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2843 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2845 return atomic_read(&error->reset_counter) & I915_WEDGED;
2848 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2850 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2853 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2855 return dev_priv->gpu_error.stop_rings == 0 ||
2856 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2859 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2861 return dev_priv->gpu_error.stop_rings == 0 ||
2862 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2865 void i915_gem_reset(struct drm_device *dev);
2866 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2867 int __must_check i915_gem_init(struct drm_device *dev);
2868 int i915_gem_init_rings(struct drm_device *dev);
2869 int __must_check i915_gem_init_hw(struct drm_device *dev);
2870 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2871 void i915_gem_init_swizzling(struct drm_device *dev);
2872 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2873 int __must_check i915_gpu_idle(struct drm_device *dev);
2874 int __must_check i915_gem_suspend(struct drm_device *dev);
2875 int __i915_add_request(struct intel_engine_cs *ring,
2876 struct drm_file *file,
2877 struct drm_i915_gem_object *batch_obj);
2878 #define i915_add_request(ring) \
2879 __i915_add_request(ring, NULL, NULL)
2880 int __i915_wait_request(struct drm_i915_gem_request *req,
2881 unsigned reset_counter,
2884 struct intel_rps_client *rps);
2885 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2886 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2888 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2891 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2894 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2896 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2898 struct intel_engine_cs *pipelined,
2899 const struct i915_ggtt_view *view);
2900 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2901 const struct i915_ggtt_view *view);
2902 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2904 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2905 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2908 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2910 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2911 int tiling_mode, bool fenced);
2913 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2914 enum i915_cache_level cache_level);
2916 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2917 struct dma_buf *dma_buf);
2919 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2920 struct drm_gem_object *gem_obj, int flags);
2922 void i915_gem_restore_fences(struct drm_device *dev);
2925 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2926 const struct i915_ggtt_view *view);
2928 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2929 struct i915_address_space *vm);
2930 static inline unsigned long
2931 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2933 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2936 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2937 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2938 const struct i915_ggtt_view *view);
2939 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2940 struct i915_address_space *vm);
2942 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2943 struct i915_address_space *vm);
2945 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2946 struct i915_address_space *vm);
2948 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2949 const struct i915_ggtt_view *view);
2952 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2953 struct i915_address_space *vm);
2955 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2956 const struct i915_ggtt_view *view);
2958 static inline struct i915_vma *
2959 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2961 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2963 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2965 /* Some GGTT VM helpers */
2966 #define i915_obj_to_ggtt(obj) \
2967 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2968 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2970 struct i915_address_space *ggtt =
2971 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2975 static inline struct i915_hw_ppgtt *
2976 i915_vm_to_ppgtt(struct i915_address_space *vm)
2978 WARN_ON(i915_is_ggtt(vm));
2980 return container_of(vm, struct i915_hw_ppgtt, base);
2984 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2986 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2989 static inline unsigned long
2990 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2992 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2995 static inline int __must_check
2996 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3000 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3001 alignment, flags | PIN_GLOBAL);
3005 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3007 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3010 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3011 const struct i915_ggtt_view *view);
3013 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3015 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3018 /* i915_gem_context.c */
3019 int __must_check i915_gem_context_init(struct drm_device *dev);
3020 void i915_gem_context_fini(struct drm_device *dev);
3021 void i915_gem_context_reset(struct drm_device *dev);
3022 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3023 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
3024 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3025 int i915_switch_context(struct intel_engine_cs *ring,
3026 struct intel_context *to);
3027 struct intel_context *
3028 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3029 void i915_gem_context_free(struct kref *ctx_ref);
3030 struct drm_i915_gem_object *
3031 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3032 static inline void i915_gem_context_reference(struct intel_context *ctx)
3034 kref_get(&ctx->ref);
3037 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3039 kref_put(&ctx->ref, i915_gem_context_free);
3042 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3044 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3047 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3048 struct drm_file *file);
3049 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3050 struct drm_file *file);
3051 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3052 struct drm_file *file_priv);
3053 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3054 struct drm_file *file_priv);
3056 /* i915_gem_evict.c */
3057 int __must_check i915_gem_evict_something(struct drm_device *dev,
3058 struct i915_address_space *vm,
3061 unsigned cache_level,
3062 unsigned long start,
3065 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3066 int i915_gem_evict_everything(struct drm_device *dev);
3068 /* belongs in i915_gem_gtt.h */
3069 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3071 if (INTEL_INFO(dev)->gen < 6)
3072 intel_gtt_chipset_flush();
3075 /* i915_gem_stolen.c */
3076 int i915_gem_init_stolen(struct drm_device *dev);
3077 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
3078 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
3079 void i915_gem_cleanup_stolen(struct drm_device *dev);
3080 struct drm_i915_gem_object *
3081 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3082 struct drm_i915_gem_object *
3083 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3088 /* i915_gem_shrinker.c */
3089 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3092 #define I915_SHRINK_PURGEABLE 0x1
3093 #define I915_SHRINK_UNBOUND 0x2
3094 #define I915_SHRINK_BOUND 0x4
3095 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3096 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3099 /* i915_gem_tiling.c */
3100 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3102 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3104 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3105 obj->tiling_mode != I915_TILING_NONE;
3108 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3109 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3110 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3112 /* i915_gem_debug.c */
3114 int i915_verify_lists(struct drm_device *dev);
3116 #define i915_verify_lists(dev) 0
3119 /* i915_debugfs.c */
3120 int i915_debugfs_init(struct drm_minor *minor);
3121 void i915_debugfs_cleanup(struct drm_minor *minor);
3122 #ifdef CONFIG_DEBUG_FS
3123 int i915_debugfs_connector_add(struct drm_connector *connector);
3124 void intel_display_crc_init(struct drm_device *dev);
3126 static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
3127 static inline void intel_display_crc_init(struct drm_device *dev) {}
3130 /* i915_gpu_error.c */
3132 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3133 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3134 const struct i915_error_state_file_priv *error);
3135 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3136 struct drm_i915_private *i915,
3137 size_t count, loff_t pos);
3138 static inline void i915_error_state_buf_release(
3139 struct drm_i915_error_state_buf *eb)
3143 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3144 const char *error_msg);
3145 void i915_error_state_get(struct drm_device *dev,
3146 struct i915_error_state_file_priv *error_priv);
3147 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3148 void i915_destroy_error_state(struct drm_device *dev);
3150 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3151 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3153 /* i915_cmd_parser.c */
3154 int i915_cmd_parser_get_version(void);
3155 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3156 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3157 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3158 int i915_parse_cmds(struct intel_engine_cs *ring,
3159 struct drm_i915_gem_object *batch_obj,
3160 struct drm_i915_gem_object *shadow_batch_obj,
3161 u32 batch_start_offset,
3165 /* i915_suspend.c */
3166 extern int i915_save_state(struct drm_device *dev);
3167 extern int i915_restore_state(struct drm_device *dev);
3170 void i915_setup_sysfs(struct drm_device *dev_priv);
3171 void i915_teardown_sysfs(struct drm_device *dev_priv);
3174 extern int intel_setup_gmbus(struct drm_device *dev);
3175 extern void intel_teardown_gmbus(struct drm_device *dev);
3176 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3179 extern struct i2c_adapter *
3180 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3181 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3182 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3183 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3185 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3187 extern void intel_i2c_reset(struct drm_device *dev);
3189 /* intel_opregion.c */
3191 extern int intel_opregion_setup(struct drm_device *dev);
3192 extern void intel_opregion_init(struct drm_device *dev);
3193 extern void intel_opregion_fini(struct drm_device *dev);
3194 extern void intel_opregion_asle_intr(struct drm_device *dev);
3195 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3197 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3200 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3201 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3202 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3203 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3205 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3210 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3218 extern void intel_register_dsm_handler(void);
3219 extern void intel_unregister_dsm_handler(void);
3221 static inline void intel_register_dsm_handler(void) { return; }
3222 static inline void intel_unregister_dsm_handler(void) { return; }
3223 #endif /* CONFIG_ACPI */
3226 extern void intel_modeset_init_hw(struct drm_device *dev);
3227 extern void intel_modeset_init(struct drm_device *dev);
3228 extern void intel_modeset_gem_init(struct drm_device *dev);
3229 extern void intel_modeset_cleanup(struct drm_device *dev);
3230 extern void intel_connector_unregister(struct intel_connector *);
3231 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3232 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3233 bool force_restore);
3234 extern void i915_redisable_vga(struct drm_device *dev);
3235 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3236 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3237 extern void intel_init_pch_refclk(struct drm_device *dev);
3238 extern void intel_set_rps(struct drm_device *dev, u8 val);
3239 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3241 extern void intel_detect_pch(struct drm_device *dev);
3242 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3243 extern int intel_enable_rc6(const struct drm_device *dev);
3245 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3246 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3247 struct drm_file *file);
3248 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3249 struct drm_file *file);
3252 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3253 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3254 struct intel_overlay_error_state *error);
3256 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3257 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3258 struct drm_device *dev,
3259 struct intel_display_error_state *error);
3261 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3262 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3264 /* intel_sideband.c */
3265 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3266 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3267 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3268 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3269 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3270 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3271 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3272 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3273 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3274 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3275 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3276 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3277 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3278 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3279 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3280 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3281 enum intel_sbi_destination destination);
3282 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3283 enum intel_sbi_destination destination);
3284 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3285 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3287 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3288 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3290 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3291 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3293 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3294 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3295 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3296 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3298 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3299 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3300 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3301 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3303 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3304 * will be implemented using 2 32-bit writes in an arbitrary order with
3305 * an arbitrary delay between them. This can cause the hardware to
3306 * act upon the intermediate value, possibly leading to corruption and
3307 * machine death. You have been warned.
3309 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3310 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3312 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3313 u32 upper = I915_READ(upper_reg); \
3314 u32 lower = I915_READ(lower_reg); \
3315 u32 tmp = I915_READ(upper_reg); \
3316 if (upper != tmp) { \
3318 lower = I915_READ(lower_reg); \
3319 WARN_ON(I915_READ(upper_reg) != upper); \
3321 (u64)upper << 32 | lower; })
3323 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3324 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3326 /* These are untraced mmio-accessors that are only valid to be used inside
3327 * criticial sections inside IRQ handlers where forcewake is explicitly
3329 * Think twice, and think again, before using these.
3330 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3331 * intel_uncore_forcewake_irqunlock().
3333 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3334 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3335 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3337 /* "Broadcast RGB" property */
3338 #define INTEL_BROADCAST_RGB_AUTO 0
3339 #define INTEL_BROADCAST_RGB_FULL 1
3340 #define INTEL_BROADCAST_RGB_LIMITED 2
3342 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3344 if (IS_VALLEYVIEW(dev))
3345 return VLV_VGACNTRL;
3346 else if (INTEL_INFO(dev)->gen >= 5)
3347 return CPU_VGACNTRL;
3352 static inline void __user *to_user_ptr(u64 address)
3354 return (void __user *)(uintptr_t)address;
3357 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3359 unsigned long j = msecs_to_jiffies(m);
3361 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3364 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3366 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3369 static inline unsigned long
3370 timespec_to_jiffies_timeout(const struct timespec *value)
3372 unsigned long j = timespec_to_jiffies(value);
3374 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3378 * If you need to wait X milliseconds between events A and B, but event B
3379 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3380 * when event A happened, then just before event B you call this function and
3381 * pass the timestamp as the first argument, and X as the second argument.
3384 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3386 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3389 * Don't re-read the value of "jiffies" every time since it may change
3390 * behind our back and break the math.
3392 tmp_jiffies = jiffies;
3393 target_jiffies = timestamp_jiffies +
3394 msecs_to_jiffies_timeout(to_wait_ms);
3396 if (time_after(target_jiffies, tmp_jiffies)) {
3397 remaining_jiffies = target_jiffies - tmp_jiffies;
3398 while (remaining_jiffies)
3400 schedule_timeout_uninterruptible(remaining_jiffies);
3404 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3405 struct drm_i915_gem_request *req)
3407 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3408 i915_gem_request_assign(&ring->trace_irq_req, req);