1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain {
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct intel_pch_pll {
136 int refcount; /* count of number of CRTCs sharing this PLL */
137 int active; /* count of number of active CRTCs (i.e. DPMS on) */
138 bool on; /* is the PLL actually active? Disabled during modeset */
143 #define I915_NUM_PLLS 2
145 /* Used by dp and fdi links */
146 struct intel_link_m_n {
154 void intel_link_compute_m_n(int bpp, int nlanes,
155 int pixel_clock, int link_clock,
156 struct intel_link_m_n *m_n);
158 struct intel_ddi_plls {
164 /* Interface history:
167 * 1.2: Add Power Management
168 * 1.3: Add vblank support
169 * 1.4: Fix cmdbuffer path, add heap destroy
170 * 1.5: Add vblank pipe configuration
171 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
172 * - Support vertical blank on secondary display pipe
174 #define DRIVER_MAJOR 1
175 #define DRIVER_MINOR 6
176 #define DRIVER_PATCHLEVEL 0
178 #define WATCH_COHERENCY 0
179 #define WATCH_LISTS 0
182 #define I915_GEM_PHYS_CURSOR_0 1
183 #define I915_GEM_PHYS_CURSOR_1 2
184 #define I915_GEM_PHYS_OVERLAY_REGS 3
185 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
187 struct drm_i915_gem_phys_object {
189 struct page **page_list;
190 drm_dma_handle_t *handle;
191 struct drm_i915_gem_object *cur_obj;
194 struct opregion_header;
195 struct opregion_acpi;
196 struct opregion_swsci;
197 struct opregion_asle;
198 struct drm_i915_private;
200 struct intel_opregion {
201 struct opregion_header __iomem *header;
202 struct opregion_acpi __iomem *acpi;
203 struct opregion_swsci __iomem *swsci;
204 struct opregion_asle __iomem *asle;
206 u32 __iomem *lid_state;
208 #define OPREGION_SIZE (8*1024)
210 struct intel_overlay;
211 struct intel_overlay_error_state;
213 struct drm_i915_master_private {
214 drm_local_map_t *sarea;
215 struct _drm_i915_sarea *sarea_priv;
217 #define I915_FENCE_REG_NONE -1
218 #define I915_MAX_NUM_FENCES 32
219 /* 32 fences + sign bit for FENCE_REG_NONE */
220 #define I915_MAX_NUM_FENCE_BITS 6
222 struct drm_i915_fence_reg {
223 struct list_head lru_list;
224 struct drm_i915_gem_object *obj;
228 struct sdvo_device_mapping {
237 struct intel_display_error_state;
239 struct drm_i915_error_state {
247 bool waiting[I915_NUM_RINGS];
248 u32 pipestat[I915_MAX_PIPES];
249 u32 tail[I915_NUM_RINGS];
250 u32 head[I915_NUM_RINGS];
251 u32 ctl[I915_NUM_RINGS];
252 u32 ipeir[I915_NUM_RINGS];
253 u32 ipehr[I915_NUM_RINGS];
254 u32 instdone[I915_NUM_RINGS];
255 u32 acthd[I915_NUM_RINGS];
256 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
257 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
258 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
259 /* our own tracking of ring head and tail */
260 u32 cpu_ring_head[I915_NUM_RINGS];
261 u32 cpu_ring_tail[I915_NUM_RINGS];
262 u32 error; /* gen6+ */
263 u32 err_int; /* gen7 */
264 u32 instpm[I915_NUM_RINGS];
265 u32 instps[I915_NUM_RINGS];
266 u32 extra_instdone[I915_NUM_INSTDONE_REG];
267 u32 seqno[I915_NUM_RINGS];
269 u32 fault_reg[I915_NUM_RINGS];
271 u32 faddr[I915_NUM_RINGS];
272 u64 fence[I915_MAX_NUM_FENCES];
274 struct drm_i915_error_ring {
275 struct drm_i915_error_object {
279 } *ringbuffer, *batchbuffer, *ctx;
280 struct drm_i915_error_request {
286 } ring[I915_NUM_RINGS];
287 struct drm_i915_error_buffer {
294 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
301 } *active_bo, *pinned_bo;
302 u32 active_bo_count, pinned_bo_count;
303 struct intel_overlay_error_state *overlay;
304 struct intel_display_error_state *display;
307 struct intel_crtc_config;
310 struct drm_i915_display_funcs {
311 bool (*fbc_enabled)(struct drm_device *dev);
312 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
313 void (*disable_fbc)(struct drm_device *dev);
314 int (*get_display_clock_speed)(struct drm_device *dev);
315 int (*get_fifo_size)(struct drm_device *dev, int plane);
316 void (*update_wm)(struct drm_device *dev);
317 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
318 uint32_t sprite_width, int pixel_size);
319 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
320 struct drm_display_mode *mode);
321 void (*modeset_global_resources)(struct drm_device *dev);
322 /* Returns the active state of the crtc, and if the crtc is active,
323 * fills out the pipe-config with the hw state. */
324 bool (*get_pipe_config)(struct intel_crtc *,
325 struct intel_crtc_config *);
326 int (*crtc_mode_set)(struct drm_crtc *crtc,
328 struct drm_framebuffer *old_fb);
329 void (*crtc_enable)(struct drm_crtc *crtc);
330 void (*crtc_disable)(struct drm_crtc *crtc);
331 void (*off)(struct drm_crtc *crtc);
332 void (*write_eld)(struct drm_connector *connector,
333 struct drm_crtc *crtc);
334 void (*fdi_link_train)(struct drm_crtc *crtc);
335 void (*init_clock_gating)(struct drm_device *dev);
336 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
337 struct drm_framebuffer *fb,
338 struct drm_i915_gem_object *obj);
339 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
341 void (*hpd_irq_setup)(struct drm_device *dev);
342 /* clock updates for mode set */
344 /* render clock increase/decrease */
345 /* display clock increase/decrease */
346 /* pll clock increase/decrease */
349 struct drm_i915_gt_funcs {
350 void (*force_wake_get)(struct drm_i915_private *dev_priv);
351 void (*force_wake_put)(struct drm_i915_private *dev_priv);
354 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
355 func(is_mobile) sep \
358 func(is_i945gm) sep \
360 func(need_gfx_hws) sep \
362 func(is_pineview) sep \
363 func(is_broadwater) sep \
364 func(is_crestline) sep \
365 func(is_ivybridge) sep \
366 func(is_valleyview) sep \
367 func(is_haswell) sep \
368 func(has_force_wake) sep \
370 func(has_pipe_cxsr) sep \
371 func(has_hotplug) sep \
372 func(cursor_needs_physical) sep \
373 func(has_overlay) sep \
374 func(overlay_needs_physical) sep \
375 func(supports_tv) sep \
376 func(has_bsd_ring) sep \
377 func(has_blt_ring) sep \
382 #define DEFINE_FLAG(name) u8 name:1
383 #define SEP_SEMICOLON ;
385 struct intel_device_info {
386 u32 display_mmio_offset;
389 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
395 enum i915_cache_level {
398 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
401 typedef uint32_t gen6_gtt_pte_t;
403 /* The Graphics Translation Table is the way in which GEN hardware translates a
404 * Graphics Virtual Address into a Physical Address. In addition to the normal
405 * collateral associated with any va->pa translations GEN hardware also has a
406 * portion of the GTT which can be mapped by the CPU and remain both coherent
407 * and correct (in cases like swizzling). That region is referred to as GMADR in
411 unsigned long start; /* Start offset of used GTT */
412 size_t total; /* Total size GTT can map */
413 size_t stolen_size; /* Total size of stolen memory */
415 unsigned long mappable_end; /* End offset that we can CPU map */
416 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
417 phys_addr_t mappable_base; /* PA of our GMADR */
419 /** "Graphics Stolen Memory" holds the global PTEs */
423 dma_addr_t scratch_page_dma;
424 struct page *scratch_page;
427 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
428 size_t *stolen, phys_addr_t *mappable_base,
429 unsigned long *mappable_end);
430 void (*gtt_remove)(struct drm_device *dev);
431 void (*gtt_clear_range)(struct drm_device *dev,
432 unsigned int first_entry,
433 unsigned int num_entries);
434 void (*gtt_insert_entries)(struct drm_device *dev,
436 unsigned int pg_start,
437 enum i915_cache_level cache_level);
438 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
440 enum i915_cache_level level);
442 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
444 #define I915_PPGTT_PD_ENTRIES 512
445 #define I915_PPGTT_PT_ENTRIES 1024
446 struct i915_hw_ppgtt {
447 struct drm_device *dev;
448 unsigned num_pd_entries;
449 struct page **pt_pages;
451 dma_addr_t *pt_dma_addr;
452 dma_addr_t scratch_page_dma_addr;
454 /* pte functions, mirroring the interface of the global gtt. */
455 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
456 unsigned int first_entry,
457 unsigned int num_entries);
458 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
460 unsigned int pg_start,
461 enum i915_cache_level cache_level);
462 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
464 enum i915_cache_level level);
465 int (*enable)(struct drm_device *dev);
466 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
470 /* This must match up with the value previously used for execbuf2.rsvd1. */
471 #define DEFAULT_CONTEXT_ID 0
472 struct i915_hw_context {
476 struct drm_i915_file_private *file_priv;
477 struct intel_ring_buffer *ring;
478 struct drm_i915_gem_object *obj;
482 FBC_NO_OUTPUT, /* no outputs enabled to compress */
483 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
484 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
485 FBC_MODE_TOO_LARGE, /* mode too large for compression */
486 FBC_BAD_PLANE, /* fbc not supported on plane */
487 FBC_NOT_TILED, /* buffer not tiled */
488 FBC_MULTIPLE_PIPES, /* more than one pipe active */
493 PCH_NONE = 0, /* No PCH present */
494 PCH_IBX, /* Ibexpeak PCH */
495 PCH_CPT, /* Cougarpoint PCH */
496 PCH_LPT, /* Lynxpoint PCH */
500 enum intel_sbi_destination {
505 #define QUIRK_PIPEA_FORCE (1<<0)
506 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
507 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
510 struct intel_fbc_work;
513 struct i2c_adapter adapter;
517 struct i2c_algo_bit_data bit_algo;
518 struct drm_i915_private *dev_priv;
521 struct i915_suspend_saved_registers {
542 u32 saveTRANS_HTOTAL_A;
543 u32 saveTRANS_HBLANK_A;
544 u32 saveTRANS_HSYNC_A;
545 u32 saveTRANS_VTOTAL_A;
546 u32 saveTRANS_VBLANK_A;
547 u32 saveTRANS_VSYNC_A;
555 u32 savePFIT_PGM_RATIOS;
556 u32 saveBLC_HIST_CTL;
558 u32 saveBLC_PWM_CTL2;
559 u32 saveBLC_CPU_PWM_CTL;
560 u32 saveBLC_CPU_PWM_CTL2;
573 u32 saveTRANS_HTOTAL_B;
574 u32 saveTRANS_HBLANK_B;
575 u32 saveTRANS_HSYNC_B;
576 u32 saveTRANS_VTOTAL_B;
577 u32 saveTRANS_VBLANK_B;
578 u32 saveTRANS_VSYNC_B;
592 u32 savePP_ON_DELAYS;
593 u32 savePP_OFF_DELAYS;
601 u32 savePFIT_CONTROL;
602 u32 save_palette_a[256];
603 u32 save_palette_b[256];
604 u32 saveDPFC_CB_BASE;
605 u32 saveFBC_CFB_BASE;
608 u32 saveFBC_CONTROL2;
618 u32 saveCACHE_MODE_0;
619 u32 saveMI_ARB_STATE;
630 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
641 u32 savePIPEA_GMCH_DATA_M;
642 u32 savePIPEB_GMCH_DATA_M;
643 u32 savePIPEA_GMCH_DATA_N;
644 u32 savePIPEB_GMCH_DATA_N;
645 u32 savePIPEA_DP_LINK_M;
646 u32 savePIPEB_DP_LINK_M;
647 u32 savePIPEA_DP_LINK_N;
648 u32 savePIPEB_DP_LINK_N;
659 u32 savePCH_DREF_CONTROL;
660 u32 saveDISP_ARB_CTL;
661 u32 savePIPEA_DATA_M1;
662 u32 savePIPEA_DATA_N1;
663 u32 savePIPEA_LINK_M1;
664 u32 savePIPEA_LINK_N1;
665 u32 savePIPEB_DATA_M1;
666 u32 savePIPEB_DATA_N1;
667 u32 savePIPEB_LINK_M1;
668 u32 savePIPEB_LINK_N1;
669 u32 saveMCHBAR_RENDER_STANDBY;
670 u32 savePCH_PORT_HOTPLUG;
673 struct intel_gen6_power_mgmt {
674 struct work_struct work;
675 struct delayed_work vlv_work;
677 /* lock - irqsave spinlock that protectects the work_struct and
681 /* The below variables an all the rps hw state are protected by
682 * dev->struct mutext. */
689 struct delayed_work delayed_resume_work;
692 * Protects RPS/RC6 register access and PCU communication.
693 * Must be taken after struct_mutex if nested.
695 struct mutex hw_lock;
698 /* defined intel_pm.c */
699 extern spinlock_t mchdev_lock;
701 struct intel_ilk_power_mgmt {
709 unsigned long last_time1;
710 unsigned long chipset_power;
712 struct timespec last_time2;
713 unsigned long gfx_power;
719 struct drm_i915_gem_object *pwrctx;
720 struct drm_i915_gem_object *renderctx;
723 struct i915_dri1_state {
724 unsigned allow_batchbuffer : 1;
725 u32 __iomem *gfx_hws_cpu_addr;
736 struct intel_l3_parity {
738 struct work_struct error_work;
742 /** Memory allocator for GTT stolen memory */
743 struct drm_mm stolen;
744 /** Memory allocator for GTT */
745 struct drm_mm gtt_space;
746 /** List of all objects in gtt_space. Used to restore gtt
747 * mappings on resume */
748 struct list_head bound_list;
750 * List of objects which are not bound to the GTT (thus
751 * are idle and not used by the GPU) but still have
752 * (presumably uncached) pages still attached.
754 struct list_head unbound_list;
756 /** Usable portion of the GTT for GEM */
757 unsigned long stolen_base; /* limited to low memory (32-bit) */
761 /** PPGTT used for aliasing the PPGTT with the GTT */
762 struct i915_hw_ppgtt *aliasing_ppgtt;
764 struct shrinker inactive_shrinker;
765 bool shrinker_no_lock_stealing;
768 * List of objects currently involved in rendering.
770 * Includes buffers having the contents of their GPU caches
771 * flushed, not necessarily primitives. last_rendering_seqno
772 * represents when the rendering involved will be completed.
774 * A reference is held on the buffer while on this list.
776 struct list_head active_list;
779 * LRU list of objects which are not in the ringbuffer and
780 * are ready to unbind, but are still in the GTT.
782 * last_rendering_seqno is 0 while an object is in this list.
784 * A reference is not held on the buffer while on this list,
785 * as merely being GTT-bound shouldn't prevent its being
786 * freed, and we'll pull it off the list in the free path.
788 struct list_head inactive_list;
790 /** LRU list of objects with fence regs on them. */
791 struct list_head fence_list;
794 * We leave the user IRQ off as much as possible,
795 * but this means that requests will finish and never
796 * be retired once the system goes idle. Set a timer to
797 * fire periodically while the ring is running. When it
798 * fires, go retire requests.
800 struct delayed_work retire_work;
803 * Are we in a non-interruptible section of code like
809 * Flag if the X Server, and thus DRM, is not currently in
810 * control of the device.
812 * This is set between LeaveVT and EnterVT. It needs to be
813 * replaced with a semaphore. It also needs to be
814 * transitioned away from for kernel modesetting.
818 /** Bit 6 swizzling required for X tiling */
819 uint32_t bit_6_swizzle_x;
820 /** Bit 6 swizzling required for Y tiling */
821 uint32_t bit_6_swizzle_y;
823 /* storage for physical objects */
824 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
826 /* accounting, useful for userland debugging */
827 size_t object_memory;
831 struct i915_gpu_error {
832 /* For hangcheck timer */
833 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
834 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
835 struct timer_list hangcheck_timer;
837 uint32_t last_acthd[I915_NUM_RINGS];
838 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
840 /* For reset and error_state handling. */
842 /* Protected by the above dev->gpu_error.lock. */
843 struct drm_i915_error_state *first_error;
844 struct work_struct work;
846 unsigned long last_reset;
849 * State variable and reset counter controlling the reset flow
851 * Upper bits are for the reset counter. This counter is used by the
852 * wait_seqno code to race-free noticed that a reset event happened and
853 * that it needs to restart the entire ioctl (since most likely the
854 * seqno it waited for won't ever signal anytime soon).
856 * This is important for lock-free wait paths, where no contended lock
857 * naturally enforces the correct ordering between the bail-out of the
858 * waiter and the gpu reset work code.
860 * Lowest bit controls the reset state machine: Set means a reset is in
861 * progress. This state will (presuming we don't have any bugs) decay
862 * into either unset (successful reset) or the special WEDGED value (hw
863 * terminally sour). All waiters on the reset_queue will be woken when
866 atomic_t reset_counter;
869 * Special values/flags for reset_counter
871 * Note that the code relies on
872 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
875 #define I915_RESET_IN_PROGRESS_FLAG 1
876 #define I915_WEDGED 0xffffffff
879 * Waitqueue to signal when the reset has completed. Used by clients
880 * that wait for dev_priv->mm.wedged to settle.
882 wait_queue_head_t reset_queue;
884 /* For gpu hang simulation. */
885 unsigned int stop_rings;
888 enum modeset_restore {
894 typedef struct drm_i915_private {
895 struct drm_device *dev;
896 struct kmem_cache *slab;
898 const struct intel_device_info *info;
900 int relative_constants_mode;
904 struct drm_i915_gt_funcs gt;
905 /** gt_fifo_count and the subsequent register write are synchronized
906 * with dev->struct_mutex. */
907 unsigned gt_fifo_count;
908 /** forcewake_count is protected by gt_lock */
909 unsigned forcewake_count;
910 /** gt_lock is also taken in irq contexts. */
913 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
916 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
917 * controller on different i2c buses. */
918 struct mutex gmbus_mutex;
921 * Base address of the gmbus and gpio block.
923 uint32_t gpio_mmio_base;
925 wait_queue_head_t gmbus_wait_queue;
927 struct pci_dev *bridge_dev;
928 struct intel_ring_buffer ring[I915_NUM_RINGS];
929 uint32_t last_seqno, next_seqno;
931 drm_dma_handle_t *status_page_dmah;
932 struct resource mch_res;
934 atomic_t irq_received;
936 /* protects the irq masks */
939 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
940 struct pm_qos_request pm_qos;
942 /* DPIO indirect register protection */
943 struct mutex dpio_lock;
945 /** Cached value of IMR to avoid reads in updating the bitfield */
949 struct work_struct hotplug_work;
950 bool enable_hotplug_processing;
952 unsigned long hpd_last_jiffies;
957 HPD_MARK_DISABLED = 2
959 } hpd_stats[HPD_NUM_PINS];
961 struct timer_list hotplug_reenable_timer;
966 unsigned long cfb_size;
968 enum plane cfb_plane;
970 struct intel_fbc_work *fbc_work;
972 struct intel_opregion opregion;
975 struct intel_overlay *overlay;
976 unsigned int sprite_scaling_enabled;
982 spinlock_t lock; /* bl registers and the above bl fields */
983 struct backlight_device *device;
987 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
988 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
990 /* Feature bits from the VBIOS */
991 unsigned int int_tv_support:1;
992 unsigned int lvds_dither:1;
993 unsigned int lvds_vbt:1;
994 unsigned int int_crt_support:1;
995 unsigned int lvds_use_ssc:1;
996 unsigned int display_clock_mode:1;
997 unsigned int fdi_rx_polarity_inverted:1;
999 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1009 struct edp_power_seq pps;
1011 bool no_aux_handshake;
1014 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1015 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1016 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1018 unsigned int fsb_freq, mem_freq, is_ddr3;
1020 struct workqueue_struct *wq;
1022 /* Display functions */
1023 struct drm_i915_display_funcs display;
1025 /* PCH chipset type */
1026 enum intel_pch pch_type;
1027 unsigned short pch_id;
1029 unsigned long quirks;
1031 enum modeset_restore modeset_restore;
1032 struct mutex modeset_restore_lock;
1034 struct i915_gtt gtt;
1036 struct i915_gem_mm mm;
1038 /* Kernel Modesetting */
1040 struct sdvo_device_mapping sdvo_mappings[2];
1042 struct drm_crtc *plane_to_crtc_mapping[3];
1043 struct drm_crtc *pipe_to_crtc_mapping[3];
1044 wait_queue_head_t pending_flip_queue;
1046 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
1047 struct intel_ddi_plls ddi_plls;
1049 /* Reclocking support */
1050 bool render_reclock_avail;
1051 bool lvds_downclock_avail;
1052 /* indicates the reduced downclock for LVDS*/
1056 struct child_device_config *child_dev;
1058 bool mchbar_need_disable;
1060 struct intel_l3_parity l3_parity;
1062 /* gen6+ rps state */
1063 struct intel_gen6_power_mgmt rps;
1065 /* ilk-only ips/rps state. Everything in here is protected by the global
1066 * mchdev_lock in intel_pm.c */
1067 struct intel_ilk_power_mgmt ips;
1069 enum no_fbc_reason no_fbc_reason;
1071 struct drm_mm_node *compressed_fb;
1072 struct drm_mm_node *compressed_llb;
1074 struct i915_gpu_error gpu_error;
1076 struct drm_i915_gem_object *vlv_pctx;
1078 /* list of fbdev register on this device */
1079 struct intel_fbdev *fbdev;
1082 * The console may be contended at resume, but we don't
1083 * want it to block on it.
1085 struct work_struct console_resume_work;
1087 struct drm_property *broadcast_rgb_property;
1088 struct drm_property *force_audio_property;
1090 bool hw_contexts_disabled;
1091 uint32_t hw_context_size;
1095 struct i915_suspend_saved_registers regfile;
1097 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1099 struct i915_dri1_state dri1;
1100 } drm_i915_private_t;
1102 /* Iterate over initialised rings */
1103 #define for_each_ring(ring__, dev_priv__, i__) \
1104 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1105 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1107 enum hdmi_force_audio {
1108 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1109 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1110 HDMI_AUDIO_AUTO, /* trust EDID */
1111 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1114 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1116 struct drm_i915_gem_object_ops {
1117 /* Interface between the GEM object and its backing storage.
1118 * get_pages() is called once prior to the use of the associated set
1119 * of pages before to binding them into the GTT, and put_pages() is
1120 * called after we no longer need them. As we expect there to be
1121 * associated cost with migrating pages between the backing storage
1122 * and making them available for the GPU (e.g. clflush), we may hold
1123 * onto the pages after they are no longer referenced by the GPU
1124 * in case they may be used again shortly (for example migrating the
1125 * pages to a different memory domain within the GTT). put_pages()
1126 * will therefore most likely be called when the object itself is
1127 * being released or under memory pressure (where we attempt to
1128 * reap pages for the shrinker).
1130 int (*get_pages)(struct drm_i915_gem_object *);
1131 void (*put_pages)(struct drm_i915_gem_object *);
1134 struct drm_i915_gem_object {
1135 struct drm_gem_object base;
1137 const struct drm_i915_gem_object_ops *ops;
1139 /** Current space allocated to this object in the GTT, if any. */
1140 struct drm_mm_node *gtt_space;
1141 /** Stolen memory for this object, instead of being backed by shmem. */
1142 struct drm_mm_node *stolen;
1143 struct list_head gtt_list;
1145 /** This object's place on the active/inactive lists */
1146 struct list_head ring_list;
1147 struct list_head mm_list;
1148 /** This object's place in the batchbuffer or on the eviction list */
1149 struct list_head exec_list;
1152 * This is set if the object is on the active lists (has pending
1153 * rendering and so a non-zero seqno), and is not set if it i s on
1154 * inactive (ready to be unbound) list.
1156 unsigned int active:1;
1159 * This is set if the object has been written to since last bound
1162 unsigned int dirty:1;
1165 * Fence register bits (if any) for this object. Will be set
1166 * as needed when mapped into the GTT.
1167 * Protected by dev->struct_mutex.
1169 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1172 * Advice: are the backing pages purgeable?
1174 unsigned int madv:2;
1177 * Current tiling mode for the object.
1179 unsigned int tiling_mode:2;
1181 * Whether the tiling parameters for the currently associated fence
1182 * register have changed. Note that for the purposes of tracking
1183 * tiling changes we also treat the unfenced register, the register
1184 * slot that the object occupies whilst it executes a fenced
1185 * command (such as BLT on gen2/3), as a "fence".
1187 unsigned int fence_dirty:1;
1189 /** How many users have pinned this object in GTT space. The following
1190 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1191 * (via user_pin_count), execbuffer (objects are not allowed multiple
1192 * times for the same batchbuffer), and the framebuffer code. When
1193 * switching/pageflipping, the framebuffer code has at most two buffers
1196 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1197 * bits with absolutely no headroom. So use 4 bits. */
1198 unsigned int pin_count:4;
1199 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1202 * Is the object at the current location in the gtt mappable and
1203 * fenceable? Used to avoid costly recalculations.
1205 unsigned int map_and_fenceable:1;
1208 * Whether the current gtt mapping needs to be mappable (and isn't just
1209 * mappable by accident). Track pin and fault separate for a more
1210 * accurate mappable working set.
1212 unsigned int fault_mappable:1;
1213 unsigned int pin_mappable:1;
1216 * Is the GPU currently using a fence to access this buffer,
1218 unsigned int pending_fenced_gpu_access:1;
1219 unsigned int fenced_gpu_access:1;
1221 unsigned int cache_level:2;
1223 unsigned int has_aliasing_ppgtt_mapping:1;
1224 unsigned int has_global_gtt_mapping:1;
1225 unsigned int has_dma_mapping:1;
1227 struct sg_table *pages;
1228 int pages_pin_count;
1230 /* prime dma-buf support */
1231 void *dma_buf_vmapping;
1235 * Used for performing relocations during execbuffer insertion.
1237 struct hlist_node exec_node;
1238 unsigned long exec_handle;
1239 struct drm_i915_gem_exec_object2 *exec_entry;
1242 * Current offset of the object in GTT space.
1244 * This is the same as gtt_space->start
1246 uint32_t gtt_offset;
1248 struct intel_ring_buffer *ring;
1250 /** Breadcrumb of last rendering to the buffer. */
1251 uint32_t last_read_seqno;
1252 uint32_t last_write_seqno;
1253 /** Breadcrumb of last fenced GPU access to the buffer. */
1254 uint32_t last_fenced_seqno;
1256 /** Current tiling stride for the object, if it's tiled. */
1259 /** Record of address bit 17 of each page at last unbind. */
1260 unsigned long *bit_17;
1262 /** User space pin count and filp owning the pin */
1263 uint32_t user_pin_count;
1264 struct drm_file *pin_filp;
1266 /** for phy allocated objects */
1267 struct drm_i915_gem_phys_object *phys_obj;
1269 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1271 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1274 * Request queue structure.
1276 * The request queue allows us to note sequence numbers that have been emitted
1277 * and may be associated with active buffers to be retired.
1279 * By keeping this list, we can avoid having to do questionable
1280 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1281 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1283 struct drm_i915_gem_request {
1284 /** On Which ring this request was generated */
1285 struct intel_ring_buffer *ring;
1287 /** GEM sequence number associated with this request. */
1290 /** Postion in the ringbuffer of the end of the request */
1293 /** Context related to this request */
1294 struct i915_hw_context *ctx;
1296 /** Time at which this request was emitted, in jiffies. */
1297 unsigned long emitted_jiffies;
1299 /** global list entry for this request */
1300 struct list_head list;
1302 struct drm_i915_file_private *file_priv;
1303 /** file_priv list entry for this request */
1304 struct list_head client_list;
1307 struct drm_i915_file_private {
1310 struct list_head request_list;
1312 struct idr context_idr;
1315 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1317 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1318 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1319 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1320 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1321 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1322 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1323 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1324 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1325 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1326 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1327 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1328 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1329 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1330 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1331 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1332 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1333 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1334 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1335 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1336 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1337 (dev)->pci_device == 0x0152 || \
1338 (dev)->pci_device == 0x015a)
1339 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1340 (dev)->pci_device == 0x0106 || \
1341 (dev)->pci_device == 0x010A)
1342 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1343 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1344 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1345 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1346 ((dev)->pci_device & 0xFF00) == 0x0A00)
1349 * The genX designation typically refers to the render engine, so render
1350 * capability related checks should use IS_GEN, while display and other checks
1351 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1354 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1355 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1356 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1357 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1358 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1359 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1361 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1362 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1363 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1364 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1366 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1367 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1369 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1370 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1372 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1373 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1375 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1376 * rows, which changed the alignment requirements and fence programming.
1378 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1380 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1381 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1382 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1383 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1384 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1385 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1386 /* dsparb controlled by hw only */
1387 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1389 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1390 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1391 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1393 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1395 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1396 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1397 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1399 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1400 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1401 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1402 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1403 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1404 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1406 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1407 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1408 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1409 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1410 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1411 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1413 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1415 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1417 #define GT_FREQUENCY_MULTIPLIER 50
1419 #include "i915_trace.h"
1422 * RC6 is a special power stage which allows the GPU to enter an very
1423 * low-voltage mode when idle, using down to 0V while at this stage. This
1424 * stage is entered automatically when the GPU is idle when RC6 support is
1425 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1427 * There are different RC6 modes available in Intel GPU, which differentiate
1428 * among each other with the latency required to enter and leave RC6 and
1429 * voltage consumed by the GPU in different states.
1431 * The combination of the following flags define which states GPU is allowed
1432 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1433 * RC6pp is deepest RC6. Their support by hardware varies according to the
1434 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1435 * which brings the most power savings; deeper states save more power, but
1436 * require higher latency to switch to and wake up.
1438 #define INTEL_RC6_ENABLE (1<<0)
1439 #define INTEL_RC6p_ENABLE (1<<1)
1440 #define INTEL_RC6pp_ENABLE (1<<2)
1442 extern struct drm_ioctl_desc i915_ioctls[];
1443 extern int i915_max_ioctl;
1444 extern unsigned int i915_fbpercrtc __always_unused;
1445 extern int i915_panel_ignore_lid __read_mostly;
1446 extern unsigned int i915_powersave __read_mostly;
1447 extern int i915_semaphores __read_mostly;
1448 extern unsigned int i915_lvds_downclock __read_mostly;
1449 extern int i915_lvds_channel_mode __read_mostly;
1450 extern int i915_panel_use_ssc __read_mostly;
1451 extern int i915_vbt_sdvo_panel_type __read_mostly;
1452 extern int i915_enable_rc6 __read_mostly;
1453 extern int i915_enable_fbc __read_mostly;
1454 extern bool i915_enable_hangcheck __read_mostly;
1455 extern int i915_enable_ppgtt __read_mostly;
1456 extern unsigned int i915_preliminary_hw_support __read_mostly;
1457 extern int i915_disable_power_well __read_mostly;
1459 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1460 extern int i915_resume(struct drm_device *dev);
1461 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1462 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1465 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1466 extern void i915_kernel_lost_context(struct drm_device * dev);
1467 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1468 extern int i915_driver_unload(struct drm_device *);
1469 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1470 extern void i915_driver_lastclose(struct drm_device * dev);
1471 extern void i915_driver_preclose(struct drm_device *dev,
1472 struct drm_file *file_priv);
1473 extern void i915_driver_postclose(struct drm_device *dev,
1474 struct drm_file *file_priv);
1475 extern int i915_driver_device_is_agp(struct drm_device * dev);
1476 #ifdef CONFIG_COMPAT
1477 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1480 extern int i915_emit_box(struct drm_device *dev,
1481 struct drm_clip_rect *box,
1483 extern int intel_gpu_reset(struct drm_device *dev);
1484 extern int i915_reset(struct drm_device *dev);
1485 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1486 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1487 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1488 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1490 extern void intel_console_resume(struct work_struct *work);
1493 void i915_hangcheck_elapsed(unsigned long data);
1494 void i915_handle_error(struct drm_device *dev, bool wedged);
1496 extern void intel_irq_init(struct drm_device *dev);
1497 extern void intel_hpd_init(struct drm_device *dev);
1498 extern void intel_gt_init(struct drm_device *dev);
1499 extern void intel_gt_reset(struct drm_device *dev);
1501 void i915_error_state_free(struct kref *error_ref);
1504 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1507 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1509 #ifdef CONFIG_DEBUG_FS
1510 extern void i915_destroy_error_state(struct drm_device *dev);
1512 #define i915_destroy_error_state(x)
1517 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1518 struct drm_file *file_priv);
1519 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1520 struct drm_file *file_priv);
1521 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1522 struct drm_file *file_priv);
1523 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1524 struct drm_file *file_priv);
1525 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1526 struct drm_file *file_priv);
1527 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1528 struct drm_file *file_priv);
1529 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1530 struct drm_file *file_priv);
1531 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1532 struct drm_file *file_priv);
1533 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1534 struct drm_file *file_priv);
1535 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1536 struct drm_file *file_priv);
1537 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1538 struct drm_file *file_priv);
1539 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1540 struct drm_file *file_priv);
1541 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1542 struct drm_file *file_priv);
1543 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1544 struct drm_file *file);
1545 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1546 struct drm_file *file);
1547 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1548 struct drm_file *file_priv);
1549 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1550 struct drm_file *file_priv);
1551 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1552 struct drm_file *file_priv);
1553 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1554 struct drm_file *file_priv);
1555 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1556 struct drm_file *file_priv);
1557 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1558 struct drm_file *file_priv);
1559 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1560 struct drm_file *file_priv);
1561 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1562 struct drm_file *file_priv);
1563 void i915_gem_load(struct drm_device *dev);
1564 void *i915_gem_object_alloc(struct drm_device *dev);
1565 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1566 int i915_gem_init_object(struct drm_gem_object *obj);
1567 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1568 const struct drm_i915_gem_object_ops *ops);
1569 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1571 void i915_gem_free_object(struct drm_gem_object *obj);
1573 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1575 bool map_and_fenceable,
1577 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1578 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1579 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1580 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1581 void i915_gem_lastclose(struct drm_device *dev);
1583 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1584 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1586 struct sg_page_iter sg_iter;
1588 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1589 return sg_page_iter_page(&sg_iter);
1593 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1595 BUG_ON(obj->pages == NULL);
1596 obj->pages_pin_count++;
1598 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1600 BUG_ON(obj->pages_pin_count == 0);
1601 obj->pages_pin_count--;
1604 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1605 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1606 struct intel_ring_buffer *to);
1607 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1608 struct intel_ring_buffer *ring);
1610 int i915_gem_dumb_create(struct drm_file *file_priv,
1611 struct drm_device *dev,
1612 struct drm_mode_create_dumb *args);
1613 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1614 uint32_t handle, uint64_t *offset);
1615 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1618 * Returns true if seq1 is later than seq2.
1621 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1623 return (int32_t)(seq1 - seq2) >= 0;
1626 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1627 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1628 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1629 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1632 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1634 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1635 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1636 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1643 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1645 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1646 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1647 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1651 void i915_gem_retire_requests(struct drm_device *dev);
1652 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1653 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1654 bool interruptible);
1655 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1657 return unlikely(atomic_read(&error->reset_counter)
1658 & I915_RESET_IN_PROGRESS_FLAG);
1661 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1663 return atomic_read(&error->reset_counter) == I915_WEDGED;
1666 void i915_gem_reset(struct drm_device *dev);
1667 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1668 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1669 uint32_t read_domains,
1670 uint32_t write_domain);
1671 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1672 int __must_check i915_gem_init(struct drm_device *dev);
1673 int __must_check i915_gem_init_hw(struct drm_device *dev);
1674 void i915_gem_l3_remap(struct drm_device *dev);
1675 void i915_gem_init_swizzling(struct drm_device *dev);
1676 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1677 int __must_check i915_gpu_idle(struct drm_device *dev);
1678 int __must_check i915_gem_idle(struct drm_device *dev);
1679 int i915_add_request(struct intel_ring_buffer *ring,
1680 struct drm_file *file,
1682 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1684 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1686 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1689 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1691 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1693 struct intel_ring_buffer *pipelined);
1694 int i915_gem_attach_phys_object(struct drm_device *dev,
1695 struct drm_i915_gem_object *obj,
1698 void i915_gem_detach_phys_object(struct drm_device *dev,
1699 struct drm_i915_gem_object *obj);
1700 void i915_gem_free_all_phys_object(struct drm_device *dev);
1701 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1704 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1706 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1707 int tiling_mode, bool fenced);
1709 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1710 enum i915_cache_level cache_level);
1712 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1713 struct dma_buf *dma_buf);
1715 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1716 struct drm_gem_object *gem_obj, int flags);
1718 /* i915_gem_context.c */
1719 void i915_gem_context_init(struct drm_device *dev);
1720 void i915_gem_context_fini(struct drm_device *dev);
1721 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1722 int i915_switch_context(struct intel_ring_buffer *ring,
1723 struct drm_file *file, int to_id);
1724 void i915_gem_context_free(struct kref *ctx_ref);
1725 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1727 kref_get(&ctx->ref);
1730 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1732 kref_put(&ctx->ref, i915_gem_context_free);
1735 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1736 struct drm_file *file);
1737 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1738 struct drm_file *file);
1740 /* i915_gem_gtt.c */
1741 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1742 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1743 struct drm_i915_gem_object *obj,
1744 enum i915_cache_level cache_level);
1745 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1746 struct drm_i915_gem_object *obj);
1748 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1749 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1750 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1751 enum i915_cache_level cache_level);
1752 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1753 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1754 void i915_gem_init_global_gtt(struct drm_device *dev);
1755 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1756 unsigned long mappable_end, unsigned long end);
1757 int i915_gem_gtt_init(struct drm_device *dev);
1758 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1760 if (INTEL_INFO(dev)->gen < 6)
1761 intel_gtt_chipset_flush();
1765 /* i915_gem_evict.c */
1766 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1768 unsigned cache_level,
1771 int i915_gem_evict_everything(struct drm_device *dev);
1773 /* i915_gem_stolen.c */
1774 int i915_gem_init_stolen(struct drm_device *dev);
1775 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1776 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1777 void i915_gem_cleanup_stolen(struct drm_device *dev);
1778 struct drm_i915_gem_object *
1779 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1780 struct drm_i915_gem_object *
1781 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1785 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1787 /* i915_gem_tiling.c */
1788 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1790 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1792 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1793 obj->tiling_mode != I915_TILING_NONE;
1796 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1797 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1798 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1800 /* i915_gem_debug.c */
1801 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1802 const char *where, uint32_t mark);
1804 int i915_verify_lists(struct drm_device *dev);
1806 #define i915_verify_lists(dev) 0
1808 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1810 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1811 const char *where, uint32_t mark);
1813 /* i915_debugfs.c */
1814 int i915_debugfs_init(struct drm_minor *minor);
1815 void i915_debugfs_cleanup(struct drm_minor *minor);
1817 /* i915_suspend.c */
1818 extern int i915_save_state(struct drm_device *dev);
1819 extern int i915_restore_state(struct drm_device *dev);
1822 void i915_save_display_reg(struct drm_device *dev);
1823 void i915_restore_display_reg(struct drm_device *dev);
1826 void i915_setup_sysfs(struct drm_device *dev_priv);
1827 void i915_teardown_sysfs(struct drm_device *dev_priv);
1830 extern int intel_setup_gmbus(struct drm_device *dev);
1831 extern void intel_teardown_gmbus(struct drm_device *dev);
1832 static inline bool intel_gmbus_is_port_valid(unsigned port)
1834 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1837 extern struct i2c_adapter *intel_gmbus_get_adapter(
1838 struct drm_i915_private *dev_priv, unsigned port);
1839 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1840 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1841 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1843 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1845 extern void intel_i2c_reset(struct drm_device *dev);
1847 /* intel_opregion.c */
1848 extern int intel_opregion_setup(struct drm_device *dev);
1850 extern void intel_opregion_init(struct drm_device *dev);
1851 extern void intel_opregion_fini(struct drm_device *dev);
1852 extern void intel_opregion_asle_intr(struct drm_device *dev);
1854 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1855 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1856 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1861 extern void intel_register_dsm_handler(void);
1862 extern void intel_unregister_dsm_handler(void);
1864 static inline void intel_register_dsm_handler(void) { return; }
1865 static inline void intel_unregister_dsm_handler(void) { return; }
1866 #endif /* CONFIG_ACPI */
1869 extern void intel_modeset_init_hw(struct drm_device *dev);
1870 extern void intel_modeset_suspend_hw(struct drm_device *dev);
1871 extern void intel_modeset_init(struct drm_device *dev);
1872 extern void intel_modeset_gem_init(struct drm_device *dev);
1873 extern void intel_modeset_cleanup(struct drm_device *dev);
1874 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1875 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1876 bool force_restore);
1877 extern void i915_redisable_vga(struct drm_device *dev);
1878 extern bool intel_fbc_enabled(struct drm_device *dev);
1879 extern void intel_disable_fbc(struct drm_device *dev);
1880 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1881 extern void intel_init_pch_refclk(struct drm_device *dev);
1882 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1883 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1884 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
1885 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
1886 extern void intel_detect_pch(struct drm_device *dev);
1887 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1888 extern int intel_enable_rc6(const struct drm_device *dev);
1890 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1891 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1892 struct drm_file *file);
1895 #ifdef CONFIG_DEBUG_FS
1896 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1897 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1899 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1900 extern void intel_display_print_error_state(struct seq_file *m,
1901 struct drm_device *dev,
1902 struct intel_display_error_state *error);
1905 /* On SNB platform, before reading ring registers forcewake bit
1906 * must be set to prevent GT core from power down and stale values being
1909 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1910 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1911 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1913 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1914 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1915 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1916 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1917 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1919 int vlv_gpu_freq(int ddr_freq, int val);
1920 int vlv_freq_opcode(int ddr_freq, int val);
1922 #define __i915_read(x, y) \
1923 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1931 #define __i915_write(x, y) \
1932 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1940 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1941 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1943 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1944 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1945 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1946 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1948 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1949 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1950 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1951 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1953 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1954 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1956 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1957 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1959 /* "Broadcast RGB" property */
1960 #define INTEL_BROADCAST_RGB_AUTO 0
1961 #define INTEL_BROADCAST_RGB_FULL 1
1962 #define INTEL_BROADCAST_RGB_LIMITED 2
1964 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1966 if (HAS_PCH_SPLIT(dev))
1967 return CPU_VGACNTRL;
1968 else if (IS_VALLEYVIEW(dev))
1969 return VLV_VGACNTRL;
1974 static inline void __user *to_user_ptr(u64 address)
1976 return (void __user *)(uintptr_t)address;