1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
56 #include "intel_dpll_mgr.h"
58 /* General customization:
61 #define DRIVER_NAME "i915"
62 #define DRIVER_DESC "Intel Graphics"
63 #define DRIVER_DATE "20160330"
66 /* Many gcc seem to no see through this and fall over :( */
68 #define WARN_ON(x) ({ \
69 bool __i915_warn_cond = (x); \
70 if (__builtin_constant_p(__i915_warn_cond)) \
71 BUILD_BUG_ON(__i915_warn_cond); \
72 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
74 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
78 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
80 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
81 (long) (x), __func__);
83 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
84 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
85 * which may not necessarily be a user visible problem. This will either
86 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
87 * enable distros and users to tailor their preferred amount of i915 abrt
90 #define I915_STATE_WARN(condition, format...) ({ \
91 int __ret_warn_on = !!(condition); \
92 if (unlikely(__ret_warn_on)) \
93 if (!WARN(i915.verbose_state_checks, format)) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(x) \
99 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
101 bool __i915_inject_load_failure(const char *func, int line);
102 #define i915_inject_load_failure() \
103 __i915_inject_load_failure(__func__, __LINE__)
105 static inline const char *yesno(bool v)
107 return v ? "yes" : "no";
110 static inline const char *onoff(bool v)
112 return v ? "on" : "off";
121 I915_MAX_PIPES = _PIPE_EDP
123 #define pipe_name(p) ((p) + 'A')
135 static inline const char *transcoder_name(enum transcoder transcoder)
137 switch (transcoder) {
146 case TRANSCODER_DSI_A:
148 case TRANSCODER_DSI_C:
155 static inline bool transcoder_is_dsi(enum transcoder transcoder)
157 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
161 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
162 * number of planes per CRTC. Not all platforms really have this many planes,
163 * which means some arrays of size I915_MAX_PLANES may have unused entries
164 * between the topmost sprite plane and the cursor plane.
173 #define plane_name(p) ((p) + 'A')
175 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
185 #define port_name(p) ((p) + 'A')
187 #define I915_NUM_PHYS_VLV 2
199 enum intel_display_power_domain {
203 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
204 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
205 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
206 POWER_DOMAIN_TRANSCODER_A,
207 POWER_DOMAIN_TRANSCODER_B,
208 POWER_DOMAIN_TRANSCODER_C,
209 POWER_DOMAIN_TRANSCODER_EDP,
210 POWER_DOMAIN_TRANSCODER_DSI_A,
211 POWER_DOMAIN_TRANSCODER_DSI_C,
212 POWER_DOMAIN_PORT_DDI_A_LANES,
213 POWER_DOMAIN_PORT_DDI_B_LANES,
214 POWER_DOMAIN_PORT_DDI_C_LANES,
215 POWER_DOMAIN_PORT_DDI_D_LANES,
216 POWER_DOMAIN_PORT_DDI_E_LANES,
217 POWER_DOMAIN_PORT_DSI,
218 POWER_DOMAIN_PORT_CRT,
219 POWER_DOMAIN_PORT_OTHER,
228 POWER_DOMAIN_MODESET,
234 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
235 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
236 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
237 #define POWER_DOMAIN_TRANSCODER(tran) \
238 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
239 (tran) + POWER_DOMAIN_TRANSCODER_A)
243 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
255 #define for_each_hpd_pin(__pin) \
256 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
258 struct i915_hotplug {
259 struct work_struct hotplug_work;
262 unsigned long last_jiffies;
267 HPD_MARK_DISABLED = 2
269 } stats[HPD_NUM_PINS];
271 struct delayed_work reenable_work;
273 struct intel_digital_port *irq_port[I915_MAX_PORTS];
276 struct work_struct dig_port_work;
279 * if we get a HPD irq from DP and a HPD irq from non-DP
280 * the non-DP HPD could block the workqueue on a mode config
281 * mutex getting, that userspace may have taken. However
282 * userspace is waiting on the DP workqueue to run which is
283 * blocked behind the non-DP one.
285 struct workqueue_struct *dp_wq;
288 #define I915_GEM_GPU_DOMAINS \
289 (I915_GEM_DOMAIN_RENDER | \
290 I915_GEM_DOMAIN_SAMPLER | \
291 I915_GEM_DOMAIN_COMMAND | \
292 I915_GEM_DOMAIN_INSTRUCTION | \
293 I915_GEM_DOMAIN_VERTEX)
295 #define for_each_pipe(__dev_priv, __p) \
296 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
297 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
298 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
299 for_each_if ((__mask) & (1 << (__p)))
300 #define for_each_plane(__dev_priv, __pipe, __p) \
302 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
304 #define for_each_sprite(__dev_priv, __p, __s) \
306 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
309 #define for_each_port_masked(__port, __ports_mask) \
310 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
311 for_each_if ((__ports_mask) & (1 << (__port)))
313 #define for_each_crtc(dev, crtc) \
314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
316 #define for_each_intel_plane(dev, intel_plane) \
317 list_for_each_entry(intel_plane, \
318 &dev->mode_config.plane_list, \
321 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
322 list_for_each_entry(intel_plane, \
323 &(dev)->mode_config.plane_list, \
325 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
327 #define for_each_intel_crtc(dev, intel_crtc) \
328 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
330 #define for_each_intel_encoder(dev, intel_encoder) \
331 list_for_each_entry(intel_encoder, \
332 &(dev)->mode_config.encoder_list, \
335 #define for_each_intel_connector(dev, intel_connector) \
336 list_for_each_entry(intel_connector, \
337 &dev->mode_config.connector_list, \
340 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
341 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
342 for_each_if ((intel_encoder)->base.crtc == (__crtc))
344 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
345 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
346 for_each_if ((intel_connector)->base.encoder == (__encoder))
348 #define for_each_power_domain(domain, mask) \
349 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
350 for_each_if ((1 << (domain)) & (mask))
352 struct drm_i915_private;
353 struct i915_mm_struct;
354 struct i915_mmu_object;
356 struct drm_i915_file_private {
357 struct drm_i915_private *dev_priv;
358 struct drm_file *file;
362 struct list_head request_list;
363 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
364 * chosen to prevent the CPU getting more than a frame ahead of the GPU
365 * (when using lax throttling for the frontbuffer). We also use it to
366 * offer free GPU waitboosts for severely congested workloads.
368 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
370 struct idr context_idr;
372 struct intel_rps_client {
373 struct list_head link;
377 unsigned int bsd_ring;
380 /* Used by dp and fdi links */
381 struct intel_link_m_n {
389 void intel_link_compute_m_n(int bpp, int nlanes,
390 int pixel_clock, int link_clock,
391 struct intel_link_m_n *m_n);
393 /* Interface history:
396 * 1.2: Add Power Management
397 * 1.3: Add vblank support
398 * 1.4: Fix cmdbuffer path, add heap destroy
399 * 1.5: Add vblank pipe configuration
400 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
401 * - Support vertical blank on secondary display pipe
403 #define DRIVER_MAJOR 1
404 #define DRIVER_MINOR 6
405 #define DRIVER_PATCHLEVEL 0
407 #define WATCH_LISTS 0
409 struct opregion_header;
410 struct opregion_acpi;
411 struct opregion_swsci;
412 struct opregion_asle;
414 struct intel_opregion {
415 struct opregion_header *header;
416 struct opregion_acpi *acpi;
417 struct opregion_swsci *swsci;
418 u32 swsci_gbda_sub_functions;
419 u32 swsci_sbcb_sub_functions;
420 struct opregion_asle *asle;
425 struct work_struct asle_work;
427 #define OPREGION_SIZE (8*1024)
429 struct intel_overlay;
430 struct intel_overlay_error_state;
432 #define I915_FENCE_REG_NONE -1
433 #define I915_MAX_NUM_FENCES 32
434 /* 32 fences + sign bit for FENCE_REG_NONE */
435 #define I915_MAX_NUM_FENCE_BITS 6
437 struct drm_i915_fence_reg {
438 struct list_head lru_list;
439 struct drm_i915_gem_object *obj;
443 struct sdvo_device_mapping {
452 struct intel_display_error_state;
454 struct drm_i915_error_state {
463 /* Generic register state */
471 u32 error; /* gen6+ */
472 u32 err_int; /* gen7 */
473 u32 fault_data0; /* gen8, gen9 */
474 u32 fault_data1; /* gen8, gen9 */
480 u32 extra_instdone[I915_NUM_INSTDONE_REG];
481 u64 fence[I915_MAX_NUM_FENCES];
482 struct intel_overlay_error_state *overlay;
483 struct intel_display_error_state *display;
484 struct drm_i915_error_object *semaphore_obj;
486 struct drm_i915_error_ring {
488 /* Software tracked state */
491 enum intel_ring_hangcheck_action hangcheck_action;
494 /* our own tracking of ring head and tail */
498 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
517 u32 rc_psmi; /* sleep state */
518 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
520 struct drm_i915_error_object {
524 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
526 struct drm_i915_error_object *wa_ctx;
528 struct drm_i915_error_request {
543 char comm[TASK_COMM_LEN];
544 } ring[I915_NUM_ENGINES];
546 struct drm_i915_error_buffer {
549 u32 rseqno[I915_NUM_ENGINES], wseqno;
553 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
561 } **active_bo, **pinned_bo;
563 u32 *active_bo_count, *pinned_bo_count;
567 struct intel_connector;
568 struct intel_encoder;
569 struct intel_crtc_state;
570 struct intel_initial_plane_config;
575 struct drm_i915_display_funcs {
576 int (*get_display_clock_speed)(struct drm_device *dev);
577 int (*get_fifo_size)(struct drm_device *dev, int plane);
578 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
579 int (*compute_intermediate_wm)(struct drm_device *dev,
580 struct intel_crtc *intel_crtc,
581 struct intel_crtc_state *newstate);
582 void (*initial_watermarks)(struct intel_crtc_state *cstate);
583 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
584 void (*update_wm)(struct drm_crtc *crtc);
585 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
586 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
587 /* Returns the active state of the crtc, and if the crtc is active,
588 * fills out the pipe-config with the hw state. */
589 bool (*get_pipe_config)(struct intel_crtc *,
590 struct intel_crtc_state *);
591 void (*get_initial_plane_config)(struct intel_crtc *,
592 struct intel_initial_plane_config *);
593 int (*crtc_compute_clock)(struct intel_crtc *crtc,
594 struct intel_crtc_state *crtc_state);
595 void (*crtc_enable)(struct drm_crtc *crtc);
596 void (*crtc_disable)(struct drm_crtc *crtc);
597 void (*audio_codec_enable)(struct drm_connector *connector,
598 struct intel_encoder *encoder,
599 const struct drm_display_mode *adjusted_mode);
600 void (*audio_codec_disable)(struct intel_encoder *encoder);
601 void (*fdi_link_train)(struct drm_crtc *crtc);
602 void (*init_clock_gating)(struct drm_device *dev);
603 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
604 struct drm_framebuffer *fb,
605 struct drm_i915_gem_object *obj,
606 struct drm_i915_gem_request *req,
608 void (*hpd_irq_setup)(struct drm_device *dev);
609 /* clock updates for mode set */
611 /* render clock increase/decrease */
612 /* display clock increase/decrease */
613 /* pll clock increase/decrease */
615 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
616 void (*load_luts)(struct drm_crtc_state *crtc_state);
619 enum forcewake_domain_id {
620 FW_DOMAIN_ID_RENDER = 0,
621 FW_DOMAIN_ID_BLITTER,
627 enum forcewake_domains {
628 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
629 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
630 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
631 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
636 struct intel_uncore_funcs {
637 void (*force_wake_get)(struct drm_i915_private *dev_priv,
638 enum forcewake_domains domains);
639 void (*force_wake_put)(struct drm_i915_private *dev_priv,
640 enum forcewake_domains domains);
642 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
643 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
644 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
645 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
647 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
648 uint8_t val, bool trace);
649 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
650 uint16_t val, bool trace);
651 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
652 uint32_t val, bool trace);
653 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
654 uint64_t val, bool trace);
657 struct intel_uncore {
658 spinlock_t lock; /** lock is also taken in irq contexts. */
660 struct intel_uncore_funcs funcs;
663 enum forcewake_domains fw_domains;
665 struct intel_uncore_forcewake_domain {
666 struct drm_i915_private *i915;
667 enum forcewake_domain_id id;
669 struct timer_list timer;
676 } fw_domain[FW_DOMAIN_ID_COUNT];
678 int unclaimed_mmio_check;
681 /* Iterate over initialised fw domains */
682 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
683 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
684 (i__) < FW_DOMAIN_ID_COUNT; \
685 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
686 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
688 #define for_each_fw_domain(domain__, dev_priv__, i__) \
689 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
691 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
692 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
693 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
696 struct work_struct work;
698 uint32_t *dmc_payload;
699 uint32_t dmc_fw_size;
702 i915_reg_t mmioaddr[8];
703 uint32_t mmiodata[8];
705 uint32_t allowed_dc_mask;
708 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
709 func(is_mobile) sep \
712 func(is_i945gm) sep \
714 func(need_gfx_hws) sep \
716 func(is_pineview) sep \
717 func(is_broadwater) sep \
718 func(is_crestline) sep \
719 func(is_ivybridge) sep \
720 func(is_valleyview) sep \
721 func(is_cherryview) sep \
722 func(is_haswell) sep \
723 func(is_skylake) sep \
724 func(is_broxton) sep \
725 func(is_kabylake) sep \
726 func(is_preliminary) sep \
728 func(has_pipe_cxsr) sep \
729 func(has_hotplug) sep \
730 func(cursor_needs_physical) sep \
731 func(has_overlay) sep \
732 func(overlay_needs_physical) sep \
733 func(supports_tv) sep \
735 func(has_snoop) sep \
739 #define DEFINE_FLAG(name) u8 name:1
740 #define SEP_SEMICOLON ;
742 struct intel_device_info {
743 u32 display_mmio_offset;
746 u8 num_sprites[I915_MAX_PIPES];
748 u8 ring_mask; /* Rings supported by the HW */
749 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
750 /* Register offsets for the various display pipes and transcoders */
751 int pipe_offsets[I915_MAX_TRANSCODERS];
752 int trans_offsets[I915_MAX_TRANSCODERS];
753 int palette_offsets[I915_MAX_PIPES];
754 int cursor_offsets[I915_MAX_PIPES];
756 /* Slice/subslice/EU info */
759 u8 subslice_per_slice;
762 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
765 u8 has_subslice_pg:1;
769 u16 degamma_lut_size;
777 enum i915_cache_level {
779 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
780 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
781 caches, eg sampler/render caches, and the
782 large Last-Level-Cache. LLC is coherent with
783 the CPU, but L3 is only visible to the GPU. */
784 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
787 struct i915_ctx_hang_stats {
788 /* This context had batch pending when hang was declared */
789 unsigned batch_pending;
791 /* This context had batch active when hang was declared */
792 unsigned batch_active;
794 /* Time when this context was last blamed for a GPU reset */
795 unsigned long guilty_ts;
797 /* If the contexts causes a second GPU hang within this time,
798 * it is permanently banned from submitting any more work.
800 unsigned long ban_period_seconds;
802 /* This context is banned to submit more work */
806 /* This must match up with the value previously used for execbuf2.rsvd1. */
807 #define DEFAULT_CONTEXT_HANDLE 0
809 #define CONTEXT_NO_ZEROMAP (1<<0)
811 * struct intel_context - as the name implies, represents a context.
812 * @ref: reference count.
813 * @user_handle: userspace tracking identity for this context.
814 * @remap_slice: l3 row remapping information.
815 * @flags: context specific flags:
816 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
817 * @file_priv: filp associated with this context (NULL for global default
819 * @hang_stats: information about the role of this context in possible GPU
821 * @ppgtt: virtual memory space used by this context.
822 * @legacy_hw_ctx: render context backing object and whether it is correctly
823 * initialized (legacy ring submission mechanism only).
824 * @link: link in the global list of contexts.
826 * Contexts are memory images used by the hardware to store copies of their
829 struct intel_context {
833 struct drm_i915_private *i915;
835 struct drm_i915_file_private *file_priv;
836 struct i915_ctx_hang_stats hang_stats;
837 struct i915_hw_ppgtt *ppgtt;
839 /* Legacy ring buffer submission */
841 struct drm_i915_gem_object *rcs_state;
847 struct drm_i915_gem_object *state;
848 struct intel_ringbuffer *ringbuf;
850 struct i915_vma *lrc_vma;
852 uint32_t *lrc_reg_state;
853 } engine[I915_NUM_ENGINES];
855 struct list_head link;
867 /* This is always the inner lock when overlapping with struct_mutex and
868 * it's the outer lock when overlapping with stolen_lock. */
871 unsigned int possible_framebuffer_bits;
872 unsigned int busy_bits;
873 unsigned int visible_pipes_mask;
874 struct intel_crtc *crtc;
876 struct drm_mm_node compressed_fb;
877 struct drm_mm_node *compressed_llb;
884 struct intel_fbc_state_cache {
886 unsigned int mode_flags;
887 uint32_t hsw_bdw_pixel_rate;
891 unsigned int rotation;
899 uint32_t pixel_format;
902 unsigned int tiling_mode;
906 struct intel_fbc_reg_params {
910 unsigned int fence_y_offset;
915 uint32_t pixel_format;
923 struct intel_fbc_work {
925 u32 scheduled_vblank;
926 struct work_struct work;
929 const char *no_fbc_reason;
933 * HIGH_RR is the highest eDP panel refresh rate read from EDID
934 * LOW_RR is the lowest eDP panel refresh rate found from EDID
935 * parsing for same resolution.
937 enum drrs_refresh_rate_type {
940 DRRS_MAX_RR, /* RR count */
943 enum drrs_support_type {
944 DRRS_NOT_SUPPORTED = 0,
945 STATIC_DRRS_SUPPORT = 1,
946 SEAMLESS_DRRS_SUPPORT = 2
952 struct delayed_work work;
954 unsigned busy_frontbuffer_bits;
955 enum drrs_refresh_rate_type refresh_rate_type;
956 enum drrs_support_type type;
963 struct intel_dp *enabled;
965 struct delayed_work work;
966 unsigned busy_frontbuffer_bits;
973 PCH_NONE = 0, /* No PCH present */
974 PCH_IBX, /* Ibexpeak PCH */
975 PCH_CPT, /* Cougarpoint PCH */
976 PCH_LPT, /* Lynxpoint PCH */
977 PCH_SPT, /* Sunrisepoint PCH */
981 enum intel_sbi_destination {
986 #define QUIRK_PIPEA_FORCE (1<<0)
987 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
988 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
989 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
990 #define QUIRK_PIPEB_FORCE (1<<4)
991 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
994 struct intel_fbc_work;
997 struct i2c_adapter adapter;
1000 i915_reg_t gpio_reg;
1001 struct i2c_algo_bit_data bit_algo;
1002 struct drm_i915_private *dev_priv;
1005 struct i915_suspend_saved_registers {
1008 u32 savePP_ON_DELAYS;
1009 u32 savePP_OFF_DELAYS;
1014 u32 saveFBC_CONTROL;
1015 u32 saveCACHE_MODE_0;
1016 u32 saveMI_ARB_STATE;
1020 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1021 u32 savePCH_PORT_HOTPLUG;
1025 struct vlv_s0ix_state {
1032 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1033 u32 media_max_req_count;
1034 u32 gfx_max_req_count;
1060 u32 rp_down_timeout;
1066 /* Display 1 CZ domain */
1071 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1073 /* GT SA CZ domain */
1080 /* Display 2 CZ domain */
1084 u32 clock_gate_dis2;
1087 struct intel_rps_ei {
1093 struct intel_gen6_power_mgmt {
1095 * work, interrupts_enabled and pm_iir are protected by
1096 * dev_priv->irq_lock
1098 struct work_struct work;
1099 bool interrupts_enabled;
1102 /* Frequencies are stored in potentially platform dependent multiples.
1103 * In other words, *_freq needs to be multiplied by X to be interesting.
1104 * Soft limits are those which are used for the dynamic reclocking done
1105 * by the driver (raise frequencies under heavy loads, and lower for
1106 * lighter loads). Hard limits are those imposed by the hardware.
1108 * A distinction is made for overclocking, which is never enabled by
1109 * default, and is considered to be above the hard limit if it's
1112 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1113 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1114 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1115 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1116 u8 min_freq; /* AKA RPn. Minimum frequency */
1117 u8 idle_freq; /* Frequency to request when we are idle */
1118 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1119 u8 rp1_freq; /* "less than" RP0 power/freqency */
1120 u8 rp0_freq; /* Non-overclocked max frequency. */
1122 u8 up_threshold; /* Current %busy required to uplock */
1123 u8 down_threshold; /* Current %busy required to downclock */
1126 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1128 spinlock_t client_lock;
1129 struct list_head clients;
1133 struct delayed_work delayed_resume_work;
1136 struct intel_rps_client semaphores, mmioflips;
1138 /* manual wa residency calculations */
1139 struct intel_rps_ei up_ei, down_ei;
1142 * Protects RPS/RC6 register access and PCU communication.
1143 * Must be taken after struct_mutex if nested. Note that
1144 * this lock may be held for long periods of time when
1145 * talking to hw - so only take it when talking to hw!
1147 struct mutex hw_lock;
1150 /* defined intel_pm.c */
1151 extern spinlock_t mchdev_lock;
1153 struct intel_ilk_power_mgmt {
1161 unsigned long last_time1;
1162 unsigned long chipset_power;
1165 unsigned long gfx_power;
1172 struct drm_i915_private;
1173 struct i915_power_well;
1175 struct i915_power_well_ops {
1177 * Synchronize the well's hw state to match the current sw state, for
1178 * example enable/disable it based on the current refcount. Called
1179 * during driver init and resume time, possibly after first calling
1180 * the enable/disable handlers.
1182 void (*sync_hw)(struct drm_i915_private *dev_priv,
1183 struct i915_power_well *power_well);
1185 * Enable the well and resources that depend on it (for example
1186 * interrupts located on the well). Called after the 0->1 refcount
1189 void (*enable)(struct drm_i915_private *dev_priv,
1190 struct i915_power_well *power_well);
1192 * Disable the well and resources that depend on it. Called after
1193 * the 1->0 refcount transition.
1195 void (*disable)(struct drm_i915_private *dev_priv,
1196 struct i915_power_well *power_well);
1197 /* Returns the hw enabled state. */
1198 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1199 struct i915_power_well *power_well);
1202 /* Power well structure for haswell */
1203 struct i915_power_well {
1206 /* power well enable/disable usage count */
1208 /* cached hw enabled state */
1210 unsigned long domains;
1212 const struct i915_power_well_ops *ops;
1215 struct i915_power_domains {
1217 * Power wells needed for initialization at driver init and suspend
1218 * time are on. They are kept on until after the first modeset.
1222 int power_well_count;
1225 int domain_use_count[POWER_DOMAIN_NUM];
1226 struct i915_power_well *power_wells;
1229 #define MAX_L3_SLICES 2
1230 struct intel_l3_parity {
1231 u32 *remap_info[MAX_L3_SLICES];
1232 struct work_struct error_work;
1236 struct i915_gem_mm {
1237 /** Memory allocator for GTT stolen memory */
1238 struct drm_mm stolen;
1239 /** Protects the usage of the GTT stolen memory allocator. This is
1240 * always the inner lock when overlapping with struct_mutex. */
1241 struct mutex stolen_lock;
1243 /** List of all objects in gtt_space. Used to restore gtt
1244 * mappings on resume */
1245 struct list_head bound_list;
1247 * List of objects which are not bound to the GTT (thus
1248 * are idle and not used by the GPU) but still have
1249 * (presumably uncached) pages still attached.
1251 struct list_head unbound_list;
1253 /** Usable portion of the GTT for GEM */
1254 unsigned long stolen_base; /* limited to low memory (32-bit) */
1256 /** PPGTT used for aliasing the PPGTT with the GTT */
1257 struct i915_hw_ppgtt *aliasing_ppgtt;
1259 struct notifier_block oom_notifier;
1260 struct shrinker shrinker;
1261 bool shrinker_no_lock_stealing;
1263 /** LRU list of objects with fence regs on them. */
1264 struct list_head fence_list;
1267 * We leave the user IRQ off as much as possible,
1268 * but this means that requests will finish and never
1269 * be retired once the system goes idle. Set a timer to
1270 * fire periodically while the ring is running. When it
1271 * fires, go retire requests.
1273 struct delayed_work retire_work;
1276 * When we detect an idle GPU, we want to turn on
1277 * powersaving features. So once we see that there
1278 * are no more requests outstanding and no more
1279 * arrive within a small period of time, we fire
1280 * off the idle_work.
1282 struct delayed_work idle_work;
1285 * Are we in a non-interruptible section of code like
1291 * Is the GPU currently considered idle, or busy executing userspace
1292 * requests? Whilst idle, we attempt to power down the hardware and
1293 * display clocks. In order to reduce the effect on performance, there
1294 * is a slight delay before we do so.
1298 /* the indicator for dispatch video commands on two BSD rings */
1299 unsigned int bsd_ring_dispatch_index;
1301 /** Bit 6 swizzling required for X tiling */
1302 uint32_t bit_6_swizzle_x;
1303 /** Bit 6 swizzling required for Y tiling */
1304 uint32_t bit_6_swizzle_y;
1306 /* accounting, useful for userland debugging */
1307 spinlock_t object_stat_lock;
1308 size_t object_memory;
1312 struct drm_i915_error_state_buf {
1313 struct drm_i915_private *i915;
1322 struct i915_error_state_file_priv {
1323 struct drm_device *dev;
1324 struct drm_i915_error_state *error;
1327 struct i915_gpu_error {
1328 /* For hangcheck timer */
1329 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1330 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1331 /* Hang gpu twice in this window and your context gets banned */
1332 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1334 struct workqueue_struct *hangcheck_wq;
1335 struct delayed_work hangcheck_work;
1337 /* For reset and error_state handling. */
1339 /* Protected by the above dev->gpu_error.lock. */
1340 struct drm_i915_error_state *first_error;
1342 unsigned long missed_irq_rings;
1345 * State variable controlling the reset flow and count
1347 * This is a counter which gets incremented when reset is triggered,
1348 * and again when reset has been handled. So odd values (lowest bit set)
1349 * means that reset is in progress and even values that
1350 * (reset_counter >> 1):th reset was successfully completed.
1352 * If reset is not completed succesfully, the I915_WEDGE bit is
1353 * set meaning that hardware is terminally sour and there is no
1354 * recovery. All waiters on the reset_queue will be woken when
1357 * This counter is used by the wait_seqno code to notice that reset
1358 * event happened and it needs to restart the entire ioctl (since most
1359 * likely the seqno it waited for won't ever signal anytime soon).
1361 * This is important for lock-free wait paths, where no contended lock
1362 * naturally enforces the correct ordering between the bail-out of the
1363 * waiter and the gpu reset work code.
1365 atomic_t reset_counter;
1367 #define I915_RESET_IN_PROGRESS_FLAG 1
1368 #define I915_WEDGED (1 << 31)
1371 * Waitqueue to signal when the reset has completed. Used by clients
1372 * that wait for dev_priv->mm.wedged to settle.
1374 wait_queue_head_t reset_queue;
1376 /* Userspace knobs for gpu hang simulation;
1377 * combines both a ring mask, and extra flags
1380 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1381 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1383 /* For missed irq/seqno simulation. */
1384 unsigned int test_irq_rings;
1386 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1387 bool reload_in_reset;
1390 enum modeset_restore {
1391 MODESET_ON_LID_OPEN,
1396 #define DP_AUX_A 0x40
1397 #define DP_AUX_B 0x10
1398 #define DP_AUX_C 0x20
1399 #define DP_AUX_D 0x30
1401 #define DDC_PIN_B 0x05
1402 #define DDC_PIN_C 0x04
1403 #define DDC_PIN_D 0x06
1405 struct ddi_vbt_port_info {
1407 * This is an index in the HDMI/DVI DDI buffer translation table.
1408 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1409 * populate this field.
1411 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1412 uint8_t hdmi_level_shift;
1414 uint8_t supports_dvi:1;
1415 uint8_t supports_hdmi:1;
1416 uint8_t supports_dp:1;
1418 uint8_t alternate_aux_channel;
1419 uint8_t alternate_ddc_pin;
1421 uint8_t dp_boost_level;
1422 uint8_t hdmi_boost_level;
1425 enum psr_lines_to_wait {
1426 PSR_0_LINES_TO_WAIT = 0,
1428 PSR_4_LINES_TO_WAIT,
1432 struct intel_vbt_data {
1433 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1434 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1437 unsigned int int_tv_support:1;
1438 unsigned int lvds_dither:1;
1439 unsigned int lvds_vbt:1;
1440 unsigned int int_crt_support:1;
1441 unsigned int lvds_use_ssc:1;
1442 unsigned int display_clock_mode:1;
1443 unsigned int fdi_rx_polarity_inverted:1;
1445 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1447 enum drrs_support_type drrs_type;
1458 struct edp_power_seq pps;
1463 bool require_aux_wakeup;
1465 enum psr_lines_to_wait lines_to_wait;
1466 int tp1_wakeup_time;
1467 int tp2_tp3_wakeup_time;
1473 bool active_low_pwm;
1474 u8 min_brightness; /* min_brightness/255 of max */
1480 struct mipi_config *config;
1481 struct mipi_pps_data *pps;
1485 const u8 *sequence[MIPI_SEQ_MAX];
1491 union child_device_config *child_dev;
1493 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1494 struct sdvo_device_mapping sdvo_mappings[2];
1497 enum intel_ddb_partitioning {
1499 INTEL_DDB_PART_5_6, /* IVB+ */
1502 struct intel_wm_level {
1510 struct ilk_wm_values {
1511 uint32_t wm_pipe[3];
1513 uint32_t wm_lp_spr[3];
1514 uint32_t wm_linetime[3];
1516 enum intel_ddb_partitioning partitioning;
1519 struct vlv_pipe_wm {
1530 struct vlv_wm_values {
1531 struct vlv_pipe_wm pipe[3];
1532 struct vlv_sr_wm sr;
1542 struct skl_ddb_entry {
1543 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1546 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1548 return entry->end - entry->start;
1551 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1552 const struct skl_ddb_entry *e2)
1554 if (e1->start == e2->start && e1->end == e2->end)
1560 struct skl_ddb_allocation {
1561 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1562 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1563 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1566 struct skl_wm_values {
1567 bool dirty[I915_MAX_PIPES];
1568 struct skl_ddb_allocation ddb;
1569 uint32_t wm_linetime[I915_MAX_PIPES];
1570 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1571 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1574 struct skl_wm_level {
1575 bool plane_en[I915_MAX_PLANES];
1576 uint16_t plane_res_b[I915_MAX_PLANES];
1577 uint8_t plane_res_l[I915_MAX_PLANES];
1581 * This struct helps tracking the state needed for runtime PM, which puts the
1582 * device in PCI D3 state. Notice that when this happens, nothing on the
1583 * graphics device works, even register access, so we don't get interrupts nor
1586 * Every piece of our code that needs to actually touch the hardware needs to
1587 * either call intel_runtime_pm_get or call intel_display_power_get with the
1588 * appropriate power domain.
1590 * Our driver uses the autosuspend delay feature, which means we'll only really
1591 * suspend if we stay with zero refcount for a certain amount of time. The
1592 * default value is currently very conservative (see intel_runtime_pm_enable), but
1593 * it can be changed with the standard runtime PM files from sysfs.
1595 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1596 * goes back to false exactly before we reenable the IRQs. We use this variable
1597 * to check if someone is trying to enable/disable IRQs while they're supposed
1598 * to be disabled. This shouldn't happen and we'll print some error messages in
1601 * For more, read the Documentation/power/runtime_pm.txt.
1603 struct i915_runtime_pm {
1604 atomic_t wakeref_count;
1605 atomic_t atomic_seq;
1610 enum intel_pipe_crc_source {
1611 INTEL_PIPE_CRC_SOURCE_NONE,
1612 INTEL_PIPE_CRC_SOURCE_PLANE1,
1613 INTEL_PIPE_CRC_SOURCE_PLANE2,
1614 INTEL_PIPE_CRC_SOURCE_PF,
1615 INTEL_PIPE_CRC_SOURCE_PIPE,
1616 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1617 INTEL_PIPE_CRC_SOURCE_TV,
1618 INTEL_PIPE_CRC_SOURCE_DP_B,
1619 INTEL_PIPE_CRC_SOURCE_DP_C,
1620 INTEL_PIPE_CRC_SOURCE_DP_D,
1621 INTEL_PIPE_CRC_SOURCE_AUTO,
1622 INTEL_PIPE_CRC_SOURCE_MAX,
1625 struct intel_pipe_crc_entry {
1630 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1631 struct intel_pipe_crc {
1633 bool opened; /* exclusive access to the result file */
1634 struct intel_pipe_crc_entry *entries;
1635 enum intel_pipe_crc_source source;
1637 wait_queue_head_t wq;
1640 struct i915_frontbuffer_tracking {
1644 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1651 struct i915_wa_reg {
1654 /* bitmask representing WA bits */
1659 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1660 * allowing it for RCS as we don't foresee any requirement of having
1661 * a whitelist for other engines. When it is really required for
1662 * other engines then the limit need to be increased.
1664 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1666 struct i915_workarounds {
1667 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1669 u32 hw_whitelist_count[I915_NUM_ENGINES];
1672 struct i915_virtual_gpu {
1676 struct i915_execbuffer_params {
1677 struct drm_device *dev;
1678 struct drm_file *file;
1679 uint32_t dispatch_flags;
1680 uint32_t args_batch_start_offset;
1681 uint64_t batch_obj_vm_offset;
1682 struct intel_engine_cs *engine;
1683 struct drm_i915_gem_object *batch_obj;
1684 struct intel_context *ctx;
1685 struct drm_i915_gem_request *request;
1688 /* used in computing the new watermarks state */
1689 struct intel_wm_config {
1690 unsigned int num_pipes_active;
1691 bool sprites_enabled;
1692 bool sprites_scaled;
1695 struct drm_i915_private {
1696 struct drm_device *dev;
1697 struct kmem_cache *objects;
1698 struct kmem_cache *vmas;
1699 struct kmem_cache *requests;
1701 const struct intel_device_info info;
1703 int relative_constants_mode;
1707 struct intel_uncore uncore;
1709 struct i915_virtual_gpu vgpu;
1711 struct intel_guc guc;
1713 struct intel_csr csr;
1715 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1717 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1718 * controller on different i2c buses. */
1719 struct mutex gmbus_mutex;
1722 * Base address of the gmbus and gpio block.
1724 uint32_t gpio_mmio_base;
1726 /* MMIO base address for MIPI regs */
1727 uint32_t mipi_mmio_base;
1729 uint32_t psr_mmio_base;
1731 wait_queue_head_t gmbus_wait_queue;
1733 struct pci_dev *bridge_dev;
1734 struct intel_engine_cs engine[I915_NUM_ENGINES];
1735 struct drm_i915_gem_object *semaphore_obj;
1736 uint32_t last_seqno, next_seqno;
1738 struct drm_dma_handle *status_page_dmah;
1739 struct resource mch_res;
1741 /* protects the irq masks */
1742 spinlock_t irq_lock;
1744 /* protects the mmio flip data */
1745 spinlock_t mmio_flip_lock;
1747 bool display_irqs_enabled;
1749 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1750 struct pm_qos_request pm_qos;
1752 /* Sideband mailbox protection */
1753 struct mutex sb_lock;
1755 /** Cached value of IMR to avoid reads in updating the bitfield */
1758 u32 de_irq_mask[I915_MAX_PIPES];
1763 u32 pipestat_irq_mask[I915_MAX_PIPES];
1765 struct i915_hotplug hotplug;
1766 struct intel_fbc fbc;
1767 struct i915_drrs drrs;
1768 struct intel_opregion opregion;
1769 struct intel_vbt_data vbt;
1771 bool preserve_bios_swizzle;
1774 struct intel_overlay *overlay;
1776 /* backlight registers and fields in struct intel_panel */
1777 struct mutex backlight_lock;
1780 bool no_aux_handshake;
1782 /* protects panel power sequencer state */
1783 struct mutex pps_mutex;
1785 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1786 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1788 unsigned int fsb_freq, mem_freq, is_ddr3;
1789 unsigned int skl_boot_cdclk;
1790 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1791 unsigned int max_dotclk_freq;
1792 unsigned int rawclk_freq;
1793 unsigned int hpll_freq;
1794 unsigned int czclk_freq;
1797 * wq - Driver workqueue for GEM.
1799 * NOTE: Work items scheduled here are not allowed to grab any modeset
1800 * locks, for otherwise the flushing done in the pageflip code will
1801 * result in deadlocks.
1803 struct workqueue_struct *wq;
1805 /* Display functions */
1806 struct drm_i915_display_funcs display;
1808 /* PCH chipset type */
1809 enum intel_pch pch_type;
1810 unsigned short pch_id;
1812 unsigned long quirks;
1814 enum modeset_restore modeset_restore;
1815 struct mutex modeset_restore_lock;
1816 struct drm_atomic_state *modeset_restore_state;
1818 struct list_head vm_list; /* Global list of all address spaces */
1819 struct i915_ggtt ggtt; /* VM representing the global address space */
1821 struct i915_gem_mm mm;
1822 DECLARE_HASHTABLE(mm_structs, 7);
1823 struct mutex mm_lock;
1825 /* Kernel Modesetting */
1827 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1828 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1829 wait_queue_head_t pending_flip_queue;
1831 #ifdef CONFIG_DEBUG_FS
1832 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1835 /* dpll and cdclk state is protected by connection_mutex */
1836 int num_shared_dpll;
1837 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1838 const struct intel_dpll_mgr *dpll_mgr;
1841 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1842 * Must be global rather than per dpll, because on some platforms
1843 * plls share registers.
1845 struct mutex dpll_lock;
1847 unsigned int active_crtcs;
1848 unsigned int min_pixclk[I915_MAX_PIPES];
1850 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1852 struct i915_workarounds workarounds;
1854 struct i915_frontbuffer_tracking fb_tracking;
1858 bool mchbar_need_disable;
1860 struct intel_l3_parity l3_parity;
1862 /* Cannot be determined by PCIID. You must always read a register. */
1865 /* gen6+ rps state */
1866 struct intel_gen6_power_mgmt rps;
1868 /* ilk-only ips/rps state. Everything in here is protected by the global
1869 * mchdev_lock in intel_pm.c */
1870 struct intel_ilk_power_mgmt ips;
1872 struct i915_power_domains power_domains;
1874 struct i915_psr psr;
1876 struct i915_gpu_error gpu_error;
1878 struct drm_i915_gem_object *vlv_pctx;
1880 #ifdef CONFIG_DRM_FBDEV_EMULATION
1881 /* list of fbdev register on this device */
1882 struct intel_fbdev *fbdev;
1883 struct work_struct fbdev_suspend_work;
1886 struct drm_property *broadcast_rgb_property;
1887 struct drm_property *force_audio_property;
1889 /* hda/i915 audio component */
1890 struct i915_audio_component *audio_component;
1891 bool audio_component_registered;
1893 * av_mutex - mutex for audio/video sync
1896 struct mutex av_mutex;
1898 uint32_t hw_context_size;
1899 struct list_head context_list;
1903 u32 chv_phy_control;
1906 bool suspended_to_idle;
1907 struct i915_suspend_saved_registers regfile;
1908 struct vlv_s0ix_state vlv_s0ix_state;
1912 * Raw watermark latency values:
1913 * in 0.1us units for WM0,
1914 * in 0.5us units for WM1+.
1917 uint16_t pri_latency[5];
1919 uint16_t spr_latency[5];
1921 uint16_t cur_latency[5];
1923 * Raw watermark memory latency values
1924 * for SKL for all 8 levels
1927 uint16_t skl_latency[8];
1929 /* Committed wm config */
1930 struct intel_wm_config config;
1933 * The skl_wm_values structure is a bit too big for stack
1934 * allocation, so we keep the staging struct where we store
1935 * intermediate results here instead.
1937 struct skl_wm_values skl_results;
1939 /* current hardware state */
1941 struct ilk_wm_values hw;
1942 struct skl_wm_values skl_hw;
1943 struct vlv_wm_values vlv;
1949 * Should be held around atomic WM register writing; also
1950 * protects * intel_crtc->wm.active and
1951 * cstate->wm.need_postvbl_update.
1953 struct mutex wm_mutex;
1956 struct i915_runtime_pm pm;
1958 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1960 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1961 struct drm_i915_gem_execbuffer2 *args,
1962 struct list_head *vmas);
1963 int (*init_engines)(struct drm_device *dev);
1964 void (*cleanup_engine)(struct intel_engine_cs *engine);
1965 void (*stop_engine)(struct intel_engine_cs *engine);
1968 struct intel_context *kernel_context;
1970 /* perform PHY state sanity checks? */
1971 bool chv_phy_assert[2];
1973 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1976 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1977 * will be rejected. Instead look for a better place.
1981 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1983 return dev->dev_private;
1986 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1988 return to_i915(dev_get_drvdata(dev));
1991 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1993 return container_of(guc, struct drm_i915_private, guc);
1996 /* Simple iterator over all initialised engines */
1997 #define for_each_engine(engine__, dev_priv__) \
1998 for ((engine__) = &(dev_priv__)->engine[0]; \
1999 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2001 for_each_if (intel_engine_initialized(engine__))
2003 /* Iterator with engine_id */
2004 #define for_each_engine_id(engine__, dev_priv__, id__) \
2005 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2006 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2008 for_each_if (((id__) = (engine__)->id, \
2009 intel_engine_initialized(engine__)))
2011 /* Iterator over subset of engines selected by mask */
2012 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2013 for ((engine__) = &(dev_priv__)->engine[0]; \
2014 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2016 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2017 intel_engine_initialized(engine__))
2019 enum hdmi_force_audio {
2020 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2021 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2022 HDMI_AUDIO_AUTO, /* trust EDID */
2023 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2026 #define I915_GTT_OFFSET_NONE ((u32)-1)
2028 struct drm_i915_gem_object_ops {
2030 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2032 /* Interface between the GEM object and its backing storage.
2033 * get_pages() is called once prior to the use of the associated set
2034 * of pages before to binding them into the GTT, and put_pages() is
2035 * called after we no longer need them. As we expect there to be
2036 * associated cost with migrating pages between the backing storage
2037 * and making them available for the GPU (e.g. clflush), we may hold
2038 * onto the pages after they are no longer referenced by the GPU
2039 * in case they may be used again shortly (for example migrating the
2040 * pages to a different memory domain within the GTT). put_pages()
2041 * will therefore most likely be called when the object itself is
2042 * being released or under memory pressure (where we attempt to
2043 * reap pages for the shrinker).
2045 int (*get_pages)(struct drm_i915_gem_object *);
2046 void (*put_pages)(struct drm_i915_gem_object *);
2048 int (*dmabuf_export)(struct drm_i915_gem_object *);
2049 void (*release)(struct drm_i915_gem_object *);
2053 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2054 * considered to be the frontbuffer for the given plane interface-wise. This
2055 * doesn't mean that the hw necessarily already scans it out, but that any
2056 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2058 * We have one bit per pipe and per scanout plane type.
2060 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2061 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2062 #define INTEL_FRONTBUFFER_BITS \
2063 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2064 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2065 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2066 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2067 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2068 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2069 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2070 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2071 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2072 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2073 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2075 struct drm_i915_gem_object {
2076 struct drm_gem_object base;
2078 const struct drm_i915_gem_object_ops *ops;
2080 /** List of VMAs backed by this object */
2081 struct list_head vma_list;
2083 /** Stolen memory for this object, instead of being backed by shmem. */
2084 struct drm_mm_node *stolen;
2085 struct list_head global_list;
2087 struct list_head engine_list[I915_NUM_ENGINES];
2088 /** Used in execbuf to temporarily hold a ref */
2089 struct list_head obj_exec_link;
2091 struct list_head batch_pool_link;
2094 * This is set if the object is on the active lists (has pending
2095 * rendering and so a non-zero seqno), and is not set if it i s on
2096 * inactive (ready to be unbound) list.
2098 unsigned int active:I915_NUM_ENGINES;
2101 * This is set if the object has been written to since last bound
2104 unsigned int dirty:1;
2107 * Fence register bits (if any) for this object. Will be set
2108 * as needed when mapped into the GTT.
2109 * Protected by dev->struct_mutex.
2111 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2114 * Advice: are the backing pages purgeable?
2116 unsigned int madv:2;
2119 * Current tiling mode for the object.
2121 unsigned int tiling_mode:2;
2123 * Whether the tiling parameters for the currently associated fence
2124 * register have changed. Note that for the purposes of tracking
2125 * tiling changes we also treat the unfenced register, the register
2126 * slot that the object occupies whilst it executes a fenced
2127 * command (such as BLT on gen2/3), as a "fence".
2129 unsigned int fence_dirty:1;
2132 * Is the object at the current location in the gtt mappable and
2133 * fenceable? Used to avoid costly recalculations.
2135 unsigned int map_and_fenceable:1;
2138 * Whether the current gtt mapping needs to be mappable (and isn't just
2139 * mappable by accident). Track pin and fault separate for a more
2140 * accurate mappable working set.
2142 unsigned int fault_mappable:1;
2145 * Is the object to be mapped as read-only to the GPU
2146 * Only honoured if hardware has relevant pte bit
2148 unsigned long gt_ro:1;
2149 unsigned int cache_level:3;
2150 unsigned int cache_dirty:1;
2152 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2154 unsigned int pin_display;
2156 struct sg_table *pages;
2157 int pages_pin_count;
2159 struct scatterlist *sg;
2163 /* prime dma-buf support */
2164 void *dma_buf_vmapping;
2167 /** Breadcrumb of last rendering to the buffer.
2168 * There can only be one writer, but we allow for multiple readers.
2169 * If there is a writer that necessarily implies that all other
2170 * read requests are complete - but we may only be lazily clearing
2171 * the read requests. A read request is naturally the most recent
2172 * request on a ring, so we may have two different write and read
2173 * requests on one ring where the write request is older than the
2174 * read request. This allows for the CPU to read from an active
2175 * buffer by only waiting for the write to complete.
2177 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2178 struct drm_i915_gem_request *last_write_req;
2179 /** Breadcrumb of last fenced GPU access to the buffer. */
2180 struct drm_i915_gem_request *last_fenced_req;
2182 /** Current tiling stride for the object, if it's tiled. */
2185 /** References from framebuffers, locks out tiling changes. */
2186 unsigned long framebuffer_references;
2188 /** Record of address bit 17 of each page at last unbind. */
2189 unsigned long *bit_17;
2192 /** for phy allocated objects */
2193 struct drm_dma_handle *phys_handle;
2195 struct i915_gem_userptr {
2197 unsigned read_only :1;
2198 unsigned workers :4;
2199 #define I915_GEM_USERPTR_MAX_WORKERS 15
2201 struct i915_mm_struct *mm;
2202 struct i915_mmu_object *mmu_object;
2203 struct work_struct *work;
2207 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2209 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2210 struct drm_i915_gem_object *new,
2211 unsigned frontbuffer_bits);
2214 * Request queue structure.
2216 * The request queue allows us to note sequence numbers that have been emitted
2217 * and may be associated with active buffers to be retired.
2219 * By keeping this list, we can avoid having to do questionable sequence
2220 * number comparisons on buffer last_read|write_seqno. It also allows an
2221 * emission time to be associated with the request for tracking how far ahead
2222 * of the GPU the submission is.
2224 * The requests are reference counted, so upon creation they should have an
2225 * initial reference taken using kref_init
2227 struct drm_i915_gem_request {
2230 /** On Which ring this request was generated */
2231 struct drm_i915_private *i915;
2232 struct intel_engine_cs *engine;
2234 /** GEM sequence number associated with the previous request,
2235 * when the HWS breadcrumb is equal to this the GPU is processing
2240 /** GEM sequence number associated with this request,
2241 * when the HWS breadcrumb is equal or greater than this the GPU
2242 * has finished processing this request.
2246 /** Position in the ringbuffer of the start of the request */
2250 * Position in the ringbuffer of the start of the postfix.
2251 * This is required to calculate the maximum available ringbuffer
2252 * space without overwriting the postfix.
2256 /** Position in the ringbuffer of the end of the whole request */
2260 * Context and ring buffer related to this request
2261 * Contexts are refcounted, so when this request is associated with a
2262 * context, we must increment the context's refcount, to guarantee that
2263 * it persists while any request is linked to it. Requests themselves
2264 * are also refcounted, so the request will only be freed when the last
2265 * reference to it is dismissed, and the code in
2266 * i915_gem_request_free() will then decrement the refcount on the
2269 struct intel_context *ctx;
2270 struct intel_ringbuffer *ringbuf;
2272 /** Batch buffer related to this request if any (used for
2273 error state dump only) */
2274 struct drm_i915_gem_object *batch_obj;
2276 /** Time at which this request was emitted, in jiffies. */
2277 unsigned long emitted_jiffies;
2279 /** global list entry for this request */
2280 struct list_head list;
2282 struct drm_i915_file_private *file_priv;
2283 /** file_priv list entry for this request */
2284 struct list_head client_list;
2286 /** process identifier submitting this request */
2290 * The ELSP only accepts two elements at a time, so we queue
2291 * context/tail pairs on a given queue (ring->execlist_queue) until the
2292 * hardware is available. The queue serves a double purpose: we also use
2293 * it to keep track of the up to 2 contexts currently in the hardware
2294 * (usually one in execution and the other queued up by the GPU): We
2295 * only remove elements from the head of the queue when the hardware
2296 * informs us that an element has been completed.
2298 * All accesses to the queue are mediated by a spinlock
2299 * (ring->execlist_lock).
2302 /** Execlist link in the submission queue.*/
2303 struct list_head execlist_link;
2305 /** Execlists no. of times this request has been sent to the ELSP */
2310 struct drm_i915_gem_request * __must_check
2311 i915_gem_request_alloc(struct intel_engine_cs *engine,
2312 struct intel_context *ctx);
2313 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2314 void i915_gem_request_free(struct kref *req_ref);
2315 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2316 struct drm_file *file);
2318 static inline uint32_t
2319 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2321 return req ? req->seqno : 0;
2324 static inline struct intel_engine_cs *
2325 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2327 return req ? req->engine : NULL;
2330 static inline struct drm_i915_gem_request *
2331 i915_gem_request_reference(struct drm_i915_gem_request *req)
2334 kref_get(&req->ref);
2339 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2341 WARN_ON(!mutex_is_locked(&req->engine->dev->struct_mutex));
2342 kref_put(&req->ref, i915_gem_request_free);
2346 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2348 struct drm_device *dev;
2353 dev = req->engine->dev;
2354 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2355 mutex_unlock(&dev->struct_mutex);
2358 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2359 struct drm_i915_gem_request *src)
2362 i915_gem_request_reference(src);
2365 i915_gem_request_unreference(*pdst);
2371 * XXX: i915_gem_request_completed should be here but currently needs the
2372 * definition of i915_seqno_passed() which is below. It will be moved in
2373 * a later patch when the call to i915_seqno_passed() is obsoleted...
2377 * A command that requires special handling by the command parser.
2379 struct drm_i915_cmd_descriptor {
2381 * Flags describing how the command parser processes the command.
2383 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2384 * a length mask if not set
2385 * CMD_DESC_SKIP: The command is allowed but does not follow the
2386 * standard length encoding for the opcode range in
2388 * CMD_DESC_REJECT: The command is never allowed
2389 * CMD_DESC_REGISTER: The command should be checked against the
2390 * register whitelist for the appropriate ring
2391 * CMD_DESC_MASTER: The command is allowed if the submitting process
2395 #define CMD_DESC_FIXED (1<<0)
2396 #define CMD_DESC_SKIP (1<<1)
2397 #define CMD_DESC_REJECT (1<<2)
2398 #define CMD_DESC_REGISTER (1<<3)
2399 #define CMD_DESC_BITMASK (1<<4)
2400 #define CMD_DESC_MASTER (1<<5)
2403 * The command's unique identification bits and the bitmask to get them.
2404 * This isn't strictly the opcode field as defined in the spec and may
2405 * also include type, subtype, and/or subop fields.
2413 * The command's length. The command is either fixed length (i.e. does
2414 * not include a length field) or has a length field mask. The flag
2415 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2416 * a length mask. All command entries in a command table must include
2417 * length information.
2425 * Describes where to find a register address in the command to check
2426 * against the ring's register whitelist. Only valid if flags has the
2427 * CMD_DESC_REGISTER bit set.
2429 * A non-zero step value implies that the command may access multiple
2430 * registers in sequence (e.g. LRI), in that case step gives the
2431 * distance in dwords between individual offset fields.
2439 #define MAX_CMD_DESC_BITMASKS 3
2441 * Describes command checks where a particular dword is masked and
2442 * compared against an expected value. If the command does not match
2443 * the expected value, the parser rejects it. Only valid if flags has
2444 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2447 * If the check specifies a non-zero condition_mask then the parser
2448 * only performs the check when the bits specified by condition_mask
2455 u32 condition_offset;
2457 } bits[MAX_CMD_DESC_BITMASKS];
2461 * A table of commands requiring special handling by the command parser.
2463 * Each ring has an array of tables. Each table consists of an array of command
2464 * descriptors, which must be sorted with command opcodes in ascending order.
2466 struct drm_i915_cmd_table {
2467 const struct drm_i915_cmd_descriptor *table;
2471 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2472 #define __I915__(p) ({ \
2473 struct drm_i915_private *__p; \
2474 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2475 __p = (struct drm_i915_private *)p; \
2476 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2477 __p = to_i915((struct drm_device *)p); \
2482 #define INTEL_INFO(p) (&__I915__(p)->info)
2483 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2484 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2486 #define REVID_FOREVER 0xff
2488 * Return true if revision is in range [since,until] inclusive.
2490 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2492 #define IS_REVID(p, since, until) \
2493 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2495 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2496 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2497 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2498 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2499 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2500 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2501 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2502 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2503 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2504 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2505 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2506 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2507 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2508 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2509 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2510 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2511 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2512 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2513 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2514 INTEL_DEVID(dev) == 0x0152 || \
2515 INTEL_DEVID(dev) == 0x015a)
2516 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2517 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2518 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2519 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2520 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2521 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2522 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2523 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2524 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2525 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2526 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2527 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2528 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2529 (INTEL_DEVID(dev) & 0xf) == 0xe))
2530 /* ULX machines are also considered ULT. */
2531 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2532 (INTEL_DEVID(dev) & 0xf) == 0xe)
2533 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2534 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2535 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2536 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2537 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2538 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2539 /* ULX machines are also considered ULT. */
2540 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2541 INTEL_DEVID(dev) == 0x0A1E)
2542 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2543 INTEL_DEVID(dev) == 0x1913 || \
2544 INTEL_DEVID(dev) == 0x1916 || \
2545 INTEL_DEVID(dev) == 0x1921 || \
2546 INTEL_DEVID(dev) == 0x1926)
2547 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2548 INTEL_DEVID(dev) == 0x1915 || \
2549 INTEL_DEVID(dev) == 0x191E)
2550 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2551 INTEL_DEVID(dev) == 0x5913 || \
2552 INTEL_DEVID(dev) == 0x5916 || \
2553 INTEL_DEVID(dev) == 0x5921 || \
2554 INTEL_DEVID(dev) == 0x5926)
2555 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2556 INTEL_DEVID(dev) == 0x5915 || \
2557 INTEL_DEVID(dev) == 0x591E)
2558 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2559 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2560 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2561 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2563 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2565 #define SKL_REVID_A0 0x0
2566 #define SKL_REVID_B0 0x1
2567 #define SKL_REVID_C0 0x2
2568 #define SKL_REVID_D0 0x3
2569 #define SKL_REVID_E0 0x4
2570 #define SKL_REVID_F0 0x5
2572 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2574 #define BXT_REVID_A0 0x0
2575 #define BXT_REVID_A1 0x1
2576 #define BXT_REVID_B0 0x3
2577 #define BXT_REVID_C0 0x9
2579 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2582 * The genX designation typically refers to the render engine, so render
2583 * capability related checks should use IS_GEN, while display and other checks
2584 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2587 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2588 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2589 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2590 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2591 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2592 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2593 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2594 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2596 #define RENDER_RING (1<<RCS)
2597 #define BSD_RING (1<<VCS)
2598 #define BLT_RING (1<<BCS)
2599 #define VEBOX_RING (1<<VECS)
2600 #define BSD2_RING (1<<VCS2)
2601 #define ALL_ENGINES (~0)
2603 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2604 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2605 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2606 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2607 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2608 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2609 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2610 __I915__(dev)->ellc_size)
2611 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2613 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2614 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2615 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2616 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2617 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2619 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2620 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2622 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2623 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2625 /* WaRsDisableCoarsePowerGating:skl,bxt */
2626 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2627 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2628 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2630 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2631 * even when in MSI mode. This results in spurious interrupt warnings if the
2632 * legacy irq no. is shared with another device. The kernel then disables that
2633 * interrupt source and so prevents the other device from working properly.
2635 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2636 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2638 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2639 * rows, which changed the alignment requirements and fence programming.
2641 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2643 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2644 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2646 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2647 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2648 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2650 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2652 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2653 INTEL_INFO(dev)->gen >= 9)
2655 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2656 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2657 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2658 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2659 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2660 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2661 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2662 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2664 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2665 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2667 #define HAS_CSR(dev) (IS_GEN9(dev))
2669 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2670 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2672 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2673 INTEL_INFO(dev)->gen >= 8)
2675 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2676 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2679 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2680 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2681 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2682 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2683 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2684 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2685 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2686 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2687 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2688 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2689 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2691 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2692 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2693 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2694 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2695 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2696 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2697 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2698 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2699 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2701 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2702 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2704 /* DPF == dynamic parity feature */
2705 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2706 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2708 #define GT_FREQUENCY_MULTIPLIER 50
2709 #define GEN9_FREQ_SCALER 3
2711 #include "i915_trace.h"
2713 extern const struct drm_ioctl_desc i915_ioctls[];
2714 extern int i915_max_ioctl;
2716 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2717 extern int i915_resume_switcheroo(struct drm_device *dev);
2721 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2722 const char *fmt, ...);
2724 #define i915_report_error(dev_priv, fmt, ...) \
2725 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2727 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2728 extern int i915_driver_unload(struct drm_device *);
2729 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2730 extern void i915_driver_lastclose(struct drm_device * dev);
2731 extern void i915_driver_preclose(struct drm_device *dev,
2732 struct drm_file *file);
2733 extern void i915_driver_postclose(struct drm_device *dev,
2734 struct drm_file *file);
2735 #ifdef CONFIG_COMPAT
2736 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2739 extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
2740 extern bool intel_has_gpu_reset(struct drm_device *dev);
2741 extern int i915_reset(struct drm_device *dev);
2742 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2743 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2744 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2745 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2746 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2747 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2749 /* intel_hotplug.c */
2750 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2751 void intel_hpd_init(struct drm_i915_private *dev_priv);
2752 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2753 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2754 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2757 void i915_queue_hangcheck(struct drm_device *dev);
2759 void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2760 const char *fmt, ...);
2762 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2763 int intel_irq_install(struct drm_i915_private *dev_priv);
2764 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2766 extern void intel_uncore_sanitize(struct drm_device *dev);
2767 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2768 bool restore_forcewake);
2769 extern void intel_uncore_init(struct drm_device *dev);
2770 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2771 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2772 extern void intel_uncore_fini(struct drm_device *dev);
2773 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2774 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2775 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2776 enum forcewake_domains domains);
2777 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2778 enum forcewake_domains domains);
2779 /* Like above but the caller must manage the uncore.lock itself.
2780 * Must be used with I915_READ_FW and friends.
2782 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2783 enum forcewake_domains domains);
2784 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2785 enum forcewake_domains domains);
2786 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2787 static inline bool intel_vgpu_active(struct drm_device *dev)
2789 return to_i915(dev)->vgpu.active;
2793 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2797 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2800 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2801 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2802 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2805 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2806 uint32_t interrupt_mask,
2807 uint32_t enabled_irq_mask);
2809 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2811 ilk_update_display_irq(dev_priv, bits, bits);
2814 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2816 ilk_update_display_irq(dev_priv, bits, 0);
2818 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2820 uint32_t interrupt_mask,
2821 uint32_t enabled_irq_mask);
2822 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2823 enum pipe pipe, uint32_t bits)
2825 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2827 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2828 enum pipe pipe, uint32_t bits)
2830 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2832 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2833 uint32_t interrupt_mask,
2834 uint32_t enabled_irq_mask);
2836 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2838 ibx_display_interrupt_update(dev_priv, bits, bits);
2841 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2843 ibx_display_interrupt_update(dev_priv, bits, 0);
2848 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2849 struct drm_file *file_priv);
2850 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2851 struct drm_file *file_priv);
2852 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2853 struct drm_file *file_priv);
2854 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2855 struct drm_file *file_priv);
2856 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2857 struct drm_file *file_priv);
2858 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2859 struct drm_file *file_priv);
2860 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2861 struct drm_file *file_priv);
2862 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2863 struct drm_i915_gem_request *req);
2864 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2865 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2866 struct drm_i915_gem_execbuffer2 *args,
2867 struct list_head *vmas);
2868 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2869 struct drm_file *file_priv);
2870 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2871 struct drm_file *file_priv);
2872 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2873 struct drm_file *file_priv);
2874 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2875 struct drm_file *file);
2876 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2877 struct drm_file *file);
2878 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2879 struct drm_file *file_priv);
2880 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2881 struct drm_file *file_priv);
2882 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2883 struct drm_file *file_priv);
2884 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2885 struct drm_file *file_priv);
2886 int i915_gem_init_userptr(struct drm_device *dev);
2887 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2888 struct drm_file *file);
2889 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2890 struct drm_file *file_priv);
2891 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2892 struct drm_file *file_priv);
2893 void i915_gem_load_init(struct drm_device *dev);
2894 void i915_gem_load_cleanup(struct drm_device *dev);
2895 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2896 void *i915_gem_object_alloc(struct drm_device *dev);
2897 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2898 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2899 const struct drm_i915_gem_object_ops *ops);
2900 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2902 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2903 struct drm_device *dev, const void *data, size_t size);
2904 void i915_gem_free_object(struct drm_gem_object *obj);
2905 void i915_gem_vma_destroy(struct i915_vma *vma);
2907 /* Flags used by pin/bind&friends. */
2908 #define PIN_MAPPABLE (1<<0)
2909 #define PIN_NONBLOCK (1<<1)
2910 #define PIN_GLOBAL (1<<2)
2911 #define PIN_OFFSET_BIAS (1<<3)
2912 #define PIN_USER (1<<4)
2913 #define PIN_UPDATE (1<<5)
2914 #define PIN_ZONE_4G (1<<6)
2915 #define PIN_HIGH (1<<7)
2916 #define PIN_OFFSET_FIXED (1<<8)
2917 #define PIN_OFFSET_MASK (~4095)
2919 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2920 struct i915_address_space *vm,
2924 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2925 const struct i915_ggtt_view *view,
2929 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2931 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2932 int __must_check i915_vma_unbind(struct i915_vma *vma);
2934 * BEWARE: Do not use the function below unless you can _absolutely_
2935 * _guarantee_ VMA in question is _not in use_ anywhere.
2937 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2938 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2939 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2940 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2942 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2943 int *needs_clflush);
2945 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2947 static inline int __sg_page_count(struct scatterlist *sg)
2949 return sg->length >> PAGE_SHIFT;
2953 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2955 static inline struct page *
2956 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2958 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2961 if (n < obj->get_page.last) {
2962 obj->get_page.sg = obj->pages->sgl;
2963 obj->get_page.last = 0;
2966 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2967 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2968 if (unlikely(sg_is_chain(obj->get_page.sg)))
2969 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2972 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2975 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2977 BUG_ON(obj->pages == NULL);
2978 obj->pages_pin_count++;
2980 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2982 BUG_ON(obj->pages_pin_count == 0);
2983 obj->pages_pin_count--;
2986 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2987 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2988 struct intel_engine_cs *to,
2989 struct drm_i915_gem_request **to_req);
2990 void i915_vma_move_to_active(struct i915_vma *vma,
2991 struct drm_i915_gem_request *req);
2992 int i915_gem_dumb_create(struct drm_file *file_priv,
2993 struct drm_device *dev,
2994 struct drm_mode_create_dumb *args);
2995 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2996 uint32_t handle, uint64_t *offset);
2998 * Returns true if seq1 is later than seq2.
3001 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3003 return (int32_t)(seq1 - seq2) >= 0;
3006 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3007 bool lazy_coherency)
3009 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
3010 return i915_seqno_passed(seqno, req->previous_seqno);
3013 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3014 bool lazy_coherency)
3016 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
3017 return i915_seqno_passed(seqno, req->seqno);
3020 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3021 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3023 struct drm_i915_gem_request *
3024 i915_gem_find_active_request(struct intel_engine_cs *engine);
3026 bool i915_gem_retire_requests(struct drm_device *dev);
3027 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3028 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3029 bool interruptible);
3031 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3033 return unlikely(atomic_read(&error->reset_counter)
3034 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3037 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3039 return atomic_read(&error->reset_counter) & I915_WEDGED;
3042 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3044 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3047 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3049 return dev_priv->gpu_error.stop_rings == 0 ||
3050 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3053 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3055 return dev_priv->gpu_error.stop_rings == 0 ||
3056 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3059 void i915_gem_reset(struct drm_device *dev);
3060 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3061 int __must_check i915_gem_init(struct drm_device *dev);
3062 int i915_gem_init_engines(struct drm_device *dev);
3063 int __must_check i915_gem_init_hw(struct drm_device *dev);
3064 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3065 void i915_gem_init_swizzling(struct drm_device *dev);
3066 void i915_gem_cleanup_engines(struct drm_device *dev);
3067 int __must_check i915_gpu_idle(struct drm_device *dev);
3068 int __must_check i915_gem_suspend(struct drm_device *dev);
3069 void __i915_add_request(struct drm_i915_gem_request *req,
3070 struct drm_i915_gem_object *batch_obj,
3072 #define i915_add_request(req) \
3073 __i915_add_request(req, NULL, true)
3074 #define i915_add_request_no_flush(req) \
3075 __i915_add_request(req, NULL, false)
3076 int __i915_wait_request(struct drm_i915_gem_request *req,
3077 unsigned reset_counter,
3080 struct intel_rps_client *rps);
3081 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3082 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3084 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3087 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3090 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3092 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3094 const struct i915_ggtt_view *view);
3095 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3096 const struct i915_ggtt_view *view);
3097 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3099 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3100 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3103 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3105 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3106 int tiling_mode, bool fenced);
3108 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3109 enum i915_cache_level cache_level);
3111 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3112 struct dma_buf *dma_buf);
3114 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3115 struct drm_gem_object *gem_obj, int flags);
3117 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3118 const struct i915_ggtt_view *view);
3119 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3120 struct i915_address_space *vm);
3122 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3124 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3127 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3128 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3129 const struct i915_ggtt_view *view);
3130 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3131 struct i915_address_space *vm);
3133 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3134 struct i915_address_space *vm);
3136 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3137 struct i915_address_space *vm);
3139 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3140 const struct i915_ggtt_view *view);
3143 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3144 struct i915_address_space *vm);
3146 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3147 const struct i915_ggtt_view *view);
3149 static inline struct i915_vma *
3150 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3152 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3154 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3156 /* Some GGTT VM helpers */
3157 #define i915_obj_to_ggtt(obj) \
3158 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->ggtt.base)
3160 static inline struct i915_hw_ppgtt *
3161 i915_vm_to_ppgtt(struct i915_address_space *vm)
3163 WARN_ON(i915_is_ggtt(vm));
3164 return container_of(vm, struct i915_hw_ppgtt, base);
3168 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3170 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3173 static inline unsigned long
3174 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3176 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3179 static inline int __must_check
3180 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3184 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3185 alignment, flags | PIN_GLOBAL);
3189 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3191 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3194 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3195 const struct i915_ggtt_view *view);
3197 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3199 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3202 /* i915_gem_fence.c */
3203 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3204 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3206 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3207 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3209 void i915_gem_restore_fences(struct drm_device *dev);
3211 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3212 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3213 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3215 /* i915_gem_context.c */
3216 int __must_check i915_gem_context_init(struct drm_device *dev);
3217 void i915_gem_context_fini(struct drm_device *dev);
3218 void i915_gem_context_reset(struct drm_device *dev);
3219 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3220 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3221 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3222 int i915_switch_context(struct drm_i915_gem_request *req);
3223 struct intel_context *
3224 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3225 void i915_gem_context_free(struct kref *ctx_ref);
3226 struct drm_i915_gem_object *
3227 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3228 static inline void i915_gem_context_reference(struct intel_context *ctx)
3230 kref_get(&ctx->ref);
3233 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3235 kref_put(&ctx->ref, i915_gem_context_free);
3238 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3240 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3243 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3244 struct drm_file *file);
3245 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3246 struct drm_file *file);
3247 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3248 struct drm_file *file_priv);
3249 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3250 struct drm_file *file_priv);
3252 /* i915_gem_evict.c */
3253 int __must_check i915_gem_evict_something(struct drm_device *dev,
3254 struct i915_address_space *vm,
3257 unsigned cache_level,
3258 unsigned long start,
3261 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3262 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3264 /* belongs in i915_gem_gtt.h */
3265 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3267 if (INTEL_INFO(dev)->gen < 6)
3268 intel_gtt_chipset_flush();
3271 /* i915_gem_stolen.c */
3272 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3273 struct drm_mm_node *node, u64 size,
3274 unsigned alignment);
3275 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3276 struct drm_mm_node *node, u64 size,
3277 unsigned alignment, u64 start,
3279 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3280 struct drm_mm_node *node);
3281 int i915_gem_init_stolen(struct drm_device *dev);
3282 void i915_gem_cleanup_stolen(struct drm_device *dev);
3283 struct drm_i915_gem_object *
3284 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3285 struct drm_i915_gem_object *
3286 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3291 /* i915_gem_shrinker.c */
3292 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3293 unsigned long target,
3295 #define I915_SHRINK_PURGEABLE 0x1
3296 #define I915_SHRINK_UNBOUND 0x2
3297 #define I915_SHRINK_BOUND 0x4
3298 #define I915_SHRINK_ACTIVE 0x8
3299 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3300 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3301 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3304 /* i915_gem_tiling.c */
3305 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3307 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3309 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3310 obj->tiling_mode != I915_TILING_NONE;
3313 /* i915_gem_debug.c */
3315 int i915_verify_lists(struct drm_device *dev);
3317 #define i915_verify_lists(dev) 0
3320 /* i915_debugfs.c */
3321 int i915_debugfs_init(struct drm_minor *minor);
3322 void i915_debugfs_cleanup(struct drm_minor *minor);
3323 #ifdef CONFIG_DEBUG_FS
3324 int i915_debugfs_connector_add(struct drm_connector *connector);
3325 void intel_display_crc_init(struct drm_device *dev);
3327 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3329 static inline void intel_display_crc_init(struct drm_device *dev) {}
3332 /* i915_gpu_error.c */
3334 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3335 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3336 const struct i915_error_state_file_priv *error);
3337 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3338 struct drm_i915_private *i915,
3339 size_t count, loff_t pos);
3340 static inline void i915_error_state_buf_release(
3341 struct drm_i915_error_state_buf *eb)
3345 void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
3346 const char *error_msg);
3347 void i915_error_state_get(struct drm_device *dev,
3348 struct i915_error_state_file_priv *error_priv);
3349 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3350 void i915_destroy_error_state(struct drm_device *dev);
3352 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3353 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3355 /* i915_cmd_parser.c */
3356 int i915_cmd_parser_get_version(void);
3357 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3358 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3359 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3360 int i915_parse_cmds(struct intel_engine_cs *engine,
3361 struct drm_i915_gem_object *batch_obj,
3362 struct drm_i915_gem_object *shadow_batch_obj,
3363 u32 batch_start_offset,
3367 /* i915_suspend.c */
3368 extern int i915_save_state(struct drm_device *dev);
3369 extern int i915_restore_state(struct drm_device *dev);
3372 void i915_setup_sysfs(struct drm_device *dev_priv);
3373 void i915_teardown_sysfs(struct drm_device *dev_priv);
3376 extern int intel_setup_gmbus(struct drm_device *dev);
3377 extern void intel_teardown_gmbus(struct drm_device *dev);
3378 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3381 extern struct i2c_adapter *
3382 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3383 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3384 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3385 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3387 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3389 extern void intel_i2c_reset(struct drm_device *dev);
3392 int intel_bios_init(struct drm_i915_private *dev_priv);
3393 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3394 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3395 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3396 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3397 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3399 /* intel_opregion.c */
3401 extern int intel_opregion_setup(struct drm_device *dev);
3402 extern void intel_opregion_init(struct drm_device *dev);
3403 extern void intel_opregion_fini(struct drm_device *dev);
3404 extern void intel_opregion_asle_intr(struct drm_device *dev);
3405 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3407 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3410 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3411 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3412 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3413 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3415 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3420 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3428 extern void intel_register_dsm_handler(void);
3429 extern void intel_unregister_dsm_handler(void);
3431 static inline void intel_register_dsm_handler(void) { return; }
3432 static inline void intel_unregister_dsm_handler(void) { return; }
3433 #endif /* CONFIG_ACPI */
3436 extern void intel_modeset_init_hw(struct drm_device *dev);
3437 extern void intel_modeset_init(struct drm_device *dev);
3438 extern void intel_modeset_gem_init(struct drm_device *dev);
3439 extern void intel_modeset_cleanup(struct drm_device *dev);
3440 extern void intel_connector_unregister(struct intel_connector *);
3441 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3442 extern void intel_display_resume(struct drm_device *dev);
3443 extern void i915_redisable_vga(struct drm_device *dev);
3444 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3445 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3446 extern void intel_init_pch_refclk(struct drm_device *dev);
3447 extern void intel_set_rps(struct drm_device *dev, u8 val);
3448 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3450 extern void intel_detect_pch(struct drm_device *dev);
3451 extern int intel_enable_rc6(const struct drm_device *dev);
3453 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3454 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3455 struct drm_file *file);
3456 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3457 struct drm_file *file);
3460 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3461 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3462 struct intel_overlay_error_state *error);
3464 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3465 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3466 struct drm_device *dev,
3467 struct intel_display_error_state *error);
3469 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3470 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3472 /* intel_sideband.c */
3473 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3474 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3475 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3476 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3477 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3478 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3479 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3480 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3481 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3482 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3483 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3484 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3485 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3486 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3487 enum intel_sbi_destination destination);
3488 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3489 enum intel_sbi_destination destination);
3490 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3491 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3493 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3494 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3496 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3497 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3499 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3500 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3501 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3502 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3504 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3505 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3506 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3507 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3509 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3510 * will be implemented using 2 32-bit writes in an arbitrary order with
3511 * an arbitrary delay between them. This can cause the hardware to
3512 * act upon the intermediate value, possibly leading to corruption and
3513 * machine death. You have been warned.
3515 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3516 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3518 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3519 u32 upper, lower, old_upper, loop = 0; \
3520 upper = I915_READ(upper_reg); \
3522 old_upper = upper; \
3523 lower = I915_READ(lower_reg); \
3524 upper = I915_READ(upper_reg); \
3525 } while (upper != old_upper && loop++ < 2); \
3526 (u64)upper << 32 | lower; })
3528 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3529 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3531 #define __raw_read(x, s) \
3532 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3535 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3538 #define __raw_write(x, s) \
3539 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3540 i915_reg_t reg, uint##x##_t val) \
3542 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3557 /* These are untraced mmio-accessors that are only valid to be used inside
3558 * criticial sections inside IRQ handlers where forcewake is explicitly
3560 * Think twice, and think again, before using these.
3561 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3562 * intel_uncore_forcewake_irqunlock().
3564 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3565 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3566 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3568 /* "Broadcast RGB" property */
3569 #define INTEL_BROADCAST_RGB_AUTO 0
3570 #define INTEL_BROADCAST_RGB_FULL 1
3571 #define INTEL_BROADCAST_RGB_LIMITED 2
3573 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3575 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3576 return VLV_VGACNTRL;
3577 else if (INTEL_INFO(dev)->gen >= 5)
3578 return CPU_VGACNTRL;
3583 static inline void __user *to_user_ptr(u64 address)
3585 return (void __user *)(uintptr_t)address;
3588 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3590 unsigned long j = msecs_to_jiffies(m);
3592 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3595 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3597 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3600 static inline unsigned long
3601 timespec_to_jiffies_timeout(const struct timespec *value)
3603 unsigned long j = timespec_to_jiffies(value);
3605 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3609 * If you need to wait X milliseconds between events A and B, but event B
3610 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3611 * when event A happened, then just before event B you call this function and
3612 * pass the timestamp as the first argument, and X as the second argument.
3615 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3617 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3620 * Don't re-read the value of "jiffies" every time since it may change
3621 * behind our back and break the math.
3623 tmp_jiffies = jiffies;
3624 target_jiffies = timestamp_jiffies +
3625 msecs_to_jiffies_timeout(to_wait_ms);
3627 if (time_after(target_jiffies, tmp_jiffies)) {
3628 remaining_jiffies = target_jiffies - tmp_jiffies;
3629 while (remaining_jiffies)
3631 schedule_timeout_uninterruptible(remaining_jiffies);
3635 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3636 struct drm_i915_gem_request *req)
3638 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3639 i915_gem_request_assign(&engine->trace_irq_req, req);