1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150508"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_plane(dev, intel_plane) \
242 list_for_each_entry(intel_plane, \
243 &dev->mode_config.plane_list, \
246 #define for_each_intel_crtc(dev, intel_crtc) \
247 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
249 #define for_each_intel_encoder(dev, intel_encoder) \
250 list_for_each_entry(intel_encoder, \
251 &(dev)->mode_config.encoder_list, \
254 #define for_each_intel_connector(dev, intel_connector) \
255 list_for_each_entry(intel_connector, \
256 &dev->mode_config.connector_list, \
259 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
260 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
261 if ((intel_encoder)->base.crtc == (__crtc))
263 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
264 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
265 if ((intel_connector)->base.encoder == (__encoder))
267 #define for_each_power_domain(domain, mask) \
268 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
269 if ((1 << (domain)) & (mask))
271 struct drm_i915_private;
272 struct i915_mm_struct;
273 struct i915_mmu_object;
275 struct drm_i915_file_private {
276 struct drm_i915_private *dev_priv;
277 struct drm_file *file;
281 struct list_head request_list;
283 struct idr context_idr;
285 struct list_head rps_boost;
286 struct intel_engine_cs *bsd_ring;
292 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
293 /* real shared dpll ids must be >= 0 */
294 DPLL_ID_PCH_PLL_A = 0,
295 DPLL_ID_PCH_PLL_B = 1,
300 DPLL_ID_SKL_DPLL1 = 0,
301 DPLL_ID_SKL_DPLL2 = 1,
302 DPLL_ID_SKL_DPLL3 = 2,
304 #define I915_NUM_PLLS 3
306 struct intel_dpll_hw_state {
318 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
319 * lower part of ctrl1 and they get shifted into position when writing
320 * the register. This allows us to easily compare the state to share
324 /* HDMI only, 0 when used for DP */
325 uint32_t cfgcr1, cfgcr2;
328 uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
331 struct intel_shared_dpll_config {
332 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
333 struct intel_dpll_hw_state hw_state;
336 struct intel_shared_dpll {
337 struct intel_shared_dpll_config config;
338 struct intel_shared_dpll_config *new_config;
340 int active; /* count of number of active CRTCs (i.e. DPMS on) */
341 bool on; /* is the PLL actually active? Disabled during modeset */
343 /* should match the index in the dev_priv->shared_dplls array */
344 enum intel_dpll_id id;
345 /* The mode_set hook is optional and should be used together with the
346 * intel_prepare_shared_dpll function. */
347 void (*mode_set)(struct drm_i915_private *dev_priv,
348 struct intel_shared_dpll *pll);
349 void (*enable)(struct drm_i915_private *dev_priv,
350 struct intel_shared_dpll *pll);
351 void (*disable)(struct drm_i915_private *dev_priv,
352 struct intel_shared_dpll *pll);
353 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
354 struct intel_shared_dpll *pll,
355 struct intel_dpll_hw_state *hw_state);
363 /* Used by dp and fdi links */
364 struct intel_link_m_n {
372 void intel_link_compute_m_n(int bpp, int nlanes,
373 int pixel_clock, int link_clock,
374 struct intel_link_m_n *m_n);
376 /* Interface history:
379 * 1.2: Add Power Management
380 * 1.3: Add vblank support
381 * 1.4: Fix cmdbuffer path, add heap destroy
382 * 1.5: Add vblank pipe configuration
383 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
384 * - Support vertical blank on secondary display pipe
386 #define DRIVER_MAJOR 1
387 #define DRIVER_MINOR 6
388 #define DRIVER_PATCHLEVEL 0
390 #define WATCH_LISTS 0
392 struct opregion_header;
393 struct opregion_acpi;
394 struct opregion_swsci;
395 struct opregion_asle;
397 struct intel_opregion {
398 struct opregion_header __iomem *header;
399 struct opregion_acpi __iomem *acpi;
400 struct opregion_swsci __iomem *swsci;
401 u32 swsci_gbda_sub_functions;
402 u32 swsci_sbcb_sub_functions;
403 struct opregion_asle __iomem *asle;
405 u32 __iomem *lid_state;
406 struct work_struct asle_work;
408 #define OPREGION_SIZE (8*1024)
410 struct intel_overlay;
411 struct intel_overlay_error_state;
413 #define I915_FENCE_REG_NONE -1
414 #define I915_MAX_NUM_FENCES 32
415 /* 32 fences + sign bit for FENCE_REG_NONE */
416 #define I915_MAX_NUM_FENCE_BITS 6
418 struct drm_i915_fence_reg {
419 struct list_head lru_list;
420 struct drm_i915_gem_object *obj;
424 struct sdvo_device_mapping {
433 struct intel_display_error_state;
435 struct drm_i915_error_state {
443 /* Generic register state */
451 u32 error; /* gen6+ */
452 u32 err_int; /* gen7 */
453 u32 fault_data0; /* gen8, gen9 */
454 u32 fault_data1; /* gen8, gen9 */
460 u32 extra_instdone[I915_NUM_INSTDONE_REG];
461 u64 fence[I915_MAX_NUM_FENCES];
462 struct intel_overlay_error_state *overlay;
463 struct intel_display_error_state *display;
464 struct drm_i915_error_object *semaphore_obj;
466 struct drm_i915_error_ring {
468 /* Software tracked state */
471 enum intel_ring_hangcheck_action hangcheck_action;
474 /* our own tracking of ring head and tail */
478 u32 semaphore_seqno[I915_NUM_RINGS - 1];
497 u32 rc_psmi; /* sleep state */
498 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
500 struct drm_i915_error_object {
504 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
506 struct drm_i915_error_request {
521 char comm[TASK_COMM_LEN];
522 } ring[I915_NUM_RINGS];
524 struct drm_i915_error_buffer {
527 u32 rseqno[I915_NUM_RINGS], wseqno;
531 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
539 } **active_bo, **pinned_bo;
541 u32 *active_bo_count, *pinned_bo_count;
545 struct intel_connector;
546 struct intel_encoder;
547 struct intel_crtc_state;
548 struct intel_initial_plane_config;
553 struct drm_i915_display_funcs {
554 bool (*fbc_enabled)(struct drm_device *dev);
555 void (*enable_fbc)(struct drm_crtc *crtc);
556 void (*disable_fbc)(struct drm_device *dev);
557 int (*get_display_clock_speed)(struct drm_device *dev);
558 int (*get_fifo_size)(struct drm_device *dev, int plane);
560 * find_dpll() - Find the best values for the PLL
561 * @limit: limits for the PLL
562 * @crtc: current CRTC
563 * @target: target frequency in kHz
564 * @refclk: reference clock frequency in kHz
565 * @match_clock: if provided, @best_clock P divider must
566 * match the P divider from @match_clock
567 * used for LVDS downclocking
568 * @best_clock: best PLL values found
570 * Returns true on success, false on failure.
572 bool (*find_dpll)(const struct intel_limit *limit,
573 struct intel_crtc_state *crtc_state,
574 int target, int refclk,
575 struct dpll *match_clock,
576 struct dpll *best_clock);
577 void (*update_wm)(struct drm_crtc *crtc);
578 void (*update_sprite_wm)(struct drm_plane *plane,
579 struct drm_crtc *crtc,
580 uint32_t sprite_width, uint32_t sprite_height,
581 int pixel_size, bool enable, bool scaled);
582 void (*modeset_global_resources)(struct drm_atomic_state *state);
583 /* Returns the active state of the crtc, and if the crtc is active,
584 * fills out the pipe-config with the hw state. */
585 bool (*get_pipe_config)(struct intel_crtc *,
586 struct intel_crtc_state *);
587 void (*get_initial_plane_config)(struct intel_crtc *,
588 struct intel_initial_plane_config *);
589 int (*crtc_compute_clock)(struct intel_crtc *crtc,
590 struct intel_crtc_state *crtc_state);
591 void (*crtc_enable)(struct drm_crtc *crtc);
592 void (*crtc_disable)(struct drm_crtc *crtc);
593 void (*off)(struct drm_crtc *crtc);
594 void (*audio_codec_enable)(struct drm_connector *connector,
595 struct intel_encoder *encoder,
596 struct drm_display_mode *mode);
597 void (*audio_codec_disable)(struct intel_encoder *encoder);
598 void (*fdi_link_train)(struct drm_crtc *crtc);
599 void (*init_clock_gating)(struct drm_device *dev);
600 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
601 struct drm_framebuffer *fb,
602 struct drm_i915_gem_object *obj,
603 struct intel_engine_cs *ring,
605 void (*update_primary_plane)(struct drm_crtc *crtc,
606 struct drm_framebuffer *fb,
608 void (*hpd_irq_setup)(struct drm_device *dev);
609 /* clock updates for mode set */
611 /* render clock increase/decrease */
612 /* display clock increase/decrease */
613 /* pll clock increase/decrease */
615 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
616 uint32_t (*get_backlight)(struct intel_connector *connector);
617 void (*set_backlight)(struct intel_connector *connector,
619 void (*disable_backlight)(struct intel_connector *connector);
620 void (*enable_backlight)(struct intel_connector *connector);
623 enum forcewake_domain_id {
624 FW_DOMAIN_ID_RENDER = 0,
625 FW_DOMAIN_ID_BLITTER,
631 enum forcewake_domains {
632 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
633 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
634 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
635 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
640 struct intel_uncore_funcs {
641 void (*force_wake_get)(struct drm_i915_private *dev_priv,
642 enum forcewake_domains domains);
643 void (*force_wake_put)(struct drm_i915_private *dev_priv,
644 enum forcewake_domains domains);
646 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
647 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
648 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
649 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
651 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
652 uint8_t val, bool trace);
653 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
654 uint16_t val, bool trace);
655 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
656 uint32_t val, bool trace);
657 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
658 uint64_t val, bool trace);
661 struct intel_uncore {
662 spinlock_t lock; /** lock is also taken in irq contexts. */
664 struct intel_uncore_funcs funcs;
667 enum forcewake_domains fw_domains;
669 struct intel_uncore_forcewake_domain {
670 struct drm_i915_private *i915;
671 enum forcewake_domain_id id;
673 struct timer_list timer;
680 } fw_domain[FW_DOMAIN_ID_COUNT];
683 /* Iterate over initialised fw domains */
684 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
685 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
686 (i__) < FW_DOMAIN_ID_COUNT; \
687 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
688 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
690 #define for_each_fw_domain(domain__, dev_priv__, i__) \
691 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
694 FW_UNINITIALIZED = 0,
702 uint32_t dmc_fw_size;
704 uint32_t mmioaddr[8];
705 uint32_t mmiodata[8];
706 enum csr_state state;
709 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
710 func(is_mobile) sep \
713 func(is_i945gm) sep \
715 func(need_gfx_hws) sep \
717 func(is_pineview) sep \
718 func(is_broadwater) sep \
719 func(is_crestline) sep \
720 func(is_ivybridge) sep \
721 func(is_valleyview) sep \
722 func(is_haswell) sep \
723 func(is_skylake) sep \
724 func(is_preliminary) sep \
726 func(has_pipe_cxsr) sep \
727 func(has_hotplug) sep \
728 func(cursor_needs_physical) sep \
729 func(has_overlay) sep \
730 func(overlay_needs_physical) sep \
731 func(supports_tv) sep \
736 #define DEFINE_FLAG(name) u8 name:1
737 #define SEP_SEMICOLON ;
739 struct intel_device_info {
740 u32 display_mmio_offset;
743 u8 num_sprites[I915_MAX_PIPES];
745 u8 ring_mask; /* Rings supported by the HW */
746 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
747 /* Register offsets for the various display pipes and transcoders */
748 int pipe_offsets[I915_MAX_TRANSCODERS];
749 int trans_offsets[I915_MAX_TRANSCODERS];
750 int palette_offsets[I915_MAX_PIPES];
751 int cursor_offsets[I915_MAX_PIPES];
753 /* Slice/subslice/EU info */
756 u8 subslice_per_slice;
759 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
762 u8 has_subslice_pg:1;
769 enum i915_cache_level {
771 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
772 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
773 caches, eg sampler/render caches, and the
774 large Last-Level-Cache. LLC is coherent with
775 the CPU, but L3 is only visible to the GPU. */
776 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
779 struct i915_ctx_hang_stats {
780 /* This context had batch pending when hang was declared */
781 unsigned batch_pending;
783 /* This context had batch active when hang was declared */
784 unsigned batch_active;
786 /* Time when this context was last blamed for a GPU reset */
787 unsigned long guilty_ts;
789 /* If the contexts causes a second GPU hang within this time,
790 * it is permanently banned from submitting any more work.
792 unsigned long ban_period_seconds;
794 /* This context is banned to submit more work */
798 /* This must match up with the value previously used for execbuf2.rsvd1. */
799 #define DEFAULT_CONTEXT_HANDLE 0
801 * struct intel_context - as the name implies, represents a context.
802 * @ref: reference count.
803 * @user_handle: userspace tracking identity for this context.
804 * @remap_slice: l3 row remapping information.
805 * @file_priv: filp associated with this context (NULL for global default
807 * @hang_stats: information about the role of this context in possible GPU
809 * @ppgtt: virtual memory space used by this context.
810 * @legacy_hw_ctx: render context backing object and whether it is correctly
811 * initialized (legacy ring submission mechanism only).
812 * @link: link in the global list of contexts.
814 * Contexts are memory images used by the hardware to store copies of their
817 struct intel_context {
821 struct drm_i915_file_private *file_priv;
822 struct i915_ctx_hang_stats hang_stats;
823 struct i915_hw_ppgtt *ppgtt;
825 /* Legacy ring buffer submission */
827 struct drm_i915_gem_object *rcs_state;
832 bool rcs_initialized;
834 struct drm_i915_gem_object *state;
835 struct intel_ringbuffer *ringbuf;
837 } engine[I915_NUM_RINGS];
839 struct list_head link;
850 unsigned long uncompressed_size;
853 unsigned int possible_framebuffer_bits;
854 unsigned int busy_bits;
855 struct intel_crtc *crtc;
858 struct drm_mm_node compressed_fb;
859 struct drm_mm_node *compressed_llb;
863 /* Tracks whether the HW is actually enabled, not whether the feature is
867 struct intel_fbc_work {
868 struct delayed_work work;
869 struct drm_crtc *crtc;
870 struct drm_framebuffer *fb;
874 FBC_OK, /* FBC is enabled */
875 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
876 FBC_NO_OUTPUT, /* no outputs enabled to compress */
877 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
878 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
879 FBC_MODE_TOO_LARGE, /* mode too large for compression */
880 FBC_BAD_PLANE, /* fbc not supported on plane */
881 FBC_NOT_TILED, /* buffer not tiled */
882 FBC_MULTIPLE_PIPES, /* more than one pipe active */
884 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
889 * HIGH_RR is the highest eDP panel refresh rate read from EDID
890 * LOW_RR is the lowest eDP panel refresh rate found from EDID
891 * parsing for same resolution.
893 enum drrs_refresh_rate_type {
896 DRRS_MAX_RR, /* RR count */
899 enum drrs_support_type {
900 DRRS_NOT_SUPPORTED = 0,
901 STATIC_DRRS_SUPPORT = 1,
902 SEAMLESS_DRRS_SUPPORT = 2
908 struct delayed_work work;
910 unsigned busy_frontbuffer_bits;
911 enum drrs_refresh_rate_type refresh_rate_type;
912 enum drrs_support_type type;
919 struct intel_dp *enabled;
921 struct delayed_work work;
922 unsigned busy_frontbuffer_bits;
928 PCH_NONE = 0, /* No PCH present */
929 PCH_IBX, /* Ibexpeak PCH */
930 PCH_CPT, /* Cougarpoint PCH */
931 PCH_LPT, /* Lynxpoint PCH */
932 PCH_SPT, /* Sunrisepoint PCH */
936 enum intel_sbi_destination {
941 #define QUIRK_PIPEA_FORCE (1<<0)
942 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
943 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
944 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
945 #define QUIRK_PIPEB_FORCE (1<<4)
946 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
949 struct intel_fbc_work;
952 struct i2c_adapter adapter;
956 struct i2c_algo_bit_data bit_algo;
957 struct drm_i915_private *dev_priv;
960 struct i915_suspend_saved_registers {
963 u32 savePP_ON_DELAYS;
964 u32 savePP_OFF_DELAYS;
970 u32 saveCACHE_MODE_0;
971 u32 saveMI_ARB_STATE;
975 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
976 u32 savePCH_PORT_HOTPLUG;
980 struct vlv_s0ix_state {
987 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
988 u32 media_max_req_count;
989 u32 gfx_max_req_count;
1015 u32 rp_down_timeout;
1021 /* Display 1 CZ domain */
1026 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1028 /* GT SA CZ domain */
1035 /* Display 2 CZ domain */
1039 u32 clock_gate_dis2;
1042 struct intel_rps_ei {
1048 struct intel_gen6_power_mgmt {
1050 * work, interrupts_enabled and pm_iir are protected by
1051 * dev_priv->irq_lock
1053 struct work_struct work;
1054 bool interrupts_enabled;
1057 /* Frequencies are stored in potentially platform dependent multiples.
1058 * In other words, *_freq needs to be multiplied by X to be interesting.
1059 * Soft limits are those which are used for the dynamic reclocking done
1060 * by the driver (raise frequencies under heavy loads, and lower for
1061 * lighter loads). Hard limits are those imposed by the hardware.
1063 * A distinction is made for overclocking, which is never enabled by
1064 * default, and is considered to be above the hard limit if it's
1067 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1068 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1069 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1070 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1071 u8 min_freq; /* AKA RPn. Minimum frequency */
1072 u8 idle_freq; /* Frequency to request when we are idle */
1073 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1074 u8 rp1_freq; /* "less than" RP0 power/freqency */
1075 u8 rp0_freq; /* Non-overclocked max frequency. */
1078 u8 up_threshold; /* Current %busy required to uplock */
1079 u8 down_threshold; /* Current %busy required to downclock */
1082 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1085 struct delayed_work delayed_resume_work;
1086 struct list_head clients;
1089 struct drm_i915_file_private semaphores;
1091 /* manual wa residency calculations */
1092 struct intel_rps_ei up_ei, down_ei;
1095 * Protects RPS/RC6 register access and PCU communication.
1096 * Must be taken after struct_mutex if nested.
1098 struct mutex hw_lock;
1101 /* defined intel_pm.c */
1102 extern spinlock_t mchdev_lock;
1104 struct intel_ilk_power_mgmt {
1112 unsigned long last_time1;
1113 unsigned long chipset_power;
1116 unsigned long gfx_power;
1123 struct drm_i915_private;
1124 struct i915_power_well;
1126 struct i915_power_well_ops {
1128 * Synchronize the well's hw state to match the current sw state, for
1129 * example enable/disable it based on the current refcount. Called
1130 * during driver init and resume time, possibly after first calling
1131 * the enable/disable handlers.
1133 void (*sync_hw)(struct drm_i915_private *dev_priv,
1134 struct i915_power_well *power_well);
1136 * Enable the well and resources that depend on it (for example
1137 * interrupts located on the well). Called after the 0->1 refcount
1140 void (*enable)(struct drm_i915_private *dev_priv,
1141 struct i915_power_well *power_well);
1143 * Disable the well and resources that depend on it. Called after
1144 * the 1->0 refcount transition.
1146 void (*disable)(struct drm_i915_private *dev_priv,
1147 struct i915_power_well *power_well);
1148 /* Returns the hw enabled state. */
1149 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1150 struct i915_power_well *power_well);
1153 /* Power well structure for haswell */
1154 struct i915_power_well {
1157 /* power well enable/disable usage count */
1159 /* cached hw enabled state */
1161 unsigned long domains;
1163 const struct i915_power_well_ops *ops;
1166 struct i915_power_domains {
1168 * Power wells needed for initialization at driver init and suspend
1169 * time are on. They are kept on until after the first modeset.
1173 int power_well_count;
1176 int domain_use_count[POWER_DOMAIN_NUM];
1177 struct i915_power_well *power_wells;
1180 #define MAX_L3_SLICES 2
1181 struct intel_l3_parity {
1182 u32 *remap_info[MAX_L3_SLICES];
1183 struct work_struct error_work;
1187 struct i915_gem_mm {
1188 /** Memory allocator for GTT stolen memory */
1189 struct drm_mm stolen;
1190 /** List of all objects in gtt_space. Used to restore gtt
1191 * mappings on resume */
1192 struct list_head bound_list;
1194 * List of objects which are not bound to the GTT (thus
1195 * are idle and not used by the GPU) but still have
1196 * (presumably uncached) pages still attached.
1198 struct list_head unbound_list;
1200 /** Usable portion of the GTT for GEM */
1201 unsigned long stolen_base; /* limited to low memory (32-bit) */
1203 /** PPGTT used for aliasing the PPGTT with the GTT */
1204 struct i915_hw_ppgtt *aliasing_ppgtt;
1206 struct notifier_block oom_notifier;
1207 struct shrinker shrinker;
1208 bool shrinker_no_lock_stealing;
1210 /** LRU list of objects with fence regs on them. */
1211 struct list_head fence_list;
1214 * We leave the user IRQ off as much as possible,
1215 * but this means that requests will finish and never
1216 * be retired once the system goes idle. Set a timer to
1217 * fire periodically while the ring is running. When it
1218 * fires, go retire requests.
1220 struct delayed_work retire_work;
1223 * When we detect an idle GPU, we want to turn on
1224 * powersaving features. So once we see that there
1225 * are no more requests outstanding and no more
1226 * arrive within a small period of time, we fire
1227 * off the idle_work.
1229 struct delayed_work idle_work;
1232 * Are we in a non-interruptible section of code like
1238 * Is the GPU currently considered idle, or busy executing userspace
1239 * requests? Whilst idle, we attempt to power down the hardware and
1240 * display clocks. In order to reduce the effect on performance, there
1241 * is a slight delay before we do so.
1245 /* the indicator for dispatch video commands on two BSD rings */
1246 int bsd_ring_dispatch_index;
1248 /** Bit 6 swizzling required for X tiling */
1249 uint32_t bit_6_swizzle_x;
1250 /** Bit 6 swizzling required for Y tiling */
1251 uint32_t bit_6_swizzle_y;
1253 /* accounting, useful for userland debugging */
1254 spinlock_t object_stat_lock;
1255 size_t object_memory;
1259 struct drm_i915_error_state_buf {
1260 struct drm_i915_private *i915;
1269 struct i915_error_state_file_priv {
1270 struct drm_device *dev;
1271 struct drm_i915_error_state *error;
1274 struct i915_gpu_error {
1275 /* For hangcheck timer */
1276 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1277 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1278 /* Hang gpu twice in this window and your context gets banned */
1279 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1281 struct workqueue_struct *hangcheck_wq;
1282 struct delayed_work hangcheck_work;
1284 /* For reset and error_state handling. */
1286 /* Protected by the above dev->gpu_error.lock. */
1287 struct drm_i915_error_state *first_error;
1289 unsigned long missed_irq_rings;
1292 * State variable controlling the reset flow and count
1294 * This is a counter which gets incremented when reset is triggered,
1295 * and again when reset has been handled. So odd values (lowest bit set)
1296 * means that reset is in progress and even values that
1297 * (reset_counter >> 1):th reset was successfully completed.
1299 * If reset is not completed succesfully, the I915_WEDGE bit is
1300 * set meaning that hardware is terminally sour and there is no
1301 * recovery. All waiters on the reset_queue will be woken when
1304 * This counter is used by the wait_seqno code to notice that reset
1305 * event happened and it needs to restart the entire ioctl (since most
1306 * likely the seqno it waited for won't ever signal anytime soon).
1308 * This is important for lock-free wait paths, where no contended lock
1309 * naturally enforces the correct ordering between the bail-out of the
1310 * waiter and the gpu reset work code.
1312 atomic_t reset_counter;
1314 #define I915_RESET_IN_PROGRESS_FLAG 1
1315 #define I915_WEDGED (1 << 31)
1318 * Waitqueue to signal when the reset has completed. Used by clients
1319 * that wait for dev_priv->mm.wedged to settle.
1321 wait_queue_head_t reset_queue;
1323 /* Userspace knobs for gpu hang simulation;
1324 * combines both a ring mask, and extra flags
1327 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1328 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1330 /* For missed irq/seqno simulation. */
1331 unsigned int test_irq_rings;
1333 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1334 bool reload_in_reset;
1337 enum modeset_restore {
1338 MODESET_ON_LID_OPEN,
1343 struct ddi_vbt_port_info {
1345 * This is an index in the HDMI/DVI DDI buffer translation table.
1346 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1347 * populate this field.
1349 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1350 uint8_t hdmi_level_shift;
1352 uint8_t supports_dvi:1;
1353 uint8_t supports_hdmi:1;
1354 uint8_t supports_dp:1;
1357 enum psr_lines_to_wait {
1358 PSR_0_LINES_TO_WAIT = 0,
1360 PSR_4_LINES_TO_WAIT,
1364 struct intel_vbt_data {
1365 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1366 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1369 unsigned int int_tv_support:1;
1370 unsigned int lvds_dither:1;
1371 unsigned int lvds_vbt:1;
1372 unsigned int int_crt_support:1;
1373 unsigned int lvds_use_ssc:1;
1374 unsigned int display_clock_mode:1;
1375 unsigned int fdi_rx_polarity_inverted:1;
1376 unsigned int has_mipi:1;
1378 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1380 enum drrs_support_type drrs_type;
1385 int edp_preemphasis;
1387 bool edp_initialized;
1390 struct edp_power_seq edp_pps;
1394 bool require_aux_wakeup;
1396 enum psr_lines_to_wait lines_to_wait;
1397 int tp1_wakeup_time;
1398 int tp2_tp3_wakeup_time;
1404 bool active_low_pwm;
1405 u8 min_brightness; /* min_brightness/255 of max */
1412 struct mipi_config *config;
1413 struct mipi_pps_data *pps;
1417 u8 *sequence[MIPI_SEQ_MAX];
1423 union child_device_config *child_dev;
1425 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1428 enum intel_ddb_partitioning {
1430 INTEL_DDB_PART_5_6, /* IVB+ */
1433 struct intel_wm_level {
1441 struct ilk_wm_values {
1442 uint32_t wm_pipe[3];
1444 uint32_t wm_lp_spr[3];
1445 uint32_t wm_linetime[3];
1447 enum intel_ddb_partitioning partitioning;
1450 struct vlv_wm_values {
1469 struct skl_ddb_entry {
1470 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1473 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1475 return entry->end - entry->start;
1478 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1479 const struct skl_ddb_entry *e2)
1481 if (e1->start == e2->start && e1->end == e2->end)
1487 struct skl_ddb_allocation {
1488 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1489 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1490 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1491 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1494 struct skl_wm_values {
1495 bool dirty[I915_MAX_PIPES];
1496 struct skl_ddb_allocation ddb;
1497 uint32_t wm_linetime[I915_MAX_PIPES];
1498 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1499 uint32_t cursor[I915_MAX_PIPES][8];
1500 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1501 uint32_t cursor_trans[I915_MAX_PIPES];
1504 struct skl_wm_level {
1505 bool plane_en[I915_MAX_PLANES];
1507 uint16_t plane_res_b[I915_MAX_PLANES];
1508 uint8_t plane_res_l[I915_MAX_PLANES];
1509 uint16_t cursor_res_b;
1510 uint8_t cursor_res_l;
1514 * This struct helps tracking the state needed for runtime PM, which puts the
1515 * device in PCI D3 state. Notice that when this happens, nothing on the
1516 * graphics device works, even register access, so we don't get interrupts nor
1519 * Every piece of our code that needs to actually touch the hardware needs to
1520 * either call intel_runtime_pm_get or call intel_display_power_get with the
1521 * appropriate power domain.
1523 * Our driver uses the autosuspend delay feature, which means we'll only really
1524 * suspend if we stay with zero refcount for a certain amount of time. The
1525 * default value is currently very conservative (see intel_runtime_pm_enable), but
1526 * it can be changed with the standard runtime PM files from sysfs.
1528 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1529 * goes back to false exactly before we reenable the IRQs. We use this variable
1530 * to check if someone is trying to enable/disable IRQs while they're supposed
1531 * to be disabled. This shouldn't happen and we'll print some error messages in
1534 * For more, read the Documentation/power/runtime_pm.txt.
1536 struct i915_runtime_pm {
1541 enum intel_pipe_crc_source {
1542 INTEL_PIPE_CRC_SOURCE_NONE,
1543 INTEL_PIPE_CRC_SOURCE_PLANE1,
1544 INTEL_PIPE_CRC_SOURCE_PLANE2,
1545 INTEL_PIPE_CRC_SOURCE_PF,
1546 INTEL_PIPE_CRC_SOURCE_PIPE,
1547 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1548 INTEL_PIPE_CRC_SOURCE_TV,
1549 INTEL_PIPE_CRC_SOURCE_DP_B,
1550 INTEL_PIPE_CRC_SOURCE_DP_C,
1551 INTEL_PIPE_CRC_SOURCE_DP_D,
1552 INTEL_PIPE_CRC_SOURCE_AUTO,
1553 INTEL_PIPE_CRC_SOURCE_MAX,
1556 struct intel_pipe_crc_entry {
1561 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1562 struct intel_pipe_crc {
1564 bool opened; /* exclusive access to the result file */
1565 struct intel_pipe_crc_entry *entries;
1566 enum intel_pipe_crc_source source;
1568 wait_queue_head_t wq;
1571 struct i915_frontbuffer_tracking {
1575 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1582 struct i915_wa_reg {
1585 /* bitmask representing WA bits */
1589 #define I915_MAX_WA_REGS 16
1591 struct i915_workarounds {
1592 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1596 struct i915_virtual_gpu {
1600 struct drm_i915_private {
1601 struct drm_device *dev;
1602 struct kmem_cache *objects;
1603 struct kmem_cache *vmas;
1604 struct kmem_cache *requests;
1606 const struct intel_device_info info;
1608 int relative_constants_mode;
1612 struct intel_uncore uncore;
1614 struct i915_virtual_gpu vgpu;
1616 struct intel_csr csr;
1618 /* Display CSR-related protection */
1619 struct mutex csr_lock;
1621 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1623 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1624 * controller on different i2c buses. */
1625 struct mutex gmbus_mutex;
1628 * Base address of the gmbus and gpio block.
1630 uint32_t gpio_mmio_base;
1632 /* MMIO base address for MIPI regs */
1633 uint32_t mipi_mmio_base;
1635 wait_queue_head_t gmbus_wait_queue;
1637 struct pci_dev *bridge_dev;
1638 struct intel_engine_cs ring[I915_NUM_RINGS];
1639 struct drm_i915_gem_object *semaphore_obj;
1640 uint32_t last_seqno, next_seqno;
1642 struct drm_dma_handle *status_page_dmah;
1643 struct resource mch_res;
1645 /* protects the irq masks */
1646 spinlock_t irq_lock;
1648 /* protects the mmio flip data */
1649 spinlock_t mmio_flip_lock;
1651 bool display_irqs_enabled;
1653 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1654 struct pm_qos_request pm_qos;
1656 /* DPIO indirect register protection */
1657 struct mutex dpio_lock;
1659 /** Cached value of IMR to avoid reads in updating the bitfield */
1662 u32 de_irq_mask[I915_MAX_PIPES];
1667 u32 pipestat_irq_mask[I915_MAX_PIPES];
1669 struct work_struct hotplug_work;
1671 unsigned long hpd_last_jiffies;
1676 HPD_MARK_DISABLED = 2
1678 } hpd_stats[HPD_NUM_PINS];
1680 struct delayed_work hotplug_reenable_work;
1682 struct i915_fbc fbc;
1683 struct i915_drrs drrs;
1684 struct intel_opregion opregion;
1685 struct intel_vbt_data vbt;
1687 bool preserve_bios_swizzle;
1690 struct intel_overlay *overlay;
1692 /* backlight registers and fields in struct intel_panel */
1693 struct mutex backlight_lock;
1696 bool no_aux_handshake;
1698 /* protects panel power sequencer state */
1699 struct mutex pps_mutex;
1701 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1702 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1703 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1705 unsigned int fsb_freq, mem_freq, is_ddr3;
1706 unsigned int cdclk_freq;
1707 unsigned int hpll_freq;
1710 * wq - Driver workqueue for GEM.
1712 * NOTE: Work items scheduled here are not allowed to grab any modeset
1713 * locks, for otherwise the flushing done in the pageflip code will
1714 * result in deadlocks.
1716 struct workqueue_struct *wq;
1718 /* Display functions */
1719 struct drm_i915_display_funcs display;
1721 /* PCH chipset type */
1722 enum intel_pch pch_type;
1723 unsigned short pch_id;
1725 unsigned long quirks;
1727 enum modeset_restore modeset_restore;
1728 struct mutex modeset_restore_lock;
1730 struct list_head vm_list; /* Global list of all address spaces */
1731 struct i915_gtt gtt; /* VM representing the global address space */
1733 struct i915_gem_mm mm;
1734 DECLARE_HASHTABLE(mm_structs, 7);
1735 struct mutex mm_lock;
1737 /* Kernel Modesetting */
1739 struct sdvo_device_mapping sdvo_mappings[2];
1741 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1742 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1743 wait_queue_head_t pending_flip_queue;
1745 #ifdef CONFIG_DEBUG_FS
1746 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1749 int num_shared_dpll;
1750 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1751 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1753 struct i915_workarounds workarounds;
1755 /* Reclocking support */
1756 bool render_reclock_avail;
1757 bool lvds_downclock_avail;
1758 /* indicates the reduced downclock for LVDS*/
1761 struct i915_frontbuffer_tracking fb_tracking;
1765 bool mchbar_need_disable;
1767 struct intel_l3_parity l3_parity;
1769 /* Cannot be determined by PCIID. You must always read a register. */
1772 /* gen6+ rps state */
1773 struct intel_gen6_power_mgmt rps;
1775 /* ilk-only ips/rps state. Everything in here is protected by the global
1776 * mchdev_lock in intel_pm.c */
1777 struct intel_ilk_power_mgmt ips;
1779 struct i915_power_domains power_domains;
1781 struct i915_psr psr;
1783 struct i915_gpu_error gpu_error;
1785 struct drm_i915_gem_object *vlv_pctx;
1787 #ifdef CONFIG_DRM_I915_FBDEV
1788 /* list of fbdev register on this device */
1789 struct intel_fbdev *fbdev;
1790 struct work_struct fbdev_suspend_work;
1793 struct drm_property *broadcast_rgb_property;
1794 struct drm_property *force_audio_property;
1796 /* hda/i915 audio component */
1797 bool audio_component_registered;
1799 uint32_t hw_context_size;
1800 struct list_head context_list;
1804 u32 chv_phy_control;
1807 struct i915_suspend_saved_registers regfile;
1808 struct vlv_s0ix_state vlv_s0ix_state;
1812 * Raw watermark latency values:
1813 * in 0.1us units for WM0,
1814 * in 0.5us units for WM1+.
1817 uint16_t pri_latency[5];
1819 uint16_t spr_latency[5];
1821 uint16_t cur_latency[5];
1823 * Raw watermark memory latency values
1824 * for SKL for all 8 levels
1827 uint16_t skl_latency[8];
1830 * The skl_wm_values structure is a bit too big for stack
1831 * allocation, so we keep the staging struct where we store
1832 * intermediate results here instead.
1834 struct skl_wm_values skl_results;
1836 /* current hardware state */
1838 struct ilk_wm_values hw;
1839 struct skl_wm_values skl_hw;
1840 struct vlv_wm_values vlv;
1844 struct i915_runtime_pm pm;
1846 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1847 u32 long_hpd_port_mask;
1848 u32 short_hpd_port_mask;
1849 struct work_struct dig_port_work;
1852 * if we get a HPD irq from DP and a HPD irq from non-DP
1853 * the non-DP HPD could block the workqueue on a mode config
1854 * mutex getting, that userspace may have taken. However
1855 * userspace is waiting on the DP workqueue to run which is
1856 * blocked behind the non-DP one.
1858 struct workqueue_struct *dp_wq;
1860 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1862 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1863 struct intel_engine_cs *ring,
1864 struct intel_context *ctx,
1865 struct drm_i915_gem_execbuffer2 *args,
1866 struct list_head *vmas,
1867 struct drm_i915_gem_object *batch_obj,
1868 u64 exec_start, u32 flags);
1869 int (*init_rings)(struct drm_device *dev);
1870 void (*cleanup_ring)(struct intel_engine_cs *ring);
1871 void (*stop_ring)(struct intel_engine_cs *ring);
1874 bool edp_low_vswing;
1877 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1878 * will be rejected. Instead look for a better place.
1882 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1884 return dev->dev_private;
1887 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1889 return to_i915(dev_get_drvdata(dev));
1892 /* Iterate over initialised rings */
1893 #define for_each_ring(ring__, dev_priv__, i__) \
1894 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1895 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1897 enum hdmi_force_audio {
1898 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1899 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1900 HDMI_AUDIO_AUTO, /* trust EDID */
1901 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1904 #define I915_GTT_OFFSET_NONE ((u32)-1)
1906 struct drm_i915_gem_object_ops {
1907 /* Interface between the GEM object and its backing storage.
1908 * get_pages() is called once prior to the use of the associated set
1909 * of pages before to binding them into the GTT, and put_pages() is
1910 * called after we no longer need them. As we expect there to be
1911 * associated cost with migrating pages between the backing storage
1912 * and making them available for the GPU (e.g. clflush), we may hold
1913 * onto the pages after they are no longer referenced by the GPU
1914 * in case they may be used again shortly (for example migrating the
1915 * pages to a different memory domain within the GTT). put_pages()
1916 * will therefore most likely be called when the object itself is
1917 * being released or under memory pressure (where we attempt to
1918 * reap pages for the shrinker).
1920 int (*get_pages)(struct drm_i915_gem_object *);
1921 void (*put_pages)(struct drm_i915_gem_object *);
1922 int (*dmabuf_export)(struct drm_i915_gem_object *);
1923 void (*release)(struct drm_i915_gem_object *);
1927 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1928 * considered to be the frontbuffer for the given plane interface-vise. This
1929 * doesn't mean that the hw necessarily already scans it out, but that any
1930 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1932 * We have one bit per pipe and per scanout plane type.
1934 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1935 #define INTEL_FRONTBUFFER_BITS \
1936 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1937 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1938 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1939 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1940 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1941 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1942 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1943 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1944 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1945 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1946 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1948 struct drm_i915_gem_object {
1949 struct drm_gem_object base;
1951 const struct drm_i915_gem_object_ops *ops;
1953 /** List of VMAs backed by this object */
1954 struct list_head vma_list;
1956 /** Stolen memory for this object, instead of being backed by shmem. */
1957 struct drm_mm_node *stolen;
1958 struct list_head global_list;
1960 struct list_head ring_list[I915_NUM_RINGS];
1961 /** Used in execbuf to temporarily hold a ref */
1962 struct list_head obj_exec_link;
1964 struct list_head batch_pool_link;
1967 * This is set if the object is on the active lists (has pending
1968 * rendering and so a non-zero seqno), and is not set if it i s on
1969 * inactive (ready to be unbound) list.
1971 unsigned int active:I915_NUM_RINGS;
1974 * This is set if the object has been written to since last bound
1977 unsigned int dirty:1;
1980 * Fence register bits (if any) for this object. Will be set
1981 * as needed when mapped into the GTT.
1982 * Protected by dev->struct_mutex.
1984 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1987 * Advice: are the backing pages purgeable?
1989 unsigned int madv:2;
1992 * Current tiling mode for the object.
1994 unsigned int tiling_mode:2;
1996 * Whether the tiling parameters for the currently associated fence
1997 * register have changed. Note that for the purposes of tracking
1998 * tiling changes we also treat the unfenced register, the register
1999 * slot that the object occupies whilst it executes a fenced
2000 * command (such as BLT on gen2/3), as a "fence".
2002 unsigned int fence_dirty:1;
2005 * Is the object at the current location in the gtt mappable and
2006 * fenceable? Used to avoid costly recalculations.
2008 unsigned int map_and_fenceable:1;
2011 * Whether the current gtt mapping needs to be mappable (and isn't just
2012 * mappable by accident). Track pin and fault separate for a more
2013 * accurate mappable working set.
2015 unsigned int fault_mappable:1;
2018 * Is the object to be mapped as read-only to the GPU
2019 * Only honoured if hardware has relevant pte bit
2021 unsigned long gt_ro:1;
2022 unsigned int cache_level:3;
2023 unsigned int cache_dirty:1;
2025 unsigned int has_dma_mapping:1;
2027 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2029 unsigned int pin_display;
2031 struct sg_table *pages;
2032 int pages_pin_count;
2034 struct scatterlist *sg;
2038 /* prime dma-buf support */
2039 void *dma_buf_vmapping;
2042 /** Breadcrumb of last rendering to the buffer.
2043 * There can only be one writer, but we allow for multiple readers.
2044 * If there is a writer that necessarily implies that all other
2045 * read requests are complete - but we may only be lazily clearing
2046 * the read requests. A read request is naturally the most recent
2047 * request on a ring, so we may have two different write and read
2048 * requests on one ring where the write request is older than the
2049 * read request. This allows for the CPU to read from an active
2050 * buffer by only waiting for the write to complete.
2052 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2053 struct drm_i915_gem_request *last_write_req;
2054 /** Breadcrumb of last fenced GPU access to the buffer. */
2055 struct drm_i915_gem_request *last_fenced_req;
2057 /** Current tiling stride for the object, if it's tiled. */
2060 /** References from framebuffers, locks out tiling changes. */
2061 unsigned long framebuffer_references;
2063 /** Record of address bit 17 of each page at last unbind. */
2064 unsigned long *bit_17;
2067 /** for phy allocated objects */
2068 struct drm_dma_handle *phys_handle;
2070 struct i915_gem_userptr {
2072 unsigned read_only :1;
2073 unsigned workers :4;
2074 #define I915_GEM_USERPTR_MAX_WORKERS 15
2076 struct i915_mm_struct *mm;
2077 struct i915_mmu_object *mmu_object;
2078 struct work_struct *work;
2082 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2084 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2085 struct drm_i915_gem_object *new,
2086 unsigned frontbuffer_bits);
2089 * Request queue structure.
2091 * The request queue allows us to note sequence numbers that have been emitted
2092 * and may be associated with active buffers to be retired.
2094 * By keeping this list, we can avoid having to do questionable sequence
2095 * number comparisons on buffer last_read|write_seqno. It also allows an
2096 * emission time to be associated with the request for tracking how far ahead
2097 * of the GPU the submission is.
2099 * The requests are reference counted, so upon creation they should have an
2100 * initial reference taken using kref_init
2102 struct drm_i915_gem_request {
2105 /** On Which ring this request was generated */
2106 struct drm_i915_private *i915;
2107 struct intel_engine_cs *ring;
2109 /** GEM sequence number associated with this request. */
2112 /** Position in the ringbuffer of the start of the request */
2116 * Position in the ringbuffer of the start of the postfix.
2117 * This is required to calculate the maximum available ringbuffer
2118 * space without overwriting the postfix.
2122 /** Position in the ringbuffer of the end of the whole request */
2126 * Context and ring buffer related to this request
2127 * Contexts are refcounted, so when this request is associated with a
2128 * context, we must increment the context's refcount, to guarantee that
2129 * it persists while any request is linked to it. Requests themselves
2130 * are also refcounted, so the request will only be freed when the last
2131 * reference to it is dismissed, and the code in
2132 * i915_gem_request_free() will then decrement the refcount on the
2135 struct intel_context *ctx;
2136 struct intel_ringbuffer *ringbuf;
2138 /** Batch buffer related to this request if any */
2139 struct drm_i915_gem_object *batch_obj;
2141 /** Time at which this request was emitted, in jiffies. */
2142 unsigned long emitted_jiffies;
2144 /** global list entry for this request */
2145 struct list_head list;
2147 struct drm_i915_file_private *file_priv;
2148 /** file_priv list entry for this request */
2149 struct list_head client_list;
2151 /** process identifier submitting this request */
2155 * The ELSP only accepts two elements at a time, so we queue
2156 * context/tail pairs on a given queue (ring->execlist_queue) until the
2157 * hardware is available. The queue serves a double purpose: we also use
2158 * it to keep track of the up to 2 contexts currently in the hardware
2159 * (usually one in execution and the other queued up by the GPU): We
2160 * only remove elements from the head of the queue when the hardware
2161 * informs us that an element has been completed.
2163 * All accesses to the queue are mediated by a spinlock
2164 * (ring->execlist_lock).
2167 /** Execlist link in the submission queue.*/
2168 struct list_head execlist_link;
2170 /** Execlists no. of times this request has been sent to the ELSP */
2175 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2176 struct intel_context *ctx);
2177 void i915_gem_request_free(struct kref *req_ref);
2179 static inline uint32_t
2180 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2182 return req ? req->seqno : 0;
2185 static inline struct intel_engine_cs *
2186 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2188 return req ? req->ring : NULL;
2191 static inline struct drm_i915_gem_request *
2192 i915_gem_request_reference(struct drm_i915_gem_request *req)
2195 kref_get(&req->ref);
2200 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2202 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2203 kref_put(&req->ref, i915_gem_request_free);
2207 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2209 struct drm_device *dev;
2214 dev = req->ring->dev;
2215 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2216 mutex_unlock(&dev->struct_mutex);
2219 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2220 struct drm_i915_gem_request *src)
2223 i915_gem_request_reference(src);
2226 i915_gem_request_unreference(*pdst);
2232 * XXX: i915_gem_request_completed should be here but currently needs the
2233 * definition of i915_seqno_passed() which is below. It will be moved in
2234 * a later patch when the call to i915_seqno_passed() is obsoleted...
2238 * A command that requires special handling by the command parser.
2240 struct drm_i915_cmd_descriptor {
2242 * Flags describing how the command parser processes the command.
2244 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2245 * a length mask if not set
2246 * CMD_DESC_SKIP: The command is allowed but does not follow the
2247 * standard length encoding for the opcode range in
2249 * CMD_DESC_REJECT: The command is never allowed
2250 * CMD_DESC_REGISTER: The command should be checked against the
2251 * register whitelist for the appropriate ring
2252 * CMD_DESC_MASTER: The command is allowed if the submitting process
2256 #define CMD_DESC_FIXED (1<<0)
2257 #define CMD_DESC_SKIP (1<<1)
2258 #define CMD_DESC_REJECT (1<<2)
2259 #define CMD_DESC_REGISTER (1<<3)
2260 #define CMD_DESC_BITMASK (1<<4)
2261 #define CMD_DESC_MASTER (1<<5)
2264 * The command's unique identification bits and the bitmask to get them.
2265 * This isn't strictly the opcode field as defined in the spec and may
2266 * also include type, subtype, and/or subop fields.
2274 * The command's length. The command is either fixed length (i.e. does
2275 * not include a length field) or has a length field mask. The flag
2276 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2277 * a length mask. All command entries in a command table must include
2278 * length information.
2286 * Describes where to find a register address in the command to check
2287 * against the ring's register whitelist. Only valid if flags has the
2288 * CMD_DESC_REGISTER bit set.
2295 #define MAX_CMD_DESC_BITMASKS 3
2297 * Describes command checks where a particular dword is masked and
2298 * compared against an expected value. If the command does not match
2299 * the expected value, the parser rejects it. Only valid if flags has
2300 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2303 * If the check specifies a non-zero condition_mask then the parser
2304 * only performs the check when the bits specified by condition_mask
2311 u32 condition_offset;
2313 } bits[MAX_CMD_DESC_BITMASKS];
2317 * A table of commands requiring special handling by the command parser.
2319 * Each ring has an array of tables. Each table consists of an array of command
2320 * descriptors, which must be sorted with command opcodes in ascending order.
2322 struct drm_i915_cmd_table {
2323 const struct drm_i915_cmd_descriptor *table;
2327 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2328 #define __I915__(p) ({ \
2329 struct drm_i915_private *__p; \
2330 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2331 __p = (struct drm_i915_private *)p; \
2332 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2333 __p = to_i915((struct drm_device *)p); \
2338 #define INTEL_INFO(p) (&__I915__(p)->info)
2339 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2340 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2342 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2343 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2344 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2345 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2346 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2347 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2348 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2349 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2350 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2351 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2352 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2353 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2354 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2355 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2356 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2357 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2358 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2359 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2360 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2361 INTEL_DEVID(dev) == 0x0152 || \
2362 INTEL_DEVID(dev) == 0x015a)
2363 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2364 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2365 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2366 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2367 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2368 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2369 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2370 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2371 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2372 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2373 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2374 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2375 (INTEL_DEVID(dev) & 0xf) == 0xe))
2376 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2377 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2378 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2379 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2380 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2381 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2382 /* ULX machines are also considered ULT. */
2383 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2384 INTEL_DEVID(dev) == 0x0A1E)
2385 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2387 #define SKL_REVID_A0 (0x0)
2388 #define SKL_REVID_B0 (0x1)
2389 #define SKL_REVID_C0 (0x2)
2390 #define SKL_REVID_D0 (0x3)
2391 #define SKL_REVID_E0 (0x4)
2392 #define SKL_REVID_F0 (0x5)
2394 #define BXT_REVID_A0 (0x0)
2395 #define BXT_REVID_B0 (0x3)
2396 #define BXT_REVID_C0 (0x6)
2399 * The genX designation typically refers to the render engine, so render
2400 * capability related checks should use IS_GEN, while display and other checks
2401 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2404 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2405 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2406 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2407 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2408 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2409 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2410 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2411 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2413 #define RENDER_RING (1<<RCS)
2414 #define BSD_RING (1<<VCS)
2415 #define BLT_RING (1<<BCS)
2416 #define VEBOX_RING (1<<VECS)
2417 #define BSD2_RING (1<<VCS2)
2418 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2419 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2420 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2421 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2422 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2423 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2424 __I915__(dev)->ellc_size)
2425 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2427 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2428 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2429 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2430 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2432 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2433 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2435 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2436 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2438 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2439 * even when in MSI mode. This results in spurious interrupt warnings if the
2440 * legacy irq no. is shared with another device. The kernel then disables that
2441 * interrupt source and so prevents the other device from working properly.
2443 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2444 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2446 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2447 * rows, which changed the alignment requirements and fence programming.
2449 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2451 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2452 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2453 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2454 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2455 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2457 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2458 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2459 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2461 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2463 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2464 INTEL_INFO(dev)->gen >= 9)
2466 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2467 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2468 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2469 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2471 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2472 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2474 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2475 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2477 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2479 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2480 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2481 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2482 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2483 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2484 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2485 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2486 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2488 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2489 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2490 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2491 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2492 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2493 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2494 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2496 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2498 /* DPF == dynamic parity feature */
2499 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2500 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2502 #define GT_FREQUENCY_MULTIPLIER 50
2503 #define GEN9_FREQ_SCALER 3
2505 #include "i915_trace.h"
2507 extern const struct drm_ioctl_desc i915_ioctls[];
2508 extern int i915_max_ioctl;
2510 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2511 extern int i915_resume_legacy(struct drm_device *dev);
2514 struct i915_params {
2516 int panel_ignore_lid;
2518 unsigned int lvds_downclock;
2519 int lvds_channel_mode;
2521 int vbt_sdvo_panel_type;
2525 int enable_execlists;
2527 unsigned int preliminary_hw_support;
2528 int disable_power_well;
2530 int invert_brightness;
2531 int enable_cmd_parser;
2532 /* leave bools at the end to not create holes */
2533 bool enable_hangcheck;
2535 bool prefault_disable;
2536 bool load_detect_test;
2538 bool disable_display;
2539 bool disable_vtd_wa;
2542 bool verbose_state_checks;
2543 bool nuclear_pageflip;
2546 extern struct i915_params i915 __read_mostly;
2549 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2550 extern int i915_driver_unload(struct drm_device *);
2551 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2552 extern void i915_driver_lastclose(struct drm_device * dev);
2553 extern void i915_driver_preclose(struct drm_device *dev,
2554 struct drm_file *file);
2555 extern void i915_driver_postclose(struct drm_device *dev,
2556 struct drm_file *file);
2557 extern int i915_driver_device_is_agp(struct drm_device * dev);
2558 #ifdef CONFIG_COMPAT
2559 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2562 extern int intel_gpu_reset(struct drm_device *dev);
2563 extern int i915_reset(struct drm_device *dev);
2564 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2565 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2566 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2567 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2568 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2569 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2570 void i915_firmware_load_error_print(const char *fw_path, int err);
2573 void i915_queue_hangcheck(struct drm_device *dev);
2575 void i915_handle_error(struct drm_device *dev, bool wedged,
2576 const char *fmt, ...);
2578 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2579 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2580 int intel_irq_install(struct drm_i915_private *dev_priv);
2581 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2583 extern void intel_uncore_sanitize(struct drm_device *dev);
2584 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2585 bool restore_forcewake);
2586 extern void intel_uncore_init(struct drm_device *dev);
2587 extern void intel_uncore_check_errors(struct drm_device *dev);
2588 extern void intel_uncore_fini(struct drm_device *dev);
2589 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2590 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2591 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2592 enum forcewake_domains domains);
2593 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2594 enum forcewake_domains domains);
2595 /* Like above but the caller must manage the uncore.lock itself.
2596 * Must be used with I915_READ_FW and friends.
2598 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2599 enum forcewake_domains domains);
2600 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2601 enum forcewake_domains domains);
2602 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2603 static inline bool intel_vgpu_active(struct drm_device *dev)
2605 return to_i915(dev)->vgpu.active;
2609 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2613 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2616 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2617 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2619 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2621 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2622 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2623 uint32_t interrupt_mask,
2624 uint32_t enabled_irq_mask);
2625 #define ibx_enable_display_interrupt(dev_priv, bits) \
2626 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2627 #define ibx_disable_display_interrupt(dev_priv, bits) \
2628 ibx_display_interrupt_update((dev_priv), (bits), 0)
2631 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2632 struct drm_file *file_priv);
2633 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2634 struct drm_file *file_priv);
2635 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2636 struct drm_file *file_priv);
2637 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2638 struct drm_file *file_priv);
2639 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2640 struct drm_file *file_priv);
2641 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2642 struct drm_file *file_priv);
2643 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2644 struct drm_file *file_priv);
2645 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2646 struct intel_engine_cs *ring);
2647 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2648 struct drm_file *file,
2649 struct intel_engine_cs *ring,
2650 struct drm_i915_gem_object *obj);
2651 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2652 struct drm_file *file,
2653 struct intel_engine_cs *ring,
2654 struct intel_context *ctx,
2655 struct drm_i915_gem_execbuffer2 *args,
2656 struct list_head *vmas,
2657 struct drm_i915_gem_object *batch_obj,
2658 u64 exec_start, u32 flags);
2659 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2660 struct drm_file *file_priv);
2661 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2662 struct drm_file *file_priv);
2663 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2664 struct drm_file *file_priv);
2665 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2666 struct drm_file *file);
2667 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2668 struct drm_file *file);
2669 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2670 struct drm_file *file_priv);
2671 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2672 struct drm_file *file_priv);
2673 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2674 struct drm_file *file_priv);
2675 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2676 struct drm_file *file_priv);
2677 int i915_gem_init_userptr(struct drm_device *dev);
2678 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2679 struct drm_file *file);
2680 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2681 struct drm_file *file_priv);
2682 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2683 struct drm_file *file_priv);
2684 void i915_gem_load(struct drm_device *dev);
2685 void *i915_gem_object_alloc(struct drm_device *dev);
2686 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2687 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2688 const struct drm_i915_gem_object_ops *ops);
2689 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2691 void i915_init_vm(struct drm_i915_private *dev_priv,
2692 struct i915_address_space *vm);
2693 void i915_gem_free_object(struct drm_gem_object *obj);
2694 void i915_gem_vma_destroy(struct i915_vma *vma);
2696 /* Flags used by pin/bind&friends. */
2697 #define PIN_MAPPABLE (1<<0)
2698 #define PIN_NONBLOCK (1<<1)
2699 #define PIN_GLOBAL (1<<2)
2700 #define PIN_OFFSET_BIAS (1<<3)
2701 #define PIN_USER (1<<4)
2702 #define PIN_UPDATE (1<<5)
2703 #define PIN_OFFSET_MASK (~4095)
2705 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2706 struct i915_address_space *vm,
2710 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2711 const struct i915_ggtt_view *view,
2715 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2717 int __must_check i915_vma_unbind(struct i915_vma *vma);
2718 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2719 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2720 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2722 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2723 int *needs_clflush);
2725 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2727 static inline int __sg_page_count(struct scatterlist *sg)
2729 return sg->length >> PAGE_SHIFT;
2732 static inline struct page *
2733 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2735 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2738 if (n < obj->get_page.last) {
2739 obj->get_page.sg = obj->pages->sgl;
2740 obj->get_page.last = 0;
2743 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2744 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2745 if (unlikely(sg_is_chain(obj->get_page.sg)))
2746 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2749 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2752 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2754 BUG_ON(obj->pages == NULL);
2755 obj->pages_pin_count++;
2757 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2759 BUG_ON(obj->pages_pin_count == 0);
2760 obj->pages_pin_count--;
2763 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2764 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2765 struct intel_engine_cs *to);
2766 void i915_vma_move_to_active(struct i915_vma *vma,
2767 struct intel_engine_cs *ring);
2768 int i915_gem_dumb_create(struct drm_file *file_priv,
2769 struct drm_device *dev,
2770 struct drm_mode_create_dumb *args);
2771 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2772 uint32_t handle, uint64_t *offset);
2774 * Returns true if seq1 is later than seq2.
2777 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2779 return (int32_t)(seq1 - seq2) >= 0;
2782 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2783 bool lazy_coherency)
2787 BUG_ON(req == NULL);
2789 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2791 return i915_seqno_passed(seqno, req->seqno);
2794 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2795 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2796 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2797 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2799 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2800 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2802 struct drm_i915_gem_request *
2803 i915_gem_find_active_request(struct intel_engine_cs *ring);
2805 bool i915_gem_retire_requests(struct drm_device *dev);
2806 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2807 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2808 bool interruptible);
2809 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2811 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2813 return unlikely(atomic_read(&error->reset_counter)
2814 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2817 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2819 return atomic_read(&error->reset_counter) & I915_WEDGED;
2822 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2824 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2827 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2829 return dev_priv->gpu_error.stop_rings == 0 ||
2830 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2833 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2835 return dev_priv->gpu_error.stop_rings == 0 ||
2836 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2839 void i915_gem_reset(struct drm_device *dev);
2840 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2841 int __must_check i915_gem_init(struct drm_device *dev);
2842 int i915_gem_init_rings(struct drm_device *dev);
2843 int __must_check i915_gem_init_hw(struct drm_device *dev);
2844 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2845 void i915_gem_init_swizzling(struct drm_device *dev);
2846 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2847 int __must_check i915_gpu_idle(struct drm_device *dev);
2848 int __must_check i915_gem_suspend(struct drm_device *dev);
2849 int __i915_add_request(struct intel_engine_cs *ring,
2850 struct drm_file *file,
2851 struct drm_i915_gem_object *batch_obj);
2852 #define i915_add_request(ring) \
2853 __i915_add_request(ring, NULL, NULL)
2854 int __i915_wait_request(struct drm_i915_gem_request *req,
2855 unsigned reset_counter,
2858 struct drm_i915_file_private *file_priv);
2859 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2860 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2862 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2865 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2868 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2870 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2872 struct intel_engine_cs *pipelined,
2873 const struct i915_ggtt_view *view);
2874 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2875 const struct i915_ggtt_view *view);
2876 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2878 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2879 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2882 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2884 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2885 int tiling_mode, bool fenced);
2887 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2888 enum i915_cache_level cache_level);
2890 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2891 struct dma_buf *dma_buf);
2893 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2894 struct drm_gem_object *gem_obj, int flags);
2896 void i915_gem_restore_fences(struct drm_device *dev);
2899 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2900 const struct i915_ggtt_view *view);
2902 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2903 struct i915_address_space *vm);
2904 static inline unsigned long
2905 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2907 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2910 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2911 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2912 const struct i915_ggtt_view *view);
2913 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2914 struct i915_address_space *vm);
2916 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2917 struct i915_address_space *vm);
2919 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2920 struct i915_address_space *vm);
2922 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2923 const struct i915_ggtt_view *view);
2926 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2927 struct i915_address_space *vm);
2929 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2930 const struct i915_ggtt_view *view);
2932 static inline struct i915_vma *
2933 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2935 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2937 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2939 /* Some GGTT VM helpers */
2940 #define i915_obj_to_ggtt(obj) \
2941 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2942 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2944 struct i915_address_space *ggtt =
2945 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2949 static inline struct i915_hw_ppgtt *
2950 i915_vm_to_ppgtt(struct i915_address_space *vm)
2952 WARN_ON(i915_is_ggtt(vm));
2954 return container_of(vm, struct i915_hw_ppgtt, base);
2958 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2960 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2963 static inline unsigned long
2964 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2966 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2969 static inline int __must_check
2970 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2974 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2975 alignment, flags | PIN_GLOBAL);
2979 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2981 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2984 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
2985 const struct i915_ggtt_view *view);
2987 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
2989 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
2992 /* i915_gem_context.c */
2993 int __must_check i915_gem_context_init(struct drm_device *dev);
2994 void i915_gem_context_fini(struct drm_device *dev);
2995 void i915_gem_context_reset(struct drm_device *dev);
2996 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2997 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2998 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2999 int i915_switch_context(struct intel_engine_cs *ring,
3000 struct intel_context *to);
3001 struct intel_context *
3002 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3003 void i915_gem_context_free(struct kref *ctx_ref);
3004 struct drm_i915_gem_object *
3005 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3006 static inline void i915_gem_context_reference(struct intel_context *ctx)
3008 kref_get(&ctx->ref);
3011 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3013 kref_put(&ctx->ref, i915_gem_context_free);
3016 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3018 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3021 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3022 struct drm_file *file);
3023 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3024 struct drm_file *file);
3025 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3026 struct drm_file *file_priv);
3027 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3028 struct drm_file *file_priv);
3030 /* i915_gem_evict.c */
3031 int __must_check i915_gem_evict_something(struct drm_device *dev,
3032 struct i915_address_space *vm,
3035 unsigned cache_level,
3036 unsigned long start,
3039 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3040 int i915_gem_evict_everything(struct drm_device *dev);
3042 /* belongs in i915_gem_gtt.h */
3043 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3045 if (INTEL_INFO(dev)->gen < 6)
3046 intel_gtt_chipset_flush();
3049 /* i915_gem_stolen.c */
3050 int i915_gem_init_stolen(struct drm_device *dev);
3051 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
3052 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
3053 void i915_gem_cleanup_stolen(struct drm_device *dev);
3054 struct drm_i915_gem_object *
3055 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3056 struct drm_i915_gem_object *
3057 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3062 /* i915_gem_shrinker.c */
3063 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3066 #define I915_SHRINK_PURGEABLE 0x1
3067 #define I915_SHRINK_UNBOUND 0x2
3068 #define I915_SHRINK_BOUND 0x4
3069 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3070 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3073 /* i915_gem_tiling.c */
3074 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3076 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3078 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3079 obj->tiling_mode != I915_TILING_NONE;
3082 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3083 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3084 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3086 /* i915_gem_debug.c */
3088 int i915_verify_lists(struct drm_device *dev);
3090 #define i915_verify_lists(dev) 0
3093 /* i915_debugfs.c */
3094 int i915_debugfs_init(struct drm_minor *minor);
3095 void i915_debugfs_cleanup(struct drm_minor *minor);
3096 #ifdef CONFIG_DEBUG_FS
3097 int i915_debugfs_connector_add(struct drm_connector *connector);
3098 void intel_display_crc_init(struct drm_device *dev);
3100 static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
3101 static inline void intel_display_crc_init(struct drm_device *dev) {}
3104 /* i915_gpu_error.c */
3106 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3107 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3108 const struct i915_error_state_file_priv *error);
3109 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3110 struct drm_i915_private *i915,
3111 size_t count, loff_t pos);
3112 static inline void i915_error_state_buf_release(
3113 struct drm_i915_error_state_buf *eb)
3117 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3118 const char *error_msg);
3119 void i915_error_state_get(struct drm_device *dev,
3120 struct i915_error_state_file_priv *error_priv);
3121 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3122 void i915_destroy_error_state(struct drm_device *dev);
3124 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3125 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3127 /* i915_cmd_parser.c */
3128 int i915_cmd_parser_get_version(void);
3129 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3130 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3131 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3132 int i915_parse_cmds(struct intel_engine_cs *ring,
3133 struct drm_i915_gem_object *batch_obj,
3134 struct drm_i915_gem_object *shadow_batch_obj,
3135 u32 batch_start_offset,
3139 /* i915_suspend.c */
3140 extern int i915_save_state(struct drm_device *dev);
3141 extern int i915_restore_state(struct drm_device *dev);
3144 void i915_setup_sysfs(struct drm_device *dev_priv);
3145 void i915_teardown_sysfs(struct drm_device *dev_priv);
3148 extern int intel_setup_gmbus(struct drm_device *dev);
3149 extern void intel_teardown_gmbus(struct drm_device *dev);
3150 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3153 extern struct i2c_adapter *
3154 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3155 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3156 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3157 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3159 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3161 extern void intel_i2c_reset(struct drm_device *dev);
3163 /* intel_opregion.c */
3165 extern int intel_opregion_setup(struct drm_device *dev);
3166 extern void intel_opregion_init(struct drm_device *dev);
3167 extern void intel_opregion_fini(struct drm_device *dev);
3168 extern void intel_opregion_asle_intr(struct drm_device *dev);
3169 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3171 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3174 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3175 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3176 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3177 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3179 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3184 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3192 extern void intel_register_dsm_handler(void);
3193 extern void intel_unregister_dsm_handler(void);
3195 static inline void intel_register_dsm_handler(void) { return; }
3196 static inline void intel_unregister_dsm_handler(void) { return; }
3197 #endif /* CONFIG_ACPI */
3200 extern void intel_modeset_init_hw(struct drm_device *dev);
3201 extern void intel_modeset_init(struct drm_device *dev);
3202 extern void intel_modeset_gem_init(struct drm_device *dev);
3203 extern void intel_modeset_cleanup(struct drm_device *dev);
3204 extern void intel_connector_unregister(struct intel_connector *);
3205 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3206 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3207 bool force_restore);
3208 extern void i915_redisable_vga(struct drm_device *dev);
3209 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3210 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3211 extern void intel_init_pch_refclk(struct drm_device *dev);
3212 extern void intel_set_rps(struct drm_device *dev, u8 val);
3213 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3215 extern void intel_detect_pch(struct drm_device *dev);
3216 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3217 extern int intel_enable_rc6(const struct drm_device *dev);
3219 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3220 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3221 struct drm_file *file);
3222 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3223 struct drm_file *file);
3226 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3227 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3228 struct intel_overlay_error_state *error);
3230 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3231 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3232 struct drm_device *dev,
3233 struct intel_display_error_state *error);
3235 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3236 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3238 /* intel_sideband.c */
3239 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3240 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3241 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3242 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3243 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3244 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3245 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3246 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3247 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3248 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3249 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3250 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3251 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3252 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3253 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3254 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3255 enum intel_sbi_destination destination);
3256 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3257 enum intel_sbi_destination destination);
3258 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3259 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3261 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3262 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3264 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3265 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3267 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3268 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3269 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3270 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3272 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3273 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3274 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3275 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3277 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3278 * will be implemented using 2 32-bit writes in an arbitrary order with
3279 * an arbitrary delay between them. This can cause the hardware to
3280 * act upon the intermediate value, possibly leading to corruption and
3281 * machine death. You have been warned.
3283 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3284 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3286 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3287 u32 upper = I915_READ(upper_reg); \
3288 u32 lower = I915_READ(lower_reg); \
3289 u32 tmp = I915_READ(upper_reg); \
3290 if (upper != tmp) { \
3292 lower = I915_READ(lower_reg); \
3293 WARN_ON(I915_READ(upper_reg) != upper); \
3295 (u64)upper << 32 | lower; })
3297 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3298 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3300 /* These are untraced mmio-accessors that are only valid to be used inside
3301 * criticial sections inside IRQ handlers where forcewake is explicitly
3303 * Think twice, and think again, before using these.
3304 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3305 * intel_uncore_forcewake_irqunlock().
3307 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3308 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3309 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3311 /* "Broadcast RGB" property */
3312 #define INTEL_BROADCAST_RGB_AUTO 0
3313 #define INTEL_BROADCAST_RGB_FULL 1
3314 #define INTEL_BROADCAST_RGB_LIMITED 2
3316 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3318 if (IS_VALLEYVIEW(dev))
3319 return VLV_VGACNTRL;
3320 else if (INTEL_INFO(dev)->gen >= 5)
3321 return CPU_VGACNTRL;
3326 static inline void __user *to_user_ptr(u64 address)
3328 return (void __user *)(uintptr_t)address;
3331 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3333 unsigned long j = msecs_to_jiffies(m);
3335 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3338 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3340 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3343 static inline unsigned long
3344 timespec_to_jiffies_timeout(const struct timespec *value)
3346 unsigned long j = timespec_to_jiffies(value);
3348 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3352 * If you need to wait X milliseconds between events A and B, but event B
3353 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3354 * when event A happened, then just before event B you call this function and
3355 * pass the timestamp as the first argument, and X as the second argument.
3358 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3360 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3363 * Don't re-read the value of "jiffies" every time since it may change
3364 * behind our back and break the math.
3366 tmp_jiffies = jiffies;
3367 target_jiffies = timestamp_jiffies +
3368 msecs_to_jiffies_timeout(to_wait_ms);
3370 if (time_after(target_jiffies, tmp_jiffies)) {
3371 remaining_jiffies = target_jiffies - tmp_jiffies;
3372 while (remaining_jiffies)
3374 schedule_timeout_uninterruptible(remaining_jiffies);
3378 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3379 struct drm_i915_gem_request *req)
3381 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3382 i915_gem_request_assign(&ring->trace_irq_req, req);