1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
65 #include "intel_gvt.h"
67 /* General customization:
70 #define DRIVER_NAME "i915"
71 #define DRIVER_DESC "Intel Graphics"
72 #define DRIVER_DATE "20160620"
75 /* Many gcc seem to no see through this and fall over :( */
77 #define WARN_ON(x) ({ \
78 bool __i915_warn_cond = (x); \
79 if (__builtin_constant_p(__i915_warn_cond)) \
80 BUILD_BUG_ON(__i915_warn_cond); \
81 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
83 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
87 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
89 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
90 (long) (x), __func__);
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915.verbose_state_checks, format)) \
104 unlikely(__ret_warn_on); \
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110 bool __i915_inject_load_failure(const char *func, int line);
111 #define i915_inject_load_failure() \
112 __i915_inject_load_failure(__func__, __LINE__)
114 static inline const char *yesno(bool v)
116 return v ? "yes" : "no";
119 static inline const char *onoff(bool v)
121 return v ? "on" : "off";
130 I915_MAX_PIPES = _PIPE_EDP
132 #define pipe_name(p) ((p) + 'A')
144 static inline const char *transcoder_name(enum transcoder transcoder)
146 switch (transcoder) {
155 case TRANSCODER_DSI_A:
157 case TRANSCODER_DSI_C:
164 static inline bool transcoder_is_dsi(enum transcoder transcoder)
166 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
170 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
171 * number of planes per CRTC. Not all platforms really have this many planes,
172 * which means some arrays of size I915_MAX_PLANES may have unused entries
173 * between the topmost sprite plane and the cursor plane.
182 #define plane_name(p) ((p) + 'A')
184 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
194 #define port_name(p) ((p) + 'A')
196 #define I915_NUM_PHYS_VLV 2
208 enum intel_display_power_domain {
212 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
213 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
214 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
215 POWER_DOMAIN_TRANSCODER_A,
216 POWER_DOMAIN_TRANSCODER_B,
217 POWER_DOMAIN_TRANSCODER_C,
218 POWER_DOMAIN_TRANSCODER_EDP,
219 POWER_DOMAIN_TRANSCODER_DSI_A,
220 POWER_DOMAIN_TRANSCODER_DSI_C,
221 POWER_DOMAIN_PORT_DDI_A_LANES,
222 POWER_DOMAIN_PORT_DDI_B_LANES,
223 POWER_DOMAIN_PORT_DDI_C_LANES,
224 POWER_DOMAIN_PORT_DDI_D_LANES,
225 POWER_DOMAIN_PORT_DDI_E_LANES,
226 POWER_DOMAIN_PORT_DSI,
227 POWER_DOMAIN_PORT_CRT,
228 POWER_DOMAIN_PORT_OTHER,
237 POWER_DOMAIN_MODESET,
243 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
244 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
245 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
246 #define POWER_DOMAIN_TRANSCODER(tran) \
247 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
248 (tran) + POWER_DOMAIN_TRANSCODER_A)
252 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
264 #define for_each_hpd_pin(__pin) \
265 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
267 struct i915_hotplug {
268 struct work_struct hotplug_work;
271 unsigned long last_jiffies;
276 HPD_MARK_DISABLED = 2
278 } stats[HPD_NUM_PINS];
280 struct delayed_work reenable_work;
282 struct intel_digital_port *irq_port[I915_MAX_PORTS];
285 struct work_struct dig_port_work;
288 * if we get a HPD irq from DP and a HPD irq from non-DP
289 * the non-DP HPD could block the workqueue on a mode config
290 * mutex getting, that userspace may have taken. However
291 * userspace is waiting on the DP workqueue to run which is
292 * blocked behind the non-DP one.
294 struct workqueue_struct *dp_wq;
297 #define I915_GEM_GPU_DOMAINS \
298 (I915_GEM_DOMAIN_RENDER | \
299 I915_GEM_DOMAIN_SAMPLER | \
300 I915_GEM_DOMAIN_COMMAND | \
301 I915_GEM_DOMAIN_INSTRUCTION | \
302 I915_GEM_DOMAIN_VERTEX)
304 #define for_each_pipe(__dev_priv, __p) \
305 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
306 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
307 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
308 for_each_if ((__mask) & (1 << (__p)))
309 #define for_each_plane(__dev_priv, __pipe, __p) \
311 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
313 #define for_each_sprite(__dev_priv, __p, __s) \
315 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
318 #define for_each_port_masked(__port, __ports_mask) \
319 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
320 for_each_if ((__ports_mask) & (1 << (__port)))
322 #define for_each_crtc(dev, crtc) \
323 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
325 #define for_each_intel_plane(dev, intel_plane) \
326 list_for_each_entry(intel_plane, \
327 &dev->mode_config.plane_list, \
330 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
331 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, \
333 for_each_if ((plane_mask) & \
334 (1 << drm_plane_index(&intel_plane->base)))
336 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
337 list_for_each_entry(intel_plane, \
338 &(dev)->mode_config.plane_list, \
340 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
342 #define for_each_intel_crtc(dev, intel_crtc) \
343 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
345 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
346 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) \
347 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
349 #define for_each_intel_encoder(dev, intel_encoder) \
350 list_for_each_entry(intel_encoder, \
351 &(dev)->mode_config.encoder_list, \
354 #define for_each_intel_connector(dev, intel_connector) \
355 list_for_each_entry(intel_connector, \
356 &dev->mode_config.connector_list, \
359 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
360 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
361 for_each_if ((intel_encoder)->base.crtc == (__crtc))
363 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
364 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
365 for_each_if ((intel_connector)->base.encoder == (__encoder))
367 #define for_each_power_domain(domain, mask) \
368 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
369 for_each_if ((1 << (domain)) & (mask))
371 struct drm_i915_private;
372 struct i915_mm_struct;
373 struct i915_mmu_object;
375 struct drm_i915_file_private {
376 struct drm_i915_private *dev_priv;
377 struct drm_file *file;
381 struct list_head request_list;
382 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
383 * chosen to prevent the CPU getting more than a frame ahead of the GPU
384 * (when using lax throttling for the frontbuffer). We also use it to
385 * offer free GPU waitboosts for severely congested workloads.
387 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
389 struct idr context_idr;
391 struct intel_rps_client {
392 struct list_head link;
396 unsigned int bsd_ring;
399 /* Used by dp and fdi links */
400 struct intel_link_m_n {
408 void intel_link_compute_m_n(int bpp, int nlanes,
409 int pixel_clock, int link_clock,
410 struct intel_link_m_n *m_n);
412 /* Interface history:
415 * 1.2: Add Power Management
416 * 1.3: Add vblank support
417 * 1.4: Fix cmdbuffer path, add heap destroy
418 * 1.5: Add vblank pipe configuration
419 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
420 * - Support vertical blank on secondary display pipe
422 #define DRIVER_MAJOR 1
423 #define DRIVER_MINOR 6
424 #define DRIVER_PATCHLEVEL 0
426 #define WATCH_LISTS 0
428 struct opregion_header;
429 struct opregion_acpi;
430 struct opregion_swsci;
431 struct opregion_asle;
433 struct intel_opregion {
434 struct opregion_header *header;
435 struct opregion_acpi *acpi;
436 struct opregion_swsci *swsci;
437 u32 swsci_gbda_sub_functions;
438 u32 swsci_sbcb_sub_functions;
439 struct opregion_asle *asle;
444 struct work_struct asle_work;
446 #define OPREGION_SIZE (8*1024)
448 struct intel_overlay;
449 struct intel_overlay_error_state;
451 #define I915_FENCE_REG_NONE -1
452 #define I915_MAX_NUM_FENCES 32
453 /* 32 fences + sign bit for FENCE_REG_NONE */
454 #define I915_MAX_NUM_FENCE_BITS 6
456 struct drm_i915_fence_reg {
457 struct list_head lru_list;
458 struct drm_i915_gem_object *obj;
462 struct sdvo_device_mapping {
471 struct intel_display_error_state;
473 struct drm_i915_error_state {
482 /* Generic register state */
490 u32 error; /* gen6+ */
491 u32 err_int; /* gen7 */
492 u32 fault_data0; /* gen8, gen9 */
493 u32 fault_data1; /* gen8, gen9 */
499 u32 extra_instdone[I915_NUM_INSTDONE_REG];
500 u64 fence[I915_MAX_NUM_FENCES];
501 struct intel_overlay_error_state *overlay;
502 struct intel_display_error_state *display;
503 struct drm_i915_error_object *semaphore_obj;
505 struct drm_i915_error_ring {
507 /* Software tracked state */
510 enum intel_ring_hangcheck_action hangcheck_action;
513 /* our own tracking of ring head and tail */
518 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
537 u32 rc_psmi; /* sleep state */
538 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
540 struct drm_i915_error_object {
544 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
546 struct drm_i915_error_object *wa_ctx;
548 struct drm_i915_error_request {
563 char comm[TASK_COMM_LEN];
564 } ring[I915_NUM_ENGINES];
566 struct drm_i915_error_buffer {
569 u32 rseqno[I915_NUM_ENGINES], wseqno;
573 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
581 } **active_bo, **pinned_bo;
583 u32 *active_bo_count, *pinned_bo_count;
587 struct intel_connector;
588 struct intel_encoder;
589 struct intel_crtc_state;
590 struct intel_initial_plane_config;
595 struct drm_i915_display_funcs {
596 int (*get_display_clock_speed)(struct drm_device *dev);
597 int (*get_fifo_size)(struct drm_device *dev, int plane);
598 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
599 int (*compute_intermediate_wm)(struct drm_device *dev,
600 struct intel_crtc *intel_crtc,
601 struct intel_crtc_state *newstate);
602 void (*initial_watermarks)(struct intel_crtc_state *cstate);
603 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
604 int (*compute_global_watermarks)(struct drm_atomic_state *state);
605 void (*update_wm)(struct drm_crtc *crtc);
606 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
607 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
608 /* Returns the active state of the crtc, and if the crtc is active,
609 * fills out the pipe-config with the hw state. */
610 bool (*get_pipe_config)(struct intel_crtc *,
611 struct intel_crtc_state *);
612 void (*get_initial_plane_config)(struct intel_crtc *,
613 struct intel_initial_plane_config *);
614 int (*crtc_compute_clock)(struct intel_crtc *crtc,
615 struct intel_crtc_state *crtc_state);
616 void (*crtc_enable)(struct drm_crtc *crtc);
617 void (*crtc_disable)(struct drm_crtc *crtc);
618 void (*audio_codec_enable)(struct drm_connector *connector,
619 struct intel_encoder *encoder,
620 const struct drm_display_mode *adjusted_mode);
621 void (*audio_codec_disable)(struct intel_encoder *encoder);
622 void (*fdi_link_train)(struct drm_crtc *crtc);
623 void (*init_clock_gating)(struct drm_device *dev);
624 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
625 struct drm_framebuffer *fb,
626 struct drm_i915_gem_object *obj,
627 struct drm_i915_gem_request *req,
629 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
630 /* clock updates for mode set */
632 /* render clock increase/decrease */
633 /* display clock increase/decrease */
634 /* pll clock increase/decrease */
636 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
637 void (*load_luts)(struct drm_crtc_state *crtc_state);
640 enum forcewake_domain_id {
641 FW_DOMAIN_ID_RENDER = 0,
642 FW_DOMAIN_ID_BLITTER,
648 enum forcewake_domains {
649 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
650 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
651 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
652 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
657 #define FW_REG_READ (1)
658 #define FW_REG_WRITE (2)
660 enum forcewake_domains
661 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
662 i915_reg_t reg, unsigned int op);
664 struct intel_uncore_funcs {
665 void (*force_wake_get)(struct drm_i915_private *dev_priv,
666 enum forcewake_domains domains);
667 void (*force_wake_put)(struct drm_i915_private *dev_priv,
668 enum forcewake_domains domains);
670 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
671 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
672 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
673 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
675 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
676 uint8_t val, bool trace);
677 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
678 uint16_t val, bool trace);
679 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
680 uint32_t val, bool trace);
681 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
682 uint64_t val, bool trace);
685 struct intel_uncore {
686 spinlock_t lock; /** lock is also taken in irq contexts. */
688 struct intel_uncore_funcs funcs;
691 enum forcewake_domains fw_domains;
693 struct intel_uncore_forcewake_domain {
694 struct drm_i915_private *i915;
695 enum forcewake_domain_id id;
696 enum forcewake_domains mask;
698 struct hrtimer timer;
705 } fw_domain[FW_DOMAIN_ID_COUNT];
707 int unclaimed_mmio_check;
710 /* Iterate over initialised fw domains */
711 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
712 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
713 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
715 for_each_if ((mask__) & (domain__)->mask)
717 #define for_each_fw_domain(domain__, dev_priv__) \
718 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
720 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
721 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
722 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
725 struct work_struct work;
727 uint32_t *dmc_payload;
728 uint32_t dmc_fw_size;
731 i915_reg_t mmioaddr[8];
732 uint32_t mmiodata[8];
734 uint32_t allowed_dc_mask;
737 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
738 func(is_mobile) sep \
741 func(is_i945gm) sep \
743 func(need_gfx_hws) sep \
745 func(is_pineview) sep \
746 func(is_broadwater) sep \
747 func(is_crestline) sep \
748 func(is_ivybridge) sep \
749 func(is_valleyview) sep \
750 func(is_cherryview) sep \
751 func(is_haswell) sep \
752 func(is_broadwell) sep \
753 func(is_skylake) sep \
754 func(is_broxton) sep \
755 func(is_kabylake) sep \
756 func(is_preliminary) sep \
758 func(has_pipe_cxsr) sep \
759 func(has_hotplug) sep \
760 func(cursor_needs_physical) sep \
761 func(has_overlay) sep \
762 func(overlay_needs_physical) sep \
763 func(supports_tv) sep \
765 func(has_snoop) sep \
767 func(has_fpga_dbg) sep \
770 #define DEFINE_FLAG(name) u8 name:1
771 #define SEP_SEMICOLON ;
773 struct intel_device_info {
774 u32 display_mmio_offset;
777 u8 num_sprites[I915_MAX_PIPES];
780 u8 ring_mask; /* Rings supported by the HW */
781 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
782 /* Register offsets for the various display pipes and transcoders */
783 int pipe_offsets[I915_MAX_TRANSCODERS];
784 int trans_offsets[I915_MAX_TRANSCODERS];
785 int palette_offsets[I915_MAX_PIPES];
786 int cursor_offsets[I915_MAX_PIPES];
788 /* Slice/subslice/EU info */
791 u8 subslice_per_slice;
795 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
798 u8 has_subslice_pg:1;
802 u16 degamma_lut_size;
810 enum i915_cache_level {
812 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
813 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
814 caches, eg sampler/render caches, and the
815 large Last-Level-Cache. LLC is coherent with
816 the CPU, but L3 is only visible to the GPU. */
817 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
820 struct i915_ctx_hang_stats {
821 /* This context had batch pending when hang was declared */
822 unsigned batch_pending;
824 /* This context had batch active when hang was declared */
825 unsigned batch_active;
827 /* Time when this context was last blamed for a GPU reset */
828 unsigned long guilty_ts;
830 /* If the contexts causes a second GPU hang within this time,
831 * it is permanently banned from submitting any more work.
833 unsigned long ban_period_seconds;
835 /* This context is banned to submit more work */
839 /* This must match up with the value previously used for execbuf2.rsvd1. */
840 #define DEFAULT_CONTEXT_HANDLE 0
843 * struct i915_gem_context - as the name implies, represents a context.
844 * @ref: reference count.
845 * @user_handle: userspace tracking identity for this context.
846 * @remap_slice: l3 row remapping information.
847 * @flags: context specific flags:
848 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
849 * @file_priv: filp associated with this context (NULL for global default
851 * @hang_stats: information about the role of this context in possible GPU
853 * @ppgtt: virtual memory space used by this context.
854 * @legacy_hw_ctx: render context backing object and whether it is correctly
855 * initialized (legacy ring submission mechanism only).
856 * @link: link in the global list of contexts.
858 * Contexts are memory images used by the hardware to store copies of their
861 struct i915_gem_context {
863 struct drm_i915_private *i915;
864 struct drm_i915_file_private *file_priv;
865 struct i915_hw_ppgtt *ppgtt;
867 struct i915_ctx_hang_stats hang_stats;
869 /* Unique identifier for this context, used by the hw for tracking */
873 #define CONTEXT_NO_ZEROMAP (1<<0)
875 struct intel_context {
876 struct drm_i915_gem_object *state;
877 struct intel_ringbuffer *ringbuf;
878 struct i915_vma *lrc_vma;
879 uint32_t *lrc_reg_state;
883 } engine[I915_NUM_ENGINES];
886 struct atomic_notifier_head status_notifier;
887 bool execlists_force_single_submission;
889 struct list_head link;
903 /* This is always the inner lock when overlapping with struct_mutex and
904 * it's the outer lock when overlapping with stolen_lock. */
907 unsigned int possible_framebuffer_bits;
908 unsigned int busy_bits;
909 unsigned int visible_pipes_mask;
910 struct intel_crtc *crtc;
912 struct drm_mm_node compressed_fb;
913 struct drm_mm_node *compressed_llb;
920 struct intel_fbc_state_cache {
922 unsigned int mode_flags;
923 uint32_t hsw_bdw_pixel_rate;
927 unsigned int rotation;
935 uint32_t pixel_format;
938 unsigned int tiling_mode;
942 struct intel_fbc_reg_params {
946 unsigned int fence_y_offset;
951 uint32_t pixel_format;
959 struct intel_fbc_work {
961 u32 scheduled_vblank;
962 struct work_struct work;
965 const char *no_fbc_reason;
969 * HIGH_RR is the highest eDP panel refresh rate read from EDID
970 * LOW_RR is the lowest eDP panel refresh rate found from EDID
971 * parsing for same resolution.
973 enum drrs_refresh_rate_type {
976 DRRS_MAX_RR, /* RR count */
979 enum drrs_support_type {
980 DRRS_NOT_SUPPORTED = 0,
981 STATIC_DRRS_SUPPORT = 1,
982 SEAMLESS_DRRS_SUPPORT = 2
988 struct delayed_work work;
990 unsigned busy_frontbuffer_bits;
991 enum drrs_refresh_rate_type refresh_rate_type;
992 enum drrs_support_type type;
999 struct intel_dp *enabled;
1001 struct delayed_work work;
1002 unsigned busy_frontbuffer_bits;
1004 bool aux_frame_sync;
1009 PCH_NONE = 0, /* No PCH present */
1010 PCH_IBX, /* Ibexpeak PCH */
1011 PCH_CPT, /* Cougarpoint PCH */
1012 PCH_LPT, /* Lynxpoint PCH */
1013 PCH_SPT, /* Sunrisepoint PCH */
1017 enum intel_sbi_destination {
1022 #define QUIRK_PIPEA_FORCE (1<<0)
1023 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1024 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1025 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1026 #define QUIRK_PIPEB_FORCE (1<<4)
1027 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1030 struct intel_fbc_work;
1032 struct intel_gmbus {
1033 struct i2c_adapter adapter;
1034 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1037 i915_reg_t gpio_reg;
1038 struct i2c_algo_bit_data bit_algo;
1039 struct drm_i915_private *dev_priv;
1042 struct i915_suspend_saved_registers {
1045 u32 savePP_ON_DELAYS;
1046 u32 savePP_OFF_DELAYS;
1051 u32 saveFBC_CONTROL;
1052 u32 saveCACHE_MODE_0;
1053 u32 saveMI_ARB_STATE;
1057 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1058 u32 savePCH_PORT_HOTPLUG;
1062 struct vlv_s0ix_state {
1069 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1070 u32 media_max_req_count;
1071 u32 gfx_max_req_count;
1097 u32 rp_down_timeout;
1103 /* Display 1 CZ domain */
1108 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1110 /* GT SA CZ domain */
1117 /* Display 2 CZ domain */
1121 u32 clock_gate_dis2;
1124 struct intel_rps_ei {
1130 struct intel_gen6_power_mgmt {
1132 * work, interrupts_enabled and pm_iir are protected by
1133 * dev_priv->irq_lock
1135 struct work_struct work;
1136 bool interrupts_enabled;
1141 /* Frequencies are stored in potentially platform dependent multiples.
1142 * In other words, *_freq needs to be multiplied by X to be interesting.
1143 * Soft limits are those which are used for the dynamic reclocking done
1144 * by the driver (raise frequencies under heavy loads, and lower for
1145 * lighter loads). Hard limits are those imposed by the hardware.
1147 * A distinction is made for overclocking, which is never enabled by
1148 * default, and is considered to be above the hard limit if it's
1151 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1152 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1153 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1154 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1155 u8 min_freq; /* AKA RPn. Minimum frequency */
1156 u8 idle_freq; /* Frequency to request when we are idle */
1157 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1158 u8 rp1_freq; /* "less than" RP0 power/freqency */
1159 u8 rp0_freq; /* Non-overclocked max frequency. */
1160 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1162 u8 up_threshold; /* Current %busy required to uplock */
1163 u8 down_threshold; /* Current %busy required to downclock */
1166 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1168 spinlock_t client_lock;
1169 struct list_head clients;
1173 struct delayed_work delayed_resume_work;
1176 struct intel_rps_client semaphores, mmioflips;
1178 /* manual wa residency calculations */
1179 struct intel_rps_ei up_ei, down_ei;
1182 * Protects RPS/RC6 register access and PCU communication.
1183 * Must be taken after struct_mutex if nested. Note that
1184 * this lock may be held for long periods of time when
1185 * talking to hw - so only take it when talking to hw!
1187 struct mutex hw_lock;
1190 /* defined intel_pm.c */
1191 extern spinlock_t mchdev_lock;
1193 struct intel_ilk_power_mgmt {
1201 unsigned long last_time1;
1202 unsigned long chipset_power;
1205 unsigned long gfx_power;
1212 struct drm_i915_private;
1213 struct i915_power_well;
1215 struct i915_power_well_ops {
1217 * Synchronize the well's hw state to match the current sw state, for
1218 * example enable/disable it based on the current refcount. Called
1219 * during driver init and resume time, possibly after first calling
1220 * the enable/disable handlers.
1222 void (*sync_hw)(struct drm_i915_private *dev_priv,
1223 struct i915_power_well *power_well);
1225 * Enable the well and resources that depend on it (for example
1226 * interrupts located on the well). Called after the 0->1 refcount
1229 void (*enable)(struct drm_i915_private *dev_priv,
1230 struct i915_power_well *power_well);
1232 * Disable the well and resources that depend on it. Called after
1233 * the 1->0 refcount transition.
1235 void (*disable)(struct drm_i915_private *dev_priv,
1236 struct i915_power_well *power_well);
1237 /* Returns the hw enabled state. */
1238 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1239 struct i915_power_well *power_well);
1242 /* Power well structure for haswell */
1243 struct i915_power_well {
1246 /* power well enable/disable usage count */
1248 /* cached hw enabled state */
1250 unsigned long domains;
1252 const struct i915_power_well_ops *ops;
1255 struct i915_power_domains {
1257 * Power wells needed for initialization at driver init and suspend
1258 * time are on. They are kept on until after the first modeset.
1262 int power_well_count;
1265 int domain_use_count[POWER_DOMAIN_NUM];
1266 struct i915_power_well *power_wells;
1269 #define MAX_L3_SLICES 2
1270 struct intel_l3_parity {
1271 u32 *remap_info[MAX_L3_SLICES];
1272 struct work_struct error_work;
1276 struct i915_gem_mm {
1277 /** Memory allocator for GTT stolen memory */
1278 struct drm_mm stolen;
1279 /** Protects the usage of the GTT stolen memory allocator. This is
1280 * always the inner lock when overlapping with struct_mutex. */
1281 struct mutex stolen_lock;
1283 /** List of all objects in gtt_space. Used to restore gtt
1284 * mappings on resume */
1285 struct list_head bound_list;
1287 * List of objects which are not bound to the GTT (thus
1288 * are idle and not used by the GPU) but still have
1289 * (presumably uncached) pages still attached.
1291 struct list_head unbound_list;
1293 /** Usable portion of the GTT for GEM */
1294 unsigned long stolen_base; /* limited to low memory (32-bit) */
1296 /** PPGTT used for aliasing the PPGTT with the GTT */
1297 struct i915_hw_ppgtt *aliasing_ppgtt;
1299 struct notifier_block oom_notifier;
1300 struct notifier_block vmap_notifier;
1301 struct shrinker shrinker;
1302 bool shrinker_no_lock_stealing;
1304 /** LRU list of objects with fence regs on them. */
1305 struct list_head fence_list;
1308 * We leave the user IRQ off as much as possible,
1309 * but this means that requests will finish and never
1310 * be retired once the system goes idle. Set a timer to
1311 * fire periodically while the ring is running. When it
1312 * fires, go retire requests.
1314 struct delayed_work retire_work;
1317 * When we detect an idle GPU, we want to turn on
1318 * powersaving features. So once we see that there
1319 * are no more requests outstanding and no more
1320 * arrive within a small period of time, we fire
1321 * off the idle_work.
1323 struct delayed_work idle_work;
1326 * Are we in a non-interruptible section of code like
1332 * Is the GPU currently considered idle, or busy executing userspace
1333 * requests? Whilst idle, we attempt to power down the hardware and
1334 * display clocks. In order to reduce the effect on performance, there
1335 * is a slight delay before we do so.
1339 /* the indicator for dispatch video commands on two BSD rings */
1340 unsigned int bsd_ring_dispatch_index;
1342 /** Bit 6 swizzling required for X tiling */
1343 uint32_t bit_6_swizzle_x;
1344 /** Bit 6 swizzling required for Y tiling */
1345 uint32_t bit_6_swizzle_y;
1347 /* accounting, useful for userland debugging */
1348 spinlock_t object_stat_lock;
1349 size_t object_memory;
1353 struct drm_i915_error_state_buf {
1354 struct drm_i915_private *i915;
1363 struct i915_error_state_file_priv {
1364 struct drm_device *dev;
1365 struct drm_i915_error_state *error;
1368 struct i915_gpu_error {
1369 /* For hangcheck timer */
1370 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1371 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1372 /* Hang gpu twice in this window and your context gets banned */
1373 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1375 struct workqueue_struct *hangcheck_wq;
1376 struct delayed_work hangcheck_work;
1378 /* For reset and error_state handling. */
1380 /* Protected by the above dev->gpu_error.lock. */
1381 struct drm_i915_error_state *first_error;
1383 unsigned long missed_irq_rings;
1386 * State variable controlling the reset flow and count
1388 * This is a counter which gets incremented when reset is triggered,
1389 * and again when reset has been handled. So odd values (lowest bit set)
1390 * means that reset is in progress and even values that
1391 * (reset_counter >> 1):th reset was successfully completed.
1393 * If reset is not completed succesfully, the I915_WEDGE bit is
1394 * set meaning that hardware is terminally sour and there is no
1395 * recovery. All waiters on the reset_queue will be woken when
1398 * This counter is used by the wait_seqno code to notice that reset
1399 * event happened and it needs to restart the entire ioctl (since most
1400 * likely the seqno it waited for won't ever signal anytime soon).
1402 * This is important for lock-free wait paths, where no contended lock
1403 * naturally enforces the correct ordering between the bail-out of the
1404 * waiter and the gpu reset work code.
1406 atomic_t reset_counter;
1408 #define I915_RESET_IN_PROGRESS_FLAG 1
1409 #define I915_WEDGED (1 << 31)
1412 * Waitqueue to signal when the reset has completed. Used by clients
1413 * that wait for dev_priv->mm.wedged to settle.
1415 wait_queue_head_t reset_queue;
1417 /* Userspace knobs for gpu hang simulation;
1418 * combines both a ring mask, and extra flags
1421 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1422 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1424 /* For missed irq/seqno simulation. */
1425 unsigned int test_irq_rings;
1428 enum modeset_restore {
1429 MODESET_ON_LID_OPEN,
1434 #define DP_AUX_A 0x40
1435 #define DP_AUX_B 0x10
1436 #define DP_AUX_C 0x20
1437 #define DP_AUX_D 0x30
1439 #define DDC_PIN_B 0x05
1440 #define DDC_PIN_C 0x04
1441 #define DDC_PIN_D 0x06
1443 struct ddi_vbt_port_info {
1445 * This is an index in the HDMI/DVI DDI buffer translation table.
1446 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1447 * populate this field.
1449 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1450 uint8_t hdmi_level_shift;
1452 uint8_t supports_dvi:1;
1453 uint8_t supports_hdmi:1;
1454 uint8_t supports_dp:1;
1456 uint8_t alternate_aux_channel;
1457 uint8_t alternate_ddc_pin;
1459 uint8_t dp_boost_level;
1460 uint8_t hdmi_boost_level;
1463 enum psr_lines_to_wait {
1464 PSR_0_LINES_TO_WAIT = 0,
1466 PSR_4_LINES_TO_WAIT,
1470 struct intel_vbt_data {
1471 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1472 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1475 unsigned int int_tv_support:1;
1476 unsigned int lvds_dither:1;
1477 unsigned int lvds_vbt:1;
1478 unsigned int int_crt_support:1;
1479 unsigned int lvds_use_ssc:1;
1480 unsigned int display_clock_mode:1;
1481 unsigned int fdi_rx_polarity_inverted:1;
1482 unsigned int panel_type:4;
1484 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1486 enum drrs_support_type drrs_type;
1497 struct edp_power_seq pps;
1502 bool require_aux_wakeup;
1504 enum psr_lines_to_wait lines_to_wait;
1505 int tp1_wakeup_time;
1506 int tp2_tp3_wakeup_time;
1512 bool active_low_pwm;
1513 u8 min_brightness; /* min_brightness/255 of max */
1514 enum intel_backlight_type type;
1520 struct mipi_config *config;
1521 struct mipi_pps_data *pps;
1525 const u8 *sequence[MIPI_SEQ_MAX];
1531 union child_device_config *child_dev;
1533 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1534 struct sdvo_device_mapping sdvo_mappings[2];
1537 enum intel_ddb_partitioning {
1539 INTEL_DDB_PART_5_6, /* IVB+ */
1542 struct intel_wm_level {
1550 struct ilk_wm_values {
1551 uint32_t wm_pipe[3];
1553 uint32_t wm_lp_spr[3];
1554 uint32_t wm_linetime[3];
1556 enum intel_ddb_partitioning partitioning;
1559 struct vlv_pipe_wm {
1570 struct vlv_wm_values {
1571 struct vlv_pipe_wm pipe[3];
1572 struct vlv_sr_wm sr;
1582 struct skl_ddb_entry {
1583 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1586 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1588 return entry->end - entry->start;
1591 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1592 const struct skl_ddb_entry *e2)
1594 if (e1->start == e2->start && e1->end == e2->end)
1600 struct skl_ddb_allocation {
1601 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1602 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1603 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1606 struct skl_wm_values {
1607 unsigned dirty_pipes;
1608 struct skl_ddb_allocation ddb;
1609 uint32_t wm_linetime[I915_MAX_PIPES];
1610 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1611 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1614 struct skl_wm_level {
1615 bool plane_en[I915_MAX_PLANES];
1616 uint16_t plane_res_b[I915_MAX_PLANES];
1617 uint8_t plane_res_l[I915_MAX_PLANES];
1621 * This struct helps tracking the state needed for runtime PM, which puts the
1622 * device in PCI D3 state. Notice that when this happens, nothing on the
1623 * graphics device works, even register access, so we don't get interrupts nor
1626 * Every piece of our code that needs to actually touch the hardware needs to
1627 * either call intel_runtime_pm_get or call intel_display_power_get with the
1628 * appropriate power domain.
1630 * Our driver uses the autosuspend delay feature, which means we'll only really
1631 * suspend if we stay with zero refcount for a certain amount of time. The
1632 * default value is currently very conservative (see intel_runtime_pm_enable), but
1633 * it can be changed with the standard runtime PM files from sysfs.
1635 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1636 * goes back to false exactly before we reenable the IRQs. We use this variable
1637 * to check if someone is trying to enable/disable IRQs while they're supposed
1638 * to be disabled. This shouldn't happen and we'll print some error messages in
1641 * For more, read the Documentation/power/runtime_pm.txt.
1643 struct i915_runtime_pm {
1644 atomic_t wakeref_count;
1645 atomic_t atomic_seq;
1650 enum intel_pipe_crc_source {
1651 INTEL_PIPE_CRC_SOURCE_NONE,
1652 INTEL_PIPE_CRC_SOURCE_PLANE1,
1653 INTEL_PIPE_CRC_SOURCE_PLANE2,
1654 INTEL_PIPE_CRC_SOURCE_PF,
1655 INTEL_PIPE_CRC_SOURCE_PIPE,
1656 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1657 INTEL_PIPE_CRC_SOURCE_TV,
1658 INTEL_PIPE_CRC_SOURCE_DP_B,
1659 INTEL_PIPE_CRC_SOURCE_DP_C,
1660 INTEL_PIPE_CRC_SOURCE_DP_D,
1661 INTEL_PIPE_CRC_SOURCE_AUTO,
1662 INTEL_PIPE_CRC_SOURCE_MAX,
1665 struct intel_pipe_crc_entry {
1670 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1671 struct intel_pipe_crc {
1673 bool opened; /* exclusive access to the result file */
1674 struct intel_pipe_crc_entry *entries;
1675 enum intel_pipe_crc_source source;
1677 wait_queue_head_t wq;
1680 struct i915_frontbuffer_tracking {
1684 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1691 struct i915_wa_reg {
1694 /* bitmask representing WA bits */
1699 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1700 * allowing it for RCS as we don't foresee any requirement of having
1701 * a whitelist for other engines. When it is really required for
1702 * other engines then the limit need to be increased.
1704 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1706 struct i915_workarounds {
1707 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1709 u32 hw_whitelist_count[I915_NUM_ENGINES];
1712 struct i915_virtual_gpu {
1716 struct i915_execbuffer_params {
1717 struct drm_device *dev;
1718 struct drm_file *file;
1719 uint32_t dispatch_flags;
1720 uint32_t args_batch_start_offset;
1721 uint64_t batch_obj_vm_offset;
1722 struct intel_engine_cs *engine;
1723 struct drm_i915_gem_object *batch_obj;
1724 struct i915_gem_context *ctx;
1725 struct drm_i915_gem_request *request;
1728 /* used in computing the new watermarks state */
1729 struct intel_wm_config {
1730 unsigned int num_pipes_active;
1731 bool sprites_enabled;
1732 bool sprites_scaled;
1735 struct drm_i915_private {
1736 struct drm_device *dev;
1737 struct kmem_cache *objects;
1738 struct kmem_cache *vmas;
1739 struct kmem_cache *requests;
1741 const struct intel_device_info info;
1743 int relative_constants_mode;
1747 struct intel_uncore uncore;
1749 struct i915_virtual_gpu vgpu;
1751 struct intel_gvt gvt;
1753 struct intel_guc guc;
1755 struct intel_csr csr;
1757 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1759 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1760 * controller on different i2c buses. */
1761 struct mutex gmbus_mutex;
1764 * Base address of the gmbus and gpio block.
1766 uint32_t gpio_mmio_base;
1768 /* MMIO base address for MIPI regs */
1769 uint32_t mipi_mmio_base;
1771 uint32_t psr_mmio_base;
1773 wait_queue_head_t gmbus_wait_queue;
1775 struct pci_dev *bridge_dev;
1776 struct i915_gem_context *kernel_context;
1777 struct intel_engine_cs engine[I915_NUM_ENGINES];
1778 struct drm_i915_gem_object *semaphore_obj;
1779 uint32_t last_seqno, next_seqno;
1781 struct drm_dma_handle *status_page_dmah;
1782 struct resource mch_res;
1784 /* protects the irq masks */
1785 spinlock_t irq_lock;
1787 /* protects the mmio flip data */
1788 spinlock_t mmio_flip_lock;
1790 bool display_irqs_enabled;
1792 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1793 struct pm_qos_request pm_qos;
1795 /* Sideband mailbox protection */
1796 struct mutex sb_lock;
1798 /** Cached value of IMR to avoid reads in updating the bitfield */
1801 u32 de_irq_mask[I915_MAX_PIPES];
1806 u32 pipestat_irq_mask[I915_MAX_PIPES];
1808 struct i915_hotplug hotplug;
1809 struct intel_fbc fbc;
1810 struct i915_drrs drrs;
1811 struct intel_opregion opregion;
1812 struct intel_vbt_data vbt;
1814 bool preserve_bios_swizzle;
1817 struct intel_overlay *overlay;
1819 /* backlight registers and fields in struct intel_panel */
1820 struct mutex backlight_lock;
1823 bool no_aux_handshake;
1825 /* protects panel power sequencer state */
1826 struct mutex pps_mutex;
1828 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1829 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1831 unsigned int fsb_freq, mem_freq, is_ddr3;
1832 unsigned int skl_preferred_vco_freq;
1833 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1834 unsigned int max_dotclk_freq;
1835 unsigned int rawclk_freq;
1836 unsigned int hpll_freq;
1837 unsigned int czclk_freq;
1840 unsigned int vco, ref;
1844 * wq - Driver workqueue for GEM.
1846 * NOTE: Work items scheduled here are not allowed to grab any modeset
1847 * locks, for otherwise the flushing done in the pageflip code will
1848 * result in deadlocks.
1850 struct workqueue_struct *wq;
1852 /* Display functions */
1853 struct drm_i915_display_funcs display;
1855 /* PCH chipset type */
1856 enum intel_pch pch_type;
1857 unsigned short pch_id;
1859 unsigned long quirks;
1861 enum modeset_restore modeset_restore;
1862 struct mutex modeset_restore_lock;
1863 struct drm_atomic_state *modeset_restore_state;
1865 struct list_head vm_list; /* Global list of all address spaces */
1866 struct i915_ggtt ggtt; /* VM representing the global address space */
1868 struct i915_gem_mm mm;
1869 DECLARE_HASHTABLE(mm_structs, 7);
1870 struct mutex mm_lock;
1872 /* The hw wants to have a stable context identifier for the lifetime
1873 * of the context (for OA, PASID, faults, etc). This is limited
1874 * in execlists to 21 bits.
1876 struct ida context_hw_ida;
1877 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1879 /* Kernel Modesetting */
1881 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1882 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1883 wait_queue_head_t pending_flip_queue;
1885 #ifdef CONFIG_DEBUG_FS
1886 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1889 /* dpll and cdclk state is protected by connection_mutex */
1890 int num_shared_dpll;
1891 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1892 const struct intel_dpll_mgr *dpll_mgr;
1895 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1896 * Must be global rather than per dpll, because on some platforms
1897 * plls share registers.
1899 struct mutex dpll_lock;
1901 unsigned int active_crtcs;
1902 unsigned int min_pixclk[I915_MAX_PIPES];
1904 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1906 struct i915_workarounds workarounds;
1908 struct i915_frontbuffer_tracking fb_tracking;
1912 bool mchbar_need_disable;
1914 struct intel_l3_parity l3_parity;
1916 /* Cannot be determined by PCIID. You must always read a register. */
1919 /* gen6+ rps state */
1920 struct intel_gen6_power_mgmt rps;
1922 /* ilk-only ips/rps state. Everything in here is protected by the global
1923 * mchdev_lock in intel_pm.c */
1924 struct intel_ilk_power_mgmt ips;
1926 struct i915_power_domains power_domains;
1928 struct i915_psr psr;
1930 struct i915_gpu_error gpu_error;
1932 struct drm_i915_gem_object *vlv_pctx;
1934 #ifdef CONFIG_DRM_FBDEV_EMULATION
1935 /* list of fbdev register on this device */
1936 struct intel_fbdev *fbdev;
1937 struct work_struct fbdev_suspend_work;
1940 struct drm_property *broadcast_rgb_property;
1941 struct drm_property *force_audio_property;
1943 /* hda/i915 audio component */
1944 struct i915_audio_component *audio_component;
1945 bool audio_component_registered;
1947 * av_mutex - mutex for audio/video sync
1950 struct mutex av_mutex;
1952 uint32_t hw_context_size;
1953 struct list_head context_list;
1957 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1958 u32 chv_phy_control;
1960 * Shadows for CHV DPLL_MD regs to keep the state
1961 * checker somewhat working in the presence hardware
1962 * crappiness (can't read out DPLL_MD for pipes B & C).
1964 u32 chv_dpll_md[I915_MAX_PIPES];
1968 bool suspended_to_idle;
1969 struct i915_suspend_saved_registers regfile;
1970 struct vlv_s0ix_state vlv_s0ix_state;
1974 * Raw watermark latency values:
1975 * in 0.1us units for WM0,
1976 * in 0.5us units for WM1+.
1979 uint16_t pri_latency[5];
1981 uint16_t spr_latency[5];
1983 uint16_t cur_latency[5];
1985 * Raw watermark memory latency values
1986 * for SKL for all 8 levels
1989 uint16_t skl_latency[8];
1992 * The skl_wm_values structure is a bit too big for stack
1993 * allocation, so we keep the staging struct where we store
1994 * intermediate results here instead.
1996 struct skl_wm_values skl_results;
1998 /* current hardware state */
2000 struct ilk_wm_values hw;
2001 struct skl_wm_values skl_hw;
2002 struct vlv_wm_values vlv;
2008 * Should be held around atomic WM register writing; also
2009 * protects * intel_crtc->wm.active and
2010 * cstate->wm.need_postvbl_update.
2012 struct mutex wm_mutex;
2015 * Set during HW readout of watermarks/DDB. Some platforms
2016 * need to know when we're still using BIOS-provided values
2017 * (which we don't fully trust).
2019 bool distrust_bios_wm;
2022 struct i915_runtime_pm pm;
2024 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2026 int (*execbuf_submit)(struct i915_execbuffer_params *params,
2027 struct drm_i915_gem_execbuffer2 *args,
2028 struct list_head *vmas);
2029 int (*init_engines)(struct drm_device *dev);
2030 void (*cleanup_engine)(struct intel_engine_cs *engine);
2031 void (*stop_engine)(struct intel_engine_cs *engine);
2034 /* perform PHY state sanity checks? */
2035 bool chv_phy_assert[2];
2037 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2040 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2041 * will be rejected. Instead look for a better place.
2045 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2047 return dev->dev_private;
2050 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2052 return to_i915(dev_get_drvdata(dev));
2055 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2057 return container_of(guc, struct drm_i915_private, guc);
2060 /* Simple iterator over all initialised engines */
2061 #define for_each_engine(engine__, dev_priv__) \
2062 for ((engine__) = &(dev_priv__)->engine[0]; \
2063 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2065 for_each_if (intel_engine_initialized(engine__))
2067 /* Iterator with engine_id */
2068 #define for_each_engine_id(engine__, dev_priv__, id__) \
2069 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2070 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2072 for_each_if (((id__) = (engine__)->id, \
2073 intel_engine_initialized(engine__)))
2075 /* Iterator over subset of engines selected by mask */
2076 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2077 for ((engine__) = &(dev_priv__)->engine[0]; \
2078 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2080 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2081 intel_engine_initialized(engine__))
2083 enum hdmi_force_audio {
2084 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2085 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2086 HDMI_AUDIO_AUTO, /* trust EDID */
2087 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2090 #define I915_GTT_OFFSET_NONE ((u32)-1)
2092 struct drm_i915_gem_object_ops {
2094 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2096 /* Interface between the GEM object and its backing storage.
2097 * get_pages() is called once prior to the use of the associated set
2098 * of pages before to binding them into the GTT, and put_pages() is
2099 * called after we no longer need them. As we expect there to be
2100 * associated cost with migrating pages between the backing storage
2101 * and making them available for the GPU (e.g. clflush), we may hold
2102 * onto the pages after they are no longer referenced by the GPU
2103 * in case they may be used again shortly (for example migrating the
2104 * pages to a different memory domain within the GTT). put_pages()
2105 * will therefore most likely be called when the object itself is
2106 * being released or under memory pressure (where we attempt to
2107 * reap pages for the shrinker).
2109 int (*get_pages)(struct drm_i915_gem_object *);
2110 void (*put_pages)(struct drm_i915_gem_object *);
2112 int (*dmabuf_export)(struct drm_i915_gem_object *);
2113 void (*release)(struct drm_i915_gem_object *);
2117 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2118 * considered to be the frontbuffer for the given plane interface-wise. This
2119 * doesn't mean that the hw necessarily already scans it out, but that any
2120 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2122 * We have one bit per pipe and per scanout plane type.
2124 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2125 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2126 #define INTEL_FRONTBUFFER_BITS \
2127 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2128 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2129 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2130 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2131 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2132 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2133 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2134 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2135 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2136 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2137 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2139 struct drm_i915_gem_object {
2140 struct drm_gem_object base;
2142 const struct drm_i915_gem_object_ops *ops;
2144 /** List of VMAs backed by this object */
2145 struct list_head vma_list;
2147 /** Stolen memory for this object, instead of being backed by shmem. */
2148 struct drm_mm_node *stolen;
2149 struct list_head global_list;
2151 struct list_head engine_list[I915_NUM_ENGINES];
2152 /** Used in execbuf to temporarily hold a ref */
2153 struct list_head obj_exec_link;
2155 struct list_head batch_pool_link;
2158 * This is set if the object is on the active lists (has pending
2159 * rendering and so a non-zero seqno), and is not set if it i s on
2160 * inactive (ready to be unbound) list.
2162 unsigned int active:I915_NUM_ENGINES;
2165 * This is set if the object has been written to since last bound
2168 unsigned int dirty:1;
2171 * Fence register bits (if any) for this object. Will be set
2172 * as needed when mapped into the GTT.
2173 * Protected by dev->struct_mutex.
2175 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2178 * Advice: are the backing pages purgeable?
2180 unsigned int madv:2;
2183 * Current tiling mode for the object.
2185 unsigned int tiling_mode:2;
2187 * Whether the tiling parameters for the currently associated fence
2188 * register have changed. Note that for the purposes of tracking
2189 * tiling changes we also treat the unfenced register, the register
2190 * slot that the object occupies whilst it executes a fenced
2191 * command (such as BLT on gen2/3), as a "fence".
2193 unsigned int fence_dirty:1;
2196 * Is the object at the current location in the gtt mappable and
2197 * fenceable? Used to avoid costly recalculations.
2199 unsigned int map_and_fenceable:1;
2202 * Whether the current gtt mapping needs to be mappable (and isn't just
2203 * mappable by accident). Track pin and fault separate for a more
2204 * accurate mappable working set.
2206 unsigned int fault_mappable:1;
2209 * Is the object to be mapped as read-only to the GPU
2210 * Only honoured if hardware has relevant pte bit
2212 unsigned long gt_ro:1;
2213 unsigned int cache_level:3;
2214 unsigned int cache_dirty:1;
2216 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2218 unsigned int has_wc_mmap;
2219 unsigned int pin_display;
2221 struct sg_table *pages;
2222 int pages_pin_count;
2224 struct scatterlist *sg;
2229 /** Breadcrumb of last rendering to the buffer.
2230 * There can only be one writer, but we allow for multiple readers.
2231 * If there is a writer that necessarily implies that all other
2232 * read requests are complete - but we may only be lazily clearing
2233 * the read requests. A read request is naturally the most recent
2234 * request on a ring, so we may have two different write and read
2235 * requests on one ring where the write request is older than the
2236 * read request. This allows for the CPU to read from an active
2237 * buffer by only waiting for the write to complete.
2239 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2240 struct drm_i915_gem_request *last_write_req;
2241 /** Breadcrumb of last fenced GPU access to the buffer. */
2242 struct drm_i915_gem_request *last_fenced_req;
2244 /** Current tiling stride for the object, if it's tiled. */
2247 /** References from framebuffers, locks out tiling changes. */
2248 unsigned long framebuffer_references;
2250 /** Record of address bit 17 of each page at last unbind. */
2251 unsigned long *bit_17;
2254 /** for phy allocated objects */
2255 struct drm_dma_handle *phys_handle;
2257 struct i915_gem_userptr {
2259 unsigned read_only :1;
2260 unsigned workers :4;
2261 #define I915_GEM_USERPTR_MAX_WORKERS 15
2263 struct i915_mm_struct *mm;
2264 struct i915_mmu_object *mmu_object;
2265 struct work_struct *work;
2269 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2272 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2274 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2278 * Optimised SGL iterator for GEM objects
2280 static __always_inline struct sgt_iter {
2281 struct scatterlist *sgp;
2288 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2289 struct sgt_iter s = { .sgp = sgl };
2292 s.max = s.curr = s.sgp->offset;
2293 s.max += s.sgp->length;
2295 s.dma = sg_dma_address(s.sgp);
2297 s.pfn = page_to_pfn(sg_page(s.sgp));
2304 * __sg_next - return the next scatterlist entry in a list
2305 * @sg: The current sg entry
2308 * If the entry is the last, return NULL; otherwise, step to the next
2309 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2310 * otherwise just return the pointer to the current element.
2312 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2314 #ifdef CONFIG_DEBUG_SG
2315 BUG_ON(sg->sg_magic != SG_MAGIC);
2317 return sg_is_last(sg) ? NULL :
2318 likely(!sg_is_chain(++sg)) ? sg :
2323 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2324 * @__dmap: DMA address (output)
2325 * @__iter: 'struct sgt_iter' (iterator state, internal)
2326 * @__sgt: sg_table to iterate over (input)
2328 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2329 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2330 ((__dmap) = (__iter).dma + (__iter).curr); \
2331 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2332 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2335 * for_each_sgt_page - iterate over the pages of the given sg_table
2336 * @__pp: page pointer (output)
2337 * @__iter: 'struct sgt_iter' (iterator state, internal)
2338 * @__sgt: sg_table to iterate over (input)
2340 #define for_each_sgt_page(__pp, __iter, __sgt) \
2341 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2342 ((__pp) = (__iter).pfn == 0 ? NULL : \
2343 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2344 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2345 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2348 * Request queue structure.
2350 * The request queue allows us to note sequence numbers that have been emitted
2351 * and may be associated with active buffers to be retired.
2353 * By keeping this list, we can avoid having to do questionable sequence
2354 * number comparisons on buffer last_read|write_seqno. It also allows an
2355 * emission time to be associated with the request for tracking how far ahead
2356 * of the GPU the submission is.
2358 * The requests are reference counted, so upon creation they should have an
2359 * initial reference taken using kref_init
2361 struct drm_i915_gem_request {
2364 /** On Which ring this request was generated */
2365 struct drm_i915_private *i915;
2366 struct intel_engine_cs *engine;
2367 unsigned reset_counter;
2369 /** GEM sequence number associated with the previous request,
2370 * when the HWS breadcrumb is equal to this the GPU is processing
2375 /** GEM sequence number associated with this request,
2376 * when the HWS breadcrumb is equal or greater than this the GPU
2377 * has finished processing this request.
2381 /** Position in the ringbuffer of the start of the request */
2385 * Position in the ringbuffer of the start of the postfix.
2386 * This is required to calculate the maximum available ringbuffer
2387 * space without overwriting the postfix.
2391 /** Position in the ringbuffer of the end of the whole request */
2394 /** Preallocate space in the ringbuffer for the emitting the request */
2398 * Context and ring buffer related to this request
2399 * Contexts are refcounted, so when this request is associated with a
2400 * context, we must increment the context's refcount, to guarantee that
2401 * it persists while any request is linked to it. Requests themselves
2402 * are also refcounted, so the request will only be freed when the last
2403 * reference to it is dismissed, and the code in
2404 * i915_gem_request_free() will then decrement the refcount on the
2407 struct i915_gem_context *ctx;
2408 struct intel_ringbuffer *ringbuf;
2411 * Context related to the previous request.
2412 * As the contexts are accessed by the hardware until the switch is
2413 * completed to a new context, the hardware may still be writing
2414 * to the context object after the breadcrumb is visible. We must
2415 * not unpin/unbind/prune that object whilst still active and so
2416 * we keep the previous context pinned until the following (this)
2417 * request is retired.
2419 struct i915_gem_context *previous_context;
2421 /** Batch buffer related to this request if any (used for
2422 error state dump only) */
2423 struct drm_i915_gem_object *batch_obj;
2425 /** Time at which this request was emitted, in jiffies. */
2426 unsigned long emitted_jiffies;
2428 /** global list entry for this request */
2429 struct list_head list;
2431 struct drm_i915_file_private *file_priv;
2432 /** file_priv list entry for this request */
2433 struct list_head client_list;
2435 /** process identifier submitting this request */
2439 * The ELSP only accepts two elements at a time, so we queue
2440 * context/tail pairs on a given queue (ring->execlist_queue) until the
2441 * hardware is available. The queue serves a double purpose: we also use
2442 * it to keep track of the up to 2 contexts currently in the hardware
2443 * (usually one in execution and the other queued up by the GPU): We
2444 * only remove elements from the head of the queue when the hardware
2445 * informs us that an element has been completed.
2447 * All accesses to the queue are mediated by a spinlock
2448 * (ring->execlist_lock).
2451 /** Execlist link in the submission queue.*/
2452 struct list_head execlist_link;
2454 /** Execlists no. of times this request has been sent to the ELSP */
2457 /** Execlists context hardware id. */
2461 struct drm_i915_gem_request * __must_check
2462 i915_gem_request_alloc(struct intel_engine_cs *engine,
2463 struct i915_gem_context *ctx);
2464 void i915_gem_request_free(struct kref *req_ref);
2465 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2466 struct drm_file *file);
2468 static inline uint32_t
2469 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2471 return req ? req->seqno : 0;
2474 static inline struct intel_engine_cs *
2475 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2477 return req ? req->engine : NULL;
2480 static inline struct drm_i915_gem_request *
2481 i915_gem_request_reference(struct drm_i915_gem_request *req)
2484 kref_get(&req->ref);
2489 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2491 kref_put(&req->ref, i915_gem_request_free);
2494 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2495 struct drm_i915_gem_request *src)
2498 i915_gem_request_reference(src);
2501 i915_gem_request_unreference(*pdst);
2507 * XXX: i915_gem_request_completed should be here but currently needs the
2508 * definition of i915_seqno_passed() which is below. It will be moved in
2509 * a later patch when the call to i915_seqno_passed() is obsoleted...
2513 * A command that requires special handling by the command parser.
2515 struct drm_i915_cmd_descriptor {
2517 * Flags describing how the command parser processes the command.
2519 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2520 * a length mask if not set
2521 * CMD_DESC_SKIP: The command is allowed but does not follow the
2522 * standard length encoding for the opcode range in
2524 * CMD_DESC_REJECT: The command is never allowed
2525 * CMD_DESC_REGISTER: The command should be checked against the
2526 * register whitelist for the appropriate ring
2527 * CMD_DESC_MASTER: The command is allowed if the submitting process
2531 #define CMD_DESC_FIXED (1<<0)
2532 #define CMD_DESC_SKIP (1<<1)
2533 #define CMD_DESC_REJECT (1<<2)
2534 #define CMD_DESC_REGISTER (1<<3)
2535 #define CMD_DESC_BITMASK (1<<4)
2536 #define CMD_DESC_MASTER (1<<5)
2539 * The command's unique identification bits and the bitmask to get them.
2540 * This isn't strictly the opcode field as defined in the spec and may
2541 * also include type, subtype, and/or subop fields.
2549 * The command's length. The command is either fixed length (i.e. does
2550 * not include a length field) or has a length field mask. The flag
2551 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2552 * a length mask. All command entries in a command table must include
2553 * length information.
2561 * Describes where to find a register address in the command to check
2562 * against the ring's register whitelist. Only valid if flags has the
2563 * CMD_DESC_REGISTER bit set.
2565 * A non-zero step value implies that the command may access multiple
2566 * registers in sequence (e.g. LRI), in that case step gives the
2567 * distance in dwords between individual offset fields.
2575 #define MAX_CMD_DESC_BITMASKS 3
2577 * Describes command checks where a particular dword is masked and
2578 * compared against an expected value. If the command does not match
2579 * the expected value, the parser rejects it. Only valid if flags has
2580 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2583 * If the check specifies a non-zero condition_mask then the parser
2584 * only performs the check when the bits specified by condition_mask
2591 u32 condition_offset;
2593 } bits[MAX_CMD_DESC_BITMASKS];
2597 * A table of commands requiring special handling by the command parser.
2599 * Each ring has an array of tables. Each table consists of an array of command
2600 * descriptors, which must be sorted with command opcodes in ascending order.
2602 struct drm_i915_cmd_table {
2603 const struct drm_i915_cmd_descriptor *table;
2607 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2608 #define __I915__(p) ({ \
2609 struct drm_i915_private *__p; \
2610 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2611 __p = (struct drm_i915_private *)p; \
2612 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2613 __p = to_i915((struct drm_device *)p); \
2618 #define INTEL_INFO(p) (&__I915__(p)->info)
2619 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2620 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2622 #define REVID_FOREVER 0xff
2623 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2625 #define GEN_FOREVER (0)
2627 * Returns true if Gen is in inclusive range [Start, End].
2629 * Use GEN_FOREVER for unbound start and or end.
2631 #define IS_GEN(p, s, e) ({ \
2632 unsigned int __s = (s), __e = (e); \
2633 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2634 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2635 if ((__s) != GEN_FOREVER) \
2637 if ((__e) == GEN_FOREVER) \
2638 __e = BITS_PER_LONG - 1; \
2641 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2645 * Return true if revision is in range [since,until] inclusive.
2647 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2649 #define IS_REVID(p, since, until) \
2650 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2652 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2653 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2654 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2655 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2656 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2657 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2658 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2659 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2660 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2661 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2662 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2663 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2664 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2665 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2666 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2667 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2668 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2669 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2670 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2671 INTEL_DEVID(dev) == 0x0152 || \
2672 INTEL_DEVID(dev) == 0x015a)
2673 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2674 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2675 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2676 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2677 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2678 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2679 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2680 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2681 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2682 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2683 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2684 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2685 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2686 (INTEL_DEVID(dev) & 0xf) == 0xe))
2687 /* ULX machines are also considered ULT. */
2688 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2689 (INTEL_DEVID(dev) & 0xf) == 0xe)
2690 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2691 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2692 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2693 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2694 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2695 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2696 /* ULX machines are also considered ULT. */
2697 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2698 INTEL_DEVID(dev) == 0x0A1E)
2699 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2700 INTEL_DEVID(dev) == 0x1913 || \
2701 INTEL_DEVID(dev) == 0x1916 || \
2702 INTEL_DEVID(dev) == 0x1921 || \
2703 INTEL_DEVID(dev) == 0x1926)
2704 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2705 INTEL_DEVID(dev) == 0x1915 || \
2706 INTEL_DEVID(dev) == 0x191E)
2707 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2708 INTEL_DEVID(dev) == 0x5913 || \
2709 INTEL_DEVID(dev) == 0x5916 || \
2710 INTEL_DEVID(dev) == 0x5921 || \
2711 INTEL_DEVID(dev) == 0x5926)
2712 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2713 INTEL_DEVID(dev) == 0x5915 || \
2714 INTEL_DEVID(dev) == 0x591E)
2715 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2716 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2717 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2718 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2720 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2722 #define SKL_REVID_A0 0x0
2723 #define SKL_REVID_B0 0x1
2724 #define SKL_REVID_C0 0x2
2725 #define SKL_REVID_D0 0x3
2726 #define SKL_REVID_E0 0x4
2727 #define SKL_REVID_F0 0x5
2729 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2731 #define BXT_REVID_A0 0x0
2732 #define BXT_REVID_A1 0x1
2733 #define BXT_REVID_B0 0x3
2734 #define BXT_REVID_C0 0x9
2736 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2738 #define KBL_REVID_A0 0x0
2739 #define KBL_REVID_B0 0x1
2740 #define KBL_REVID_C0 0x2
2741 #define KBL_REVID_D0 0x3
2742 #define KBL_REVID_E0 0x4
2744 #define IS_KBL_REVID(p, since, until) \
2745 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2748 * The genX designation typically refers to the render engine, so render
2749 * capability related checks should use IS_GEN, while display and other checks
2750 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2753 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen_mask & BIT(1))
2754 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen_mask & BIT(2))
2755 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen_mask & BIT(3))
2756 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen_mask & BIT(4))
2757 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen_mask & BIT(5))
2758 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen_mask & BIT(6))
2759 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
2760 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
2762 #define ENGINE_MASK(id) BIT(id)
2763 #define RENDER_RING ENGINE_MASK(RCS)
2764 #define BSD_RING ENGINE_MASK(VCS)
2765 #define BLT_RING ENGINE_MASK(BCS)
2766 #define VEBOX_RING ENGINE_MASK(VECS)
2767 #define BSD2_RING ENGINE_MASK(VCS2)
2768 #define ALL_ENGINES (~0)
2770 #define HAS_ENGINE(dev_priv, id) \
2771 (INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))
2773 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2774 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2775 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2776 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2778 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2779 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2780 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2781 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2783 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2785 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2786 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2787 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2788 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2789 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2791 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2792 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2794 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2795 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2797 /* WaRsDisableCoarsePowerGating:skl,bxt */
2798 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2799 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2800 IS_SKL_GT3(dev_priv) || \
2801 IS_SKL_GT4(dev_priv))
2804 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2805 * even when in MSI mode. This results in spurious interrupt warnings if the
2806 * legacy irq no. is shared with another device. The kernel then disables that
2807 * interrupt source and so prevents the other device from working properly.
2809 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2810 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2812 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2813 * rows, which changed the alignment requirements and fence programming.
2815 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2817 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2818 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2820 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2821 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2822 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2824 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2826 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2827 INTEL_INFO(dev)->gen >= 9)
2829 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2830 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2831 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2832 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2833 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2834 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2835 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2836 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2837 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2838 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2839 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2841 #define HAS_CSR(dev) (IS_GEN9(dev))
2844 * For now, anything with a GuC requires uCode loading, and then supports
2845 * command submission once loaded. But these are logically independent
2846 * properties, so we have separate macros to test them.
2848 #define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2849 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2850 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2852 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2853 INTEL_INFO(dev)->gen >= 8)
2855 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2856 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2859 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2861 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2862 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2863 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2864 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2865 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2866 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2867 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2868 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2869 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2870 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2871 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2873 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2874 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2875 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2876 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2877 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2878 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2879 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2880 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2881 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2883 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2884 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2886 /* DPF == dynamic parity feature */
2887 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2888 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2890 #define GT_FREQUENCY_MULTIPLIER 50
2891 #define GEN9_FREQ_SCALER 3
2893 #include "i915_trace.h"
2895 extern const struct drm_ioctl_desc i915_ioctls[];
2896 extern int i915_max_ioctl;
2898 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2899 extern int i915_resume_switcheroo(struct drm_device *dev);
2901 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2906 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2907 const char *fmt, ...);
2909 #define i915_report_error(dev_priv, fmt, ...) \
2910 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2912 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2913 extern int i915_driver_unload(struct drm_device *);
2914 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2915 extern void i915_driver_lastclose(struct drm_device * dev);
2916 extern void i915_driver_preclose(struct drm_device *dev,
2917 struct drm_file *file);
2918 extern void i915_driver_postclose(struct drm_device *dev,
2919 struct drm_file *file);
2920 #ifdef CONFIG_COMPAT
2921 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2924 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2925 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2926 extern int i915_reset(struct drm_i915_private *dev_priv);
2927 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2928 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2929 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2930 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2931 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2932 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2933 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2935 /* intel_hotplug.c */
2936 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2937 u32 pin_mask, u32 long_mask);
2938 void intel_hpd_init(struct drm_i915_private *dev_priv);
2939 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2940 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2941 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2944 void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
2946 void i915_handle_error(struct drm_i915_private *dev_priv,
2948 const char *fmt, ...);
2950 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2951 int intel_irq_install(struct drm_i915_private *dev_priv);
2952 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2954 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2955 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2956 bool restore_forcewake);
2957 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2958 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2959 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2960 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2961 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2963 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2964 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2965 enum forcewake_domains domains);
2966 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2967 enum forcewake_domains domains);
2968 /* Like above but the caller must manage the uncore.lock itself.
2969 * Must be used with I915_READ_FW and friends.
2971 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2972 enum forcewake_domains domains);
2973 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2974 enum forcewake_domains domains);
2975 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2977 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2979 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2981 return dev_priv->gvt.initialized;
2984 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2986 return dev_priv->vgpu.active;
2990 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2994 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2997 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2998 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2999 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3002 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3003 uint32_t interrupt_mask,
3004 uint32_t enabled_irq_mask);
3006 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3008 ilk_update_display_irq(dev_priv, bits, bits);
3011 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3013 ilk_update_display_irq(dev_priv, bits, 0);
3015 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3017 uint32_t interrupt_mask,
3018 uint32_t enabled_irq_mask);
3019 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3020 enum pipe pipe, uint32_t bits)
3022 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3024 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3025 enum pipe pipe, uint32_t bits)
3027 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3029 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3030 uint32_t interrupt_mask,
3031 uint32_t enabled_irq_mask);
3033 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3035 ibx_display_interrupt_update(dev_priv, bits, bits);
3038 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3040 ibx_display_interrupt_update(dev_priv, bits, 0);
3045 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3046 struct drm_file *file_priv);
3047 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3048 struct drm_file *file_priv);
3049 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3050 struct drm_file *file_priv);
3051 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3052 struct drm_file *file_priv);
3053 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3054 struct drm_file *file_priv);
3055 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3056 struct drm_file *file_priv);
3057 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3058 struct drm_file *file_priv);
3059 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
3060 struct drm_i915_gem_request *req);
3061 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
3062 struct drm_i915_gem_execbuffer2 *args,
3063 struct list_head *vmas);
3064 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3065 struct drm_file *file_priv);
3066 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3067 struct drm_file *file_priv);
3068 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3069 struct drm_file *file_priv);
3070 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3071 struct drm_file *file);
3072 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3073 struct drm_file *file);
3074 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3075 struct drm_file *file_priv);
3076 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3077 struct drm_file *file_priv);
3078 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3079 struct drm_file *file_priv);
3080 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3081 struct drm_file *file_priv);
3082 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3083 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3084 struct drm_file *file);
3085 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3086 struct drm_file *file_priv);
3087 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3088 struct drm_file *file_priv);
3089 void i915_gem_load_init(struct drm_device *dev);
3090 void i915_gem_load_cleanup(struct drm_device *dev);
3091 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3092 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3094 void *i915_gem_object_alloc(struct drm_device *dev);
3095 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3096 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3097 const struct drm_i915_gem_object_ops *ops);
3098 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3100 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3101 struct drm_device *dev, const void *data, size_t size);
3102 void i915_gem_free_object(struct drm_gem_object *obj);
3103 void i915_gem_vma_destroy(struct i915_vma *vma);
3105 /* Flags used by pin/bind&friends. */
3106 #define PIN_MAPPABLE (1<<0)
3107 #define PIN_NONBLOCK (1<<1)
3108 #define PIN_GLOBAL (1<<2)
3109 #define PIN_OFFSET_BIAS (1<<3)
3110 #define PIN_USER (1<<4)
3111 #define PIN_UPDATE (1<<5)
3112 #define PIN_ZONE_4G (1<<6)
3113 #define PIN_HIGH (1<<7)
3114 #define PIN_OFFSET_FIXED (1<<8)
3115 #define PIN_OFFSET_MASK (~4095)
3117 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3118 struct i915_address_space *vm,
3122 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3123 const struct i915_ggtt_view *view,
3127 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3129 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3130 int __must_check i915_vma_unbind(struct i915_vma *vma);
3132 * BEWARE: Do not use the function below unless you can _absolutely_
3133 * _guarantee_ VMA in question is _not in use_ anywhere.
3135 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3136 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3137 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3138 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3140 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3141 int *needs_clflush);
3143 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3145 static inline int __sg_page_count(struct scatterlist *sg)
3147 return sg->length >> PAGE_SHIFT;
3151 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3153 static inline dma_addr_t
3154 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3156 if (n < obj->get_page.last) {
3157 obj->get_page.sg = obj->pages->sgl;
3158 obj->get_page.last = 0;
3161 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3162 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3163 if (unlikely(sg_is_chain(obj->get_page.sg)))
3164 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3167 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3170 static inline struct page *
3171 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3173 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3176 if (n < obj->get_page.last) {
3177 obj->get_page.sg = obj->pages->sgl;
3178 obj->get_page.last = 0;
3181 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3182 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3183 if (unlikely(sg_is_chain(obj->get_page.sg)))
3184 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3187 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3190 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3192 BUG_ON(obj->pages == NULL);
3193 obj->pages_pin_count++;
3196 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3198 BUG_ON(obj->pages_pin_count == 0);
3199 obj->pages_pin_count--;
3203 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3204 * @obj - the object to map into kernel address space
3206 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3207 * pages and then returns a contiguous mapping of the backing storage into
3208 * the kernel address space.
3210 * The caller must hold the struct_mutex, and is responsible for calling
3211 * i915_gem_object_unpin_map() when the mapping is no longer required.
3213 * Returns the pointer through which to access the mapped object, or an
3214 * ERR_PTR() on error.
3216 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3219 * i915_gem_object_unpin_map - releases an earlier mapping
3220 * @obj - the object to unmap
3222 * After pinning the object and mapping its pages, once you are finished
3223 * with your access, call i915_gem_object_unpin_map() to release the pin
3224 * upon the mapping. Once the pin count reaches zero, that mapping may be
3227 * The caller must hold the struct_mutex.
3229 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3231 lockdep_assert_held(&obj->base.dev->struct_mutex);
3232 i915_gem_object_unpin_pages(obj);
3235 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3236 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3237 struct intel_engine_cs *to,
3238 struct drm_i915_gem_request **to_req);
3239 void i915_vma_move_to_active(struct i915_vma *vma,
3240 struct drm_i915_gem_request *req);
3241 int i915_gem_dumb_create(struct drm_file *file_priv,
3242 struct drm_device *dev,
3243 struct drm_mode_create_dumb *args);
3244 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3245 uint32_t handle, uint64_t *offset);
3247 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3248 struct drm_i915_gem_object *new,
3249 unsigned frontbuffer_bits);
3252 * Returns true if seq1 is later than seq2.
3255 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3257 return (int32_t)(seq1 - seq2) >= 0;
3260 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3261 bool lazy_coherency)
3263 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3264 req->engine->irq_seqno_barrier(req->engine);
3265 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3266 req->previous_seqno);
3269 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3270 bool lazy_coherency)
3272 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3273 req->engine->irq_seqno_barrier(req->engine);
3274 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3278 int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
3279 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3281 struct drm_i915_gem_request *
3282 i915_gem_find_active_request(struct intel_engine_cs *engine);
3284 bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3285 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3287 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3289 return atomic_read(&error->reset_counter);
3292 static inline bool __i915_reset_in_progress(u32 reset)
3294 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3297 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3299 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3302 static inline bool __i915_terminally_wedged(u32 reset)
3304 return unlikely(reset & I915_WEDGED);
3307 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3309 return __i915_reset_in_progress(i915_reset_counter(error));
3312 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3314 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3317 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3319 return __i915_terminally_wedged(i915_reset_counter(error));
3322 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3324 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3327 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3329 return dev_priv->gpu_error.stop_rings == 0 ||
3330 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3333 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3335 return dev_priv->gpu_error.stop_rings == 0 ||
3336 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3339 void i915_gem_reset(struct drm_device *dev);
3340 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3341 int __must_check i915_gem_init(struct drm_device *dev);
3342 int i915_gem_init_engines(struct drm_device *dev);
3343 int __must_check i915_gem_init_hw(struct drm_device *dev);
3344 void i915_gem_init_swizzling(struct drm_device *dev);
3345 void i915_gem_cleanup_engines(struct drm_device *dev);
3346 int __must_check i915_gpu_idle(struct drm_device *dev);
3347 int __must_check i915_gem_suspend(struct drm_device *dev);
3348 void __i915_add_request(struct drm_i915_gem_request *req,
3349 struct drm_i915_gem_object *batch_obj,
3351 #define i915_add_request(req) \
3352 __i915_add_request(req, NULL, true)
3353 #define i915_add_request_no_flush(req) \
3354 __i915_add_request(req, NULL, false)
3355 int __i915_wait_request(struct drm_i915_gem_request *req,
3358 struct intel_rps_client *rps);
3359 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3360 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3362 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3365 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3368 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3370 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3372 const struct i915_ggtt_view *view);
3373 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3374 const struct i915_ggtt_view *view);
3375 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3377 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3378 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3381 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3383 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3384 int tiling_mode, bool fenced);
3386 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3387 enum i915_cache_level cache_level);
3389 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3390 struct dma_buf *dma_buf);
3392 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3393 struct drm_gem_object *gem_obj, int flags);
3395 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3396 const struct i915_ggtt_view *view);
3397 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3398 struct i915_address_space *vm);
3400 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3402 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3405 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3406 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3407 const struct i915_ggtt_view *view);
3408 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3409 struct i915_address_space *vm);
3412 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3413 struct i915_address_space *vm);
3415 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3416 const struct i915_ggtt_view *view);
3419 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3420 struct i915_address_space *vm);
3422 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3423 const struct i915_ggtt_view *view);
3425 static inline struct i915_vma *
3426 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3428 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3430 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3432 /* Some GGTT VM helpers */
3433 static inline struct i915_hw_ppgtt *
3434 i915_vm_to_ppgtt(struct i915_address_space *vm)
3436 return container_of(vm, struct i915_hw_ppgtt, base);
3440 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3442 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3446 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
3448 static inline int __must_check
3449 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3453 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3454 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3456 return i915_gem_object_pin(obj, &ggtt->base,
3457 alignment, flags | PIN_GLOBAL);
3460 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3461 const struct i915_ggtt_view *view);
3463 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3465 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3468 /* i915_gem_fence.c */
3469 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3470 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3472 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3473 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3475 void i915_gem_restore_fences(struct drm_device *dev);
3477 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3478 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3479 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3481 /* i915_gem_context.c */
3482 int __must_check i915_gem_context_init(struct drm_device *dev);
3483 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3484 void i915_gem_context_fini(struct drm_device *dev);
3485 void i915_gem_context_reset(struct drm_device *dev);
3486 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3487 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3488 int i915_switch_context(struct drm_i915_gem_request *req);
3489 void i915_gem_context_free(struct kref *ctx_ref);
3490 struct drm_i915_gem_object *
3491 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3492 struct i915_gem_context *
3493 i915_gem_context_create_gvt(struct drm_device *dev);
3495 static inline struct i915_gem_context *
3496 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3498 struct i915_gem_context *ctx;
3500 lockdep_assert_held(&file_priv->dev_priv->dev->struct_mutex);
3502 ctx = idr_find(&file_priv->context_idr, id);
3504 return ERR_PTR(-ENOENT);
3509 static inline void i915_gem_context_reference(struct i915_gem_context *ctx)
3511 kref_get(&ctx->ref);
3514 static inline void i915_gem_context_unreference(struct i915_gem_context *ctx)
3516 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
3517 kref_put(&ctx->ref, i915_gem_context_free);
3520 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3522 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3525 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3526 struct drm_file *file);
3527 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3528 struct drm_file *file);
3529 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3530 struct drm_file *file_priv);
3531 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3532 struct drm_file *file_priv);
3533 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3534 struct drm_file *file);
3536 /* i915_gem_evict.c */
3537 int __must_check i915_gem_evict_something(struct drm_device *dev,
3538 struct i915_address_space *vm,
3541 unsigned cache_level,
3542 unsigned long start,
3545 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3546 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3548 /* belongs in i915_gem_gtt.h */
3549 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3551 if (INTEL_GEN(dev_priv) < 6)
3552 intel_gtt_chipset_flush();
3555 /* i915_gem_stolen.c */
3556 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3557 struct drm_mm_node *node, u64 size,
3558 unsigned alignment);
3559 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3560 struct drm_mm_node *node, u64 size,
3561 unsigned alignment, u64 start,
3563 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3564 struct drm_mm_node *node);
3565 int i915_gem_init_stolen(struct drm_device *dev);
3566 void i915_gem_cleanup_stolen(struct drm_device *dev);
3567 struct drm_i915_gem_object *
3568 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3569 struct drm_i915_gem_object *
3570 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3575 /* i915_gem_shrinker.c */
3576 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3577 unsigned long target,
3579 #define I915_SHRINK_PURGEABLE 0x1
3580 #define I915_SHRINK_UNBOUND 0x2
3581 #define I915_SHRINK_BOUND 0x4
3582 #define I915_SHRINK_ACTIVE 0x8
3583 #define I915_SHRINK_VMAPS 0x10
3584 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3585 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3586 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3589 /* i915_gem_tiling.c */
3590 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3592 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3594 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3595 obj->tiling_mode != I915_TILING_NONE;
3598 /* i915_gem_debug.c */
3600 int i915_verify_lists(struct drm_device *dev);
3602 #define i915_verify_lists(dev) 0
3605 /* i915_debugfs.c */
3606 int i915_debugfs_init(struct drm_minor *minor);
3607 void i915_debugfs_cleanup(struct drm_minor *minor);
3608 #ifdef CONFIG_DEBUG_FS
3609 int i915_debugfs_connector_add(struct drm_connector *connector);
3610 void intel_display_crc_init(struct drm_device *dev);
3612 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3614 static inline void intel_display_crc_init(struct drm_device *dev) {}
3617 /* i915_gpu_error.c */
3619 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3620 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3621 const struct i915_error_state_file_priv *error);
3622 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3623 struct drm_i915_private *i915,
3624 size_t count, loff_t pos);
3625 static inline void i915_error_state_buf_release(
3626 struct drm_i915_error_state_buf *eb)
3630 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3632 const char *error_msg);
3633 void i915_error_state_get(struct drm_device *dev,
3634 struct i915_error_state_file_priv *error_priv);
3635 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3636 void i915_destroy_error_state(struct drm_device *dev);
3638 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3639 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3641 /* i915_cmd_parser.c */
3642 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3643 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3644 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3645 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3646 int i915_parse_cmds(struct intel_engine_cs *engine,
3647 struct drm_i915_gem_object *batch_obj,
3648 struct drm_i915_gem_object *shadow_batch_obj,
3649 u32 batch_start_offset,
3653 /* i915_suspend.c */
3654 extern int i915_save_state(struct drm_device *dev);
3655 extern int i915_restore_state(struct drm_device *dev);
3658 void i915_setup_sysfs(struct drm_device *dev_priv);
3659 void i915_teardown_sysfs(struct drm_device *dev_priv);
3662 extern int intel_setup_gmbus(struct drm_device *dev);
3663 extern void intel_teardown_gmbus(struct drm_device *dev);
3664 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3667 extern struct i2c_adapter *
3668 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3669 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3670 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3671 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3673 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3675 extern void intel_i2c_reset(struct drm_device *dev);
3678 int intel_bios_init(struct drm_i915_private *dev_priv);
3679 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3680 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3681 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3682 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3683 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3684 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3685 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3686 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3689 /* intel_opregion.c */
3691 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3692 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3693 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3694 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3695 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3697 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3699 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3701 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3702 static inline void intel_opregion_init(struct drm_i915_private *dev) { }
3703 static inline void intel_opregion_fini(struct drm_i915_private *dev) { }
3704 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3708 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3713 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3717 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3725 extern void intel_register_dsm_handler(void);
3726 extern void intel_unregister_dsm_handler(void);
3728 static inline void intel_register_dsm_handler(void) { return; }
3729 static inline void intel_unregister_dsm_handler(void) { return; }
3730 #endif /* CONFIG_ACPI */
3733 extern void intel_modeset_init_hw(struct drm_device *dev);
3734 extern void intel_modeset_init(struct drm_device *dev);
3735 extern void intel_modeset_gem_init(struct drm_device *dev);
3736 extern void intel_modeset_cleanup(struct drm_device *dev);
3737 extern void intel_connector_unregister(struct drm_connector *);
3738 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3739 extern void intel_display_resume(struct drm_device *dev);
3740 extern void i915_redisable_vga(struct drm_device *dev);
3741 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3742 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3743 extern void intel_init_pch_refclk(struct drm_device *dev);
3744 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3745 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3747 extern void intel_detect_pch(struct drm_device *dev);
3749 extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
3750 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3751 struct drm_file *file);
3754 extern struct intel_overlay_error_state *
3755 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3756 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3757 struct intel_overlay_error_state *error);
3759 extern struct intel_display_error_state *
3760 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3761 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3762 struct drm_device *dev,
3763 struct intel_display_error_state *error);
3765 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3766 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3768 /* intel_sideband.c */
3769 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3770 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3771 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3772 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3773 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3774 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3775 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3776 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3777 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3778 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3779 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3780 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3781 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3782 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3783 enum intel_sbi_destination destination);
3784 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3785 enum intel_sbi_destination destination);
3786 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3787 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3789 /* intel_dpio_phy.c */
3790 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3791 u32 deemph_reg_value, u32 margin_reg_value,
3792 bool uniq_trans_scale);
3793 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3795 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3796 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3797 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3798 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3800 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3801 u32 demph_reg_value, u32 preemph_reg_value,
3802 u32 uniqtranscale_reg_value, u32 tx3_demph);
3803 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3804 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3805 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3807 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3808 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3810 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3811 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3813 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3814 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3815 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3816 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3818 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3819 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3820 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3821 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3823 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3824 * will be implemented using 2 32-bit writes in an arbitrary order with
3825 * an arbitrary delay between them. This can cause the hardware to
3826 * act upon the intermediate value, possibly leading to corruption and
3827 * machine death. You have been warned.
3829 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3830 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3832 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3833 u32 upper, lower, old_upper, loop = 0; \
3834 upper = I915_READ(upper_reg); \
3836 old_upper = upper; \
3837 lower = I915_READ(lower_reg); \
3838 upper = I915_READ(upper_reg); \
3839 } while (upper != old_upper && loop++ < 2); \
3840 (u64)upper << 32 | lower; })
3842 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3843 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3845 #define __raw_read(x, s) \
3846 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3849 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3852 #define __raw_write(x, s) \
3853 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3854 i915_reg_t reg, uint##x##_t val) \
3856 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3871 /* These are untraced mmio-accessors that are only valid to be used inside
3872 * criticial sections inside IRQ handlers where forcewake is explicitly
3874 * Think twice, and think again, before using these.
3875 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3876 * intel_uncore_forcewake_irqunlock().
3878 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3879 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3880 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3882 /* "Broadcast RGB" property */
3883 #define INTEL_BROADCAST_RGB_AUTO 0
3884 #define INTEL_BROADCAST_RGB_FULL 1
3885 #define INTEL_BROADCAST_RGB_LIMITED 2
3887 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3889 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3890 return VLV_VGACNTRL;
3891 else if (INTEL_INFO(dev)->gen >= 5)
3892 return CPU_VGACNTRL;
3897 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3899 unsigned long j = msecs_to_jiffies(m);
3901 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3904 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3906 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3909 static inline unsigned long
3910 timespec_to_jiffies_timeout(const struct timespec *value)
3912 unsigned long j = timespec_to_jiffies(value);
3914 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3918 * If you need to wait X milliseconds between events A and B, but event B
3919 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3920 * when event A happened, then just before event B you call this function and
3921 * pass the timestamp as the first argument, and X as the second argument.
3924 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3926 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3929 * Don't re-read the value of "jiffies" every time since it may change
3930 * behind our back and break the math.
3932 tmp_jiffies = jiffies;
3933 target_jiffies = timestamp_jiffies +
3934 msecs_to_jiffies_timeout(to_wait_ms);
3936 if (time_after(target_jiffies, tmp_jiffies)) {
3937 remaining_jiffies = target_jiffies - tmp_jiffies;
3938 while (remaining_jiffies)
3940 schedule_timeout_uninterruptible(remaining_jiffies);
3944 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3945 struct drm_i915_gem_request *req)
3947 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3948 i915_gem_request_assign(&engine->trace_irq_req, req);