1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
65 /* General customization:
68 #define DRIVER_NAME "i915"
69 #define DRIVER_DESC "Intel Graphics"
70 #define DRIVER_DATE "20160606"
73 /* Many gcc seem to no see through this and fall over :( */
75 #define WARN_ON(x) ({ \
76 bool __i915_warn_cond = (x); \
77 if (__builtin_constant_p(__i915_warn_cond)) \
78 BUILD_BUG_ON(__i915_warn_cond); \
79 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
81 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
85 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
87 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
88 (long) (x), __func__);
90 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
91 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
92 * which may not necessarily be a user visible problem. This will either
93 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
94 * enable distros and users to tailor their preferred amount of i915 abrt
97 #define I915_STATE_WARN(condition, format...) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) \
100 if (!WARN(i915.verbose_state_checks, format)) \
102 unlikely(__ret_warn_on); \
105 #define I915_STATE_WARN_ON(x) \
106 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
108 bool __i915_inject_load_failure(const char *func, int line);
109 #define i915_inject_load_failure() \
110 __i915_inject_load_failure(__func__, __LINE__)
112 static inline const char *yesno(bool v)
114 return v ? "yes" : "no";
117 static inline const char *onoff(bool v)
119 return v ? "on" : "off";
128 I915_MAX_PIPES = _PIPE_EDP
130 #define pipe_name(p) ((p) + 'A')
142 static inline const char *transcoder_name(enum transcoder transcoder)
144 switch (transcoder) {
153 case TRANSCODER_DSI_A:
155 case TRANSCODER_DSI_C:
162 static inline bool transcoder_is_dsi(enum transcoder transcoder)
164 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
168 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
169 * number of planes per CRTC. Not all platforms really have this many planes,
170 * which means some arrays of size I915_MAX_PLANES may have unused entries
171 * between the topmost sprite plane and the cursor plane.
180 #define plane_name(p) ((p) + 'A')
182 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
192 #define port_name(p) ((p) + 'A')
194 #define I915_NUM_PHYS_VLV 2
206 enum intel_display_power_domain {
210 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
211 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
212 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
213 POWER_DOMAIN_TRANSCODER_A,
214 POWER_DOMAIN_TRANSCODER_B,
215 POWER_DOMAIN_TRANSCODER_C,
216 POWER_DOMAIN_TRANSCODER_EDP,
217 POWER_DOMAIN_TRANSCODER_DSI_A,
218 POWER_DOMAIN_TRANSCODER_DSI_C,
219 POWER_DOMAIN_PORT_DDI_A_LANES,
220 POWER_DOMAIN_PORT_DDI_B_LANES,
221 POWER_DOMAIN_PORT_DDI_C_LANES,
222 POWER_DOMAIN_PORT_DDI_D_LANES,
223 POWER_DOMAIN_PORT_DDI_E_LANES,
224 POWER_DOMAIN_PORT_DSI,
225 POWER_DOMAIN_PORT_CRT,
226 POWER_DOMAIN_PORT_OTHER,
235 POWER_DOMAIN_MODESET,
241 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
242 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
243 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
244 #define POWER_DOMAIN_TRANSCODER(tran) \
245 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
246 (tran) + POWER_DOMAIN_TRANSCODER_A)
250 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
262 #define for_each_hpd_pin(__pin) \
263 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
265 struct i915_hotplug {
266 struct work_struct hotplug_work;
269 unsigned long last_jiffies;
274 HPD_MARK_DISABLED = 2
276 } stats[HPD_NUM_PINS];
278 struct delayed_work reenable_work;
280 struct intel_digital_port *irq_port[I915_MAX_PORTS];
283 struct work_struct dig_port_work;
286 * if we get a HPD irq from DP and a HPD irq from non-DP
287 * the non-DP HPD could block the workqueue on a mode config
288 * mutex getting, that userspace may have taken. However
289 * userspace is waiting on the DP workqueue to run which is
290 * blocked behind the non-DP one.
292 struct workqueue_struct *dp_wq;
295 #define I915_GEM_GPU_DOMAINS \
296 (I915_GEM_DOMAIN_RENDER | \
297 I915_GEM_DOMAIN_SAMPLER | \
298 I915_GEM_DOMAIN_COMMAND | \
299 I915_GEM_DOMAIN_INSTRUCTION | \
300 I915_GEM_DOMAIN_VERTEX)
302 #define for_each_pipe(__dev_priv, __p) \
303 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
304 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
305 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
306 for_each_if ((__mask) & (1 << (__p)))
307 #define for_each_plane(__dev_priv, __pipe, __p) \
309 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
311 #define for_each_sprite(__dev_priv, __p, __s) \
313 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
316 #define for_each_port_masked(__port, __ports_mask) \
317 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
318 for_each_if ((__ports_mask) & (1 << (__port)))
320 #define for_each_crtc(dev, crtc) \
321 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
323 #define for_each_intel_plane(dev, intel_plane) \
324 list_for_each_entry(intel_plane, \
325 &dev->mode_config.plane_list, \
328 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
329 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, \
331 for_each_if ((plane_mask) & \
332 (1 << drm_plane_index(&intel_plane->base)))
334 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
338 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
340 #define for_each_intel_crtc(dev, intel_crtc) \
341 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
343 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
344 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) \
345 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
347 #define for_each_intel_encoder(dev, intel_encoder) \
348 list_for_each_entry(intel_encoder, \
349 &(dev)->mode_config.encoder_list, \
352 #define for_each_intel_connector(dev, intel_connector) \
353 list_for_each_entry(intel_connector, \
354 &dev->mode_config.connector_list, \
357 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
358 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
359 for_each_if ((intel_encoder)->base.crtc == (__crtc))
361 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
362 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
363 for_each_if ((intel_connector)->base.encoder == (__encoder))
365 #define for_each_power_domain(domain, mask) \
366 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
367 for_each_if ((1 << (domain)) & (mask))
369 struct drm_i915_private;
370 struct i915_mm_struct;
371 struct i915_mmu_object;
373 struct drm_i915_file_private {
374 struct drm_i915_private *dev_priv;
375 struct drm_file *file;
379 struct list_head request_list;
380 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
381 * chosen to prevent the CPU getting more than a frame ahead of the GPU
382 * (when using lax throttling for the frontbuffer). We also use it to
383 * offer free GPU waitboosts for severely congested workloads.
385 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
387 struct idr context_idr;
389 struct intel_rps_client {
390 struct list_head link;
394 unsigned int bsd_ring;
397 /* Used by dp and fdi links */
398 struct intel_link_m_n {
406 void intel_link_compute_m_n(int bpp, int nlanes,
407 int pixel_clock, int link_clock,
408 struct intel_link_m_n *m_n);
410 /* Interface history:
413 * 1.2: Add Power Management
414 * 1.3: Add vblank support
415 * 1.4: Fix cmdbuffer path, add heap destroy
416 * 1.5: Add vblank pipe configuration
417 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
418 * - Support vertical blank on secondary display pipe
420 #define DRIVER_MAJOR 1
421 #define DRIVER_MINOR 6
422 #define DRIVER_PATCHLEVEL 0
424 #define WATCH_LISTS 0
426 struct opregion_header;
427 struct opregion_acpi;
428 struct opregion_swsci;
429 struct opregion_asle;
431 struct intel_opregion {
432 struct opregion_header *header;
433 struct opregion_acpi *acpi;
434 struct opregion_swsci *swsci;
435 u32 swsci_gbda_sub_functions;
436 u32 swsci_sbcb_sub_functions;
437 struct opregion_asle *asle;
442 struct work_struct asle_work;
444 #define OPREGION_SIZE (8*1024)
446 struct intel_overlay;
447 struct intel_overlay_error_state;
449 #define I915_FENCE_REG_NONE -1
450 #define I915_MAX_NUM_FENCES 32
451 /* 32 fences + sign bit for FENCE_REG_NONE */
452 #define I915_MAX_NUM_FENCE_BITS 6
454 struct drm_i915_fence_reg {
455 struct list_head lru_list;
456 struct drm_i915_gem_object *obj;
460 struct sdvo_device_mapping {
469 struct intel_display_error_state;
471 struct drm_i915_error_state {
480 /* Generic register state */
488 u32 error; /* gen6+ */
489 u32 err_int; /* gen7 */
490 u32 fault_data0; /* gen8, gen9 */
491 u32 fault_data1; /* gen8, gen9 */
497 u32 extra_instdone[I915_NUM_INSTDONE_REG];
498 u64 fence[I915_MAX_NUM_FENCES];
499 struct intel_overlay_error_state *overlay;
500 struct intel_display_error_state *display;
501 struct drm_i915_error_object *semaphore_obj;
503 struct drm_i915_error_ring {
505 /* Software tracked state */
508 enum intel_ring_hangcheck_action hangcheck_action;
511 /* our own tracking of ring head and tail */
516 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
535 u32 rc_psmi; /* sleep state */
536 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
538 struct drm_i915_error_object {
542 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
544 struct drm_i915_error_object *wa_ctx;
546 struct drm_i915_error_request {
561 char comm[TASK_COMM_LEN];
562 } ring[I915_NUM_ENGINES];
564 struct drm_i915_error_buffer {
567 u32 rseqno[I915_NUM_ENGINES], wseqno;
571 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
579 } **active_bo, **pinned_bo;
581 u32 *active_bo_count, *pinned_bo_count;
585 struct intel_connector;
586 struct intel_encoder;
587 struct intel_crtc_state;
588 struct intel_initial_plane_config;
593 struct drm_i915_display_funcs {
594 int (*get_display_clock_speed)(struct drm_device *dev);
595 int (*get_fifo_size)(struct drm_device *dev, int plane);
596 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
597 int (*compute_intermediate_wm)(struct drm_device *dev,
598 struct intel_crtc *intel_crtc,
599 struct intel_crtc_state *newstate);
600 void (*initial_watermarks)(struct intel_crtc_state *cstate);
601 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
602 int (*compute_global_watermarks)(struct drm_atomic_state *state);
603 void (*update_wm)(struct drm_crtc *crtc);
604 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
605 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
606 /* Returns the active state of the crtc, and if the crtc is active,
607 * fills out the pipe-config with the hw state. */
608 bool (*get_pipe_config)(struct intel_crtc *,
609 struct intel_crtc_state *);
610 void (*get_initial_plane_config)(struct intel_crtc *,
611 struct intel_initial_plane_config *);
612 int (*crtc_compute_clock)(struct intel_crtc *crtc,
613 struct intel_crtc_state *crtc_state);
614 void (*crtc_enable)(struct drm_crtc *crtc);
615 void (*crtc_disable)(struct drm_crtc *crtc);
616 void (*audio_codec_enable)(struct drm_connector *connector,
617 struct intel_encoder *encoder,
618 const struct drm_display_mode *adjusted_mode);
619 void (*audio_codec_disable)(struct intel_encoder *encoder);
620 void (*fdi_link_train)(struct drm_crtc *crtc);
621 void (*init_clock_gating)(struct drm_device *dev);
622 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
623 struct drm_framebuffer *fb,
624 struct drm_i915_gem_object *obj,
625 struct drm_i915_gem_request *req,
627 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
628 /* clock updates for mode set */
630 /* render clock increase/decrease */
631 /* display clock increase/decrease */
632 /* pll clock increase/decrease */
634 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
635 void (*load_luts)(struct drm_crtc_state *crtc_state);
638 enum forcewake_domain_id {
639 FW_DOMAIN_ID_RENDER = 0,
640 FW_DOMAIN_ID_BLITTER,
646 enum forcewake_domains {
647 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
648 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
649 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
650 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
655 #define FW_REG_READ (1)
656 #define FW_REG_WRITE (2)
658 enum forcewake_domains
659 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
660 i915_reg_t reg, unsigned int op);
662 struct intel_uncore_funcs {
663 void (*force_wake_get)(struct drm_i915_private *dev_priv,
664 enum forcewake_domains domains);
665 void (*force_wake_put)(struct drm_i915_private *dev_priv,
666 enum forcewake_domains domains);
668 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
669 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
670 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
671 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
673 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
674 uint8_t val, bool trace);
675 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
676 uint16_t val, bool trace);
677 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
678 uint32_t val, bool trace);
679 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
680 uint64_t val, bool trace);
683 struct intel_uncore {
684 spinlock_t lock; /** lock is also taken in irq contexts. */
686 struct intel_uncore_funcs funcs;
689 enum forcewake_domains fw_domains;
691 struct intel_uncore_forcewake_domain {
692 struct drm_i915_private *i915;
693 enum forcewake_domain_id id;
694 enum forcewake_domains mask;
696 struct hrtimer timer;
703 } fw_domain[FW_DOMAIN_ID_COUNT];
705 int unclaimed_mmio_check;
708 /* Iterate over initialised fw domains */
709 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
710 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
711 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
713 for_each_if ((mask__) & (domain__)->mask)
715 #define for_each_fw_domain(domain__, dev_priv__) \
716 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
718 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
719 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
720 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
723 struct work_struct work;
725 uint32_t *dmc_payload;
726 uint32_t dmc_fw_size;
729 i915_reg_t mmioaddr[8];
730 uint32_t mmiodata[8];
732 uint32_t allowed_dc_mask;
735 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
736 func(is_mobile) sep \
739 func(is_i945gm) sep \
741 func(need_gfx_hws) sep \
743 func(is_pineview) sep \
744 func(is_broadwater) sep \
745 func(is_crestline) sep \
746 func(is_ivybridge) sep \
747 func(is_valleyview) sep \
748 func(is_cherryview) sep \
749 func(is_haswell) sep \
750 func(is_broadwell) sep \
751 func(is_skylake) sep \
752 func(is_broxton) sep \
753 func(is_kabylake) sep \
754 func(is_preliminary) sep \
756 func(has_pipe_cxsr) sep \
757 func(has_hotplug) sep \
758 func(cursor_needs_physical) sep \
759 func(has_overlay) sep \
760 func(overlay_needs_physical) sep \
761 func(supports_tv) sep \
763 func(has_snoop) sep \
767 #define DEFINE_FLAG(name) u8 name:1
768 #define SEP_SEMICOLON ;
770 struct intel_device_info {
771 u32 display_mmio_offset;
774 u8 num_sprites[I915_MAX_PIPES];
777 u8 ring_mask; /* Rings supported by the HW */
778 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
779 /* Register offsets for the various display pipes and transcoders */
780 int pipe_offsets[I915_MAX_TRANSCODERS];
781 int trans_offsets[I915_MAX_TRANSCODERS];
782 int palette_offsets[I915_MAX_PIPES];
783 int cursor_offsets[I915_MAX_PIPES];
785 /* Slice/subslice/EU info */
788 u8 subslice_per_slice;
791 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
794 u8 has_subslice_pg:1;
798 u16 degamma_lut_size;
806 enum i915_cache_level {
808 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
809 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
810 caches, eg sampler/render caches, and the
811 large Last-Level-Cache. LLC is coherent with
812 the CPU, but L3 is only visible to the GPU. */
813 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
816 struct i915_ctx_hang_stats {
817 /* This context had batch pending when hang was declared */
818 unsigned batch_pending;
820 /* This context had batch active when hang was declared */
821 unsigned batch_active;
823 /* Time when this context was last blamed for a GPU reset */
824 unsigned long guilty_ts;
826 /* If the contexts causes a second GPU hang within this time,
827 * it is permanently banned from submitting any more work.
829 unsigned long ban_period_seconds;
831 /* This context is banned to submit more work */
835 /* This must match up with the value previously used for execbuf2.rsvd1. */
836 #define DEFAULT_CONTEXT_HANDLE 0
839 * struct i915_gem_context - as the name implies, represents a context.
840 * @ref: reference count.
841 * @user_handle: userspace tracking identity for this context.
842 * @remap_slice: l3 row remapping information.
843 * @flags: context specific flags:
844 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
845 * @file_priv: filp associated with this context (NULL for global default
847 * @hang_stats: information about the role of this context in possible GPU
849 * @ppgtt: virtual memory space used by this context.
850 * @legacy_hw_ctx: render context backing object and whether it is correctly
851 * initialized (legacy ring submission mechanism only).
852 * @link: link in the global list of contexts.
854 * Contexts are memory images used by the hardware to store copies of their
857 struct i915_gem_context {
859 struct drm_i915_private *i915;
860 struct drm_i915_file_private *file_priv;
861 struct i915_hw_ppgtt *ppgtt;
863 struct i915_ctx_hang_stats hang_stats;
865 /* Unique identifier for this context, used by the hw for tracking */
869 #define CONTEXT_NO_ZEROMAP (1<<0)
871 struct intel_context {
872 struct drm_i915_gem_object *state;
873 struct intel_ringbuffer *ringbuf;
874 struct i915_vma *lrc_vma;
875 uint32_t *lrc_reg_state;
879 } engine[I915_NUM_ENGINES];
881 struct list_head link;
895 /* This is always the inner lock when overlapping with struct_mutex and
896 * it's the outer lock when overlapping with stolen_lock. */
899 unsigned int possible_framebuffer_bits;
900 unsigned int busy_bits;
901 unsigned int visible_pipes_mask;
902 struct intel_crtc *crtc;
904 struct drm_mm_node compressed_fb;
905 struct drm_mm_node *compressed_llb;
912 struct intel_fbc_state_cache {
914 unsigned int mode_flags;
915 uint32_t hsw_bdw_pixel_rate;
919 unsigned int rotation;
927 uint32_t pixel_format;
930 unsigned int tiling_mode;
934 struct intel_fbc_reg_params {
938 unsigned int fence_y_offset;
943 uint32_t pixel_format;
951 struct intel_fbc_work {
953 u32 scheduled_vblank;
954 struct work_struct work;
957 const char *no_fbc_reason;
961 * HIGH_RR is the highest eDP panel refresh rate read from EDID
962 * LOW_RR is the lowest eDP panel refresh rate found from EDID
963 * parsing for same resolution.
965 enum drrs_refresh_rate_type {
968 DRRS_MAX_RR, /* RR count */
971 enum drrs_support_type {
972 DRRS_NOT_SUPPORTED = 0,
973 STATIC_DRRS_SUPPORT = 1,
974 SEAMLESS_DRRS_SUPPORT = 2
980 struct delayed_work work;
982 unsigned busy_frontbuffer_bits;
983 enum drrs_refresh_rate_type refresh_rate_type;
984 enum drrs_support_type type;
991 struct intel_dp *enabled;
993 struct delayed_work work;
994 unsigned busy_frontbuffer_bits;
1001 PCH_NONE = 0, /* No PCH present */
1002 PCH_IBX, /* Ibexpeak PCH */
1003 PCH_CPT, /* Cougarpoint PCH */
1004 PCH_LPT, /* Lynxpoint PCH */
1005 PCH_SPT, /* Sunrisepoint PCH */
1009 enum intel_sbi_destination {
1014 #define QUIRK_PIPEA_FORCE (1<<0)
1015 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1016 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1017 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1018 #define QUIRK_PIPEB_FORCE (1<<4)
1019 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1022 struct intel_fbc_work;
1024 struct intel_gmbus {
1025 struct i2c_adapter adapter;
1026 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1029 i915_reg_t gpio_reg;
1030 struct i2c_algo_bit_data bit_algo;
1031 struct drm_i915_private *dev_priv;
1034 struct i915_suspend_saved_registers {
1037 u32 savePP_ON_DELAYS;
1038 u32 savePP_OFF_DELAYS;
1043 u32 saveFBC_CONTROL;
1044 u32 saveCACHE_MODE_0;
1045 u32 saveMI_ARB_STATE;
1049 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1050 u32 savePCH_PORT_HOTPLUG;
1054 struct vlv_s0ix_state {
1061 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1062 u32 media_max_req_count;
1063 u32 gfx_max_req_count;
1089 u32 rp_down_timeout;
1095 /* Display 1 CZ domain */
1100 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1102 /* GT SA CZ domain */
1109 /* Display 2 CZ domain */
1113 u32 clock_gate_dis2;
1116 struct intel_rps_ei {
1122 struct intel_gen6_power_mgmt {
1124 * work, interrupts_enabled and pm_iir are protected by
1125 * dev_priv->irq_lock
1127 struct work_struct work;
1128 bool interrupts_enabled;
1133 /* Frequencies are stored in potentially platform dependent multiples.
1134 * In other words, *_freq needs to be multiplied by X to be interesting.
1135 * Soft limits are those which are used for the dynamic reclocking done
1136 * by the driver (raise frequencies under heavy loads, and lower for
1137 * lighter loads). Hard limits are those imposed by the hardware.
1139 * A distinction is made for overclocking, which is never enabled by
1140 * default, and is considered to be above the hard limit if it's
1143 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1144 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1145 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1146 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1147 u8 min_freq; /* AKA RPn. Minimum frequency */
1148 u8 idle_freq; /* Frequency to request when we are idle */
1149 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1150 u8 rp1_freq; /* "less than" RP0 power/freqency */
1151 u8 rp0_freq; /* Non-overclocked max frequency. */
1152 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1154 u8 up_threshold; /* Current %busy required to uplock */
1155 u8 down_threshold; /* Current %busy required to downclock */
1158 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1160 spinlock_t client_lock;
1161 struct list_head clients;
1165 struct delayed_work delayed_resume_work;
1168 struct intel_rps_client semaphores, mmioflips;
1170 /* manual wa residency calculations */
1171 struct intel_rps_ei up_ei, down_ei;
1174 * Protects RPS/RC6 register access and PCU communication.
1175 * Must be taken after struct_mutex if nested. Note that
1176 * this lock may be held for long periods of time when
1177 * talking to hw - so only take it when talking to hw!
1179 struct mutex hw_lock;
1182 /* defined intel_pm.c */
1183 extern spinlock_t mchdev_lock;
1185 struct intel_ilk_power_mgmt {
1193 unsigned long last_time1;
1194 unsigned long chipset_power;
1197 unsigned long gfx_power;
1204 struct drm_i915_private;
1205 struct i915_power_well;
1207 struct i915_power_well_ops {
1209 * Synchronize the well's hw state to match the current sw state, for
1210 * example enable/disable it based on the current refcount. Called
1211 * during driver init and resume time, possibly after first calling
1212 * the enable/disable handlers.
1214 void (*sync_hw)(struct drm_i915_private *dev_priv,
1215 struct i915_power_well *power_well);
1217 * Enable the well and resources that depend on it (for example
1218 * interrupts located on the well). Called after the 0->1 refcount
1221 void (*enable)(struct drm_i915_private *dev_priv,
1222 struct i915_power_well *power_well);
1224 * Disable the well and resources that depend on it. Called after
1225 * the 1->0 refcount transition.
1227 void (*disable)(struct drm_i915_private *dev_priv,
1228 struct i915_power_well *power_well);
1229 /* Returns the hw enabled state. */
1230 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1231 struct i915_power_well *power_well);
1234 /* Power well structure for haswell */
1235 struct i915_power_well {
1238 /* power well enable/disable usage count */
1240 /* cached hw enabled state */
1242 unsigned long domains;
1244 const struct i915_power_well_ops *ops;
1247 struct i915_power_domains {
1249 * Power wells needed for initialization at driver init and suspend
1250 * time are on. They are kept on until after the first modeset.
1254 int power_well_count;
1257 int domain_use_count[POWER_DOMAIN_NUM];
1258 struct i915_power_well *power_wells;
1261 #define MAX_L3_SLICES 2
1262 struct intel_l3_parity {
1263 u32 *remap_info[MAX_L3_SLICES];
1264 struct work_struct error_work;
1268 struct i915_gem_mm {
1269 /** Memory allocator for GTT stolen memory */
1270 struct drm_mm stolen;
1271 /** Protects the usage of the GTT stolen memory allocator. This is
1272 * always the inner lock when overlapping with struct_mutex. */
1273 struct mutex stolen_lock;
1275 /** List of all objects in gtt_space. Used to restore gtt
1276 * mappings on resume */
1277 struct list_head bound_list;
1279 * List of objects which are not bound to the GTT (thus
1280 * are idle and not used by the GPU) but still have
1281 * (presumably uncached) pages still attached.
1283 struct list_head unbound_list;
1285 /** Usable portion of the GTT for GEM */
1286 unsigned long stolen_base; /* limited to low memory (32-bit) */
1288 /** PPGTT used for aliasing the PPGTT with the GTT */
1289 struct i915_hw_ppgtt *aliasing_ppgtt;
1291 struct notifier_block oom_notifier;
1292 struct notifier_block vmap_notifier;
1293 struct shrinker shrinker;
1294 bool shrinker_no_lock_stealing;
1296 /** LRU list of objects with fence regs on them. */
1297 struct list_head fence_list;
1300 * We leave the user IRQ off as much as possible,
1301 * but this means that requests will finish and never
1302 * be retired once the system goes idle. Set a timer to
1303 * fire periodically while the ring is running. When it
1304 * fires, go retire requests.
1306 struct delayed_work retire_work;
1309 * When we detect an idle GPU, we want to turn on
1310 * powersaving features. So once we see that there
1311 * are no more requests outstanding and no more
1312 * arrive within a small period of time, we fire
1313 * off the idle_work.
1315 struct delayed_work idle_work;
1318 * Are we in a non-interruptible section of code like
1324 * Is the GPU currently considered idle, or busy executing userspace
1325 * requests? Whilst idle, we attempt to power down the hardware and
1326 * display clocks. In order to reduce the effect on performance, there
1327 * is a slight delay before we do so.
1331 /* the indicator for dispatch video commands on two BSD rings */
1332 unsigned int bsd_ring_dispatch_index;
1334 /** Bit 6 swizzling required for X tiling */
1335 uint32_t bit_6_swizzle_x;
1336 /** Bit 6 swizzling required for Y tiling */
1337 uint32_t bit_6_swizzle_y;
1339 /* accounting, useful for userland debugging */
1340 spinlock_t object_stat_lock;
1341 size_t object_memory;
1345 struct drm_i915_error_state_buf {
1346 struct drm_i915_private *i915;
1355 struct i915_error_state_file_priv {
1356 struct drm_device *dev;
1357 struct drm_i915_error_state *error;
1360 struct i915_gpu_error {
1361 /* For hangcheck timer */
1362 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1363 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1364 /* Hang gpu twice in this window and your context gets banned */
1365 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1367 struct workqueue_struct *hangcheck_wq;
1368 struct delayed_work hangcheck_work;
1370 /* For reset and error_state handling. */
1372 /* Protected by the above dev->gpu_error.lock. */
1373 struct drm_i915_error_state *first_error;
1375 unsigned long missed_irq_rings;
1378 * State variable controlling the reset flow and count
1380 * This is a counter which gets incremented when reset is triggered,
1381 * and again when reset has been handled. So odd values (lowest bit set)
1382 * means that reset is in progress and even values that
1383 * (reset_counter >> 1):th reset was successfully completed.
1385 * If reset is not completed succesfully, the I915_WEDGE bit is
1386 * set meaning that hardware is terminally sour and there is no
1387 * recovery. All waiters on the reset_queue will be woken when
1390 * This counter is used by the wait_seqno code to notice that reset
1391 * event happened and it needs to restart the entire ioctl (since most
1392 * likely the seqno it waited for won't ever signal anytime soon).
1394 * This is important for lock-free wait paths, where no contended lock
1395 * naturally enforces the correct ordering between the bail-out of the
1396 * waiter and the gpu reset work code.
1398 atomic_t reset_counter;
1400 #define I915_RESET_IN_PROGRESS_FLAG 1
1401 #define I915_WEDGED (1 << 31)
1404 * Waitqueue to signal when the reset has completed. Used by clients
1405 * that wait for dev_priv->mm.wedged to settle.
1407 wait_queue_head_t reset_queue;
1409 /* Userspace knobs for gpu hang simulation;
1410 * combines both a ring mask, and extra flags
1413 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1414 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1416 /* For missed irq/seqno simulation. */
1417 unsigned int test_irq_rings;
1420 enum modeset_restore {
1421 MODESET_ON_LID_OPEN,
1426 #define DP_AUX_A 0x40
1427 #define DP_AUX_B 0x10
1428 #define DP_AUX_C 0x20
1429 #define DP_AUX_D 0x30
1431 #define DDC_PIN_B 0x05
1432 #define DDC_PIN_C 0x04
1433 #define DDC_PIN_D 0x06
1435 struct ddi_vbt_port_info {
1437 * This is an index in the HDMI/DVI DDI buffer translation table.
1438 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1439 * populate this field.
1441 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1442 uint8_t hdmi_level_shift;
1444 uint8_t supports_dvi:1;
1445 uint8_t supports_hdmi:1;
1446 uint8_t supports_dp:1;
1448 uint8_t alternate_aux_channel;
1449 uint8_t alternate_ddc_pin;
1451 uint8_t dp_boost_level;
1452 uint8_t hdmi_boost_level;
1455 enum psr_lines_to_wait {
1456 PSR_0_LINES_TO_WAIT = 0,
1458 PSR_4_LINES_TO_WAIT,
1462 struct intel_vbt_data {
1463 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1464 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1467 unsigned int int_tv_support:1;
1468 unsigned int lvds_dither:1;
1469 unsigned int lvds_vbt:1;
1470 unsigned int int_crt_support:1;
1471 unsigned int lvds_use_ssc:1;
1472 unsigned int display_clock_mode:1;
1473 unsigned int fdi_rx_polarity_inverted:1;
1474 unsigned int panel_type:4;
1476 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1478 enum drrs_support_type drrs_type;
1489 struct edp_power_seq pps;
1494 bool require_aux_wakeup;
1496 enum psr_lines_to_wait lines_to_wait;
1497 int tp1_wakeup_time;
1498 int tp2_tp3_wakeup_time;
1504 bool active_low_pwm;
1505 u8 min_brightness; /* min_brightness/255 of max */
1506 enum intel_backlight_type type;
1512 struct mipi_config *config;
1513 struct mipi_pps_data *pps;
1517 const u8 *sequence[MIPI_SEQ_MAX];
1523 union child_device_config *child_dev;
1525 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1526 struct sdvo_device_mapping sdvo_mappings[2];
1529 enum intel_ddb_partitioning {
1531 INTEL_DDB_PART_5_6, /* IVB+ */
1534 struct intel_wm_level {
1542 struct ilk_wm_values {
1543 uint32_t wm_pipe[3];
1545 uint32_t wm_lp_spr[3];
1546 uint32_t wm_linetime[3];
1548 enum intel_ddb_partitioning partitioning;
1551 struct vlv_pipe_wm {
1562 struct vlv_wm_values {
1563 struct vlv_pipe_wm pipe[3];
1564 struct vlv_sr_wm sr;
1574 struct skl_ddb_entry {
1575 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1578 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1580 return entry->end - entry->start;
1583 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1584 const struct skl_ddb_entry *e2)
1586 if (e1->start == e2->start && e1->end == e2->end)
1592 struct skl_ddb_allocation {
1593 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1594 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1595 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1598 struct skl_wm_values {
1599 unsigned dirty_pipes;
1600 struct skl_ddb_allocation ddb;
1601 uint32_t wm_linetime[I915_MAX_PIPES];
1602 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1603 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1606 struct skl_wm_level {
1607 bool plane_en[I915_MAX_PLANES];
1608 uint16_t plane_res_b[I915_MAX_PLANES];
1609 uint8_t plane_res_l[I915_MAX_PLANES];
1613 * This struct helps tracking the state needed for runtime PM, which puts the
1614 * device in PCI D3 state. Notice that when this happens, nothing on the
1615 * graphics device works, even register access, so we don't get interrupts nor
1618 * Every piece of our code that needs to actually touch the hardware needs to
1619 * either call intel_runtime_pm_get or call intel_display_power_get with the
1620 * appropriate power domain.
1622 * Our driver uses the autosuspend delay feature, which means we'll only really
1623 * suspend if we stay with zero refcount for a certain amount of time. The
1624 * default value is currently very conservative (see intel_runtime_pm_enable), but
1625 * it can be changed with the standard runtime PM files from sysfs.
1627 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1628 * goes back to false exactly before we reenable the IRQs. We use this variable
1629 * to check if someone is trying to enable/disable IRQs while they're supposed
1630 * to be disabled. This shouldn't happen and we'll print some error messages in
1633 * For more, read the Documentation/power/runtime_pm.txt.
1635 struct i915_runtime_pm {
1636 atomic_t wakeref_count;
1637 atomic_t atomic_seq;
1642 enum intel_pipe_crc_source {
1643 INTEL_PIPE_CRC_SOURCE_NONE,
1644 INTEL_PIPE_CRC_SOURCE_PLANE1,
1645 INTEL_PIPE_CRC_SOURCE_PLANE2,
1646 INTEL_PIPE_CRC_SOURCE_PF,
1647 INTEL_PIPE_CRC_SOURCE_PIPE,
1648 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1649 INTEL_PIPE_CRC_SOURCE_TV,
1650 INTEL_PIPE_CRC_SOURCE_DP_B,
1651 INTEL_PIPE_CRC_SOURCE_DP_C,
1652 INTEL_PIPE_CRC_SOURCE_DP_D,
1653 INTEL_PIPE_CRC_SOURCE_AUTO,
1654 INTEL_PIPE_CRC_SOURCE_MAX,
1657 struct intel_pipe_crc_entry {
1662 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1663 struct intel_pipe_crc {
1665 bool opened; /* exclusive access to the result file */
1666 struct intel_pipe_crc_entry *entries;
1667 enum intel_pipe_crc_source source;
1669 wait_queue_head_t wq;
1672 struct i915_frontbuffer_tracking {
1676 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1683 struct i915_wa_reg {
1686 /* bitmask representing WA bits */
1691 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1692 * allowing it for RCS as we don't foresee any requirement of having
1693 * a whitelist for other engines. When it is really required for
1694 * other engines then the limit need to be increased.
1696 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1698 struct i915_workarounds {
1699 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1701 u32 hw_whitelist_count[I915_NUM_ENGINES];
1704 struct i915_virtual_gpu {
1708 struct i915_execbuffer_params {
1709 struct drm_device *dev;
1710 struct drm_file *file;
1711 uint32_t dispatch_flags;
1712 uint32_t args_batch_start_offset;
1713 uint64_t batch_obj_vm_offset;
1714 struct intel_engine_cs *engine;
1715 struct drm_i915_gem_object *batch_obj;
1716 struct i915_gem_context *ctx;
1717 struct drm_i915_gem_request *request;
1720 /* used in computing the new watermarks state */
1721 struct intel_wm_config {
1722 unsigned int num_pipes_active;
1723 bool sprites_enabled;
1724 bool sprites_scaled;
1727 struct drm_i915_private {
1728 struct drm_device *dev;
1729 struct kmem_cache *objects;
1730 struct kmem_cache *vmas;
1731 struct kmem_cache *requests;
1733 const struct intel_device_info info;
1735 int relative_constants_mode;
1739 struct intel_uncore uncore;
1741 struct i915_virtual_gpu vgpu;
1743 struct intel_guc guc;
1745 struct intel_csr csr;
1747 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1749 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1750 * controller on different i2c buses. */
1751 struct mutex gmbus_mutex;
1754 * Base address of the gmbus and gpio block.
1756 uint32_t gpio_mmio_base;
1758 /* MMIO base address for MIPI regs */
1759 uint32_t mipi_mmio_base;
1761 uint32_t psr_mmio_base;
1763 wait_queue_head_t gmbus_wait_queue;
1765 struct pci_dev *bridge_dev;
1766 struct i915_gem_context *kernel_context;
1767 struct intel_engine_cs engine[I915_NUM_ENGINES];
1768 struct drm_i915_gem_object *semaphore_obj;
1769 uint32_t last_seqno, next_seqno;
1771 struct drm_dma_handle *status_page_dmah;
1772 struct resource mch_res;
1774 /* protects the irq masks */
1775 spinlock_t irq_lock;
1777 /* protects the mmio flip data */
1778 spinlock_t mmio_flip_lock;
1780 bool display_irqs_enabled;
1782 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1783 struct pm_qos_request pm_qos;
1785 /* Sideband mailbox protection */
1786 struct mutex sb_lock;
1788 /** Cached value of IMR to avoid reads in updating the bitfield */
1791 u32 de_irq_mask[I915_MAX_PIPES];
1796 u32 pipestat_irq_mask[I915_MAX_PIPES];
1798 struct i915_hotplug hotplug;
1799 struct intel_fbc fbc;
1800 struct i915_drrs drrs;
1801 struct intel_opregion opregion;
1802 struct intel_vbt_data vbt;
1804 bool preserve_bios_swizzle;
1807 struct intel_overlay *overlay;
1809 /* backlight registers and fields in struct intel_panel */
1810 struct mutex backlight_lock;
1813 bool no_aux_handshake;
1815 /* protects panel power sequencer state */
1816 struct mutex pps_mutex;
1818 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1819 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1821 unsigned int fsb_freq, mem_freq, is_ddr3;
1822 unsigned int skl_preferred_vco_freq;
1823 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1824 unsigned int max_dotclk_freq;
1825 unsigned int rawclk_freq;
1826 unsigned int hpll_freq;
1827 unsigned int czclk_freq;
1830 unsigned int vco, ref;
1834 * wq - Driver workqueue for GEM.
1836 * NOTE: Work items scheduled here are not allowed to grab any modeset
1837 * locks, for otherwise the flushing done in the pageflip code will
1838 * result in deadlocks.
1840 struct workqueue_struct *wq;
1842 /* Display functions */
1843 struct drm_i915_display_funcs display;
1845 /* PCH chipset type */
1846 enum intel_pch pch_type;
1847 unsigned short pch_id;
1849 unsigned long quirks;
1851 enum modeset_restore modeset_restore;
1852 struct mutex modeset_restore_lock;
1853 struct drm_atomic_state *modeset_restore_state;
1855 struct list_head vm_list; /* Global list of all address spaces */
1856 struct i915_ggtt ggtt; /* VM representing the global address space */
1858 struct i915_gem_mm mm;
1859 DECLARE_HASHTABLE(mm_structs, 7);
1860 struct mutex mm_lock;
1862 /* The hw wants to have a stable context identifier for the lifetime
1863 * of the context (for OA, PASID, faults, etc). This is limited
1864 * in execlists to 21 bits.
1866 struct ida context_hw_ida;
1867 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1869 /* Kernel Modesetting */
1871 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1872 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1873 wait_queue_head_t pending_flip_queue;
1875 #ifdef CONFIG_DEBUG_FS
1876 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1879 /* dpll and cdclk state is protected by connection_mutex */
1880 int num_shared_dpll;
1881 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1882 const struct intel_dpll_mgr *dpll_mgr;
1885 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1886 * Must be global rather than per dpll, because on some platforms
1887 * plls share registers.
1889 struct mutex dpll_lock;
1891 unsigned int active_crtcs;
1892 unsigned int min_pixclk[I915_MAX_PIPES];
1894 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1896 struct i915_workarounds workarounds;
1898 struct i915_frontbuffer_tracking fb_tracking;
1902 bool mchbar_need_disable;
1904 struct intel_l3_parity l3_parity;
1906 /* Cannot be determined by PCIID. You must always read a register. */
1909 /* gen6+ rps state */
1910 struct intel_gen6_power_mgmt rps;
1912 /* ilk-only ips/rps state. Everything in here is protected by the global
1913 * mchdev_lock in intel_pm.c */
1914 struct intel_ilk_power_mgmt ips;
1916 struct i915_power_domains power_domains;
1918 struct i915_psr psr;
1920 struct i915_gpu_error gpu_error;
1922 struct drm_i915_gem_object *vlv_pctx;
1924 #ifdef CONFIG_DRM_FBDEV_EMULATION
1925 /* list of fbdev register on this device */
1926 struct intel_fbdev *fbdev;
1927 struct work_struct fbdev_suspend_work;
1930 struct drm_property *broadcast_rgb_property;
1931 struct drm_property *force_audio_property;
1933 /* hda/i915 audio component */
1934 struct i915_audio_component *audio_component;
1935 bool audio_component_registered;
1937 * av_mutex - mutex for audio/video sync
1940 struct mutex av_mutex;
1942 uint32_t hw_context_size;
1943 struct list_head context_list;
1947 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1948 u32 chv_phy_control;
1950 * Shadows for CHV DPLL_MD regs to keep the state
1951 * checker somewhat working in the presence hardware
1952 * crappiness (can't read out DPLL_MD for pipes B & C).
1954 u32 chv_dpll_md[I915_MAX_PIPES];
1958 bool suspended_to_idle;
1959 struct i915_suspend_saved_registers regfile;
1960 struct vlv_s0ix_state vlv_s0ix_state;
1964 * Raw watermark latency values:
1965 * in 0.1us units for WM0,
1966 * in 0.5us units for WM1+.
1969 uint16_t pri_latency[5];
1971 uint16_t spr_latency[5];
1973 uint16_t cur_latency[5];
1975 * Raw watermark memory latency values
1976 * for SKL for all 8 levels
1979 uint16_t skl_latency[8];
1982 * The skl_wm_values structure is a bit too big for stack
1983 * allocation, so we keep the staging struct where we store
1984 * intermediate results here instead.
1986 struct skl_wm_values skl_results;
1988 /* current hardware state */
1990 struct ilk_wm_values hw;
1991 struct skl_wm_values skl_hw;
1992 struct vlv_wm_values vlv;
1998 * Should be held around atomic WM register writing; also
1999 * protects * intel_crtc->wm.active and
2000 * cstate->wm.need_postvbl_update.
2002 struct mutex wm_mutex;
2005 * Set during HW readout of watermarks/DDB. Some platforms
2006 * need to know when we're still using BIOS-provided values
2007 * (which we don't fully trust).
2009 bool distrust_bios_wm;
2012 struct i915_runtime_pm pm;
2014 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2016 int (*execbuf_submit)(struct i915_execbuffer_params *params,
2017 struct drm_i915_gem_execbuffer2 *args,
2018 struct list_head *vmas);
2019 int (*init_engines)(struct drm_device *dev);
2020 void (*cleanup_engine)(struct intel_engine_cs *engine);
2021 void (*stop_engine)(struct intel_engine_cs *engine);
2024 /* perform PHY state sanity checks? */
2025 bool chv_phy_assert[2];
2027 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2030 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2031 * will be rejected. Instead look for a better place.
2035 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2037 return dev->dev_private;
2040 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2042 return to_i915(dev_get_drvdata(dev));
2045 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2047 return container_of(guc, struct drm_i915_private, guc);
2050 /* Simple iterator over all initialised engines */
2051 #define for_each_engine(engine__, dev_priv__) \
2052 for ((engine__) = &(dev_priv__)->engine[0]; \
2053 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2055 for_each_if (intel_engine_initialized(engine__))
2057 /* Iterator with engine_id */
2058 #define for_each_engine_id(engine__, dev_priv__, id__) \
2059 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2060 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2062 for_each_if (((id__) = (engine__)->id, \
2063 intel_engine_initialized(engine__)))
2065 /* Iterator over subset of engines selected by mask */
2066 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2067 for ((engine__) = &(dev_priv__)->engine[0]; \
2068 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2070 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2071 intel_engine_initialized(engine__))
2073 enum hdmi_force_audio {
2074 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2075 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2076 HDMI_AUDIO_AUTO, /* trust EDID */
2077 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2080 #define I915_GTT_OFFSET_NONE ((u32)-1)
2082 struct drm_i915_gem_object_ops {
2084 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2086 /* Interface between the GEM object and its backing storage.
2087 * get_pages() is called once prior to the use of the associated set
2088 * of pages before to binding them into the GTT, and put_pages() is
2089 * called after we no longer need them. As we expect there to be
2090 * associated cost with migrating pages between the backing storage
2091 * and making them available for the GPU (e.g. clflush), we may hold
2092 * onto the pages after they are no longer referenced by the GPU
2093 * in case they may be used again shortly (for example migrating the
2094 * pages to a different memory domain within the GTT). put_pages()
2095 * will therefore most likely be called when the object itself is
2096 * being released or under memory pressure (where we attempt to
2097 * reap pages for the shrinker).
2099 int (*get_pages)(struct drm_i915_gem_object *);
2100 void (*put_pages)(struct drm_i915_gem_object *);
2102 int (*dmabuf_export)(struct drm_i915_gem_object *);
2103 void (*release)(struct drm_i915_gem_object *);
2107 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2108 * considered to be the frontbuffer for the given plane interface-wise. This
2109 * doesn't mean that the hw necessarily already scans it out, but that any
2110 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2112 * We have one bit per pipe and per scanout plane type.
2114 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2115 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2116 #define INTEL_FRONTBUFFER_BITS \
2117 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2118 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2119 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2120 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2121 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2122 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2123 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2124 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2125 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2126 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2127 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2129 struct drm_i915_gem_object {
2130 struct drm_gem_object base;
2132 const struct drm_i915_gem_object_ops *ops;
2134 /** List of VMAs backed by this object */
2135 struct list_head vma_list;
2137 /** Stolen memory for this object, instead of being backed by shmem. */
2138 struct drm_mm_node *stolen;
2139 struct list_head global_list;
2141 struct list_head engine_list[I915_NUM_ENGINES];
2142 /** Used in execbuf to temporarily hold a ref */
2143 struct list_head obj_exec_link;
2145 struct list_head batch_pool_link;
2148 * This is set if the object is on the active lists (has pending
2149 * rendering and so a non-zero seqno), and is not set if it i s on
2150 * inactive (ready to be unbound) list.
2152 unsigned int active:I915_NUM_ENGINES;
2155 * This is set if the object has been written to since last bound
2158 unsigned int dirty:1;
2161 * Fence register bits (if any) for this object. Will be set
2162 * as needed when mapped into the GTT.
2163 * Protected by dev->struct_mutex.
2165 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2168 * Advice: are the backing pages purgeable?
2170 unsigned int madv:2;
2173 * Current tiling mode for the object.
2175 unsigned int tiling_mode:2;
2177 * Whether the tiling parameters for the currently associated fence
2178 * register have changed. Note that for the purposes of tracking
2179 * tiling changes we also treat the unfenced register, the register
2180 * slot that the object occupies whilst it executes a fenced
2181 * command (such as BLT on gen2/3), as a "fence".
2183 unsigned int fence_dirty:1;
2186 * Is the object at the current location in the gtt mappable and
2187 * fenceable? Used to avoid costly recalculations.
2189 unsigned int map_and_fenceable:1;
2192 * Whether the current gtt mapping needs to be mappable (and isn't just
2193 * mappable by accident). Track pin and fault separate for a more
2194 * accurate mappable working set.
2196 unsigned int fault_mappable:1;
2199 * Is the object to be mapped as read-only to the GPU
2200 * Only honoured if hardware has relevant pte bit
2202 unsigned long gt_ro:1;
2203 unsigned int cache_level:3;
2204 unsigned int cache_dirty:1;
2206 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2208 unsigned int pin_display;
2210 struct sg_table *pages;
2211 int pages_pin_count;
2213 struct scatterlist *sg;
2218 /** Breadcrumb of last rendering to the buffer.
2219 * There can only be one writer, but we allow for multiple readers.
2220 * If there is a writer that necessarily implies that all other
2221 * read requests are complete - but we may only be lazily clearing
2222 * the read requests. A read request is naturally the most recent
2223 * request on a ring, so we may have two different write and read
2224 * requests on one ring where the write request is older than the
2225 * read request. This allows for the CPU to read from an active
2226 * buffer by only waiting for the write to complete.
2228 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2229 struct drm_i915_gem_request *last_write_req;
2230 /** Breadcrumb of last fenced GPU access to the buffer. */
2231 struct drm_i915_gem_request *last_fenced_req;
2233 /** Current tiling stride for the object, if it's tiled. */
2236 /** References from framebuffers, locks out tiling changes. */
2237 unsigned long framebuffer_references;
2239 /** Record of address bit 17 of each page at last unbind. */
2240 unsigned long *bit_17;
2243 /** for phy allocated objects */
2244 struct drm_dma_handle *phys_handle;
2246 struct i915_gem_userptr {
2248 unsigned read_only :1;
2249 unsigned workers :4;
2250 #define I915_GEM_USERPTR_MAX_WORKERS 15
2252 struct i915_mm_struct *mm;
2253 struct i915_mmu_object *mmu_object;
2254 struct work_struct *work;
2258 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2261 * Optimised SGL iterator for GEM objects
2263 static __always_inline struct sgt_iter {
2264 struct scatterlist *sgp;
2271 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2272 struct sgt_iter s = { .sgp = sgl };
2275 s.max = s.curr = s.sgp->offset;
2276 s.max += s.sgp->length;
2278 s.dma = sg_dma_address(s.sgp);
2280 s.pfn = page_to_pfn(sg_page(s.sgp));
2287 * __sg_next - return the next scatterlist entry in a list
2288 * @sg: The current sg entry
2291 * If the entry is the last, return NULL; otherwise, step to the next
2292 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2293 * otherwise just return the pointer to the current element.
2295 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2297 #ifdef CONFIG_DEBUG_SG
2298 BUG_ON(sg->sg_magic != SG_MAGIC);
2300 return sg_is_last(sg) ? NULL :
2301 likely(!sg_is_chain(++sg)) ? sg :
2306 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2307 * @__dmap: DMA address (output)
2308 * @__iter: 'struct sgt_iter' (iterator state, internal)
2309 * @__sgt: sg_table to iterate over (input)
2311 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2312 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2313 ((__dmap) = (__iter).dma + (__iter).curr); \
2314 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2315 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2318 * for_each_sgt_page - iterate over the pages of the given sg_table
2319 * @__pp: page pointer (output)
2320 * @__iter: 'struct sgt_iter' (iterator state, internal)
2321 * @__sgt: sg_table to iterate over (input)
2323 #define for_each_sgt_page(__pp, __iter, __sgt) \
2324 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2325 ((__pp) = (__iter).pfn == 0 ? NULL : \
2326 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2327 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2328 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2331 * Request queue structure.
2333 * The request queue allows us to note sequence numbers that have been emitted
2334 * and may be associated with active buffers to be retired.
2336 * By keeping this list, we can avoid having to do questionable sequence
2337 * number comparisons on buffer last_read|write_seqno. It also allows an
2338 * emission time to be associated with the request for tracking how far ahead
2339 * of the GPU the submission is.
2341 * The requests are reference counted, so upon creation they should have an
2342 * initial reference taken using kref_init
2344 struct drm_i915_gem_request {
2347 /** On Which ring this request was generated */
2348 struct drm_i915_private *i915;
2349 struct intel_engine_cs *engine;
2350 unsigned reset_counter;
2352 /** GEM sequence number associated with the previous request,
2353 * when the HWS breadcrumb is equal to this the GPU is processing
2358 /** GEM sequence number associated with this request,
2359 * when the HWS breadcrumb is equal or greater than this the GPU
2360 * has finished processing this request.
2364 /** Position in the ringbuffer of the start of the request */
2368 * Position in the ringbuffer of the start of the postfix.
2369 * This is required to calculate the maximum available ringbuffer
2370 * space without overwriting the postfix.
2374 /** Position in the ringbuffer of the end of the whole request */
2377 /** Preallocate space in the ringbuffer for the emitting the request */
2381 * Context and ring buffer related to this request
2382 * Contexts are refcounted, so when this request is associated with a
2383 * context, we must increment the context's refcount, to guarantee that
2384 * it persists while any request is linked to it. Requests themselves
2385 * are also refcounted, so the request will only be freed when the last
2386 * reference to it is dismissed, and the code in
2387 * i915_gem_request_free() will then decrement the refcount on the
2390 struct i915_gem_context *ctx;
2391 struct intel_ringbuffer *ringbuf;
2394 * Context related to the previous request.
2395 * As the contexts are accessed by the hardware until the switch is
2396 * completed to a new context, the hardware may still be writing
2397 * to the context object after the breadcrumb is visible. We must
2398 * not unpin/unbind/prune that object whilst still active and so
2399 * we keep the previous context pinned until the following (this)
2400 * request is retired.
2402 struct i915_gem_context *previous_context;
2404 /** Batch buffer related to this request if any (used for
2405 error state dump only) */
2406 struct drm_i915_gem_object *batch_obj;
2408 /** Time at which this request was emitted, in jiffies. */
2409 unsigned long emitted_jiffies;
2411 /** global list entry for this request */
2412 struct list_head list;
2414 struct drm_i915_file_private *file_priv;
2415 /** file_priv list entry for this request */
2416 struct list_head client_list;
2418 /** process identifier submitting this request */
2422 * The ELSP only accepts two elements at a time, so we queue
2423 * context/tail pairs on a given queue (ring->execlist_queue) until the
2424 * hardware is available. The queue serves a double purpose: we also use
2425 * it to keep track of the up to 2 contexts currently in the hardware
2426 * (usually one in execution and the other queued up by the GPU): We
2427 * only remove elements from the head of the queue when the hardware
2428 * informs us that an element has been completed.
2430 * All accesses to the queue are mediated by a spinlock
2431 * (ring->execlist_lock).
2434 /** Execlist link in the submission queue.*/
2435 struct list_head execlist_link;
2437 /** Execlists no. of times this request has been sent to the ELSP */
2440 /** Execlists context hardware id. */
2444 struct drm_i915_gem_request * __must_check
2445 i915_gem_request_alloc(struct intel_engine_cs *engine,
2446 struct i915_gem_context *ctx);
2447 void i915_gem_request_free(struct kref *req_ref);
2448 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2449 struct drm_file *file);
2451 static inline uint32_t
2452 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2454 return req ? req->seqno : 0;
2457 static inline struct intel_engine_cs *
2458 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2460 return req ? req->engine : NULL;
2463 static inline struct drm_i915_gem_request *
2464 i915_gem_request_reference(struct drm_i915_gem_request *req)
2467 kref_get(&req->ref);
2472 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2474 kref_put(&req->ref, i915_gem_request_free);
2477 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2478 struct drm_i915_gem_request *src)
2481 i915_gem_request_reference(src);
2484 i915_gem_request_unreference(*pdst);
2490 * XXX: i915_gem_request_completed should be here but currently needs the
2491 * definition of i915_seqno_passed() which is below. It will be moved in
2492 * a later patch when the call to i915_seqno_passed() is obsoleted...
2496 * A command that requires special handling by the command parser.
2498 struct drm_i915_cmd_descriptor {
2500 * Flags describing how the command parser processes the command.
2502 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2503 * a length mask if not set
2504 * CMD_DESC_SKIP: The command is allowed but does not follow the
2505 * standard length encoding for the opcode range in
2507 * CMD_DESC_REJECT: The command is never allowed
2508 * CMD_DESC_REGISTER: The command should be checked against the
2509 * register whitelist for the appropriate ring
2510 * CMD_DESC_MASTER: The command is allowed if the submitting process
2514 #define CMD_DESC_FIXED (1<<0)
2515 #define CMD_DESC_SKIP (1<<1)
2516 #define CMD_DESC_REJECT (1<<2)
2517 #define CMD_DESC_REGISTER (1<<3)
2518 #define CMD_DESC_BITMASK (1<<4)
2519 #define CMD_DESC_MASTER (1<<5)
2522 * The command's unique identification bits and the bitmask to get them.
2523 * This isn't strictly the opcode field as defined in the spec and may
2524 * also include type, subtype, and/or subop fields.
2532 * The command's length. The command is either fixed length (i.e. does
2533 * not include a length field) or has a length field mask. The flag
2534 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2535 * a length mask. All command entries in a command table must include
2536 * length information.
2544 * Describes where to find a register address in the command to check
2545 * against the ring's register whitelist. Only valid if flags has the
2546 * CMD_DESC_REGISTER bit set.
2548 * A non-zero step value implies that the command may access multiple
2549 * registers in sequence (e.g. LRI), in that case step gives the
2550 * distance in dwords between individual offset fields.
2558 #define MAX_CMD_DESC_BITMASKS 3
2560 * Describes command checks where a particular dword is masked and
2561 * compared against an expected value. If the command does not match
2562 * the expected value, the parser rejects it. Only valid if flags has
2563 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2566 * If the check specifies a non-zero condition_mask then the parser
2567 * only performs the check when the bits specified by condition_mask
2574 u32 condition_offset;
2576 } bits[MAX_CMD_DESC_BITMASKS];
2580 * A table of commands requiring special handling by the command parser.
2582 * Each ring has an array of tables. Each table consists of an array of command
2583 * descriptors, which must be sorted with command opcodes in ascending order.
2585 struct drm_i915_cmd_table {
2586 const struct drm_i915_cmd_descriptor *table;
2590 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2591 #define __I915__(p) ({ \
2592 struct drm_i915_private *__p; \
2593 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2594 __p = (struct drm_i915_private *)p; \
2595 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2596 __p = to_i915((struct drm_device *)p); \
2601 #define INTEL_INFO(p) (&__I915__(p)->info)
2602 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2603 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2605 #define REVID_FOREVER 0xff
2606 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2608 #define GEN_FOREVER (0)
2610 * Returns true if Gen is in inclusive range [Start, End].
2612 * Use GEN_FOREVER for unbound start and or end.
2614 #define IS_GEN(p, s, e) ({ \
2615 unsigned int __s = (s), __e = (e); \
2616 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2617 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2618 if ((__s) != GEN_FOREVER) \
2620 if ((__e) == GEN_FOREVER) \
2621 __e = BITS_PER_LONG - 1; \
2624 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2628 * Return true if revision is in range [since,until] inclusive.
2630 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2632 #define IS_REVID(p, since, until) \
2633 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2635 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2636 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2637 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2638 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2639 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2640 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2641 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2642 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2643 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2644 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2645 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2646 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2647 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2648 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2649 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2650 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2651 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2652 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2653 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2654 INTEL_DEVID(dev) == 0x0152 || \
2655 INTEL_DEVID(dev) == 0x015a)
2656 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2657 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2658 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2659 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2660 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2661 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2662 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2663 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2664 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2665 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2666 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2667 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2668 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2669 (INTEL_DEVID(dev) & 0xf) == 0xe))
2670 /* ULX machines are also considered ULT. */
2671 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2672 (INTEL_DEVID(dev) & 0xf) == 0xe)
2673 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2674 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2675 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2676 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2677 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2678 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2679 /* ULX machines are also considered ULT. */
2680 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2681 INTEL_DEVID(dev) == 0x0A1E)
2682 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2683 INTEL_DEVID(dev) == 0x1913 || \
2684 INTEL_DEVID(dev) == 0x1916 || \
2685 INTEL_DEVID(dev) == 0x1921 || \
2686 INTEL_DEVID(dev) == 0x1926)
2687 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2688 INTEL_DEVID(dev) == 0x1915 || \
2689 INTEL_DEVID(dev) == 0x191E)
2690 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2691 INTEL_DEVID(dev) == 0x5913 || \
2692 INTEL_DEVID(dev) == 0x5916 || \
2693 INTEL_DEVID(dev) == 0x5921 || \
2694 INTEL_DEVID(dev) == 0x5926)
2695 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2696 INTEL_DEVID(dev) == 0x5915 || \
2697 INTEL_DEVID(dev) == 0x591E)
2698 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2699 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2700 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2701 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2703 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2705 #define SKL_REVID_A0 0x0
2706 #define SKL_REVID_B0 0x1
2707 #define SKL_REVID_C0 0x2
2708 #define SKL_REVID_D0 0x3
2709 #define SKL_REVID_E0 0x4
2710 #define SKL_REVID_F0 0x5
2712 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2714 #define BXT_REVID_A0 0x0
2715 #define BXT_REVID_A1 0x1
2716 #define BXT_REVID_B0 0x3
2717 #define BXT_REVID_C0 0x9
2719 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2722 * The genX designation typically refers to the render engine, so render
2723 * capability related checks should use IS_GEN, while display and other checks
2724 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2727 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen_mask & BIT(1))
2728 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen_mask & BIT(2))
2729 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen_mask & BIT(3))
2730 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen_mask & BIT(4))
2731 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen_mask & BIT(5))
2732 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen_mask & BIT(6))
2733 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
2734 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
2736 #define RENDER_RING (1<<RCS)
2737 #define BSD_RING (1<<VCS)
2738 #define BLT_RING (1<<BCS)
2739 #define VEBOX_RING (1<<VECS)
2740 #define BSD2_RING (1<<VCS2)
2741 #define ALL_ENGINES (~0)
2743 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2744 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2745 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2746 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2747 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2748 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2749 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2750 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2752 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2754 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2755 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2756 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2757 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2758 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2760 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2761 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2763 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2764 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2766 /* WaRsDisableCoarsePowerGating:skl,bxt */
2767 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2768 IS_SKL_GT3(dev) || \
2772 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2773 * even when in MSI mode. This results in spurious interrupt warnings if the
2774 * legacy irq no. is shared with another device. The kernel then disables that
2775 * interrupt source and so prevents the other device from working properly.
2777 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2778 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2780 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2781 * rows, which changed the alignment requirements and fence programming.
2783 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2785 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2786 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2788 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2789 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2790 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2792 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2794 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2795 INTEL_INFO(dev)->gen >= 9)
2797 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2798 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2799 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2800 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2801 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2802 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2803 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2804 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2805 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2806 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2807 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2809 #define HAS_CSR(dev) (IS_GEN9(dev))
2812 * For now, anything with a GuC requires uCode loading, and then supports
2813 * command submission once loaded. But these are logically independent
2814 * properties, so we have separate macros to test them.
2816 #define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2817 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2818 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2820 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2821 INTEL_INFO(dev)->gen >= 8)
2823 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2824 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2827 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2828 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2829 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2830 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2831 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2832 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2833 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2834 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2835 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2836 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2837 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2839 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2840 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2841 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2842 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2843 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2844 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2845 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2846 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2847 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2849 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2850 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2852 /* DPF == dynamic parity feature */
2853 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2854 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2856 #define GT_FREQUENCY_MULTIPLIER 50
2857 #define GEN9_FREQ_SCALER 3
2859 #include "i915_trace.h"
2861 extern const struct drm_ioctl_desc i915_ioctls[];
2862 extern int i915_max_ioctl;
2864 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2865 extern int i915_resume_switcheroo(struct drm_device *dev);
2867 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2872 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2873 const char *fmt, ...);
2875 #define i915_report_error(dev_priv, fmt, ...) \
2876 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2878 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2879 extern int i915_driver_unload(struct drm_device *);
2880 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2881 extern void i915_driver_lastclose(struct drm_device * dev);
2882 extern void i915_driver_preclose(struct drm_device *dev,
2883 struct drm_file *file);
2884 extern void i915_driver_postclose(struct drm_device *dev,
2885 struct drm_file *file);
2886 #ifdef CONFIG_COMPAT
2887 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2890 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2891 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2892 extern int i915_reset(struct drm_i915_private *dev_priv);
2893 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2894 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2895 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2896 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2897 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2898 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2899 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2901 /* intel_hotplug.c */
2902 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2903 u32 pin_mask, u32 long_mask);
2904 void intel_hpd_init(struct drm_i915_private *dev_priv);
2905 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2906 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2907 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2910 void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
2912 void i915_handle_error(struct drm_i915_private *dev_priv,
2914 const char *fmt, ...);
2916 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2917 int intel_irq_install(struct drm_i915_private *dev_priv);
2918 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2920 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2921 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2922 bool restore_forcewake);
2923 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2924 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2925 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2926 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2927 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2929 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2930 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2931 enum forcewake_domains domains);
2932 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2933 enum forcewake_domains domains);
2934 /* Like above but the caller must manage the uncore.lock itself.
2935 * Must be used with I915_READ_FW and friends.
2937 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2938 enum forcewake_domains domains);
2939 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2940 enum forcewake_domains domains);
2941 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2943 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2944 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2946 return dev_priv->vgpu.active;
2950 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2954 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2957 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2958 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2959 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2962 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2963 uint32_t interrupt_mask,
2964 uint32_t enabled_irq_mask);
2966 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2968 ilk_update_display_irq(dev_priv, bits, bits);
2971 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2973 ilk_update_display_irq(dev_priv, bits, 0);
2975 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2977 uint32_t interrupt_mask,
2978 uint32_t enabled_irq_mask);
2979 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2980 enum pipe pipe, uint32_t bits)
2982 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2984 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2985 enum pipe pipe, uint32_t bits)
2987 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2989 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2990 uint32_t interrupt_mask,
2991 uint32_t enabled_irq_mask);
2993 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2995 ibx_display_interrupt_update(dev_priv, bits, bits);
2998 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3000 ibx_display_interrupt_update(dev_priv, bits, 0);
3005 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3006 struct drm_file *file_priv);
3007 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3008 struct drm_file *file_priv);
3009 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3010 struct drm_file *file_priv);
3011 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3012 struct drm_file *file_priv);
3013 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3014 struct drm_file *file_priv);
3015 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3016 struct drm_file *file_priv);
3017 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3018 struct drm_file *file_priv);
3019 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
3020 struct drm_i915_gem_request *req);
3021 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
3022 struct drm_i915_gem_execbuffer2 *args,
3023 struct list_head *vmas);
3024 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3025 struct drm_file *file_priv);
3026 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3027 struct drm_file *file_priv);
3028 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3029 struct drm_file *file_priv);
3030 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3031 struct drm_file *file);
3032 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3033 struct drm_file *file);
3034 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3035 struct drm_file *file_priv);
3036 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3037 struct drm_file *file_priv);
3038 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3039 struct drm_file *file_priv);
3040 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3041 struct drm_file *file_priv);
3042 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3043 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3044 struct drm_file *file);
3045 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3046 struct drm_file *file_priv);
3047 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3048 struct drm_file *file_priv);
3049 void i915_gem_load_init(struct drm_device *dev);
3050 void i915_gem_load_cleanup(struct drm_device *dev);
3051 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3052 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3054 void *i915_gem_object_alloc(struct drm_device *dev);
3055 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3056 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3057 const struct drm_i915_gem_object_ops *ops);
3058 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3060 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3061 struct drm_device *dev, const void *data, size_t size);
3062 void i915_gem_free_object(struct drm_gem_object *obj);
3063 void i915_gem_vma_destroy(struct i915_vma *vma);
3065 /* Flags used by pin/bind&friends. */
3066 #define PIN_MAPPABLE (1<<0)
3067 #define PIN_NONBLOCK (1<<1)
3068 #define PIN_GLOBAL (1<<2)
3069 #define PIN_OFFSET_BIAS (1<<3)
3070 #define PIN_USER (1<<4)
3071 #define PIN_UPDATE (1<<5)
3072 #define PIN_ZONE_4G (1<<6)
3073 #define PIN_HIGH (1<<7)
3074 #define PIN_OFFSET_FIXED (1<<8)
3075 #define PIN_OFFSET_MASK (~4095)
3077 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3078 struct i915_address_space *vm,
3082 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3083 const struct i915_ggtt_view *view,
3087 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3089 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3090 int __must_check i915_vma_unbind(struct i915_vma *vma);
3092 * BEWARE: Do not use the function below unless you can _absolutely_
3093 * _guarantee_ VMA in question is _not in use_ anywhere.
3095 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3096 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3097 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3098 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3100 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3101 int *needs_clflush);
3103 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3105 static inline int __sg_page_count(struct scatterlist *sg)
3107 return sg->length >> PAGE_SHIFT;
3111 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3113 static inline struct page *
3114 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3116 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3119 if (n < obj->get_page.last) {
3120 obj->get_page.sg = obj->pages->sgl;
3121 obj->get_page.last = 0;
3124 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3125 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3126 if (unlikely(sg_is_chain(obj->get_page.sg)))
3127 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3130 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3133 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3135 BUG_ON(obj->pages == NULL);
3136 obj->pages_pin_count++;
3139 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3141 BUG_ON(obj->pages_pin_count == 0);
3142 obj->pages_pin_count--;
3146 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3147 * @obj - the object to map into kernel address space
3149 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3150 * pages and then returns a contiguous mapping of the backing storage into
3151 * the kernel address space.
3153 * The caller must hold the struct_mutex, and is responsible for calling
3154 * i915_gem_object_unpin_map() when the mapping is no longer required.
3156 * Returns the pointer through which to access the mapped object, or an
3157 * ERR_PTR() on error.
3159 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3162 * i915_gem_object_unpin_map - releases an earlier mapping
3163 * @obj - the object to unmap
3165 * After pinning the object and mapping its pages, once you are finished
3166 * with your access, call i915_gem_object_unpin_map() to release the pin
3167 * upon the mapping. Once the pin count reaches zero, that mapping may be
3170 * The caller must hold the struct_mutex.
3172 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3174 lockdep_assert_held(&obj->base.dev->struct_mutex);
3175 i915_gem_object_unpin_pages(obj);
3178 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3179 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3180 struct intel_engine_cs *to,
3181 struct drm_i915_gem_request **to_req);
3182 void i915_vma_move_to_active(struct i915_vma *vma,
3183 struct drm_i915_gem_request *req);
3184 int i915_gem_dumb_create(struct drm_file *file_priv,
3185 struct drm_device *dev,
3186 struct drm_mode_create_dumb *args);
3187 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3188 uint32_t handle, uint64_t *offset);
3190 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3191 struct drm_i915_gem_object *new,
3192 unsigned frontbuffer_bits);
3195 * Returns true if seq1 is later than seq2.
3198 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3200 return (int32_t)(seq1 - seq2) >= 0;
3203 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3204 bool lazy_coherency)
3206 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3207 req->engine->irq_seqno_barrier(req->engine);
3208 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3209 req->previous_seqno);
3212 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3213 bool lazy_coherency)
3215 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3216 req->engine->irq_seqno_barrier(req->engine);
3217 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3221 int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
3222 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3224 struct drm_i915_gem_request *
3225 i915_gem_find_active_request(struct intel_engine_cs *engine);
3227 bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3228 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3230 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3232 return atomic_read(&error->reset_counter);
3235 static inline bool __i915_reset_in_progress(u32 reset)
3237 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3240 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3242 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3245 static inline bool __i915_terminally_wedged(u32 reset)
3247 return unlikely(reset & I915_WEDGED);
3250 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3252 return __i915_reset_in_progress(i915_reset_counter(error));
3255 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3257 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3260 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3262 return __i915_terminally_wedged(i915_reset_counter(error));
3265 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3267 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3270 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3272 return dev_priv->gpu_error.stop_rings == 0 ||
3273 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3276 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3278 return dev_priv->gpu_error.stop_rings == 0 ||
3279 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3282 void i915_gem_reset(struct drm_device *dev);
3283 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3284 int __must_check i915_gem_init(struct drm_device *dev);
3285 int i915_gem_init_engines(struct drm_device *dev);
3286 int __must_check i915_gem_init_hw(struct drm_device *dev);
3287 void i915_gem_init_swizzling(struct drm_device *dev);
3288 void i915_gem_cleanup_engines(struct drm_device *dev);
3289 int __must_check i915_gpu_idle(struct drm_device *dev);
3290 int __must_check i915_gem_suspend(struct drm_device *dev);
3291 void __i915_add_request(struct drm_i915_gem_request *req,
3292 struct drm_i915_gem_object *batch_obj,
3294 #define i915_add_request(req) \
3295 __i915_add_request(req, NULL, true)
3296 #define i915_add_request_no_flush(req) \
3297 __i915_add_request(req, NULL, false)
3298 int __i915_wait_request(struct drm_i915_gem_request *req,
3301 struct intel_rps_client *rps);
3302 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3303 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3305 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3308 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3311 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3313 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3315 const struct i915_ggtt_view *view);
3316 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3317 const struct i915_ggtt_view *view);
3318 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3320 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3321 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3324 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3326 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3327 int tiling_mode, bool fenced);
3329 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3330 enum i915_cache_level cache_level);
3332 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3333 struct dma_buf *dma_buf);
3335 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3336 struct drm_gem_object *gem_obj, int flags);
3338 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3339 const struct i915_ggtt_view *view);
3340 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3341 struct i915_address_space *vm);
3343 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3345 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3348 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3349 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3350 const struct i915_ggtt_view *view);
3351 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3352 struct i915_address_space *vm);
3355 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3356 struct i915_address_space *vm);
3358 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3359 const struct i915_ggtt_view *view);
3362 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3363 struct i915_address_space *vm);
3365 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3366 const struct i915_ggtt_view *view);
3368 static inline struct i915_vma *
3369 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3371 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3373 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3375 /* Some GGTT VM helpers */
3376 static inline struct i915_hw_ppgtt *
3377 i915_vm_to_ppgtt(struct i915_address_space *vm)
3379 return container_of(vm, struct i915_hw_ppgtt, base);
3383 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3385 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3389 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
3391 static inline int __must_check
3392 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3396 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3397 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3399 return i915_gem_object_pin(obj, &ggtt->base,
3400 alignment, flags | PIN_GLOBAL);
3403 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3404 const struct i915_ggtt_view *view);
3406 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3408 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3411 /* i915_gem_fence.c */
3412 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3413 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3415 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3416 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3418 void i915_gem_restore_fences(struct drm_device *dev);
3420 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3421 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3422 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3424 /* i915_gem_context.c */
3425 int __must_check i915_gem_context_init(struct drm_device *dev);
3426 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3427 void i915_gem_context_fini(struct drm_device *dev);
3428 void i915_gem_context_reset(struct drm_device *dev);
3429 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3430 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3431 int i915_switch_context(struct drm_i915_gem_request *req);
3432 void i915_gem_context_free(struct kref *ctx_ref);
3433 struct drm_i915_gem_object *
3434 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3436 static inline struct i915_gem_context *
3437 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3439 struct i915_gem_context *ctx;
3441 lockdep_assert_held(&file_priv->dev_priv->dev->struct_mutex);
3443 ctx = idr_find(&file_priv->context_idr, id);
3445 return ERR_PTR(-ENOENT);
3450 static inline void i915_gem_context_reference(struct i915_gem_context *ctx)
3452 kref_get(&ctx->ref);
3455 static inline void i915_gem_context_unreference(struct i915_gem_context *ctx)
3457 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
3458 kref_put(&ctx->ref, i915_gem_context_free);
3461 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3463 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3466 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3467 struct drm_file *file);
3468 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3469 struct drm_file *file);
3470 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3471 struct drm_file *file_priv);
3472 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3473 struct drm_file *file_priv);
3474 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3475 struct drm_file *file);
3477 /* i915_gem_evict.c */
3478 int __must_check i915_gem_evict_something(struct drm_device *dev,
3479 struct i915_address_space *vm,
3482 unsigned cache_level,
3483 unsigned long start,
3486 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3487 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3489 /* belongs in i915_gem_gtt.h */
3490 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3492 if (INTEL_GEN(dev_priv) < 6)
3493 intel_gtt_chipset_flush();
3496 /* i915_gem_stolen.c */
3497 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3498 struct drm_mm_node *node, u64 size,
3499 unsigned alignment);
3500 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3501 struct drm_mm_node *node, u64 size,
3502 unsigned alignment, u64 start,
3504 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3505 struct drm_mm_node *node);
3506 int i915_gem_init_stolen(struct drm_device *dev);
3507 void i915_gem_cleanup_stolen(struct drm_device *dev);
3508 struct drm_i915_gem_object *
3509 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3510 struct drm_i915_gem_object *
3511 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3516 /* i915_gem_shrinker.c */
3517 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3518 unsigned long target,
3520 #define I915_SHRINK_PURGEABLE 0x1
3521 #define I915_SHRINK_UNBOUND 0x2
3522 #define I915_SHRINK_BOUND 0x4
3523 #define I915_SHRINK_ACTIVE 0x8
3524 #define I915_SHRINK_VMAPS 0x10
3525 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3526 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3527 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3530 /* i915_gem_tiling.c */
3531 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3533 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3535 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3536 obj->tiling_mode != I915_TILING_NONE;
3539 /* i915_gem_debug.c */
3541 int i915_verify_lists(struct drm_device *dev);
3543 #define i915_verify_lists(dev) 0
3546 /* i915_debugfs.c */
3547 int i915_debugfs_init(struct drm_minor *minor);
3548 void i915_debugfs_cleanup(struct drm_minor *minor);
3549 #ifdef CONFIG_DEBUG_FS
3550 int i915_debugfs_connector_add(struct drm_connector *connector);
3551 void intel_display_crc_init(struct drm_device *dev);
3553 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3555 static inline void intel_display_crc_init(struct drm_device *dev) {}
3558 /* i915_gpu_error.c */
3560 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3561 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3562 const struct i915_error_state_file_priv *error);
3563 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3564 struct drm_i915_private *i915,
3565 size_t count, loff_t pos);
3566 static inline void i915_error_state_buf_release(
3567 struct drm_i915_error_state_buf *eb)
3571 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3573 const char *error_msg);
3574 void i915_error_state_get(struct drm_device *dev,
3575 struct i915_error_state_file_priv *error_priv);
3576 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3577 void i915_destroy_error_state(struct drm_device *dev);
3579 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3580 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3582 /* i915_cmd_parser.c */
3583 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3584 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3585 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3586 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3587 int i915_parse_cmds(struct intel_engine_cs *engine,
3588 struct drm_i915_gem_object *batch_obj,
3589 struct drm_i915_gem_object *shadow_batch_obj,
3590 u32 batch_start_offset,
3594 /* i915_suspend.c */
3595 extern int i915_save_state(struct drm_device *dev);
3596 extern int i915_restore_state(struct drm_device *dev);
3599 void i915_setup_sysfs(struct drm_device *dev_priv);
3600 void i915_teardown_sysfs(struct drm_device *dev_priv);
3603 extern int intel_setup_gmbus(struct drm_device *dev);
3604 extern void intel_teardown_gmbus(struct drm_device *dev);
3605 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3608 extern struct i2c_adapter *
3609 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3610 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3611 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3612 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3614 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3616 extern void intel_i2c_reset(struct drm_device *dev);
3619 int intel_bios_init(struct drm_i915_private *dev_priv);
3620 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3621 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3622 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3623 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3624 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3625 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3626 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3629 /* intel_opregion.c */
3631 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3632 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3633 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3634 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3635 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3637 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3639 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3641 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3642 static inline void intel_opregion_init(struct drm_i915_private *dev) { }
3643 static inline void intel_opregion_fini(struct drm_i915_private *dev) { }
3644 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3648 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3653 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3657 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3665 extern void intel_register_dsm_handler(void);
3666 extern void intel_unregister_dsm_handler(void);
3668 static inline void intel_register_dsm_handler(void) { return; }
3669 static inline void intel_unregister_dsm_handler(void) { return; }
3670 #endif /* CONFIG_ACPI */
3673 extern void intel_modeset_init_hw(struct drm_device *dev);
3674 extern void intel_modeset_init(struct drm_device *dev);
3675 extern void intel_modeset_gem_init(struct drm_device *dev);
3676 extern void intel_modeset_cleanup(struct drm_device *dev);
3677 extern void intel_connector_unregister(struct drm_connector *);
3678 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3679 extern void intel_display_resume(struct drm_device *dev);
3680 extern void i915_redisable_vga(struct drm_device *dev);
3681 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3682 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3683 extern void intel_init_pch_refclk(struct drm_device *dev);
3684 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3685 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3687 extern void intel_detect_pch(struct drm_device *dev);
3689 extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
3690 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3691 struct drm_file *file);
3694 extern struct intel_overlay_error_state *
3695 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3696 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3697 struct intel_overlay_error_state *error);
3699 extern struct intel_display_error_state *
3700 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3701 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3702 struct drm_device *dev,
3703 struct intel_display_error_state *error);
3705 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3706 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3708 /* intel_sideband.c */
3709 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3710 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3711 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3712 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3713 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3714 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3715 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3716 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3717 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3718 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3719 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3720 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3721 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3722 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3723 enum intel_sbi_destination destination);
3724 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3725 enum intel_sbi_destination destination);
3726 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3727 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3729 /* intel_dpio_phy.c */
3730 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3731 u32 deemph_reg_value, u32 margin_reg_value,
3732 bool uniq_trans_scale);
3733 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3735 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3736 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3737 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3738 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3740 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3741 u32 demph_reg_value, u32 preemph_reg_value,
3742 u32 uniqtranscale_reg_value, u32 tx3_demph);
3743 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3744 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3745 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3747 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3748 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3750 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3751 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3753 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3754 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3755 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3756 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3758 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3759 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3760 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3761 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3763 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3764 * will be implemented using 2 32-bit writes in an arbitrary order with
3765 * an arbitrary delay between them. This can cause the hardware to
3766 * act upon the intermediate value, possibly leading to corruption and
3767 * machine death. You have been warned.
3769 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3770 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3772 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3773 u32 upper, lower, old_upper, loop = 0; \
3774 upper = I915_READ(upper_reg); \
3776 old_upper = upper; \
3777 lower = I915_READ(lower_reg); \
3778 upper = I915_READ(upper_reg); \
3779 } while (upper != old_upper && loop++ < 2); \
3780 (u64)upper << 32 | lower; })
3782 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3783 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3785 #define __raw_read(x, s) \
3786 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3789 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3792 #define __raw_write(x, s) \
3793 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3794 i915_reg_t reg, uint##x##_t val) \
3796 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3811 /* These are untraced mmio-accessors that are only valid to be used inside
3812 * criticial sections inside IRQ handlers where forcewake is explicitly
3814 * Think twice, and think again, before using these.
3815 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3816 * intel_uncore_forcewake_irqunlock().
3818 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3819 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3820 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3822 /* "Broadcast RGB" property */
3823 #define INTEL_BROADCAST_RGB_AUTO 0
3824 #define INTEL_BROADCAST_RGB_FULL 1
3825 #define INTEL_BROADCAST_RGB_LIMITED 2
3827 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3829 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3830 return VLV_VGACNTRL;
3831 else if (INTEL_INFO(dev)->gen >= 5)
3832 return CPU_VGACNTRL;
3837 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3839 unsigned long j = msecs_to_jiffies(m);
3841 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3844 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3846 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3849 static inline unsigned long
3850 timespec_to_jiffies_timeout(const struct timespec *value)
3852 unsigned long j = timespec_to_jiffies(value);
3854 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3858 * If you need to wait X milliseconds between events A and B, but event B
3859 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3860 * when event A happened, then just before event B you call this function and
3861 * pass the timestamp as the first argument, and X as the second argument.
3864 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3866 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3869 * Don't re-read the value of "jiffies" every time since it may change
3870 * behind our back and break the math.
3872 tmp_jiffies = jiffies;
3873 target_jiffies = timestamp_jiffies +
3874 msecs_to_jiffies_timeout(to_wait_ms);
3876 if (time_after(target_jiffies, tmp_jiffies)) {
3877 remaining_jiffies = target_jiffies - tmp_jiffies;
3878 while (remaining_jiffies)
3880 schedule_timeout_uninterruptible(remaining_jiffies);
3884 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3885 struct drm_i915_gem_request *req)
3887 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3888 i915_gem_request_assign(&engine->trace_irq_req, req);