1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
56 #include "intel_dpll_mgr.h"
58 /* General customization:
61 #define DRIVER_NAME "i915"
62 #define DRIVER_DESC "Intel Graphics"
63 #define DRIVER_DATE "20160411"
66 /* Many gcc seem to no see through this and fall over :( */
68 #define WARN_ON(x) ({ \
69 bool __i915_warn_cond = (x); \
70 if (__builtin_constant_p(__i915_warn_cond)) \
71 BUILD_BUG_ON(__i915_warn_cond); \
72 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
74 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
78 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
80 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
81 (long) (x), __func__);
83 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
84 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
85 * which may not necessarily be a user visible problem. This will either
86 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
87 * enable distros and users to tailor their preferred amount of i915 abrt
90 #define I915_STATE_WARN(condition, format...) ({ \
91 int __ret_warn_on = !!(condition); \
92 if (unlikely(__ret_warn_on)) \
93 if (!WARN(i915.verbose_state_checks, format)) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(x) \
99 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
101 bool __i915_inject_load_failure(const char *func, int line);
102 #define i915_inject_load_failure() \
103 __i915_inject_load_failure(__func__, __LINE__)
105 static inline const char *yesno(bool v)
107 return v ? "yes" : "no";
110 static inline const char *onoff(bool v)
112 return v ? "on" : "off";
121 I915_MAX_PIPES = _PIPE_EDP
123 #define pipe_name(p) ((p) + 'A')
135 static inline const char *transcoder_name(enum transcoder transcoder)
137 switch (transcoder) {
146 case TRANSCODER_DSI_A:
148 case TRANSCODER_DSI_C:
155 static inline bool transcoder_is_dsi(enum transcoder transcoder)
157 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
161 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
162 * number of planes per CRTC. Not all platforms really have this many planes,
163 * which means some arrays of size I915_MAX_PLANES may have unused entries
164 * between the topmost sprite plane and the cursor plane.
173 #define plane_name(p) ((p) + 'A')
175 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
185 #define port_name(p) ((p) + 'A')
187 #define I915_NUM_PHYS_VLV 2
199 enum intel_display_power_domain {
203 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
204 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
205 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
206 POWER_DOMAIN_TRANSCODER_A,
207 POWER_DOMAIN_TRANSCODER_B,
208 POWER_DOMAIN_TRANSCODER_C,
209 POWER_DOMAIN_TRANSCODER_EDP,
210 POWER_DOMAIN_TRANSCODER_DSI_A,
211 POWER_DOMAIN_TRANSCODER_DSI_C,
212 POWER_DOMAIN_PORT_DDI_A_LANES,
213 POWER_DOMAIN_PORT_DDI_B_LANES,
214 POWER_DOMAIN_PORT_DDI_C_LANES,
215 POWER_DOMAIN_PORT_DDI_D_LANES,
216 POWER_DOMAIN_PORT_DDI_E_LANES,
217 POWER_DOMAIN_PORT_DSI,
218 POWER_DOMAIN_PORT_CRT,
219 POWER_DOMAIN_PORT_OTHER,
228 POWER_DOMAIN_MODESET,
234 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
235 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
236 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
237 #define POWER_DOMAIN_TRANSCODER(tran) \
238 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
239 (tran) + POWER_DOMAIN_TRANSCODER_A)
243 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
255 #define for_each_hpd_pin(__pin) \
256 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
258 struct i915_hotplug {
259 struct work_struct hotplug_work;
262 unsigned long last_jiffies;
267 HPD_MARK_DISABLED = 2
269 } stats[HPD_NUM_PINS];
271 struct delayed_work reenable_work;
273 struct intel_digital_port *irq_port[I915_MAX_PORTS];
276 struct work_struct dig_port_work;
279 * if we get a HPD irq from DP and a HPD irq from non-DP
280 * the non-DP HPD could block the workqueue on a mode config
281 * mutex getting, that userspace may have taken. However
282 * userspace is waiting on the DP workqueue to run which is
283 * blocked behind the non-DP one.
285 struct workqueue_struct *dp_wq;
288 #define I915_GEM_GPU_DOMAINS \
289 (I915_GEM_DOMAIN_RENDER | \
290 I915_GEM_DOMAIN_SAMPLER | \
291 I915_GEM_DOMAIN_COMMAND | \
292 I915_GEM_DOMAIN_INSTRUCTION | \
293 I915_GEM_DOMAIN_VERTEX)
295 #define for_each_pipe(__dev_priv, __p) \
296 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
297 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
298 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
299 for_each_if ((__mask) & (1 << (__p)))
300 #define for_each_plane(__dev_priv, __pipe, __p) \
302 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
304 #define for_each_sprite(__dev_priv, __p, __s) \
306 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
309 #define for_each_port_masked(__port, __ports_mask) \
310 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
311 for_each_if ((__ports_mask) & (1 << (__port)))
313 #define for_each_crtc(dev, crtc) \
314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
316 #define for_each_intel_plane(dev, intel_plane) \
317 list_for_each_entry(intel_plane, \
318 &dev->mode_config.plane_list, \
321 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
322 list_for_each_entry(intel_plane, \
323 &(dev)->mode_config.plane_list, \
325 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
327 #define for_each_intel_crtc(dev, intel_crtc) \
328 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
330 #define for_each_intel_encoder(dev, intel_encoder) \
331 list_for_each_entry(intel_encoder, \
332 &(dev)->mode_config.encoder_list, \
335 #define for_each_intel_connector(dev, intel_connector) \
336 list_for_each_entry(intel_connector, \
337 &dev->mode_config.connector_list, \
340 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
341 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
342 for_each_if ((intel_encoder)->base.crtc == (__crtc))
344 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
345 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
346 for_each_if ((intel_connector)->base.encoder == (__encoder))
348 #define for_each_power_domain(domain, mask) \
349 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
350 for_each_if ((1 << (domain)) & (mask))
352 struct drm_i915_private;
353 struct i915_mm_struct;
354 struct i915_mmu_object;
356 struct drm_i915_file_private {
357 struct drm_i915_private *dev_priv;
358 struct drm_file *file;
362 struct list_head request_list;
363 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
364 * chosen to prevent the CPU getting more than a frame ahead of the GPU
365 * (when using lax throttling for the frontbuffer). We also use it to
366 * offer free GPU waitboosts for severely congested workloads.
368 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
370 struct idr context_idr;
372 struct intel_rps_client {
373 struct list_head link;
377 unsigned int bsd_ring;
380 /* Used by dp and fdi links */
381 struct intel_link_m_n {
389 void intel_link_compute_m_n(int bpp, int nlanes,
390 int pixel_clock, int link_clock,
391 struct intel_link_m_n *m_n);
393 /* Interface history:
396 * 1.2: Add Power Management
397 * 1.3: Add vblank support
398 * 1.4: Fix cmdbuffer path, add heap destroy
399 * 1.5: Add vblank pipe configuration
400 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
401 * - Support vertical blank on secondary display pipe
403 #define DRIVER_MAJOR 1
404 #define DRIVER_MINOR 6
405 #define DRIVER_PATCHLEVEL 0
407 #define WATCH_LISTS 0
409 struct opregion_header;
410 struct opregion_acpi;
411 struct opregion_swsci;
412 struct opregion_asle;
414 struct intel_opregion {
415 struct opregion_header *header;
416 struct opregion_acpi *acpi;
417 struct opregion_swsci *swsci;
418 u32 swsci_gbda_sub_functions;
419 u32 swsci_sbcb_sub_functions;
420 struct opregion_asle *asle;
425 struct work_struct asle_work;
427 #define OPREGION_SIZE (8*1024)
429 struct intel_overlay;
430 struct intel_overlay_error_state;
432 #define I915_FENCE_REG_NONE -1
433 #define I915_MAX_NUM_FENCES 32
434 /* 32 fences + sign bit for FENCE_REG_NONE */
435 #define I915_MAX_NUM_FENCE_BITS 6
437 struct drm_i915_fence_reg {
438 struct list_head lru_list;
439 struct drm_i915_gem_object *obj;
443 struct sdvo_device_mapping {
452 struct intel_display_error_state;
454 struct drm_i915_error_state {
463 /* Generic register state */
471 u32 error; /* gen6+ */
472 u32 err_int; /* gen7 */
473 u32 fault_data0; /* gen8, gen9 */
474 u32 fault_data1; /* gen8, gen9 */
480 u32 extra_instdone[I915_NUM_INSTDONE_REG];
481 u64 fence[I915_MAX_NUM_FENCES];
482 struct intel_overlay_error_state *overlay;
483 struct intel_display_error_state *display;
484 struct drm_i915_error_object *semaphore_obj;
486 struct drm_i915_error_ring {
488 /* Software tracked state */
491 enum intel_ring_hangcheck_action hangcheck_action;
494 /* our own tracking of ring head and tail */
499 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
518 u32 rc_psmi; /* sleep state */
519 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
521 struct drm_i915_error_object {
525 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
527 struct drm_i915_error_object *wa_ctx;
529 struct drm_i915_error_request {
544 char comm[TASK_COMM_LEN];
545 } ring[I915_NUM_ENGINES];
547 struct drm_i915_error_buffer {
550 u32 rseqno[I915_NUM_ENGINES], wseqno;
554 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
562 } **active_bo, **pinned_bo;
564 u32 *active_bo_count, *pinned_bo_count;
568 struct intel_connector;
569 struct intel_encoder;
570 struct intel_crtc_state;
571 struct intel_initial_plane_config;
576 struct drm_i915_display_funcs {
577 int (*get_display_clock_speed)(struct drm_device *dev);
578 int (*get_fifo_size)(struct drm_device *dev, int plane);
579 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
580 int (*compute_intermediate_wm)(struct drm_device *dev,
581 struct intel_crtc *intel_crtc,
582 struct intel_crtc_state *newstate);
583 void (*initial_watermarks)(struct intel_crtc_state *cstate);
584 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
585 void (*update_wm)(struct drm_crtc *crtc);
586 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
587 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
588 /* Returns the active state of the crtc, and if the crtc is active,
589 * fills out the pipe-config with the hw state. */
590 bool (*get_pipe_config)(struct intel_crtc *,
591 struct intel_crtc_state *);
592 void (*get_initial_plane_config)(struct intel_crtc *,
593 struct intel_initial_plane_config *);
594 int (*crtc_compute_clock)(struct intel_crtc *crtc,
595 struct intel_crtc_state *crtc_state);
596 void (*crtc_enable)(struct drm_crtc *crtc);
597 void (*crtc_disable)(struct drm_crtc *crtc);
598 void (*audio_codec_enable)(struct drm_connector *connector,
599 struct intel_encoder *encoder,
600 const struct drm_display_mode *adjusted_mode);
601 void (*audio_codec_disable)(struct intel_encoder *encoder);
602 void (*fdi_link_train)(struct drm_crtc *crtc);
603 void (*init_clock_gating)(struct drm_device *dev);
604 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
605 struct drm_framebuffer *fb,
606 struct drm_i915_gem_object *obj,
607 struct drm_i915_gem_request *req,
609 void (*hpd_irq_setup)(struct drm_device *dev);
610 /* clock updates for mode set */
612 /* render clock increase/decrease */
613 /* display clock increase/decrease */
614 /* pll clock increase/decrease */
616 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
617 void (*load_luts)(struct drm_crtc_state *crtc_state);
620 enum forcewake_domain_id {
621 FW_DOMAIN_ID_RENDER = 0,
622 FW_DOMAIN_ID_BLITTER,
628 enum forcewake_domains {
629 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
630 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
631 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
632 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
637 #define FW_REG_READ (1)
638 #define FW_REG_WRITE (2)
640 enum forcewake_domains
641 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
642 i915_reg_t reg, unsigned int op);
644 struct intel_uncore_funcs {
645 void (*force_wake_get)(struct drm_i915_private *dev_priv,
646 enum forcewake_domains domains);
647 void (*force_wake_put)(struct drm_i915_private *dev_priv,
648 enum forcewake_domains domains);
650 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
651 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
652 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
653 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
655 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
656 uint8_t val, bool trace);
657 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
658 uint16_t val, bool trace);
659 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
660 uint32_t val, bool trace);
661 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
662 uint64_t val, bool trace);
665 struct intel_uncore {
666 spinlock_t lock; /** lock is also taken in irq contexts. */
668 struct intel_uncore_funcs funcs;
671 enum forcewake_domains fw_domains;
673 struct intel_uncore_forcewake_domain {
674 struct drm_i915_private *i915;
675 enum forcewake_domain_id id;
676 enum forcewake_domains mask;
678 struct hrtimer timer;
685 } fw_domain[FW_DOMAIN_ID_COUNT];
687 int unclaimed_mmio_check;
690 /* Iterate over initialised fw domains */
691 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
692 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
693 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
695 for_each_if ((mask__) & (domain__)->mask)
697 #define for_each_fw_domain(domain__, dev_priv__) \
698 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
700 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
701 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
702 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
705 struct work_struct work;
707 uint32_t *dmc_payload;
708 uint32_t dmc_fw_size;
711 i915_reg_t mmioaddr[8];
712 uint32_t mmiodata[8];
714 uint32_t allowed_dc_mask;
717 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
718 func(is_mobile) sep \
721 func(is_i945gm) sep \
723 func(need_gfx_hws) sep \
725 func(is_pineview) sep \
726 func(is_broadwater) sep \
727 func(is_crestline) sep \
728 func(is_ivybridge) sep \
729 func(is_valleyview) sep \
730 func(is_cherryview) sep \
731 func(is_haswell) sep \
732 func(is_skylake) sep \
733 func(is_broxton) sep \
734 func(is_kabylake) sep \
735 func(is_preliminary) sep \
737 func(has_pipe_cxsr) sep \
738 func(has_hotplug) sep \
739 func(cursor_needs_physical) sep \
740 func(has_overlay) sep \
741 func(overlay_needs_physical) sep \
742 func(supports_tv) sep \
744 func(has_snoop) sep \
748 #define DEFINE_FLAG(name) u8 name:1
749 #define SEP_SEMICOLON ;
751 struct intel_device_info {
752 u32 display_mmio_offset;
755 u8 num_sprites[I915_MAX_PIPES];
757 u8 ring_mask; /* Rings supported by the HW */
758 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
759 /* Register offsets for the various display pipes and transcoders */
760 int pipe_offsets[I915_MAX_TRANSCODERS];
761 int trans_offsets[I915_MAX_TRANSCODERS];
762 int palette_offsets[I915_MAX_PIPES];
763 int cursor_offsets[I915_MAX_PIPES];
765 /* Slice/subslice/EU info */
768 u8 subslice_per_slice;
771 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
774 u8 has_subslice_pg:1;
778 u16 degamma_lut_size;
786 enum i915_cache_level {
788 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
789 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
790 caches, eg sampler/render caches, and the
791 large Last-Level-Cache. LLC is coherent with
792 the CPU, but L3 is only visible to the GPU. */
793 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
796 struct i915_ctx_hang_stats {
797 /* This context had batch pending when hang was declared */
798 unsigned batch_pending;
800 /* This context had batch active when hang was declared */
801 unsigned batch_active;
803 /* Time when this context was last blamed for a GPU reset */
804 unsigned long guilty_ts;
806 /* If the contexts causes a second GPU hang within this time,
807 * it is permanently banned from submitting any more work.
809 unsigned long ban_period_seconds;
811 /* This context is banned to submit more work */
815 /* This must match up with the value previously used for execbuf2.rsvd1. */
816 #define DEFAULT_CONTEXT_HANDLE 0
818 #define CONTEXT_NO_ZEROMAP (1<<0)
820 * struct intel_context - as the name implies, represents a context.
821 * @ref: reference count.
822 * @user_handle: userspace tracking identity for this context.
823 * @remap_slice: l3 row remapping information.
824 * @flags: context specific flags:
825 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
826 * @file_priv: filp associated with this context (NULL for global default
828 * @hang_stats: information about the role of this context in possible GPU
830 * @ppgtt: virtual memory space used by this context.
831 * @legacy_hw_ctx: render context backing object and whether it is correctly
832 * initialized (legacy ring submission mechanism only).
833 * @link: link in the global list of contexts.
835 * Contexts are memory images used by the hardware to store copies of their
838 struct intel_context {
842 struct drm_i915_private *i915;
844 struct drm_i915_file_private *file_priv;
845 struct i915_ctx_hang_stats hang_stats;
846 struct i915_hw_ppgtt *ppgtt;
848 /* Legacy ring buffer submission */
850 struct drm_i915_gem_object *rcs_state;
856 struct drm_i915_gem_object *state;
857 struct intel_ringbuffer *ringbuf;
859 struct i915_vma *lrc_vma;
861 uint32_t *lrc_reg_state;
862 } engine[I915_NUM_ENGINES];
864 struct list_head link;
876 /* This is always the inner lock when overlapping with struct_mutex and
877 * it's the outer lock when overlapping with stolen_lock. */
880 unsigned int possible_framebuffer_bits;
881 unsigned int busy_bits;
882 unsigned int visible_pipes_mask;
883 struct intel_crtc *crtc;
885 struct drm_mm_node compressed_fb;
886 struct drm_mm_node *compressed_llb;
893 struct intel_fbc_state_cache {
895 unsigned int mode_flags;
896 uint32_t hsw_bdw_pixel_rate;
900 unsigned int rotation;
908 uint32_t pixel_format;
911 unsigned int tiling_mode;
915 struct intel_fbc_reg_params {
919 unsigned int fence_y_offset;
924 uint32_t pixel_format;
932 struct intel_fbc_work {
934 u32 scheduled_vblank;
935 struct work_struct work;
938 const char *no_fbc_reason;
942 * HIGH_RR is the highest eDP panel refresh rate read from EDID
943 * LOW_RR is the lowest eDP panel refresh rate found from EDID
944 * parsing for same resolution.
946 enum drrs_refresh_rate_type {
949 DRRS_MAX_RR, /* RR count */
952 enum drrs_support_type {
953 DRRS_NOT_SUPPORTED = 0,
954 STATIC_DRRS_SUPPORT = 1,
955 SEAMLESS_DRRS_SUPPORT = 2
961 struct delayed_work work;
963 unsigned busy_frontbuffer_bits;
964 enum drrs_refresh_rate_type refresh_rate_type;
965 enum drrs_support_type type;
972 struct intel_dp *enabled;
974 struct delayed_work work;
975 unsigned busy_frontbuffer_bits;
982 PCH_NONE = 0, /* No PCH present */
983 PCH_IBX, /* Ibexpeak PCH */
984 PCH_CPT, /* Cougarpoint PCH */
985 PCH_LPT, /* Lynxpoint PCH */
986 PCH_SPT, /* Sunrisepoint PCH */
990 enum intel_sbi_destination {
995 #define QUIRK_PIPEA_FORCE (1<<0)
996 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
997 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
998 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
999 #define QUIRK_PIPEB_FORCE (1<<4)
1000 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1003 struct intel_fbc_work;
1005 struct intel_gmbus {
1006 struct i2c_adapter adapter;
1007 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1010 i915_reg_t gpio_reg;
1011 struct i2c_algo_bit_data bit_algo;
1012 struct drm_i915_private *dev_priv;
1015 struct i915_suspend_saved_registers {
1018 u32 savePP_ON_DELAYS;
1019 u32 savePP_OFF_DELAYS;
1024 u32 saveFBC_CONTROL;
1025 u32 saveCACHE_MODE_0;
1026 u32 saveMI_ARB_STATE;
1030 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1031 u32 savePCH_PORT_HOTPLUG;
1035 struct vlv_s0ix_state {
1042 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1043 u32 media_max_req_count;
1044 u32 gfx_max_req_count;
1070 u32 rp_down_timeout;
1076 /* Display 1 CZ domain */
1081 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1083 /* GT SA CZ domain */
1090 /* Display 2 CZ domain */
1094 u32 clock_gate_dis2;
1097 struct intel_rps_ei {
1103 struct intel_gen6_power_mgmt {
1105 * work, interrupts_enabled and pm_iir are protected by
1106 * dev_priv->irq_lock
1108 struct work_struct work;
1109 bool interrupts_enabled;
1112 /* Frequencies are stored in potentially platform dependent multiples.
1113 * In other words, *_freq needs to be multiplied by X to be interesting.
1114 * Soft limits are those which are used for the dynamic reclocking done
1115 * by the driver (raise frequencies under heavy loads, and lower for
1116 * lighter loads). Hard limits are those imposed by the hardware.
1118 * A distinction is made for overclocking, which is never enabled by
1119 * default, and is considered to be above the hard limit if it's
1122 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1123 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1124 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1125 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1126 u8 min_freq; /* AKA RPn. Minimum frequency */
1127 u8 idle_freq; /* Frequency to request when we are idle */
1128 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1129 u8 rp1_freq; /* "less than" RP0 power/freqency */
1130 u8 rp0_freq; /* Non-overclocked max frequency. */
1131 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1133 u8 up_threshold; /* Current %busy required to uplock */
1134 u8 down_threshold; /* Current %busy required to downclock */
1137 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1139 spinlock_t client_lock;
1140 struct list_head clients;
1144 struct delayed_work delayed_resume_work;
1147 struct intel_rps_client semaphores, mmioflips;
1149 /* manual wa residency calculations */
1150 struct intel_rps_ei up_ei, down_ei;
1153 * Protects RPS/RC6 register access and PCU communication.
1154 * Must be taken after struct_mutex if nested. Note that
1155 * this lock may be held for long periods of time when
1156 * talking to hw - so only take it when talking to hw!
1158 struct mutex hw_lock;
1161 /* defined intel_pm.c */
1162 extern spinlock_t mchdev_lock;
1164 struct intel_ilk_power_mgmt {
1172 unsigned long last_time1;
1173 unsigned long chipset_power;
1176 unsigned long gfx_power;
1183 struct drm_i915_private;
1184 struct i915_power_well;
1186 struct i915_power_well_ops {
1188 * Synchronize the well's hw state to match the current sw state, for
1189 * example enable/disable it based on the current refcount. Called
1190 * during driver init and resume time, possibly after first calling
1191 * the enable/disable handlers.
1193 void (*sync_hw)(struct drm_i915_private *dev_priv,
1194 struct i915_power_well *power_well);
1196 * Enable the well and resources that depend on it (for example
1197 * interrupts located on the well). Called after the 0->1 refcount
1200 void (*enable)(struct drm_i915_private *dev_priv,
1201 struct i915_power_well *power_well);
1203 * Disable the well and resources that depend on it. Called after
1204 * the 1->0 refcount transition.
1206 void (*disable)(struct drm_i915_private *dev_priv,
1207 struct i915_power_well *power_well);
1208 /* Returns the hw enabled state. */
1209 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1210 struct i915_power_well *power_well);
1213 /* Power well structure for haswell */
1214 struct i915_power_well {
1217 /* power well enable/disable usage count */
1219 /* cached hw enabled state */
1221 unsigned long domains;
1223 const struct i915_power_well_ops *ops;
1226 struct i915_power_domains {
1228 * Power wells needed for initialization at driver init and suspend
1229 * time are on. They are kept on until after the first modeset.
1233 int power_well_count;
1236 int domain_use_count[POWER_DOMAIN_NUM];
1237 struct i915_power_well *power_wells;
1240 #define MAX_L3_SLICES 2
1241 struct intel_l3_parity {
1242 u32 *remap_info[MAX_L3_SLICES];
1243 struct work_struct error_work;
1247 struct i915_gem_mm {
1248 /** Memory allocator for GTT stolen memory */
1249 struct drm_mm stolen;
1250 /** Protects the usage of the GTT stolen memory allocator. This is
1251 * always the inner lock when overlapping with struct_mutex. */
1252 struct mutex stolen_lock;
1254 /** List of all objects in gtt_space. Used to restore gtt
1255 * mappings on resume */
1256 struct list_head bound_list;
1258 * List of objects which are not bound to the GTT (thus
1259 * are idle and not used by the GPU) but still have
1260 * (presumably uncached) pages still attached.
1262 struct list_head unbound_list;
1264 /** Usable portion of the GTT for GEM */
1265 unsigned long stolen_base; /* limited to low memory (32-bit) */
1267 /** PPGTT used for aliasing the PPGTT with the GTT */
1268 struct i915_hw_ppgtt *aliasing_ppgtt;
1270 struct notifier_block oom_notifier;
1271 struct notifier_block vmap_notifier;
1272 struct shrinker shrinker;
1273 bool shrinker_no_lock_stealing;
1275 /** LRU list of objects with fence regs on them. */
1276 struct list_head fence_list;
1279 * We leave the user IRQ off as much as possible,
1280 * but this means that requests will finish and never
1281 * be retired once the system goes idle. Set a timer to
1282 * fire periodically while the ring is running. When it
1283 * fires, go retire requests.
1285 struct delayed_work retire_work;
1288 * When we detect an idle GPU, we want to turn on
1289 * powersaving features. So once we see that there
1290 * are no more requests outstanding and no more
1291 * arrive within a small period of time, we fire
1292 * off the idle_work.
1294 struct delayed_work idle_work;
1297 * Are we in a non-interruptible section of code like
1303 * Is the GPU currently considered idle, or busy executing userspace
1304 * requests? Whilst idle, we attempt to power down the hardware and
1305 * display clocks. In order to reduce the effect on performance, there
1306 * is a slight delay before we do so.
1310 /* the indicator for dispatch video commands on two BSD rings */
1311 unsigned int bsd_ring_dispatch_index;
1313 /** Bit 6 swizzling required for X tiling */
1314 uint32_t bit_6_swizzle_x;
1315 /** Bit 6 swizzling required for Y tiling */
1316 uint32_t bit_6_swizzle_y;
1318 /* accounting, useful for userland debugging */
1319 spinlock_t object_stat_lock;
1320 size_t object_memory;
1324 struct drm_i915_error_state_buf {
1325 struct drm_i915_private *i915;
1334 struct i915_error_state_file_priv {
1335 struct drm_device *dev;
1336 struct drm_i915_error_state *error;
1339 struct i915_gpu_error {
1340 /* For hangcheck timer */
1341 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1342 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1343 /* Hang gpu twice in this window and your context gets banned */
1344 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1346 struct workqueue_struct *hangcheck_wq;
1347 struct delayed_work hangcheck_work;
1349 /* For reset and error_state handling. */
1351 /* Protected by the above dev->gpu_error.lock. */
1352 struct drm_i915_error_state *first_error;
1354 unsigned long missed_irq_rings;
1357 * State variable controlling the reset flow and count
1359 * This is a counter which gets incremented when reset is triggered,
1360 * and again when reset has been handled. So odd values (lowest bit set)
1361 * means that reset is in progress and even values that
1362 * (reset_counter >> 1):th reset was successfully completed.
1364 * If reset is not completed succesfully, the I915_WEDGE bit is
1365 * set meaning that hardware is terminally sour and there is no
1366 * recovery. All waiters on the reset_queue will be woken when
1369 * This counter is used by the wait_seqno code to notice that reset
1370 * event happened and it needs to restart the entire ioctl (since most
1371 * likely the seqno it waited for won't ever signal anytime soon).
1373 * This is important for lock-free wait paths, where no contended lock
1374 * naturally enforces the correct ordering between the bail-out of the
1375 * waiter and the gpu reset work code.
1377 atomic_t reset_counter;
1379 #define I915_RESET_IN_PROGRESS_FLAG 1
1380 #define I915_WEDGED (1 << 31)
1383 * Waitqueue to signal when the reset has completed. Used by clients
1384 * that wait for dev_priv->mm.wedged to settle.
1386 wait_queue_head_t reset_queue;
1388 /* Userspace knobs for gpu hang simulation;
1389 * combines both a ring mask, and extra flags
1392 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1393 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1395 /* For missed irq/seqno simulation. */
1396 unsigned int test_irq_rings;
1398 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1399 bool reload_in_reset;
1402 enum modeset_restore {
1403 MODESET_ON_LID_OPEN,
1408 #define DP_AUX_A 0x40
1409 #define DP_AUX_B 0x10
1410 #define DP_AUX_C 0x20
1411 #define DP_AUX_D 0x30
1413 #define DDC_PIN_B 0x05
1414 #define DDC_PIN_C 0x04
1415 #define DDC_PIN_D 0x06
1417 struct ddi_vbt_port_info {
1419 * This is an index in the HDMI/DVI DDI buffer translation table.
1420 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1421 * populate this field.
1423 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1424 uint8_t hdmi_level_shift;
1426 uint8_t supports_dvi:1;
1427 uint8_t supports_hdmi:1;
1428 uint8_t supports_dp:1;
1430 uint8_t alternate_aux_channel;
1431 uint8_t alternate_ddc_pin;
1433 uint8_t dp_boost_level;
1434 uint8_t hdmi_boost_level;
1437 enum psr_lines_to_wait {
1438 PSR_0_LINES_TO_WAIT = 0,
1440 PSR_4_LINES_TO_WAIT,
1444 struct intel_vbt_data {
1445 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1446 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1449 unsigned int int_tv_support:1;
1450 unsigned int lvds_dither:1;
1451 unsigned int lvds_vbt:1;
1452 unsigned int int_crt_support:1;
1453 unsigned int lvds_use_ssc:1;
1454 unsigned int display_clock_mode:1;
1455 unsigned int fdi_rx_polarity_inverted:1;
1456 unsigned int panel_type:4;
1458 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1460 enum drrs_support_type drrs_type;
1471 struct edp_power_seq pps;
1476 bool require_aux_wakeup;
1478 enum psr_lines_to_wait lines_to_wait;
1479 int tp1_wakeup_time;
1480 int tp2_tp3_wakeup_time;
1486 bool active_low_pwm;
1487 u8 min_brightness; /* min_brightness/255 of max */
1493 struct mipi_config *config;
1494 struct mipi_pps_data *pps;
1498 const u8 *sequence[MIPI_SEQ_MAX];
1504 union child_device_config *child_dev;
1506 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1507 struct sdvo_device_mapping sdvo_mappings[2];
1510 enum intel_ddb_partitioning {
1512 INTEL_DDB_PART_5_6, /* IVB+ */
1515 struct intel_wm_level {
1523 struct ilk_wm_values {
1524 uint32_t wm_pipe[3];
1526 uint32_t wm_lp_spr[3];
1527 uint32_t wm_linetime[3];
1529 enum intel_ddb_partitioning partitioning;
1532 struct vlv_pipe_wm {
1543 struct vlv_wm_values {
1544 struct vlv_pipe_wm pipe[3];
1545 struct vlv_sr_wm sr;
1555 struct skl_ddb_entry {
1556 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1559 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1561 return entry->end - entry->start;
1564 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1565 const struct skl_ddb_entry *e2)
1567 if (e1->start == e2->start && e1->end == e2->end)
1573 struct skl_ddb_allocation {
1574 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1575 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1576 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1579 struct skl_wm_values {
1580 bool dirty[I915_MAX_PIPES];
1581 struct skl_ddb_allocation ddb;
1582 uint32_t wm_linetime[I915_MAX_PIPES];
1583 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1584 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1587 struct skl_wm_level {
1588 bool plane_en[I915_MAX_PLANES];
1589 uint16_t plane_res_b[I915_MAX_PLANES];
1590 uint8_t plane_res_l[I915_MAX_PLANES];
1594 * This struct helps tracking the state needed for runtime PM, which puts the
1595 * device in PCI D3 state. Notice that when this happens, nothing on the
1596 * graphics device works, even register access, so we don't get interrupts nor
1599 * Every piece of our code that needs to actually touch the hardware needs to
1600 * either call intel_runtime_pm_get or call intel_display_power_get with the
1601 * appropriate power domain.
1603 * Our driver uses the autosuspend delay feature, which means we'll only really
1604 * suspend if we stay with zero refcount for a certain amount of time. The
1605 * default value is currently very conservative (see intel_runtime_pm_enable), but
1606 * it can be changed with the standard runtime PM files from sysfs.
1608 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1609 * goes back to false exactly before we reenable the IRQs. We use this variable
1610 * to check if someone is trying to enable/disable IRQs while they're supposed
1611 * to be disabled. This shouldn't happen and we'll print some error messages in
1614 * For more, read the Documentation/power/runtime_pm.txt.
1616 struct i915_runtime_pm {
1617 atomic_t wakeref_count;
1618 atomic_t atomic_seq;
1623 enum intel_pipe_crc_source {
1624 INTEL_PIPE_CRC_SOURCE_NONE,
1625 INTEL_PIPE_CRC_SOURCE_PLANE1,
1626 INTEL_PIPE_CRC_SOURCE_PLANE2,
1627 INTEL_PIPE_CRC_SOURCE_PF,
1628 INTEL_PIPE_CRC_SOURCE_PIPE,
1629 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1630 INTEL_PIPE_CRC_SOURCE_TV,
1631 INTEL_PIPE_CRC_SOURCE_DP_B,
1632 INTEL_PIPE_CRC_SOURCE_DP_C,
1633 INTEL_PIPE_CRC_SOURCE_DP_D,
1634 INTEL_PIPE_CRC_SOURCE_AUTO,
1635 INTEL_PIPE_CRC_SOURCE_MAX,
1638 struct intel_pipe_crc_entry {
1643 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1644 struct intel_pipe_crc {
1646 bool opened; /* exclusive access to the result file */
1647 struct intel_pipe_crc_entry *entries;
1648 enum intel_pipe_crc_source source;
1650 wait_queue_head_t wq;
1653 struct i915_frontbuffer_tracking {
1657 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1664 struct i915_wa_reg {
1667 /* bitmask representing WA bits */
1672 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1673 * allowing it for RCS as we don't foresee any requirement of having
1674 * a whitelist for other engines. When it is really required for
1675 * other engines then the limit need to be increased.
1677 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1679 struct i915_workarounds {
1680 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1682 u32 hw_whitelist_count[I915_NUM_ENGINES];
1685 struct i915_virtual_gpu {
1689 struct i915_execbuffer_params {
1690 struct drm_device *dev;
1691 struct drm_file *file;
1692 uint32_t dispatch_flags;
1693 uint32_t args_batch_start_offset;
1694 uint64_t batch_obj_vm_offset;
1695 struct intel_engine_cs *engine;
1696 struct drm_i915_gem_object *batch_obj;
1697 struct intel_context *ctx;
1698 struct drm_i915_gem_request *request;
1701 /* used in computing the new watermarks state */
1702 struct intel_wm_config {
1703 unsigned int num_pipes_active;
1704 bool sprites_enabled;
1705 bool sprites_scaled;
1708 struct drm_i915_private {
1709 struct drm_device *dev;
1710 struct kmem_cache *objects;
1711 struct kmem_cache *vmas;
1712 struct kmem_cache *requests;
1714 const struct intel_device_info info;
1716 int relative_constants_mode;
1720 struct intel_uncore uncore;
1722 struct i915_virtual_gpu vgpu;
1724 struct intel_guc guc;
1726 struct intel_csr csr;
1728 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1730 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1731 * controller on different i2c buses. */
1732 struct mutex gmbus_mutex;
1735 * Base address of the gmbus and gpio block.
1737 uint32_t gpio_mmio_base;
1739 /* MMIO base address for MIPI regs */
1740 uint32_t mipi_mmio_base;
1742 uint32_t psr_mmio_base;
1744 wait_queue_head_t gmbus_wait_queue;
1746 struct pci_dev *bridge_dev;
1747 struct intel_engine_cs engine[I915_NUM_ENGINES];
1748 struct drm_i915_gem_object *semaphore_obj;
1749 uint32_t last_seqno, next_seqno;
1751 struct drm_dma_handle *status_page_dmah;
1752 struct resource mch_res;
1754 /* protects the irq masks */
1755 spinlock_t irq_lock;
1757 /* protects the mmio flip data */
1758 spinlock_t mmio_flip_lock;
1760 bool display_irqs_enabled;
1762 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1763 struct pm_qos_request pm_qos;
1765 /* Sideband mailbox protection */
1766 struct mutex sb_lock;
1768 /** Cached value of IMR to avoid reads in updating the bitfield */
1771 u32 de_irq_mask[I915_MAX_PIPES];
1776 u32 pipestat_irq_mask[I915_MAX_PIPES];
1778 struct i915_hotplug hotplug;
1779 struct intel_fbc fbc;
1780 struct i915_drrs drrs;
1781 struct intel_opregion opregion;
1782 struct intel_vbt_data vbt;
1784 bool preserve_bios_swizzle;
1787 struct intel_overlay *overlay;
1789 /* backlight registers and fields in struct intel_panel */
1790 struct mutex backlight_lock;
1793 bool no_aux_handshake;
1795 /* protects panel power sequencer state */
1796 struct mutex pps_mutex;
1798 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1799 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1801 unsigned int fsb_freq, mem_freq, is_ddr3;
1802 unsigned int skl_boot_cdclk;
1803 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1804 unsigned int max_dotclk_freq;
1805 unsigned int rawclk_freq;
1806 unsigned int hpll_freq;
1807 unsigned int czclk_freq;
1810 * wq - Driver workqueue for GEM.
1812 * NOTE: Work items scheduled here are not allowed to grab any modeset
1813 * locks, for otherwise the flushing done in the pageflip code will
1814 * result in deadlocks.
1816 struct workqueue_struct *wq;
1818 /* Display functions */
1819 struct drm_i915_display_funcs display;
1821 /* PCH chipset type */
1822 enum intel_pch pch_type;
1823 unsigned short pch_id;
1825 unsigned long quirks;
1827 enum modeset_restore modeset_restore;
1828 struct mutex modeset_restore_lock;
1829 struct drm_atomic_state *modeset_restore_state;
1831 struct list_head vm_list; /* Global list of all address spaces */
1832 struct i915_ggtt ggtt; /* VM representing the global address space */
1834 struct i915_gem_mm mm;
1835 DECLARE_HASHTABLE(mm_structs, 7);
1836 struct mutex mm_lock;
1838 /* Kernel Modesetting */
1840 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1841 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1842 wait_queue_head_t pending_flip_queue;
1844 #ifdef CONFIG_DEBUG_FS
1845 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1848 /* dpll and cdclk state is protected by connection_mutex */
1849 int num_shared_dpll;
1850 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1851 const struct intel_dpll_mgr *dpll_mgr;
1854 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1855 * Must be global rather than per dpll, because on some platforms
1856 * plls share registers.
1858 struct mutex dpll_lock;
1860 unsigned int active_crtcs;
1861 unsigned int min_pixclk[I915_MAX_PIPES];
1863 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1865 struct i915_workarounds workarounds;
1867 struct i915_frontbuffer_tracking fb_tracking;
1871 bool mchbar_need_disable;
1873 struct intel_l3_parity l3_parity;
1875 /* Cannot be determined by PCIID. You must always read a register. */
1878 /* gen6+ rps state */
1879 struct intel_gen6_power_mgmt rps;
1881 /* ilk-only ips/rps state. Everything in here is protected by the global
1882 * mchdev_lock in intel_pm.c */
1883 struct intel_ilk_power_mgmt ips;
1885 struct i915_power_domains power_domains;
1887 struct i915_psr psr;
1889 struct i915_gpu_error gpu_error;
1891 struct drm_i915_gem_object *vlv_pctx;
1893 #ifdef CONFIG_DRM_FBDEV_EMULATION
1894 /* list of fbdev register on this device */
1895 struct intel_fbdev *fbdev;
1896 struct work_struct fbdev_suspend_work;
1899 struct drm_property *broadcast_rgb_property;
1900 struct drm_property *force_audio_property;
1902 /* hda/i915 audio component */
1903 struct i915_audio_component *audio_component;
1904 bool audio_component_registered;
1906 * av_mutex - mutex for audio/video sync
1909 struct mutex av_mutex;
1911 uint32_t hw_context_size;
1912 struct list_head context_list;
1916 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1917 u32 chv_phy_control;
1919 * Shadows for CHV DPLL_MD regs to keep the state
1920 * checker somewhat working in the presence hardware
1921 * crappiness (can't read out DPLL_MD for pipes B & C).
1923 u32 chv_dpll_md[I915_MAX_PIPES];
1926 bool suspended_to_idle;
1927 struct i915_suspend_saved_registers regfile;
1928 struct vlv_s0ix_state vlv_s0ix_state;
1932 * Raw watermark latency values:
1933 * in 0.1us units for WM0,
1934 * in 0.5us units for WM1+.
1937 uint16_t pri_latency[5];
1939 uint16_t spr_latency[5];
1941 uint16_t cur_latency[5];
1943 * Raw watermark memory latency values
1944 * for SKL for all 8 levels
1947 uint16_t skl_latency[8];
1949 /* Committed wm config */
1950 struct intel_wm_config config;
1953 * The skl_wm_values structure is a bit too big for stack
1954 * allocation, so we keep the staging struct where we store
1955 * intermediate results here instead.
1957 struct skl_wm_values skl_results;
1959 /* current hardware state */
1961 struct ilk_wm_values hw;
1962 struct skl_wm_values skl_hw;
1963 struct vlv_wm_values vlv;
1969 * Should be held around atomic WM register writing; also
1970 * protects * intel_crtc->wm.active and
1971 * cstate->wm.need_postvbl_update.
1973 struct mutex wm_mutex;
1976 struct i915_runtime_pm pm;
1978 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1980 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1981 struct drm_i915_gem_execbuffer2 *args,
1982 struct list_head *vmas);
1983 int (*init_engines)(struct drm_device *dev);
1984 void (*cleanup_engine)(struct intel_engine_cs *engine);
1985 void (*stop_engine)(struct intel_engine_cs *engine);
1988 struct intel_context *kernel_context;
1990 /* perform PHY state sanity checks? */
1991 bool chv_phy_assert[2];
1993 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1996 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1997 * will be rejected. Instead look for a better place.
2001 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2003 return dev->dev_private;
2006 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2008 return to_i915(dev_get_drvdata(dev));
2011 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2013 return container_of(guc, struct drm_i915_private, guc);
2016 /* Simple iterator over all initialised engines */
2017 #define for_each_engine(engine__, dev_priv__) \
2018 for ((engine__) = &(dev_priv__)->engine[0]; \
2019 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2021 for_each_if (intel_engine_initialized(engine__))
2023 /* Iterator with engine_id */
2024 #define for_each_engine_id(engine__, dev_priv__, id__) \
2025 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2026 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2028 for_each_if (((id__) = (engine__)->id, \
2029 intel_engine_initialized(engine__)))
2031 /* Iterator over subset of engines selected by mask */
2032 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2033 for ((engine__) = &(dev_priv__)->engine[0]; \
2034 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2036 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2037 intel_engine_initialized(engine__))
2039 enum hdmi_force_audio {
2040 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2041 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2042 HDMI_AUDIO_AUTO, /* trust EDID */
2043 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2046 #define I915_GTT_OFFSET_NONE ((u32)-1)
2048 struct drm_i915_gem_object_ops {
2050 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2052 /* Interface between the GEM object and its backing storage.
2053 * get_pages() is called once prior to the use of the associated set
2054 * of pages before to binding them into the GTT, and put_pages() is
2055 * called after we no longer need them. As we expect there to be
2056 * associated cost with migrating pages between the backing storage
2057 * and making them available for the GPU (e.g. clflush), we may hold
2058 * onto the pages after they are no longer referenced by the GPU
2059 * in case they may be used again shortly (for example migrating the
2060 * pages to a different memory domain within the GTT). put_pages()
2061 * will therefore most likely be called when the object itself is
2062 * being released or under memory pressure (where we attempt to
2063 * reap pages for the shrinker).
2065 int (*get_pages)(struct drm_i915_gem_object *);
2066 void (*put_pages)(struct drm_i915_gem_object *);
2068 int (*dmabuf_export)(struct drm_i915_gem_object *);
2069 void (*release)(struct drm_i915_gem_object *);
2073 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2074 * considered to be the frontbuffer for the given plane interface-wise. This
2075 * doesn't mean that the hw necessarily already scans it out, but that any
2076 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2078 * We have one bit per pipe and per scanout plane type.
2080 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2081 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2082 #define INTEL_FRONTBUFFER_BITS \
2083 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2084 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2085 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2086 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2087 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2088 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2089 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2090 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2091 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2092 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2093 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2095 struct drm_i915_gem_object {
2096 struct drm_gem_object base;
2098 const struct drm_i915_gem_object_ops *ops;
2100 /** List of VMAs backed by this object */
2101 struct list_head vma_list;
2103 /** Stolen memory for this object, instead of being backed by shmem. */
2104 struct drm_mm_node *stolen;
2105 struct list_head global_list;
2107 struct list_head engine_list[I915_NUM_ENGINES];
2108 /** Used in execbuf to temporarily hold a ref */
2109 struct list_head obj_exec_link;
2111 struct list_head batch_pool_link;
2114 * This is set if the object is on the active lists (has pending
2115 * rendering and so a non-zero seqno), and is not set if it i s on
2116 * inactive (ready to be unbound) list.
2118 unsigned int active:I915_NUM_ENGINES;
2121 * This is set if the object has been written to since last bound
2124 unsigned int dirty:1;
2127 * Fence register bits (if any) for this object. Will be set
2128 * as needed when mapped into the GTT.
2129 * Protected by dev->struct_mutex.
2131 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2134 * Advice: are the backing pages purgeable?
2136 unsigned int madv:2;
2139 * Current tiling mode for the object.
2141 unsigned int tiling_mode:2;
2143 * Whether the tiling parameters for the currently associated fence
2144 * register have changed. Note that for the purposes of tracking
2145 * tiling changes we also treat the unfenced register, the register
2146 * slot that the object occupies whilst it executes a fenced
2147 * command (such as BLT on gen2/3), as a "fence".
2149 unsigned int fence_dirty:1;
2152 * Is the object at the current location in the gtt mappable and
2153 * fenceable? Used to avoid costly recalculations.
2155 unsigned int map_and_fenceable:1;
2158 * Whether the current gtt mapping needs to be mappable (and isn't just
2159 * mappable by accident). Track pin and fault separate for a more
2160 * accurate mappable working set.
2162 unsigned int fault_mappable:1;
2165 * Is the object to be mapped as read-only to the GPU
2166 * Only honoured if hardware has relevant pte bit
2168 unsigned long gt_ro:1;
2169 unsigned int cache_level:3;
2170 unsigned int cache_dirty:1;
2172 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2174 unsigned int pin_display;
2176 struct sg_table *pages;
2177 int pages_pin_count;
2179 struct scatterlist *sg;
2184 /** Breadcrumb of last rendering to the buffer.
2185 * There can only be one writer, but we allow for multiple readers.
2186 * If there is a writer that necessarily implies that all other
2187 * read requests are complete - but we may only be lazily clearing
2188 * the read requests. A read request is naturally the most recent
2189 * request on a ring, so we may have two different write and read
2190 * requests on one ring where the write request is older than the
2191 * read request. This allows for the CPU to read from an active
2192 * buffer by only waiting for the write to complete.
2194 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2195 struct drm_i915_gem_request *last_write_req;
2196 /** Breadcrumb of last fenced GPU access to the buffer. */
2197 struct drm_i915_gem_request *last_fenced_req;
2199 /** Current tiling stride for the object, if it's tiled. */
2202 /** References from framebuffers, locks out tiling changes. */
2203 unsigned long framebuffer_references;
2205 /** Record of address bit 17 of each page at last unbind. */
2206 unsigned long *bit_17;
2209 /** for phy allocated objects */
2210 struct drm_dma_handle *phys_handle;
2212 struct i915_gem_userptr {
2214 unsigned read_only :1;
2215 unsigned workers :4;
2216 #define I915_GEM_USERPTR_MAX_WORKERS 15
2218 struct i915_mm_struct *mm;
2219 struct i915_mmu_object *mmu_object;
2220 struct work_struct *work;
2224 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2226 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2227 struct drm_i915_gem_object *new,
2228 unsigned frontbuffer_bits);
2231 * Request queue structure.
2233 * The request queue allows us to note sequence numbers that have been emitted
2234 * and may be associated with active buffers to be retired.
2236 * By keeping this list, we can avoid having to do questionable sequence
2237 * number comparisons on buffer last_read|write_seqno. It also allows an
2238 * emission time to be associated with the request for tracking how far ahead
2239 * of the GPU the submission is.
2241 * The requests are reference counted, so upon creation they should have an
2242 * initial reference taken using kref_init
2244 struct drm_i915_gem_request {
2247 /** On Which ring this request was generated */
2248 struct drm_i915_private *i915;
2249 struct intel_engine_cs *engine;
2251 /** GEM sequence number associated with the previous request,
2252 * when the HWS breadcrumb is equal to this the GPU is processing
2257 /** GEM sequence number associated with this request,
2258 * when the HWS breadcrumb is equal or greater than this the GPU
2259 * has finished processing this request.
2263 /** Position in the ringbuffer of the start of the request */
2267 * Position in the ringbuffer of the start of the postfix.
2268 * This is required to calculate the maximum available ringbuffer
2269 * space without overwriting the postfix.
2273 /** Position in the ringbuffer of the end of the whole request */
2277 * Context and ring buffer related to this request
2278 * Contexts are refcounted, so when this request is associated with a
2279 * context, we must increment the context's refcount, to guarantee that
2280 * it persists while any request is linked to it. Requests themselves
2281 * are also refcounted, so the request will only be freed when the last
2282 * reference to it is dismissed, and the code in
2283 * i915_gem_request_free() will then decrement the refcount on the
2286 struct intel_context *ctx;
2287 struct intel_ringbuffer *ringbuf;
2289 /** Batch buffer related to this request if any (used for
2290 error state dump only) */
2291 struct drm_i915_gem_object *batch_obj;
2293 /** Time at which this request was emitted, in jiffies. */
2294 unsigned long emitted_jiffies;
2296 /** global list entry for this request */
2297 struct list_head list;
2299 struct drm_i915_file_private *file_priv;
2300 /** file_priv list entry for this request */
2301 struct list_head client_list;
2303 /** process identifier submitting this request */
2307 * The ELSP only accepts two elements at a time, so we queue
2308 * context/tail pairs on a given queue (ring->execlist_queue) until the
2309 * hardware is available. The queue serves a double purpose: we also use
2310 * it to keep track of the up to 2 contexts currently in the hardware
2311 * (usually one in execution and the other queued up by the GPU): We
2312 * only remove elements from the head of the queue when the hardware
2313 * informs us that an element has been completed.
2315 * All accesses to the queue are mediated by a spinlock
2316 * (ring->execlist_lock).
2319 /** Execlist link in the submission queue.*/
2320 struct list_head execlist_link;
2322 /** Execlists no. of times this request has been sent to the ELSP */
2327 struct drm_i915_gem_request * __must_check
2328 i915_gem_request_alloc(struct intel_engine_cs *engine,
2329 struct intel_context *ctx);
2330 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2331 void i915_gem_request_free(struct kref *req_ref);
2332 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2333 struct drm_file *file);
2335 static inline uint32_t
2336 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2338 return req ? req->seqno : 0;
2341 static inline struct intel_engine_cs *
2342 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2344 return req ? req->engine : NULL;
2347 static inline struct drm_i915_gem_request *
2348 i915_gem_request_reference(struct drm_i915_gem_request *req)
2351 kref_get(&req->ref);
2356 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2358 WARN_ON(!mutex_is_locked(&req->engine->dev->struct_mutex));
2359 kref_put(&req->ref, i915_gem_request_free);
2363 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2365 struct drm_device *dev;
2370 dev = req->engine->dev;
2371 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2372 mutex_unlock(&dev->struct_mutex);
2375 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2376 struct drm_i915_gem_request *src)
2379 i915_gem_request_reference(src);
2382 i915_gem_request_unreference(*pdst);
2388 * XXX: i915_gem_request_completed should be here but currently needs the
2389 * definition of i915_seqno_passed() which is below. It will be moved in
2390 * a later patch when the call to i915_seqno_passed() is obsoleted...
2394 * A command that requires special handling by the command parser.
2396 struct drm_i915_cmd_descriptor {
2398 * Flags describing how the command parser processes the command.
2400 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2401 * a length mask if not set
2402 * CMD_DESC_SKIP: The command is allowed but does not follow the
2403 * standard length encoding for the opcode range in
2405 * CMD_DESC_REJECT: The command is never allowed
2406 * CMD_DESC_REGISTER: The command should be checked against the
2407 * register whitelist for the appropriate ring
2408 * CMD_DESC_MASTER: The command is allowed if the submitting process
2412 #define CMD_DESC_FIXED (1<<0)
2413 #define CMD_DESC_SKIP (1<<1)
2414 #define CMD_DESC_REJECT (1<<2)
2415 #define CMD_DESC_REGISTER (1<<3)
2416 #define CMD_DESC_BITMASK (1<<4)
2417 #define CMD_DESC_MASTER (1<<5)
2420 * The command's unique identification bits and the bitmask to get them.
2421 * This isn't strictly the opcode field as defined in the spec and may
2422 * also include type, subtype, and/or subop fields.
2430 * The command's length. The command is either fixed length (i.e. does
2431 * not include a length field) or has a length field mask. The flag
2432 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2433 * a length mask. All command entries in a command table must include
2434 * length information.
2442 * Describes where to find a register address in the command to check
2443 * against the ring's register whitelist. Only valid if flags has the
2444 * CMD_DESC_REGISTER bit set.
2446 * A non-zero step value implies that the command may access multiple
2447 * registers in sequence (e.g. LRI), in that case step gives the
2448 * distance in dwords between individual offset fields.
2456 #define MAX_CMD_DESC_BITMASKS 3
2458 * Describes command checks where a particular dword is masked and
2459 * compared against an expected value. If the command does not match
2460 * the expected value, the parser rejects it. Only valid if flags has
2461 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2464 * If the check specifies a non-zero condition_mask then the parser
2465 * only performs the check when the bits specified by condition_mask
2472 u32 condition_offset;
2474 } bits[MAX_CMD_DESC_BITMASKS];
2478 * A table of commands requiring special handling by the command parser.
2480 * Each ring has an array of tables. Each table consists of an array of command
2481 * descriptors, which must be sorted with command opcodes in ascending order.
2483 struct drm_i915_cmd_table {
2484 const struct drm_i915_cmd_descriptor *table;
2488 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2489 #define __I915__(p) ({ \
2490 struct drm_i915_private *__p; \
2491 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2492 __p = (struct drm_i915_private *)p; \
2493 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2494 __p = to_i915((struct drm_device *)p); \
2499 #define INTEL_INFO(p) (&__I915__(p)->info)
2500 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2501 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2502 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2504 #define REVID_FOREVER 0xff
2506 * Return true if revision is in range [since,until] inclusive.
2508 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2510 #define IS_REVID(p, since, until) \
2511 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2513 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2514 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2515 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2516 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2517 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2518 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2519 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2520 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2521 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2522 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2523 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2524 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2525 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2526 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2527 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2528 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2529 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2530 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2531 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2532 INTEL_DEVID(dev) == 0x0152 || \
2533 INTEL_DEVID(dev) == 0x015a)
2534 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2535 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2536 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2537 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2538 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2539 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2540 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2541 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2542 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2543 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2544 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2545 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2546 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2547 (INTEL_DEVID(dev) & 0xf) == 0xe))
2548 /* ULX machines are also considered ULT. */
2549 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2550 (INTEL_DEVID(dev) & 0xf) == 0xe)
2551 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2552 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2553 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2554 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2555 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2556 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2557 /* ULX machines are also considered ULT. */
2558 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2559 INTEL_DEVID(dev) == 0x0A1E)
2560 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2561 INTEL_DEVID(dev) == 0x1913 || \
2562 INTEL_DEVID(dev) == 0x1916 || \
2563 INTEL_DEVID(dev) == 0x1921 || \
2564 INTEL_DEVID(dev) == 0x1926)
2565 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2566 INTEL_DEVID(dev) == 0x1915 || \
2567 INTEL_DEVID(dev) == 0x191E)
2568 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2569 INTEL_DEVID(dev) == 0x5913 || \
2570 INTEL_DEVID(dev) == 0x5916 || \
2571 INTEL_DEVID(dev) == 0x5921 || \
2572 INTEL_DEVID(dev) == 0x5926)
2573 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2574 INTEL_DEVID(dev) == 0x5915 || \
2575 INTEL_DEVID(dev) == 0x591E)
2576 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2577 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2578 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2579 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2581 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2583 #define SKL_REVID_A0 0x0
2584 #define SKL_REVID_B0 0x1
2585 #define SKL_REVID_C0 0x2
2586 #define SKL_REVID_D0 0x3
2587 #define SKL_REVID_E0 0x4
2588 #define SKL_REVID_F0 0x5
2590 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2592 #define BXT_REVID_A0 0x0
2593 #define BXT_REVID_A1 0x1
2594 #define BXT_REVID_B0 0x3
2595 #define BXT_REVID_C0 0x9
2597 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2600 * The genX designation typically refers to the render engine, so render
2601 * capability related checks should use IS_GEN, while display and other checks
2602 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2605 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2606 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2607 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2608 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2609 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2610 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2611 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2612 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2614 #define RENDER_RING (1<<RCS)
2615 #define BSD_RING (1<<VCS)
2616 #define BLT_RING (1<<BCS)
2617 #define VEBOX_RING (1<<VECS)
2618 #define BSD2_RING (1<<VCS2)
2619 #define ALL_ENGINES (~0)
2621 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2622 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2623 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2624 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2625 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2626 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2627 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2628 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2630 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2632 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2633 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2634 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2635 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2636 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2638 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2639 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2641 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2642 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2644 /* WaRsDisableCoarsePowerGating:skl,bxt */
2645 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2646 IS_SKL_GT3(dev) || \
2650 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2651 * even when in MSI mode. This results in spurious interrupt warnings if the
2652 * legacy irq no. is shared with another device. The kernel then disables that
2653 * interrupt source and so prevents the other device from working properly.
2655 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2656 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2658 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2659 * rows, which changed the alignment requirements and fence programming.
2661 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2663 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2664 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2666 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2667 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2668 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2670 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2672 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2673 INTEL_INFO(dev)->gen >= 9)
2675 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2676 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2677 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2678 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2679 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2680 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2681 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2682 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2684 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2685 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2687 #define HAS_CSR(dev) (IS_GEN9(dev))
2689 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2690 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2692 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2693 INTEL_INFO(dev)->gen >= 8)
2695 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2696 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2699 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2700 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2701 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2702 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2703 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2704 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2705 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2706 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2707 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2708 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2709 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2711 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2712 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2713 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2714 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2715 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2716 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2717 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2718 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2719 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2721 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2722 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2724 /* DPF == dynamic parity feature */
2725 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2726 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2728 #define GT_FREQUENCY_MULTIPLIER 50
2729 #define GEN9_FREQ_SCALER 3
2731 #include "i915_trace.h"
2733 extern const struct drm_ioctl_desc i915_ioctls[];
2734 extern int i915_max_ioctl;
2736 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2737 extern int i915_resume_switcheroo(struct drm_device *dev);
2741 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2742 const char *fmt, ...);
2744 #define i915_report_error(dev_priv, fmt, ...) \
2745 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2747 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2748 extern int i915_driver_unload(struct drm_device *);
2749 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2750 extern void i915_driver_lastclose(struct drm_device * dev);
2751 extern void i915_driver_preclose(struct drm_device *dev,
2752 struct drm_file *file);
2753 extern void i915_driver_postclose(struct drm_device *dev,
2754 struct drm_file *file);
2755 #ifdef CONFIG_COMPAT
2756 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2759 extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
2760 extern bool intel_has_gpu_reset(struct drm_device *dev);
2761 extern int i915_reset(struct drm_device *dev);
2762 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2763 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2764 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2765 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2766 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2767 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2768 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2770 /* intel_hotplug.c */
2771 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2772 void intel_hpd_init(struct drm_i915_private *dev_priv);
2773 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2774 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2775 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2778 void i915_queue_hangcheck(struct drm_device *dev);
2780 void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2781 const char *fmt, ...);
2783 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2784 int intel_irq_install(struct drm_i915_private *dev_priv);
2785 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2787 extern void intel_uncore_sanitize(struct drm_device *dev);
2788 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2789 bool restore_forcewake);
2790 extern void intel_uncore_init(struct drm_device *dev);
2791 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2792 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2793 extern void intel_uncore_fini(struct drm_device *dev);
2794 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2795 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2796 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2797 enum forcewake_domains domains);
2798 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2799 enum forcewake_domains domains);
2800 /* Like above but the caller must manage the uncore.lock itself.
2801 * Must be used with I915_READ_FW and friends.
2803 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2804 enum forcewake_domains domains);
2805 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2806 enum forcewake_domains domains);
2807 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2809 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2810 static inline bool intel_vgpu_active(struct drm_device *dev)
2812 return to_i915(dev)->vgpu.active;
2816 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2820 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2823 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2824 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2825 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2828 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2829 uint32_t interrupt_mask,
2830 uint32_t enabled_irq_mask);
2832 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2834 ilk_update_display_irq(dev_priv, bits, bits);
2837 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2839 ilk_update_display_irq(dev_priv, bits, 0);
2841 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2843 uint32_t interrupt_mask,
2844 uint32_t enabled_irq_mask);
2845 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2846 enum pipe pipe, uint32_t bits)
2848 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2850 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2851 enum pipe pipe, uint32_t bits)
2853 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2855 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2856 uint32_t interrupt_mask,
2857 uint32_t enabled_irq_mask);
2859 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2861 ibx_display_interrupt_update(dev_priv, bits, bits);
2864 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2866 ibx_display_interrupt_update(dev_priv, bits, 0);
2871 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2872 struct drm_file *file_priv);
2873 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2874 struct drm_file *file_priv);
2875 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2876 struct drm_file *file_priv);
2877 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2878 struct drm_file *file_priv);
2879 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2880 struct drm_file *file_priv);
2881 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv);
2883 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2884 struct drm_file *file_priv);
2885 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2886 struct drm_i915_gem_request *req);
2887 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2888 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2889 struct drm_i915_gem_execbuffer2 *args,
2890 struct list_head *vmas);
2891 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2892 struct drm_file *file_priv);
2893 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2894 struct drm_file *file_priv);
2895 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2896 struct drm_file *file_priv);
2897 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2898 struct drm_file *file);
2899 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2900 struct drm_file *file);
2901 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2902 struct drm_file *file_priv);
2903 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2904 struct drm_file *file_priv);
2905 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2906 struct drm_file *file_priv);
2907 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2908 struct drm_file *file_priv);
2909 int i915_gem_init_userptr(struct drm_device *dev);
2910 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2911 struct drm_file *file);
2912 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2913 struct drm_file *file_priv);
2914 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2915 struct drm_file *file_priv);
2916 void i915_gem_load_init(struct drm_device *dev);
2917 void i915_gem_load_cleanup(struct drm_device *dev);
2918 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2919 void *i915_gem_object_alloc(struct drm_device *dev);
2920 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2921 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2922 const struct drm_i915_gem_object_ops *ops);
2923 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2925 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2926 struct drm_device *dev, const void *data, size_t size);
2927 void i915_gem_free_object(struct drm_gem_object *obj);
2928 void i915_gem_vma_destroy(struct i915_vma *vma);
2930 /* Flags used by pin/bind&friends. */
2931 #define PIN_MAPPABLE (1<<0)
2932 #define PIN_NONBLOCK (1<<1)
2933 #define PIN_GLOBAL (1<<2)
2934 #define PIN_OFFSET_BIAS (1<<3)
2935 #define PIN_USER (1<<4)
2936 #define PIN_UPDATE (1<<5)
2937 #define PIN_ZONE_4G (1<<6)
2938 #define PIN_HIGH (1<<7)
2939 #define PIN_OFFSET_FIXED (1<<8)
2940 #define PIN_OFFSET_MASK (~4095)
2942 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2943 struct i915_address_space *vm,
2947 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2948 const struct i915_ggtt_view *view,
2952 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2954 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2955 int __must_check i915_vma_unbind(struct i915_vma *vma);
2957 * BEWARE: Do not use the function below unless you can _absolutely_
2958 * _guarantee_ VMA in question is _not in use_ anywhere.
2960 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2961 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2962 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2963 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2965 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2966 int *needs_clflush);
2968 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2970 static inline int __sg_page_count(struct scatterlist *sg)
2972 return sg->length >> PAGE_SHIFT;
2976 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2978 static inline struct page *
2979 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2981 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2984 if (n < obj->get_page.last) {
2985 obj->get_page.sg = obj->pages->sgl;
2986 obj->get_page.last = 0;
2989 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2990 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2991 if (unlikely(sg_is_chain(obj->get_page.sg)))
2992 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2995 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2998 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3000 BUG_ON(obj->pages == NULL);
3001 obj->pages_pin_count++;
3004 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3006 BUG_ON(obj->pages_pin_count == 0);
3007 obj->pages_pin_count--;
3011 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3012 * @obj - the object to map into kernel address space
3014 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3015 * pages and then returns a contiguous mapping of the backing storage into
3016 * the kernel address space.
3018 * The caller must hold the struct_mutex.
3020 * Returns the pointer through which to access the backing storage.
3022 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3025 * i915_gem_object_unpin_map - releases an earlier mapping
3026 * @obj - the object to unmap
3028 * After pinning the object and mapping its pages, once you are finished
3029 * with your access, call i915_gem_object_unpin_map() to release the pin
3030 * upon the mapping. Once the pin count reaches zero, that mapping may be
3033 * The caller must hold the struct_mutex.
3035 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3037 lockdep_assert_held(&obj->base.dev->struct_mutex);
3038 i915_gem_object_unpin_pages(obj);
3041 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3042 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3043 struct intel_engine_cs *to,
3044 struct drm_i915_gem_request **to_req);
3045 void i915_vma_move_to_active(struct i915_vma *vma,
3046 struct drm_i915_gem_request *req);
3047 int i915_gem_dumb_create(struct drm_file *file_priv,
3048 struct drm_device *dev,
3049 struct drm_mode_create_dumb *args);
3050 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3051 uint32_t handle, uint64_t *offset);
3053 * Returns true if seq1 is later than seq2.
3056 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3058 return (int32_t)(seq1 - seq2) >= 0;
3061 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3062 bool lazy_coherency)
3064 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3065 req->engine->irq_seqno_barrier(req->engine);
3066 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3067 req->previous_seqno);
3070 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3071 bool lazy_coherency)
3073 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3074 req->engine->irq_seqno_barrier(req->engine);
3075 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3079 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3080 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3082 struct drm_i915_gem_request *
3083 i915_gem_find_active_request(struct intel_engine_cs *engine);
3085 bool i915_gem_retire_requests(struct drm_device *dev);
3086 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3087 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3088 bool interruptible);
3090 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3092 return unlikely(atomic_read(&error->reset_counter)
3093 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3096 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3098 return atomic_read(&error->reset_counter) & I915_WEDGED;
3101 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3103 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3106 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3108 return dev_priv->gpu_error.stop_rings == 0 ||
3109 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3112 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3114 return dev_priv->gpu_error.stop_rings == 0 ||
3115 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3118 void i915_gem_reset(struct drm_device *dev);
3119 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3120 int __must_check i915_gem_init(struct drm_device *dev);
3121 int i915_gem_init_engines(struct drm_device *dev);
3122 int __must_check i915_gem_init_hw(struct drm_device *dev);
3123 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3124 void i915_gem_init_swizzling(struct drm_device *dev);
3125 void i915_gem_cleanup_engines(struct drm_device *dev);
3126 int __must_check i915_gpu_idle(struct drm_device *dev);
3127 int __must_check i915_gem_suspend(struct drm_device *dev);
3128 void __i915_add_request(struct drm_i915_gem_request *req,
3129 struct drm_i915_gem_object *batch_obj,
3131 #define i915_add_request(req) \
3132 __i915_add_request(req, NULL, true)
3133 #define i915_add_request_no_flush(req) \
3134 __i915_add_request(req, NULL, false)
3135 int __i915_wait_request(struct drm_i915_gem_request *req,
3136 unsigned reset_counter,
3139 struct intel_rps_client *rps);
3140 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3141 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3143 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3146 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3149 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3151 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3153 const struct i915_ggtt_view *view);
3154 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3155 const struct i915_ggtt_view *view);
3156 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3158 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3159 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3162 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3164 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3165 int tiling_mode, bool fenced);
3167 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3168 enum i915_cache_level cache_level);
3170 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3171 struct dma_buf *dma_buf);
3173 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3174 struct drm_gem_object *gem_obj, int flags);
3176 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3177 const struct i915_ggtt_view *view);
3178 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3179 struct i915_address_space *vm);
3181 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3183 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3186 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3187 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3188 const struct i915_ggtt_view *view);
3189 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3190 struct i915_address_space *vm);
3192 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3193 struct i915_address_space *vm);
3195 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3196 struct i915_address_space *vm);
3198 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3199 const struct i915_ggtt_view *view);
3202 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3203 struct i915_address_space *vm);
3205 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3206 const struct i915_ggtt_view *view);
3208 static inline struct i915_vma *
3209 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3211 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3213 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3215 /* Some GGTT VM helpers */
3216 static inline struct i915_hw_ppgtt *
3217 i915_vm_to_ppgtt(struct i915_address_space *vm)
3219 return container_of(vm, struct i915_hw_ppgtt, base);
3223 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3225 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3228 static inline unsigned long
3229 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3231 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3232 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3234 return i915_gem_obj_size(obj, &ggtt->base);
3237 static inline int __must_check
3238 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3242 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3243 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3245 return i915_gem_object_pin(obj, &ggtt->base,
3246 alignment, flags | PIN_GLOBAL);
3250 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3252 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3255 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3256 const struct i915_ggtt_view *view);
3258 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3260 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3263 /* i915_gem_fence.c */
3264 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3265 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3267 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3268 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3270 void i915_gem_restore_fences(struct drm_device *dev);
3272 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3273 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3274 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3276 /* i915_gem_context.c */
3277 int __must_check i915_gem_context_init(struct drm_device *dev);
3278 void i915_gem_context_fini(struct drm_device *dev);
3279 void i915_gem_context_reset(struct drm_device *dev);
3280 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3281 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3282 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3283 int i915_switch_context(struct drm_i915_gem_request *req);
3284 struct intel_context *
3285 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3286 void i915_gem_context_free(struct kref *ctx_ref);
3287 struct drm_i915_gem_object *
3288 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3289 static inline void i915_gem_context_reference(struct intel_context *ctx)
3291 kref_get(&ctx->ref);
3294 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3296 kref_put(&ctx->ref, i915_gem_context_free);
3299 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3301 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3304 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3305 struct drm_file *file);
3306 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3307 struct drm_file *file);
3308 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3309 struct drm_file *file_priv);
3310 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3311 struct drm_file *file_priv);
3313 /* i915_gem_evict.c */
3314 int __must_check i915_gem_evict_something(struct drm_device *dev,
3315 struct i915_address_space *vm,
3318 unsigned cache_level,
3319 unsigned long start,
3322 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3323 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3325 /* belongs in i915_gem_gtt.h */
3326 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3328 if (INTEL_INFO(dev)->gen < 6)
3329 intel_gtt_chipset_flush();
3332 /* i915_gem_stolen.c */
3333 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3334 struct drm_mm_node *node, u64 size,
3335 unsigned alignment);
3336 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3337 struct drm_mm_node *node, u64 size,
3338 unsigned alignment, u64 start,
3340 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3341 struct drm_mm_node *node);
3342 int i915_gem_init_stolen(struct drm_device *dev);
3343 void i915_gem_cleanup_stolen(struct drm_device *dev);
3344 struct drm_i915_gem_object *
3345 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3346 struct drm_i915_gem_object *
3347 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3352 /* i915_gem_shrinker.c */
3353 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3354 unsigned long target,
3356 #define I915_SHRINK_PURGEABLE 0x1
3357 #define I915_SHRINK_UNBOUND 0x2
3358 #define I915_SHRINK_BOUND 0x4
3359 #define I915_SHRINK_ACTIVE 0x8
3360 #define I915_SHRINK_VMAPS 0x10
3361 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3362 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3363 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3366 /* i915_gem_tiling.c */
3367 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3369 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3371 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3372 obj->tiling_mode != I915_TILING_NONE;
3375 /* i915_gem_debug.c */
3377 int i915_verify_lists(struct drm_device *dev);
3379 #define i915_verify_lists(dev) 0
3382 /* i915_debugfs.c */
3383 int i915_debugfs_init(struct drm_minor *minor);
3384 void i915_debugfs_cleanup(struct drm_minor *minor);
3385 #ifdef CONFIG_DEBUG_FS
3386 int i915_debugfs_connector_add(struct drm_connector *connector);
3387 void intel_display_crc_init(struct drm_device *dev);
3389 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3391 static inline void intel_display_crc_init(struct drm_device *dev) {}
3394 /* i915_gpu_error.c */
3396 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3397 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3398 const struct i915_error_state_file_priv *error);
3399 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3400 struct drm_i915_private *i915,
3401 size_t count, loff_t pos);
3402 static inline void i915_error_state_buf_release(
3403 struct drm_i915_error_state_buf *eb)
3407 void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
3408 const char *error_msg);
3409 void i915_error_state_get(struct drm_device *dev,
3410 struct i915_error_state_file_priv *error_priv);
3411 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3412 void i915_destroy_error_state(struct drm_device *dev);
3414 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3415 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3417 /* i915_cmd_parser.c */
3418 int i915_cmd_parser_get_version(void);
3419 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3420 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3421 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3422 int i915_parse_cmds(struct intel_engine_cs *engine,
3423 struct drm_i915_gem_object *batch_obj,
3424 struct drm_i915_gem_object *shadow_batch_obj,
3425 u32 batch_start_offset,
3429 /* i915_suspend.c */
3430 extern int i915_save_state(struct drm_device *dev);
3431 extern int i915_restore_state(struct drm_device *dev);
3434 void i915_setup_sysfs(struct drm_device *dev_priv);
3435 void i915_teardown_sysfs(struct drm_device *dev_priv);
3438 extern int intel_setup_gmbus(struct drm_device *dev);
3439 extern void intel_teardown_gmbus(struct drm_device *dev);
3440 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3443 extern struct i2c_adapter *
3444 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3445 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3446 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3447 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3449 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3451 extern void intel_i2c_reset(struct drm_device *dev);
3454 int intel_bios_init(struct drm_i915_private *dev_priv);
3455 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3456 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3457 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3458 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3459 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3460 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3463 /* intel_opregion.c */
3465 extern int intel_opregion_setup(struct drm_device *dev);
3466 extern void intel_opregion_init(struct drm_device *dev);
3467 extern void intel_opregion_fini(struct drm_device *dev);
3468 extern void intel_opregion_asle_intr(struct drm_device *dev);
3469 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3471 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3473 extern int intel_opregion_get_panel_type(struct drm_device *dev);
3475 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3476 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3477 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3478 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3480 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3485 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3489 static inline int intel_opregion_get_panel_type(struct drm_device *dev)
3497 extern void intel_register_dsm_handler(void);
3498 extern void intel_unregister_dsm_handler(void);
3500 static inline void intel_register_dsm_handler(void) { return; }
3501 static inline void intel_unregister_dsm_handler(void) { return; }
3502 #endif /* CONFIG_ACPI */
3505 extern void intel_modeset_init_hw(struct drm_device *dev);
3506 extern void intel_modeset_init(struct drm_device *dev);
3507 extern void intel_modeset_gem_init(struct drm_device *dev);
3508 extern void intel_modeset_cleanup(struct drm_device *dev);
3509 extern void intel_connector_unregister(struct intel_connector *);
3510 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3511 extern void intel_display_resume(struct drm_device *dev);
3512 extern void i915_redisable_vga(struct drm_device *dev);
3513 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3514 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3515 extern void intel_init_pch_refclk(struct drm_device *dev);
3516 extern void intel_set_rps(struct drm_device *dev, u8 val);
3517 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3519 extern void intel_detect_pch(struct drm_device *dev);
3520 extern int intel_enable_rc6(const struct drm_device *dev);
3522 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3523 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3524 struct drm_file *file);
3525 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3526 struct drm_file *file);
3529 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3530 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3531 struct intel_overlay_error_state *error);
3533 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3534 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3535 struct drm_device *dev,
3536 struct intel_display_error_state *error);
3538 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3539 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3541 /* intel_sideband.c */
3542 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3543 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3544 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3545 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3546 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3547 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3548 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3549 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3550 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3551 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3552 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3553 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3554 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3555 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3556 enum intel_sbi_destination destination);
3557 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3558 enum intel_sbi_destination destination);
3559 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3560 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3562 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3563 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3565 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3566 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3568 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3569 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3570 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3571 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3573 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3574 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3575 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3576 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3578 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3579 * will be implemented using 2 32-bit writes in an arbitrary order with
3580 * an arbitrary delay between them. This can cause the hardware to
3581 * act upon the intermediate value, possibly leading to corruption and
3582 * machine death. You have been warned.
3584 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3585 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3587 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3588 u32 upper, lower, old_upper, loop = 0; \
3589 upper = I915_READ(upper_reg); \
3591 old_upper = upper; \
3592 lower = I915_READ(lower_reg); \
3593 upper = I915_READ(upper_reg); \
3594 } while (upper != old_upper && loop++ < 2); \
3595 (u64)upper << 32 | lower; })
3597 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3598 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3600 #define __raw_read(x, s) \
3601 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3604 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3607 #define __raw_write(x, s) \
3608 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3609 i915_reg_t reg, uint##x##_t val) \
3611 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3626 /* These are untraced mmio-accessors that are only valid to be used inside
3627 * criticial sections inside IRQ handlers where forcewake is explicitly
3629 * Think twice, and think again, before using these.
3630 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3631 * intel_uncore_forcewake_irqunlock().
3633 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3634 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3635 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3637 /* "Broadcast RGB" property */
3638 #define INTEL_BROADCAST_RGB_AUTO 0
3639 #define INTEL_BROADCAST_RGB_FULL 1
3640 #define INTEL_BROADCAST_RGB_LIMITED 2
3642 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3644 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3645 return VLV_VGACNTRL;
3646 else if (INTEL_INFO(dev)->gen >= 5)
3647 return CPU_VGACNTRL;
3652 static inline void __user *to_user_ptr(u64 address)
3654 return (void __user *)(uintptr_t)address;
3657 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3659 unsigned long j = msecs_to_jiffies(m);
3661 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3664 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3666 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3669 static inline unsigned long
3670 timespec_to_jiffies_timeout(const struct timespec *value)
3672 unsigned long j = timespec_to_jiffies(value);
3674 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3678 * If you need to wait X milliseconds between events A and B, but event B
3679 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3680 * when event A happened, then just before event B you call this function and
3681 * pass the timestamp as the first argument, and X as the second argument.
3684 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3686 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3689 * Don't re-read the value of "jiffies" every time since it may change
3690 * behind our back and break the math.
3692 tmp_jiffies = jiffies;
3693 target_jiffies = timestamp_jiffies +
3694 msecs_to_jiffies_timeout(to_wait_ms);
3696 if (time_after(target_jiffies, tmp_jiffies)) {
3697 remaining_jiffies = target_jiffies - tmp_jiffies;
3698 while (remaining_jiffies)
3700 schedule_timeout_uninterruptible(remaining_jiffies);
3704 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3705 struct drm_i915_gem_request *req)
3707 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3708 i915_gem_request_assign(&engine->trace_irq_req, req);