1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
51 #include "i915_params.h"
54 #include "intel_bios.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_guc.h"
57 #include "intel_lrc.h"
58 #include "intel_ringbuffer.h"
61 #include "i915_gem_gtt.h"
62 #include "i915_gem_render_state.h"
64 /* General customization:
67 #define DRIVER_NAME "i915"
68 #define DRIVER_DESC "Intel Graphics"
69 #define DRIVER_DATE "20160606"
72 /* Many gcc seem to no see through this and fall over :( */
74 #define WARN_ON(x) ({ \
75 bool __i915_warn_cond = (x); \
76 if (__builtin_constant_p(__i915_warn_cond)) \
77 BUILD_BUG_ON(__i915_warn_cond); \
78 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
80 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
84 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
86 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
87 (long) (x), __func__);
89 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
90 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
91 * which may not necessarily be a user visible problem. This will either
92 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
93 * enable distros and users to tailor their preferred amount of i915 abrt
96 #define I915_STATE_WARN(condition, format...) ({ \
97 int __ret_warn_on = !!(condition); \
98 if (unlikely(__ret_warn_on)) \
99 if (!WARN(i915.verbose_state_checks, format)) \
101 unlikely(__ret_warn_on); \
104 #define I915_STATE_WARN_ON(x) \
105 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
107 bool __i915_inject_load_failure(const char *func, int line);
108 #define i915_inject_load_failure() \
109 __i915_inject_load_failure(__func__, __LINE__)
111 static inline const char *yesno(bool v)
113 return v ? "yes" : "no";
116 static inline const char *onoff(bool v)
118 return v ? "on" : "off";
127 I915_MAX_PIPES = _PIPE_EDP
129 #define pipe_name(p) ((p) + 'A')
141 static inline const char *transcoder_name(enum transcoder transcoder)
143 switch (transcoder) {
152 case TRANSCODER_DSI_A:
154 case TRANSCODER_DSI_C:
161 static inline bool transcoder_is_dsi(enum transcoder transcoder)
163 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
167 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
168 * number of planes per CRTC. Not all platforms really have this many planes,
169 * which means some arrays of size I915_MAX_PLANES may have unused entries
170 * between the topmost sprite plane and the cursor plane.
179 #define plane_name(p) ((p) + 'A')
181 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
191 #define port_name(p) ((p) + 'A')
193 #define I915_NUM_PHYS_VLV 2
205 enum intel_display_power_domain {
209 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
210 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
211 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
212 POWER_DOMAIN_TRANSCODER_A,
213 POWER_DOMAIN_TRANSCODER_B,
214 POWER_DOMAIN_TRANSCODER_C,
215 POWER_DOMAIN_TRANSCODER_EDP,
216 POWER_DOMAIN_TRANSCODER_DSI_A,
217 POWER_DOMAIN_TRANSCODER_DSI_C,
218 POWER_DOMAIN_PORT_DDI_A_LANES,
219 POWER_DOMAIN_PORT_DDI_B_LANES,
220 POWER_DOMAIN_PORT_DDI_C_LANES,
221 POWER_DOMAIN_PORT_DDI_D_LANES,
222 POWER_DOMAIN_PORT_DDI_E_LANES,
223 POWER_DOMAIN_PORT_DSI,
224 POWER_DOMAIN_PORT_CRT,
225 POWER_DOMAIN_PORT_OTHER,
234 POWER_DOMAIN_MODESET,
240 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
241 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
242 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
243 #define POWER_DOMAIN_TRANSCODER(tran) \
244 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
245 (tran) + POWER_DOMAIN_TRANSCODER_A)
249 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
261 #define for_each_hpd_pin(__pin) \
262 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
264 struct i915_hotplug {
265 struct work_struct hotplug_work;
268 unsigned long last_jiffies;
273 HPD_MARK_DISABLED = 2
275 } stats[HPD_NUM_PINS];
277 struct delayed_work reenable_work;
279 struct intel_digital_port *irq_port[I915_MAX_PORTS];
282 struct work_struct dig_port_work;
285 * if we get a HPD irq from DP and a HPD irq from non-DP
286 * the non-DP HPD could block the workqueue on a mode config
287 * mutex getting, that userspace may have taken. However
288 * userspace is waiting on the DP workqueue to run which is
289 * blocked behind the non-DP one.
291 struct workqueue_struct *dp_wq;
294 #define I915_GEM_GPU_DOMAINS \
295 (I915_GEM_DOMAIN_RENDER | \
296 I915_GEM_DOMAIN_SAMPLER | \
297 I915_GEM_DOMAIN_COMMAND | \
298 I915_GEM_DOMAIN_INSTRUCTION | \
299 I915_GEM_DOMAIN_VERTEX)
301 #define for_each_pipe(__dev_priv, __p) \
302 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
303 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
304 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
305 for_each_if ((__mask) & (1 << (__p)))
306 #define for_each_plane(__dev_priv, __pipe, __p) \
308 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
310 #define for_each_sprite(__dev_priv, __p, __s) \
312 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
315 #define for_each_port_masked(__port, __ports_mask) \
316 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
317 for_each_if ((__ports_mask) & (1 << (__port)))
319 #define for_each_crtc(dev, crtc) \
320 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
322 #define for_each_intel_plane(dev, intel_plane) \
323 list_for_each_entry(intel_plane, \
324 &dev->mode_config.plane_list, \
327 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
328 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, \
330 for_each_if ((plane_mask) & \
331 (1 << drm_plane_index(&intel_plane->base)))
333 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
334 list_for_each_entry(intel_plane, \
335 &(dev)->mode_config.plane_list, \
337 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
339 #define for_each_intel_crtc(dev, intel_crtc) \
340 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
342 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
343 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) \
344 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
346 #define for_each_intel_encoder(dev, intel_encoder) \
347 list_for_each_entry(intel_encoder, \
348 &(dev)->mode_config.encoder_list, \
351 #define for_each_intel_connector(dev, intel_connector) \
352 list_for_each_entry(intel_connector, \
353 &dev->mode_config.connector_list, \
356 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
357 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
358 for_each_if ((intel_encoder)->base.crtc == (__crtc))
360 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
361 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
362 for_each_if ((intel_connector)->base.encoder == (__encoder))
364 #define for_each_power_domain(domain, mask) \
365 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
366 for_each_if ((1 << (domain)) & (mask))
368 struct drm_i915_private;
369 struct i915_mm_struct;
370 struct i915_mmu_object;
372 struct drm_i915_file_private {
373 struct drm_i915_private *dev_priv;
374 struct drm_file *file;
378 struct list_head request_list;
379 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
380 * chosen to prevent the CPU getting more than a frame ahead of the GPU
381 * (when using lax throttling for the frontbuffer). We also use it to
382 * offer free GPU waitboosts for severely congested workloads.
384 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
386 struct idr context_idr;
388 struct intel_rps_client {
389 struct list_head link;
393 unsigned int bsd_ring;
396 /* Used by dp and fdi links */
397 struct intel_link_m_n {
405 void intel_link_compute_m_n(int bpp, int nlanes,
406 int pixel_clock, int link_clock,
407 struct intel_link_m_n *m_n);
409 /* Interface history:
412 * 1.2: Add Power Management
413 * 1.3: Add vblank support
414 * 1.4: Fix cmdbuffer path, add heap destroy
415 * 1.5: Add vblank pipe configuration
416 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
417 * - Support vertical blank on secondary display pipe
419 #define DRIVER_MAJOR 1
420 #define DRIVER_MINOR 6
421 #define DRIVER_PATCHLEVEL 0
423 #define WATCH_LISTS 0
425 struct opregion_header;
426 struct opregion_acpi;
427 struct opregion_swsci;
428 struct opregion_asle;
430 struct intel_opregion {
431 struct opregion_header *header;
432 struct opregion_acpi *acpi;
433 struct opregion_swsci *swsci;
434 u32 swsci_gbda_sub_functions;
435 u32 swsci_sbcb_sub_functions;
436 struct opregion_asle *asle;
441 struct work_struct asle_work;
443 #define OPREGION_SIZE (8*1024)
445 struct intel_overlay;
446 struct intel_overlay_error_state;
448 #define I915_FENCE_REG_NONE -1
449 #define I915_MAX_NUM_FENCES 32
450 /* 32 fences + sign bit for FENCE_REG_NONE */
451 #define I915_MAX_NUM_FENCE_BITS 6
453 struct drm_i915_fence_reg {
454 struct list_head lru_list;
455 struct drm_i915_gem_object *obj;
459 struct sdvo_device_mapping {
468 struct intel_display_error_state;
470 struct drm_i915_error_state {
479 /* Generic register state */
487 u32 error; /* gen6+ */
488 u32 err_int; /* gen7 */
489 u32 fault_data0; /* gen8, gen9 */
490 u32 fault_data1; /* gen8, gen9 */
496 u32 extra_instdone[I915_NUM_INSTDONE_REG];
497 u64 fence[I915_MAX_NUM_FENCES];
498 struct intel_overlay_error_state *overlay;
499 struct intel_display_error_state *display;
500 struct drm_i915_error_object *semaphore_obj;
502 struct drm_i915_error_ring {
504 /* Software tracked state */
507 enum intel_ring_hangcheck_action hangcheck_action;
510 /* our own tracking of ring head and tail */
515 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
534 u32 rc_psmi; /* sleep state */
535 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
537 struct drm_i915_error_object {
541 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
543 struct drm_i915_error_object *wa_ctx;
545 struct drm_i915_error_request {
560 char comm[TASK_COMM_LEN];
561 } ring[I915_NUM_ENGINES];
563 struct drm_i915_error_buffer {
566 u32 rseqno[I915_NUM_ENGINES], wseqno;
570 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
578 } **active_bo, **pinned_bo;
580 u32 *active_bo_count, *pinned_bo_count;
584 struct intel_connector;
585 struct intel_encoder;
586 struct intel_crtc_state;
587 struct intel_initial_plane_config;
592 struct drm_i915_display_funcs {
593 int (*get_display_clock_speed)(struct drm_device *dev);
594 int (*get_fifo_size)(struct drm_device *dev, int plane);
595 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
596 int (*compute_intermediate_wm)(struct drm_device *dev,
597 struct intel_crtc *intel_crtc,
598 struct intel_crtc_state *newstate);
599 void (*initial_watermarks)(struct intel_crtc_state *cstate);
600 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
601 int (*compute_global_watermarks)(struct drm_atomic_state *state);
602 void (*update_wm)(struct drm_crtc *crtc);
603 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
604 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
605 /* Returns the active state of the crtc, and if the crtc is active,
606 * fills out the pipe-config with the hw state. */
607 bool (*get_pipe_config)(struct intel_crtc *,
608 struct intel_crtc_state *);
609 void (*get_initial_plane_config)(struct intel_crtc *,
610 struct intel_initial_plane_config *);
611 int (*crtc_compute_clock)(struct intel_crtc *crtc,
612 struct intel_crtc_state *crtc_state);
613 void (*crtc_enable)(struct drm_crtc *crtc);
614 void (*crtc_disable)(struct drm_crtc *crtc);
615 void (*audio_codec_enable)(struct drm_connector *connector,
616 struct intel_encoder *encoder,
617 const struct drm_display_mode *adjusted_mode);
618 void (*audio_codec_disable)(struct intel_encoder *encoder);
619 void (*fdi_link_train)(struct drm_crtc *crtc);
620 void (*init_clock_gating)(struct drm_device *dev);
621 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
622 struct drm_framebuffer *fb,
623 struct drm_i915_gem_object *obj,
624 struct drm_i915_gem_request *req,
626 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
627 /* clock updates for mode set */
629 /* render clock increase/decrease */
630 /* display clock increase/decrease */
631 /* pll clock increase/decrease */
633 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
634 void (*load_luts)(struct drm_crtc_state *crtc_state);
637 enum forcewake_domain_id {
638 FW_DOMAIN_ID_RENDER = 0,
639 FW_DOMAIN_ID_BLITTER,
645 enum forcewake_domains {
646 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
647 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
648 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
649 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
654 #define FW_REG_READ (1)
655 #define FW_REG_WRITE (2)
657 enum forcewake_domains
658 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
659 i915_reg_t reg, unsigned int op);
661 struct intel_uncore_funcs {
662 void (*force_wake_get)(struct drm_i915_private *dev_priv,
663 enum forcewake_domains domains);
664 void (*force_wake_put)(struct drm_i915_private *dev_priv,
665 enum forcewake_domains domains);
667 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
668 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
669 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
670 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
672 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
673 uint8_t val, bool trace);
674 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
675 uint16_t val, bool trace);
676 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
677 uint32_t val, bool trace);
678 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
679 uint64_t val, bool trace);
682 struct intel_uncore {
683 spinlock_t lock; /** lock is also taken in irq contexts. */
685 struct intel_uncore_funcs funcs;
688 enum forcewake_domains fw_domains;
690 struct intel_uncore_forcewake_domain {
691 struct drm_i915_private *i915;
692 enum forcewake_domain_id id;
693 enum forcewake_domains mask;
695 struct hrtimer timer;
702 } fw_domain[FW_DOMAIN_ID_COUNT];
704 int unclaimed_mmio_check;
707 /* Iterate over initialised fw domains */
708 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
709 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
710 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
712 for_each_if ((mask__) & (domain__)->mask)
714 #define for_each_fw_domain(domain__, dev_priv__) \
715 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
717 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
718 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
719 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
722 struct work_struct work;
724 uint32_t *dmc_payload;
725 uint32_t dmc_fw_size;
728 i915_reg_t mmioaddr[8];
729 uint32_t mmiodata[8];
731 uint32_t allowed_dc_mask;
734 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
735 func(is_mobile) sep \
738 func(is_i945gm) sep \
740 func(need_gfx_hws) sep \
742 func(is_pineview) sep \
743 func(is_broadwater) sep \
744 func(is_crestline) sep \
745 func(is_ivybridge) sep \
746 func(is_valleyview) sep \
747 func(is_cherryview) sep \
748 func(is_haswell) sep \
749 func(is_broadwell) sep \
750 func(is_skylake) sep \
751 func(is_broxton) sep \
752 func(is_kabylake) sep \
753 func(is_preliminary) sep \
755 func(has_pipe_cxsr) sep \
756 func(has_hotplug) sep \
757 func(cursor_needs_physical) sep \
758 func(has_overlay) sep \
759 func(overlay_needs_physical) sep \
760 func(supports_tv) sep \
762 func(has_snoop) sep \
766 #define DEFINE_FLAG(name) u8 name:1
767 #define SEP_SEMICOLON ;
769 struct intel_device_info {
770 u32 display_mmio_offset;
773 u8 num_sprites[I915_MAX_PIPES];
776 u8 ring_mask; /* Rings supported by the HW */
777 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
778 /* Register offsets for the various display pipes and transcoders */
779 int pipe_offsets[I915_MAX_TRANSCODERS];
780 int trans_offsets[I915_MAX_TRANSCODERS];
781 int palette_offsets[I915_MAX_PIPES];
782 int cursor_offsets[I915_MAX_PIPES];
784 /* Slice/subslice/EU info */
787 u8 subslice_per_slice;
790 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
793 u8 has_subslice_pg:1;
797 u16 degamma_lut_size;
805 enum i915_cache_level {
807 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
808 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
809 caches, eg sampler/render caches, and the
810 large Last-Level-Cache. LLC is coherent with
811 the CPU, but L3 is only visible to the GPU. */
812 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
815 struct i915_ctx_hang_stats {
816 /* This context had batch pending when hang was declared */
817 unsigned batch_pending;
819 /* This context had batch active when hang was declared */
820 unsigned batch_active;
822 /* Time when this context was last blamed for a GPU reset */
823 unsigned long guilty_ts;
825 /* If the contexts causes a second GPU hang within this time,
826 * it is permanently banned from submitting any more work.
828 unsigned long ban_period_seconds;
830 /* This context is banned to submit more work */
834 /* This must match up with the value previously used for execbuf2.rsvd1. */
835 #define DEFAULT_CONTEXT_HANDLE 0
838 * struct i915_gem_context - as the name implies, represents a context.
839 * @ref: reference count.
840 * @user_handle: userspace tracking identity for this context.
841 * @remap_slice: l3 row remapping information.
842 * @flags: context specific flags:
843 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
844 * @file_priv: filp associated with this context (NULL for global default
846 * @hang_stats: information about the role of this context in possible GPU
848 * @ppgtt: virtual memory space used by this context.
849 * @legacy_hw_ctx: render context backing object and whether it is correctly
850 * initialized (legacy ring submission mechanism only).
851 * @link: link in the global list of contexts.
853 * Contexts are memory images used by the hardware to store copies of their
856 struct i915_gem_context {
858 struct drm_i915_private *i915;
859 struct drm_i915_file_private *file_priv;
860 struct i915_hw_ppgtt *ppgtt;
862 struct i915_ctx_hang_stats hang_stats;
864 /* Unique identifier for this context, used by the hw for tracking */
868 #define CONTEXT_NO_ZEROMAP (1<<0)
870 struct intel_context {
871 struct drm_i915_gem_object *state;
872 struct intel_ringbuffer *ringbuf;
873 struct i915_vma *lrc_vma;
874 uint32_t *lrc_reg_state;
878 } engine[I915_NUM_ENGINES];
880 struct list_head link;
894 /* This is always the inner lock when overlapping with struct_mutex and
895 * it's the outer lock when overlapping with stolen_lock. */
898 unsigned int possible_framebuffer_bits;
899 unsigned int busy_bits;
900 unsigned int visible_pipes_mask;
901 struct intel_crtc *crtc;
903 struct drm_mm_node compressed_fb;
904 struct drm_mm_node *compressed_llb;
911 struct intel_fbc_state_cache {
913 unsigned int mode_flags;
914 uint32_t hsw_bdw_pixel_rate;
918 unsigned int rotation;
926 uint32_t pixel_format;
929 unsigned int tiling_mode;
933 struct intel_fbc_reg_params {
937 unsigned int fence_y_offset;
942 uint32_t pixel_format;
950 struct intel_fbc_work {
952 u32 scheduled_vblank;
953 struct work_struct work;
956 const char *no_fbc_reason;
960 * HIGH_RR is the highest eDP panel refresh rate read from EDID
961 * LOW_RR is the lowest eDP panel refresh rate found from EDID
962 * parsing for same resolution.
964 enum drrs_refresh_rate_type {
967 DRRS_MAX_RR, /* RR count */
970 enum drrs_support_type {
971 DRRS_NOT_SUPPORTED = 0,
972 STATIC_DRRS_SUPPORT = 1,
973 SEAMLESS_DRRS_SUPPORT = 2
979 struct delayed_work work;
981 unsigned busy_frontbuffer_bits;
982 enum drrs_refresh_rate_type refresh_rate_type;
983 enum drrs_support_type type;
990 struct intel_dp *enabled;
992 struct delayed_work work;
993 unsigned busy_frontbuffer_bits;
1000 PCH_NONE = 0, /* No PCH present */
1001 PCH_IBX, /* Ibexpeak PCH */
1002 PCH_CPT, /* Cougarpoint PCH */
1003 PCH_LPT, /* Lynxpoint PCH */
1004 PCH_SPT, /* Sunrisepoint PCH */
1008 enum intel_sbi_destination {
1013 #define QUIRK_PIPEA_FORCE (1<<0)
1014 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1015 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1016 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1017 #define QUIRK_PIPEB_FORCE (1<<4)
1018 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1021 struct intel_fbc_work;
1023 struct intel_gmbus {
1024 struct i2c_adapter adapter;
1025 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1028 i915_reg_t gpio_reg;
1029 struct i2c_algo_bit_data bit_algo;
1030 struct drm_i915_private *dev_priv;
1033 struct i915_suspend_saved_registers {
1036 u32 savePP_ON_DELAYS;
1037 u32 savePP_OFF_DELAYS;
1042 u32 saveFBC_CONTROL;
1043 u32 saveCACHE_MODE_0;
1044 u32 saveMI_ARB_STATE;
1048 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1049 u32 savePCH_PORT_HOTPLUG;
1053 struct vlv_s0ix_state {
1060 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1061 u32 media_max_req_count;
1062 u32 gfx_max_req_count;
1088 u32 rp_down_timeout;
1094 /* Display 1 CZ domain */
1099 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1101 /* GT SA CZ domain */
1108 /* Display 2 CZ domain */
1112 u32 clock_gate_dis2;
1115 struct intel_rps_ei {
1121 struct intel_gen6_power_mgmt {
1123 * work, interrupts_enabled and pm_iir are protected by
1124 * dev_priv->irq_lock
1126 struct work_struct work;
1127 bool interrupts_enabled;
1132 /* Frequencies are stored in potentially platform dependent multiples.
1133 * In other words, *_freq needs to be multiplied by X to be interesting.
1134 * Soft limits are those which are used for the dynamic reclocking done
1135 * by the driver (raise frequencies under heavy loads, and lower for
1136 * lighter loads). Hard limits are those imposed by the hardware.
1138 * A distinction is made for overclocking, which is never enabled by
1139 * default, and is considered to be above the hard limit if it's
1142 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1143 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1144 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1145 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1146 u8 min_freq; /* AKA RPn. Minimum frequency */
1147 u8 idle_freq; /* Frequency to request when we are idle */
1148 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1149 u8 rp1_freq; /* "less than" RP0 power/freqency */
1150 u8 rp0_freq; /* Non-overclocked max frequency. */
1151 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1153 u8 up_threshold; /* Current %busy required to uplock */
1154 u8 down_threshold; /* Current %busy required to downclock */
1157 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1159 spinlock_t client_lock;
1160 struct list_head clients;
1164 struct delayed_work delayed_resume_work;
1167 struct intel_rps_client semaphores, mmioflips;
1169 /* manual wa residency calculations */
1170 struct intel_rps_ei up_ei, down_ei;
1173 * Protects RPS/RC6 register access and PCU communication.
1174 * Must be taken after struct_mutex if nested. Note that
1175 * this lock may be held for long periods of time when
1176 * talking to hw - so only take it when talking to hw!
1178 struct mutex hw_lock;
1181 /* defined intel_pm.c */
1182 extern spinlock_t mchdev_lock;
1184 struct intel_ilk_power_mgmt {
1192 unsigned long last_time1;
1193 unsigned long chipset_power;
1196 unsigned long gfx_power;
1203 struct drm_i915_private;
1204 struct i915_power_well;
1206 struct i915_power_well_ops {
1208 * Synchronize the well's hw state to match the current sw state, for
1209 * example enable/disable it based on the current refcount. Called
1210 * during driver init and resume time, possibly after first calling
1211 * the enable/disable handlers.
1213 void (*sync_hw)(struct drm_i915_private *dev_priv,
1214 struct i915_power_well *power_well);
1216 * Enable the well and resources that depend on it (for example
1217 * interrupts located on the well). Called after the 0->1 refcount
1220 void (*enable)(struct drm_i915_private *dev_priv,
1221 struct i915_power_well *power_well);
1223 * Disable the well and resources that depend on it. Called after
1224 * the 1->0 refcount transition.
1226 void (*disable)(struct drm_i915_private *dev_priv,
1227 struct i915_power_well *power_well);
1228 /* Returns the hw enabled state. */
1229 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1230 struct i915_power_well *power_well);
1233 /* Power well structure for haswell */
1234 struct i915_power_well {
1237 /* power well enable/disable usage count */
1239 /* cached hw enabled state */
1241 unsigned long domains;
1243 const struct i915_power_well_ops *ops;
1246 struct i915_power_domains {
1248 * Power wells needed for initialization at driver init and suspend
1249 * time are on. They are kept on until after the first modeset.
1253 int power_well_count;
1256 int domain_use_count[POWER_DOMAIN_NUM];
1257 struct i915_power_well *power_wells;
1260 #define MAX_L3_SLICES 2
1261 struct intel_l3_parity {
1262 u32 *remap_info[MAX_L3_SLICES];
1263 struct work_struct error_work;
1267 struct i915_gem_mm {
1268 /** Memory allocator for GTT stolen memory */
1269 struct drm_mm stolen;
1270 /** Protects the usage of the GTT stolen memory allocator. This is
1271 * always the inner lock when overlapping with struct_mutex. */
1272 struct mutex stolen_lock;
1274 /** List of all objects in gtt_space. Used to restore gtt
1275 * mappings on resume */
1276 struct list_head bound_list;
1278 * List of objects which are not bound to the GTT (thus
1279 * are idle and not used by the GPU) but still have
1280 * (presumably uncached) pages still attached.
1282 struct list_head unbound_list;
1284 /** Usable portion of the GTT for GEM */
1285 unsigned long stolen_base; /* limited to low memory (32-bit) */
1287 /** PPGTT used for aliasing the PPGTT with the GTT */
1288 struct i915_hw_ppgtt *aliasing_ppgtt;
1290 struct notifier_block oom_notifier;
1291 struct notifier_block vmap_notifier;
1292 struct shrinker shrinker;
1293 bool shrinker_no_lock_stealing;
1295 /** LRU list of objects with fence regs on them. */
1296 struct list_head fence_list;
1299 * We leave the user IRQ off as much as possible,
1300 * but this means that requests will finish and never
1301 * be retired once the system goes idle. Set a timer to
1302 * fire periodically while the ring is running. When it
1303 * fires, go retire requests.
1305 struct delayed_work retire_work;
1308 * When we detect an idle GPU, we want to turn on
1309 * powersaving features. So once we see that there
1310 * are no more requests outstanding and no more
1311 * arrive within a small period of time, we fire
1312 * off the idle_work.
1314 struct delayed_work idle_work;
1317 * Are we in a non-interruptible section of code like
1323 * Is the GPU currently considered idle, or busy executing userspace
1324 * requests? Whilst idle, we attempt to power down the hardware and
1325 * display clocks. In order to reduce the effect on performance, there
1326 * is a slight delay before we do so.
1330 /* the indicator for dispatch video commands on two BSD rings */
1331 unsigned int bsd_ring_dispatch_index;
1333 /** Bit 6 swizzling required for X tiling */
1334 uint32_t bit_6_swizzle_x;
1335 /** Bit 6 swizzling required for Y tiling */
1336 uint32_t bit_6_swizzle_y;
1338 /* accounting, useful for userland debugging */
1339 spinlock_t object_stat_lock;
1340 size_t object_memory;
1344 struct drm_i915_error_state_buf {
1345 struct drm_i915_private *i915;
1354 struct i915_error_state_file_priv {
1355 struct drm_device *dev;
1356 struct drm_i915_error_state *error;
1359 struct i915_gpu_error {
1360 /* For hangcheck timer */
1361 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1362 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1363 /* Hang gpu twice in this window and your context gets banned */
1364 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1366 struct workqueue_struct *hangcheck_wq;
1367 struct delayed_work hangcheck_work;
1369 /* For reset and error_state handling. */
1371 /* Protected by the above dev->gpu_error.lock. */
1372 struct drm_i915_error_state *first_error;
1374 unsigned long missed_irq_rings;
1377 * State variable controlling the reset flow and count
1379 * This is a counter which gets incremented when reset is triggered,
1380 * and again when reset has been handled. So odd values (lowest bit set)
1381 * means that reset is in progress and even values that
1382 * (reset_counter >> 1):th reset was successfully completed.
1384 * If reset is not completed succesfully, the I915_WEDGE bit is
1385 * set meaning that hardware is terminally sour and there is no
1386 * recovery. All waiters on the reset_queue will be woken when
1389 * This counter is used by the wait_seqno code to notice that reset
1390 * event happened and it needs to restart the entire ioctl (since most
1391 * likely the seqno it waited for won't ever signal anytime soon).
1393 * This is important for lock-free wait paths, where no contended lock
1394 * naturally enforces the correct ordering between the bail-out of the
1395 * waiter and the gpu reset work code.
1397 atomic_t reset_counter;
1399 #define I915_RESET_IN_PROGRESS_FLAG 1
1400 #define I915_WEDGED (1 << 31)
1403 * Waitqueue to signal when the reset has completed. Used by clients
1404 * that wait for dev_priv->mm.wedged to settle.
1406 wait_queue_head_t reset_queue;
1408 /* Userspace knobs for gpu hang simulation;
1409 * combines both a ring mask, and extra flags
1412 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1413 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1415 /* For missed irq/seqno simulation. */
1416 unsigned int test_irq_rings;
1419 enum modeset_restore {
1420 MODESET_ON_LID_OPEN,
1425 #define DP_AUX_A 0x40
1426 #define DP_AUX_B 0x10
1427 #define DP_AUX_C 0x20
1428 #define DP_AUX_D 0x30
1430 #define DDC_PIN_B 0x05
1431 #define DDC_PIN_C 0x04
1432 #define DDC_PIN_D 0x06
1434 struct ddi_vbt_port_info {
1436 * This is an index in the HDMI/DVI DDI buffer translation table.
1437 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1438 * populate this field.
1440 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1441 uint8_t hdmi_level_shift;
1443 uint8_t supports_dvi:1;
1444 uint8_t supports_hdmi:1;
1445 uint8_t supports_dp:1;
1447 uint8_t alternate_aux_channel;
1448 uint8_t alternate_ddc_pin;
1450 uint8_t dp_boost_level;
1451 uint8_t hdmi_boost_level;
1454 enum psr_lines_to_wait {
1455 PSR_0_LINES_TO_WAIT = 0,
1457 PSR_4_LINES_TO_WAIT,
1461 struct intel_vbt_data {
1462 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1463 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1466 unsigned int int_tv_support:1;
1467 unsigned int lvds_dither:1;
1468 unsigned int lvds_vbt:1;
1469 unsigned int int_crt_support:1;
1470 unsigned int lvds_use_ssc:1;
1471 unsigned int display_clock_mode:1;
1472 unsigned int fdi_rx_polarity_inverted:1;
1473 unsigned int panel_type:4;
1475 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1477 enum drrs_support_type drrs_type;
1488 struct edp_power_seq pps;
1493 bool require_aux_wakeup;
1495 enum psr_lines_to_wait lines_to_wait;
1496 int tp1_wakeup_time;
1497 int tp2_tp3_wakeup_time;
1503 bool active_low_pwm;
1504 u8 min_brightness; /* min_brightness/255 of max */
1505 enum intel_backlight_type type;
1511 struct mipi_config *config;
1512 struct mipi_pps_data *pps;
1516 const u8 *sequence[MIPI_SEQ_MAX];
1522 union child_device_config *child_dev;
1524 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1525 struct sdvo_device_mapping sdvo_mappings[2];
1528 enum intel_ddb_partitioning {
1530 INTEL_DDB_PART_5_6, /* IVB+ */
1533 struct intel_wm_level {
1541 struct ilk_wm_values {
1542 uint32_t wm_pipe[3];
1544 uint32_t wm_lp_spr[3];
1545 uint32_t wm_linetime[3];
1547 enum intel_ddb_partitioning partitioning;
1550 struct vlv_pipe_wm {
1561 struct vlv_wm_values {
1562 struct vlv_pipe_wm pipe[3];
1563 struct vlv_sr_wm sr;
1573 struct skl_ddb_entry {
1574 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1577 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1579 return entry->end - entry->start;
1582 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1583 const struct skl_ddb_entry *e2)
1585 if (e1->start == e2->start && e1->end == e2->end)
1591 struct skl_ddb_allocation {
1592 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1593 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1594 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1597 struct skl_wm_values {
1598 unsigned dirty_pipes;
1599 struct skl_ddb_allocation ddb;
1600 uint32_t wm_linetime[I915_MAX_PIPES];
1601 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1602 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1605 struct skl_wm_level {
1606 bool plane_en[I915_MAX_PLANES];
1607 uint16_t plane_res_b[I915_MAX_PLANES];
1608 uint8_t plane_res_l[I915_MAX_PLANES];
1612 * This struct helps tracking the state needed for runtime PM, which puts the
1613 * device in PCI D3 state. Notice that when this happens, nothing on the
1614 * graphics device works, even register access, so we don't get interrupts nor
1617 * Every piece of our code that needs to actually touch the hardware needs to
1618 * either call intel_runtime_pm_get or call intel_display_power_get with the
1619 * appropriate power domain.
1621 * Our driver uses the autosuspend delay feature, which means we'll only really
1622 * suspend if we stay with zero refcount for a certain amount of time. The
1623 * default value is currently very conservative (see intel_runtime_pm_enable), but
1624 * it can be changed with the standard runtime PM files from sysfs.
1626 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1627 * goes back to false exactly before we reenable the IRQs. We use this variable
1628 * to check if someone is trying to enable/disable IRQs while they're supposed
1629 * to be disabled. This shouldn't happen and we'll print some error messages in
1632 * For more, read the Documentation/power/runtime_pm.txt.
1634 struct i915_runtime_pm {
1635 atomic_t wakeref_count;
1636 atomic_t atomic_seq;
1641 enum intel_pipe_crc_source {
1642 INTEL_PIPE_CRC_SOURCE_NONE,
1643 INTEL_PIPE_CRC_SOURCE_PLANE1,
1644 INTEL_PIPE_CRC_SOURCE_PLANE2,
1645 INTEL_PIPE_CRC_SOURCE_PF,
1646 INTEL_PIPE_CRC_SOURCE_PIPE,
1647 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1648 INTEL_PIPE_CRC_SOURCE_TV,
1649 INTEL_PIPE_CRC_SOURCE_DP_B,
1650 INTEL_PIPE_CRC_SOURCE_DP_C,
1651 INTEL_PIPE_CRC_SOURCE_DP_D,
1652 INTEL_PIPE_CRC_SOURCE_AUTO,
1653 INTEL_PIPE_CRC_SOURCE_MAX,
1656 struct intel_pipe_crc_entry {
1661 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1662 struct intel_pipe_crc {
1664 bool opened; /* exclusive access to the result file */
1665 struct intel_pipe_crc_entry *entries;
1666 enum intel_pipe_crc_source source;
1668 wait_queue_head_t wq;
1671 struct i915_frontbuffer_tracking {
1675 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1682 struct i915_wa_reg {
1685 /* bitmask representing WA bits */
1690 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1691 * allowing it for RCS as we don't foresee any requirement of having
1692 * a whitelist for other engines. When it is really required for
1693 * other engines then the limit need to be increased.
1695 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1697 struct i915_workarounds {
1698 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1700 u32 hw_whitelist_count[I915_NUM_ENGINES];
1703 struct i915_virtual_gpu {
1707 struct i915_execbuffer_params {
1708 struct drm_device *dev;
1709 struct drm_file *file;
1710 uint32_t dispatch_flags;
1711 uint32_t args_batch_start_offset;
1712 uint64_t batch_obj_vm_offset;
1713 struct intel_engine_cs *engine;
1714 struct drm_i915_gem_object *batch_obj;
1715 struct i915_gem_context *ctx;
1716 struct drm_i915_gem_request *request;
1719 /* used in computing the new watermarks state */
1720 struct intel_wm_config {
1721 unsigned int num_pipes_active;
1722 bool sprites_enabled;
1723 bool sprites_scaled;
1726 struct drm_i915_private {
1727 struct drm_device *dev;
1728 struct kmem_cache *objects;
1729 struct kmem_cache *vmas;
1730 struct kmem_cache *requests;
1732 const struct intel_device_info info;
1734 int relative_constants_mode;
1738 struct intel_uncore uncore;
1740 struct i915_virtual_gpu vgpu;
1742 struct intel_guc guc;
1744 struct intel_csr csr;
1746 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1748 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1749 * controller on different i2c buses. */
1750 struct mutex gmbus_mutex;
1753 * Base address of the gmbus and gpio block.
1755 uint32_t gpio_mmio_base;
1757 /* MMIO base address for MIPI regs */
1758 uint32_t mipi_mmio_base;
1760 uint32_t psr_mmio_base;
1762 wait_queue_head_t gmbus_wait_queue;
1764 struct pci_dev *bridge_dev;
1765 struct i915_gem_context *kernel_context;
1766 struct intel_engine_cs engine[I915_NUM_ENGINES];
1767 struct drm_i915_gem_object *semaphore_obj;
1768 uint32_t last_seqno, next_seqno;
1770 struct drm_dma_handle *status_page_dmah;
1771 struct resource mch_res;
1773 /* protects the irq masks */
1774 spinlock_t irq_lock;
1776 /* protects the mmio flip data */
1777 spinlock_t mmio_flip_lock;
1779 bool display_irqs_enabled;
1781 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1782 struct pm_qos_request pm_qos;
1784 /* Sideband mailbox protection */
1785 struct mutex sb_lock;
1787 /** Cached value of IMR to avoid reads in updating the bitfield */
1790 u32 de_irq_mask[I915_MAX_PIPES];
1795 u32 pipestat_irq_mask[I915_MAX_PIPES];
1797 struct i915_hotplug hotplug;
1798 struct intel_fbc fbc;
1799 struct i915_drrs drrs;
1800 struct intel_opregion opregion;
1801 struct intel_vbt_data vbt;
1803 bool preserve_bios_swizzle;
1806 struct intel_overlay *overlay;
1808 /* backlight registers and fields in struct intel_panel */
1809 struct mutex backlight_lock;
1812 bool no_aux_handshake;
1814 /* protects panel power sequencer state */
1815 struct mutex pps_mutex;
1817 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1818 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1820 unsigned int fsb_freq, mem_freq, is_ddr3;
1821 unsigned int skl_preferred_vco_freq;
1822 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1823 unsigned int max_dotclk_freq;
1824 unsigned int rawclk_freq;
1825 unsigned int hpll_freq;
1826 unsigned int czclk_freq;
1829 unsigned int vco, ref;
1833 * wq - Driver workqueue for GEM.
1835 * NOTE: Work items scheduled here are not allowed to grab any modeset
1836 * locks, for otherwise the flushing done in the pageflip code will
1837 * result in deadlocks.
1839 struct workqueue_struct *wq;
1841 /* Display functions */
1842 struct drm_i915_display_funcs display;
1844 /* PCH chipset type */
1845 enum intel_pch pch_type;
1846 unsigned short pch_id;
1848 unsigned long quirks;
1850 enum modeset_restore modeset_restore;
1851 struct mutex modeset_restore_lock;
1852 struct drm_atomic_state *modeset_restore_state;
1854 struct list_head vm_list; /* Global list of all address spaces */
1855 struct i915_ggtt ggtt; /* VM representing the global address space */
1857 struct i915_gem_mm mm;
1858 DECLARE_HASHTABLE(mm_structs, 7);
1859 struct mutex mm_lock;
1861 /* The hw wants to have a stable context identifier for the lifetime
1862 * of the context (for OA, PASID, faults, etc). This is limited
1863 * in execlists to 21 bits.
1865 struct ida context_hw_ida;
1866 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1868 /* Kernel Modesetting */
1870 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1871 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1872 wait_queue_head_t pending_flip_queue;
1874 #ifdef CONFIG_DEBUG_FS
1875 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1878 /* dpll and cdclk state is protected by connection_mutex */
1879 int num_shared_dpll;
1880 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1881 const struct intel_dpll_mgr *dpll_mgr;
1884 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1885 * Must be global rather than per dpll, because on some platforms
1886 * plls share registers.
1888 struct mutex dpll_lock;
1890 unsigned int active_crtcs;
1891 unsigned int min_pixclk[I915_MAX_PIPES];
1893 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1895 struct i915_workarounds workarounds;
1897 struct i915_frontbuffer_tracking fb_tracking;
1901 bool mchbar_need_disable;
1903 struct intel_l3_parity l3_parity;
1905 /* Cannot be determined by PCIID. You must always read a register. */
1908 /* gen6+ rps state */
1909 struct intel_gen6_power_mgmt rps;
1911 /* ilk-only ips/rps state. Everything in here is protected by the global
1912 * mchdev_lock in intel_pm.c */
1913 struct intel_ilk_power_mgmt ips;
1915 struct i915_power_domains power_domains;
1917 struct i915_psr psr;
1919 struct i915_gpu_error gpu_error;
1921 struct drm_i915_gem_object *vlv_pctx;
1923 #ifdef CONFIG_DRM_FBDEV_EMULATION
1924 /* list of fbdev register on this device */
1925 struct intel_fbdev *fbdev;
1926 struct work_struct fbdev_suspend_work;
1929 struct drm_property *broadcast_rgb_property;
1930 struct drm_property *force_audio_property;
1932 /* hda/i915 audio component */
1933 struct i915_audio_component *audio_component;
1934 bool audio_component_registered;
1936 * av_mutex - mutex for audio/video sync
1939 struct mutex av_mutex;
1941 uint32_t hw_context_size;
1942 struct list_head context_list;
1946 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1947 u32 chv_phy_control;
1949 * Shadows for CHV DPLL_MD regs to keep the state
1950 * checker somewhat working in the presence hardware
1951 * crappiness (can't read out DPLL_MD for pipes B & C).
1953 u32 chv_dpll_md[I915_MAX_PIPES];
1957 bool suspended_to_idle;
1958 struct i915_suspend_saved_registers regfile;
1959 struct vlv_s0ix_state vlv_s0ix_state;
1963 * Raw watermark latency values:
1964 * in 0.1us units for WM0,
1965 * in 0.5us units for WM1+.
1968 uint16_t pri_latency[5];
1970 uint16_t spr_latency[5];
1972 uint16_t cur_latency[5];
1974 * Raw watermark memory latency values
1975 * for SKL for all 8 levels
1978 uint16_t skl_latency[8];
1981 * The skl_wm_values structure is a bit too big for stack
1982 * allocation, so we keep the staging struct where we store
1983 * intermediate results here instead.
1985 struct skl_wm_values skl_results;
1987 /* current hardware state */
1989 struct ilk_wm_values hw;
1990 struct skl_wm_values skl_hw;
1991 struct vlv_wm_values vlv;
1997 * Should be held around atomic WM register writing; also
1998 * protects * intel_crtc->wm.active and
1999 * cstate->wm.need_postvbl_update.
2001 struct mutex wm_mutex;
2004 * Set during HW readout of watermarks/DDB. Some platforms
2005 * need to know when we're still using BIOS-provided values
2006 * (which we don't fully trust).
2008 bool distrust_bios_wm;
2011 struct i915_runtime_pm pm;
2013 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2015 int (*execbuf_submit)(struct i915_execbuffer_params *params,
2016 struct drm_i915_gem_execbuffer2 *args,
2017 struct list_head *vmas);
2018 int (*init_engines)(struct drm_device *dev);
2019 void (*cleanup_engine)(struct intel_engine_cs *engine);
2020 void (*stop_engine)(struct intel_engine_cs *engine);
2023 /* perform PHY state sanity checks? */
2024 bool chv_phy_assert[2];
2026 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2029 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2030 * will be rejected. Instead look for a better place.
2034 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2036 return dev->dev_private;
2039 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2041 return to_i915(dev_get_drvdata(dev));
2044 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2046 return container_of(guc, struct drm_i915_private, guc);
2049 /* Simple iterator over all initialised engines */
2050 #define for_each_engine(engine__, dev_priv__) \
2051 for ((engine__) = &(dev_priv__)->engine[0]; \
2052 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2054 for_each_if (intel_engine_initialized(engine__))
2056 /* Iterator with engine_id */
2057 #define for_each_engine_id(engine__, dev_priv__, id__) \
2058 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2059 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2061 for_each_if (((id__) = (engine__)->id, \
2062 intel_engine_initialized(engine__)))
2064 /* Iterator over subset of engines selected by mask */
2065 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2066 for ((engine__) = &(dev_priv__)->engine[0]; \
2067 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2069 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2070 intel_engine_initialized(engine__))
2072 enum hdmi_force_audio {
2073 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2074 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2075 HDMI_AUDIO_AUTO, /* trust EDID */
2076 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2079 #define I915_GTT_OFFSET_NONE ((u32)-1)
2081 struct drm_i915_gem_object_ops {
2083 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2085 /* Interface between the GEM object and its backing storage.
2086 * get_pages() is called once prior to the use of the associated set
2087 * of pages before to binding them into the GTT, and put_pages() is
2088 * called after we no longer need them. As we expect there to be
2089 * associated cost with migrating pages between the backing storage
2090 * and making them available for the GPU (e.g. clflush), we may hold
2091 * onto the pages after they are no longer referenced by the GPU
2092 * in case they may be used again shortly (for example migrating the
2093 * pages to a different memory domain within the GTT). put_pages()
2094 * will therefore most likely be called when the object itself is
2095 * being released or under memory pressure (where we attempt to
2096 * reap pages for the shrinker).
2098 int (*get_pages)(struct drm_i915_gem_object *);
2099 void (*put_pages)(struct drm_i915_gem_object *);
2101 int (*dmabuf_export)(struct drm_i915_gem_object *);
2102 void (*release)(struct drm_i915_gem_object *);
2106 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2107 * considered to be the frontbuffer for the given plane interface-wise. This
2108 * doesn't mean that the hw necessarily already scans it out, but that any
2109 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2111 * We have one bit per pipe and per scanout plane type.
2113 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2114 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2115 #define INTEL_FRONTBUFFER_BITS \
2116 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2117 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2118 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2119 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2120 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2121 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2122 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2123 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2124 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2125 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2126 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2128 struct drm_i915_gem_object {
2129 struct drm_gem_object base;
2131 const struct drm_i915_gem_object_ops *ops;
2133 /** List of VMAs backed by this object */
2134 struct list_head vma_list;
2136 /** Stolen memory for this object, instead of being backed by shmem. */
2137 struct drm_mm_node *stolen;
2138 struct list_head global_list;
2140 struct list_head engine_list[I915_NUM_ENGINES];
2141 /** Used in execbuf to temporarily hold a ref */
2142 struct list_head obj_exec_link;
2144 struct list_head batch_pool_link;
2147 * This is set if the object is on the active lists (has pending
2148 * rendering and so a non-zero seqno), and is not set if it i s on
2149 * inactive (ready to be unbound) list.
2151 unsigned int active:I915_NUM_ENGINES;
2154 * This is set if the object has been written to since last bound
2157 unsigned int dirty:1;
2160 * Fence register bits (if any) for this object. Will be set
2161 * as needed when mapped into the GTT.
2162 * Protected by dev->struct_mutex.
2164 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2167 * Advice: are the backing pages purgeable?
2169 unsigned int madv:2;
2172 * Current tiling mode for the object.
2174 unsigned int tiling_mode:2;
2176 * Whether the tiling parameters for the currently associated fence
2177 * register have changed. Note that for the purposes of tracking
2178 * tiling changes we also treat the unfenced register, the register
2179 * slot that the object occupies whilst it executes a fenced
2180 * command (such as BLT on gen2/3), as a "fence".
2182 unsigned int fence_dirty:1;
2185 * Is the object at the current location in the gtt mappable and
2186 * fenceable? Used to avoid costly recalculations.
2188 unsigned int map_and_fenceable:1;
2191 * Whether the current gtt mapping needs to be mappable (and isn't just
2192 * mappable by accident). Track pin and fault separate for a more
2193 * accurate mappable working set.
2195 unsigned int fault_mappable:1;
2198 * Is the object to be mapped as read-only to the GPU
2199 * Only honoured if hardware has relevant pte bit
2201 unsigned long gt_ro:1;
2202 unsigned int cache_level:3;
2203 unsigned int cache_dirty:1;
2205 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2207 unsigned int pin_display;
2209 struct sg_table *pages;
2210 int pages_pin_count;
2212 struct scatterlist *sg;
2217 /** Breadcrumb of last rendering to the buffer.
2218 * There can only be one writer, but we allow for multiple readers.
2219 * If there is a writer that necessarily implies that all other
2220 * read requests are complete - but we may only be lazily clearing
2221 * the read requests. A read request is naturally the most recent
2222 * request on a ring, so we may have two different write and read
2223 * requests on one ring where the write request is older than the
2224 * read request. This allows for the CPU to read from an active
2225 * buffer by only waiting for the write to complete.
2227 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2228 struct drm_i915_gem_request *last_write_req;
2229 /** Breadcrumb of last fenced GPU access to the buffer. */
2230 struct drm_i915_gem_request *last_fenced_req;
2232 /** Current tiling stride for the object, if it's tiled. */
2235 /** References from framebuffers, locks out tiling changes. */
2236 unsigned long framebuffer_references;
2238 /** Record of address bit 17 of each page at last unbind. */
2239 unsigned long *bit_17;
2242 /** for phy allocated objects */
2243 struct drm_dma_handle *phys_handle;
2245 struct i915_gem_userptr {
2247 unsigned read_only :1;
2248 unsigned workers :4;
2249 #define I915_GEM_USERPTR_MAX_WORKERS 15
2251 struct i915_mm_struct *mm;
2252 struct i915_mmu_object *mmu_object;
2253 struct work_struct *work;
2257 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2260 * Optimised SGL iterator for GEM objects
2262 static __always_inline struct sgt_iter {
2263 struct scatterlist *sgp;
2270 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2271 struct sgt_iter s = { .sgp = sgl };
2274 s.max = s.curr = s.sgp->offset;
2275 s.max += s.sgp->length;
2277 s.dma = sg_dma_address(s.sgp);
2279 s.pfn = page_to_pfn(sg_page(s.sgp));
2286 * __sg_next - return the next scatterlist entry in a list
2287 * @sg: The current sg entry
2290 * If the entry is the last, return NULL; otherwise, step to the next
2291 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2292 * otherwise just return the pointer to the current element.
2294 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2296 #ifdef CONFIG_DEBUG_SG
2297 BUG_ON(sg->sg_magic != SG_MAGIC);
2299 return sg_is_last(sg) ? NULL :
2300 likely(!sg_is_chain(++sg)) ? sg :
2305 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2306 * @__dmap: DMA address (output)
2307 * @__iter: 'struct sgt_iter' (iterator state, internal)
2308 * @__sgt: sg_table to iterate over (input)
2310 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2311 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2312 ((__dmap) = (__iter).dma + (__iter).curr); \
2313 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2314 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2317 * for_each_sgt_page - iterate over the pages of the given sg_table
2318 * @__pp: page pointer (output)
2319 * @__iter: 'struct sgt_iter' (iterator state, internal)
2320 * @__sgt: sg_table to iterate over (input)
2322 #define for_each_sgt_page(__pp, __iter, __sgt) \
2323 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2324 ((__pp) = (__iter).pfn == 0 ? NULL : \
2325 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2326 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2327 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2330 * Request queue structure.
2332 * The request queue allows us to note sequence numbers that have been emitted
2333 * and may be associated with active buffers to be retired.
2335 * By keeping this list, we can avoid having to do questionable sequence
2336 * number comparisons on buffer last_read|write_seqno. It also allows an
2337 * emission time to be associated with the request for tracking how far ahead
2338 * of the GPU the submission is.
2340 * The requests are reference counted, so upon creation they should have an
2341 * initial reference taken using kref_init
2343 struct drm_i915_gem_request {
2346 /** On Which ring this request was generated */
2347 struct drm_i915_private *i915;
2348 struct intel_engine_cs *engine;
2349 unsigned reset_counter;
2351 /** GEM sequence number associated with the previous request,
2352 * when the HWS breadcrumb is equal to this the GPU is processing
2357 /** GEM sequence number associated with this request,
2358 * when the HWS breadcrumb is equal or greater than this the GPU
2359 * has finished processing this request.
2363 /** Position in the ringbuffer of the start of the request */
2367 * Position in the ringbuffer of the start of the postfix.
2368 * This is required to calculate the maximum available ringbuffer
2369 * space without overwriting the postfix.
2373 /** Position in the ringbuffer of the end of the whole request */
2376 /** Preallocate space in the ringbuffer for the emitting the request */
2380 * Context and ring buffer related to this request
2381 * Contexts are refcounted, so when this request is associated with a
2382 * context, we must increment the context's refcount, to guarantee that
2383 * it persists while any request is linked to it. Requests themselves
2384 * are also refcounted, so the request will only be freed when the last
2385 * reference to it is dismissed, and the code in
2386 * i915_gem_request_free() will then decrement the refcount on the
2389 struct i915_gem_context *ctx;
2390 struct intel_ringbuffer *ringbuf;
2393 * Context related to the previous request.
2394 * As the contexts are accessed by the hardware until the switch is
2395 * completed to a new context, the hardware may still be writing
2396 * to the context object after the breadcrumb is visible. We must
2397 * not unpin/unbind/prune that object whilst still active and so
2398 * we keep the previous context pinned until the following (this)
2399 * request is retired.
2401 struct i915_gem_context *previous_context;
2403 /** Batch buffer related to this request if any (used for
2404 error state dump only) */
2405 struct drm_i915_gem_object *batch_obj;
2407 /** Time at which this request was emitted, in jiffies. */
2408 unsigned long emitted_jiffies;
2410 /** global list entry for this request */
2411 struct list_head list;
2413 struct drm_i915_file_private *file_priv;
2414 /** file_priv list entry for this request */
2415 struct list_head client_list;
2417 /** process identifier submitting this request */
2421 * The ELSP only accepts two elements at a time, so we queue
2422 * context/tail pairs on a given queue (ring->execlist_queue) until the
2423 * hardware is available. The queue serves a double purpose: we also use
2424 * it to keep track of the up to 2 contexts currently in the hardware
2425 * (usually one in execution and the other queued up by the GPU): We
2426 * only remove elements from the head of the queue when the hardware
2427 * informs us that an element has been completed.
2429 * All accesses to the queue are mediated by a spinlock
2430 * (ring->execlist_lock).
2433 /** Execlist link in the submission queue.*/
2434 struct list_head execlist_link;
2436 /** Execlists no. of times this request has been sent to the ELSP */
2439 /** Execlists context hardware id. */
2443 struct drm_i915_gem_request * __must_check
2444 i915_gem_request_alloc(struct intel_engine_cs *engine,
2445 struct i915_gem_context *ctx);
2446 void i915_gem_request_free(struct kref *req_ref);
2447 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2448 struct drm_file *file);
2450 static inline uint32_t
2451 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2453 return req ? req->seqno : 0;
2456 static inline struct intel_engine_cs *
2457 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2459 return req ? req->engine : NULL;
2462 static inline struct drm_i915_gem_request *
2463 i915_gem_request_reference(struct drm_i915_gem_request *req)
2466 kref_get(&req->ref);
2471 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2473 kref_put(&req->ref, i915_gem_request_free);
2476 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2477 struct drm_i915_gem_request *src)
2480 i915_gem_request_reference(src);
2483 i915_gem_request_unreference(*pdst);
2489 * XXX: i915_gem_request_completed should be here but currently needs the
2490 * definition of i915_seqno_passed() which is below. It will be moved in
2491 * a later patch when the call to i915_seqno_passed() is obsoleted...
2495 * A command that requires special handling by the command parser.
2497 struct drm_i915_cmd_descriptor {
2499 * Flags describing how the command parser processes the command.
2501 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2502 * a length mask if not set
2503 * CMD_DESC_SKIP: The command is allowed but does not follow the
2504 * standard length encoding for the opcode range in
2506 * CMD_DESC_REJECT: The command is never allowed
2507 * CMD_DESC_REGISTER: The command should be checked against the
2508 * register whitelist for the appropriate ring
2509 * CMD_DESC_MASTER: The command is allowed if the submitting process
2513 #define CMD_DESC_FIXED (1<<0)
2514 #define CMD_DESC_SKIP (1<<1)
2515 #define CMD_DESC_REJECT (1<<2)
2516 #define CMD_DESC_REGISTER (1<<3)
2517 #define CMD_DESC_BITMASK (1<<4)
2518 #define CMD_DESC_MASTER (1<<5)
2521 * The command's unique identification bits and the bitmask to get them.
2522 * This isn't strictly the opcode field as defined in the spec and may
2523 * also include type, subtype, and/or subop fields.
2531 * The command's length. The command is either fixed length (i.e. does
2532 * not include a length field) or has a length field mask. The flag
2533 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2534 * a length mask. All command entries in a command table must include
2535 * length information.
2543 * Describes where to find a register address in the command to check
2544 * against the ring's register whitelist. Only valid if flags has the
2545 * CMD_DESC_REGISTER bit set.
2547 * A non-zero step value implies that the command may access multiple
2548 * registers in sequence (e.g. LRI), in that case step gives the
2549 * distance in dwords between individual offset fields.
2557 #define MAX_CMD_DESC_BITMASKS 3
2559 * Describes command checks where a particular dword is masked and
2560 * compared against an expected value. If the command does not match
2561 * the expected value, the parser rejects it. Only valid if flags has
2562 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2565 * If the check specifies a non-zero condition_mask then the parser
2566 * only performs the check when the bits specified by condition_mask
2573 u32 condition_offset;
2575 } bits[MAX_CMD_DESC_BITMASKS];
2579 * A table of commands requiring special handling by the command parser.
2581 * Each ring has an array of tables. Each table consists of an array of command
2582 * descriptors, which must be sorted with command opcodes in ascending order.
2584 struct drm_i915_cmd_table {
2585 const struct drm_i915_cmd_descriptor *table;
2589 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2590 #define __I915__(p) ({ \
2591 struct drm_i915_private *__p; \
2592 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2593 __p = (struct drm_i915_private *)p; \
2594 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2595 __p = to_i915((struct drm_device *)p); \
2600 #define INTEL_INFO(p) (&__I915__(p)->info)
2601 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2602 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2604 #define REVID_FOREVER 0xff
2605 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2607 #define GEN_FOREVER (0)
2609 * Returns true if Gen is in inclusive range [Start, End].
2611 * Use GEN_FOREVER for unbound start and or end.
2613 #define IS_GEN(p, s, e) ({ \
2614 unsigned int __s = (s), __e = (e); \
2615 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2616 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2617 if ((__s) != GEN_FOREVER) \
2619 if ((__e) == GEN_FOREVER) \
2620 __e = BITS_PER_LONG - 1; \
2623 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2627 * Return true if revision is in range [since,until] inclusive.
2629 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2631 #define IS_REVID(p, since, until) \
2632 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2634 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2635 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2636 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2637 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2638 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2639 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2640 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2641 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2642 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2643 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2644 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2645 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2646 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2647 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2648 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2649 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2650 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2651 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2652 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2653 INTEL_DEVID(dev) == 0x0152 || \
2654 INTEL_DEVID(dev) == 0x015a)
2655 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2656 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2657 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2658 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2659 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2660 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2661 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2662 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2663 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2664 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2665 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2666 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2667 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2668 (INTEL_DEVID(dev) & 0xf) == 0xe))
2669 /* ULX machines are also considered ULT. */
2670 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2671 (INTEL_DEVID(dev) & 0xf) == 0xe)
2672 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2673 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2674 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2675 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2676 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2677 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2678 /* ULX machines are also considered ULT. */
2679 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2680 INTEL_DEVID(dev) == 0x0A1E)
2681 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2682 INTEL_DEVID(dev) == 0x1913 || \
2683 INTEL_DEVID(dev) == 0x1916 || \
2684 INTEL_DEVID(dev) == 0x1921 || \
2685 INTEL_DEVID(dev) == 0x1926)
2686 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2687 INTEL_DEVID(dev) == 0x1915 || \
2688 INTEL_DEVID(dev) == 0x191E)
2689 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2690 INTEL_DEVID(dev) == 0x5913 || \
2691 INTEL_DEVID(dev) == 0x5916 || \
2692 INTEL_DEVID(dev) == 0x5921 || \
2693 INTEL_DEVID(dev) == 0x5926)
2694 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2695 INTEL_DEVID(dev) == 0x5915 || \
2696 INTEL_DEVID(dev) == 0x591E)
2697 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2698 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2699 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2700 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2702 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2704 #define SKL_REVID_A0 0x0
2705 #define SKL_REVID_B0 0x1
2706 #define SKL_REVID_C0 0x2
2707 #define SKL_REVID_D0 0x3
2708 #define SKL_REVID_E0 0x4
2709 #define SKL_REVID_F0 0x5
2711 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2713 #define BXT_REVID_A0 0x0
2714 #define BXT_REVID_A1 0x1
2715 #define BXT_REVID_B0 0x3
2716 #define BXT_REVID_C0 0x9
2718 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2721 * The genX designation typically refers to the render engine, so render
2722 * capability related checks should use IS_GEN, while display and other checks
2723 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2726 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen_mask & BIT(1))
2727 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen_mask & BIT(2))
2728 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen_mask & BIT(3))
2729 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen_mask & BIT(4))
2730 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen_mask & BIT(5))
2731 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen_mask & BIT(6))
2732 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
2733 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
2735 #define RENDER_RING (1<<RCS)
2736 #define BSD_RING (1<<VCS)
2737 #define BLT_RING (1<<BCS)
2738 #define VEBOX_RING (1<<VECS)
2739 #define BSD2_RING (1<<VCS2)
2740 #define ALL_ENGINES (~0)
2742 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2743 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2744 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2745 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2746 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2747 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2748 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2749 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2751 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2753 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2754 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2755 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2756 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2757 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2759 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2760 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2762 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2763 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2765 /* WaRsDisableCoarsePowerGating:skl,bxt */
2766 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2767 IS_SKL_GT3(dev) || \
2771 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2772 * even when in MSI mode. This results in spurious interrupt warnings if the
2773 * legacy irq no. is shared with another device. The kernel then disables that
2774 * interrupt source and so prevents the other device from working properly.
2776 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2777 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2779 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2780 * rows, which changed the alignment requirements and fence programming.
2782 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2784 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2785 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2787 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2788 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2789 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2791 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2793 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2794 INTEL_INFO(dev)->gen >= 9)
2796 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2797 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2798 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2799 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2800 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2801 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2802 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2803 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2804 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2805 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2806 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2808 #define HAS_CSR(dev) (IS_GEN9(dev))
2811 * For now, anything with a GuC requires uCode loading, and then supports
2812 * command submission once loaded. But these are logically independent
2813 * properties, so we have separate macros to test them.
2815 #define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2816 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2817 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2819 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2820 INTEL_INFO(dev)->gen >= 8)
2822 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2823 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2826 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2827 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2828 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2829 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2830 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2831 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2832 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2833 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2834 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2835 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2836 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2838 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2839 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2840 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2841 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2842 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2843 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2844 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2845 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2846 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2848 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2849 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2851 /* DPF == dynamic parity feature */
2852 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2853 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2855 #define GT_FREQUENCY_MULTIPLIER 50
2856 #define GEN9_FREQ_SCALER 3
2858 #include "i915_trace.h"
2860 extern const struct drm_ioctl_desc i915_ioctls[];
2861 extern int i915_max_ioctl;
2863 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2864 extern int i915_resume_switcheroo(struct drm_device *dev);
2866 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2871 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2872 const char *fmt, ...);
2874 #define i915_report_error(dev_priv, fmt, ...) \
2875 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2877 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2878 extern int i915_driver_unload(struct drm_device *);
2879 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2880 extern void i915_driver_lastclose(struct drm_device * dev);
2881 extern void i915_driver_preclose(struct drm_device *dev,
2882 struct drm_file *file);
2883 extern void i915_driver_postclose(struct drm_device *dev,
2884 struct drm_file *file);
2885 #ifdef CONFIG_COMPAT
2886 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2889 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2890 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2891 extern int i915_reset(struct drm_i915_private *dev_priv);
2892 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2893 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2894 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2895 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2896 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2897 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2898 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2900 /* intel_hotplug.c */
2901 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2902 u32 pin_mask, u32 long_mask);
2903 void intel_hpd_init(struct drm_i915_private *dev_priv);
2904 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2905 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2906 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2909 void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
2911 void i915_handle_error(struct drm_i915_private *dev_priv,
2913 const char *fmt, ...);
2915 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2916 int intel_irq_install(struct drm_i915_private *dev_priv);
2917 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2919 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2920 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2921 bool restore_forcewake);
2922 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2923 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2924 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2925 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2926 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2928 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2929 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2930 enum forcewake_domains domains);
2931 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2932 enum forcewake_domains domains);
2933 /* Like above but the caller must manage the uncore.lock itself.
2934 * Must be used with I915_READ_FW and friends.
2936 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2937 enum forcewake_domains domains);
2938 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2939 enum forcewake_domains domains);
2940 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2942 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2943 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2945 return dev_priv->vgpu.active;
2949 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2953 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2956 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2957 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2958 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2961 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2962 uint32_t interrupt_mask,
2963 uint32_t enabled_irq_mask);
2965 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2967 ilk_update_display_irq(dev_priv, bits, bits);
2970 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2972 ilk_update_display_irq(dev_priv, bits, 0);
2974 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2976 uint32_t interrupt_mask,
2977 uint32_t enabled_irq_mask);
2978 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2979 enum pipe pipe, uint32_t bits)
2981 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2983 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2984 enum pipe pipe, uint32_t bits)
2986 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2988 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2989 uint32_t interrupt_mask,
2990 uint32_t enabled_irq_mask);
2992 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2994 ibx_display_interrupt_update(dev_priv, bits, bits);
2997 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2999 ibx_display_interrupt_update(dev_priv, bits, 0);
3004 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3005 struct drm_file *file_priv);
3006 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3007 struct drm_file *file_priv);
3008 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3009 struct drm_file *file_priv);
3010 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3011 struct drm_file *file_priv);
3012 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3013 struct drm_file *file_priv);
3014 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3015 struct drm_file *file_priv);
3016 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3017 struct drm_file *file_priv);
3018 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
3019 struct drm_i915_gem_request *req);
3020 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
3021 struct drm_i915_gem_execbuffer2 *args,
3022 struct list_head *vmas);
3023 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3024 struct drm_file *file_priv);
3025 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3026 struct drm_file *file_priv);
3027 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3028 struct drm_file *file_priv);
3029 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3030 struct drm_file *file);
3031 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3032 struct drm_file *file);
3033 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3034 struct drm_file *file_priv);
3035 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3036 struct drm_file *file_priv);
3037 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3038 struct drm_file *file_priv);
3039 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3040 struct drm_file *file_priv);
3041 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3042 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3043 struct drm_file *file);
3044 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3045 struct drm_file *file_priv);
3046 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3047 struct drm_file *file_priv);
3048 void i915_gem_load_init(struct drm_device *dev);
3049 void i915_gem_load_cleanup(struct drm_device *dev);
3050 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3051 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3053 void *i915_gem_object_alloc(struct drm_device *dev);
3054 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3055 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3056 const struct drm_i915_gem_object_ops *ops);
3057 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3059 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3060 struct drm_device *dev, const void *data, size_t size);
3061 void i915_gem_free_object(struct drm_gem_object *obj);
3062 void i915_gem_vma_destroy(struct i915_vma *vma);
3064 /* Flags used by pin/bind&friends. */
3065 #define PIN_MAPPABLE (1<<0)
3066 #define PIN_NONBLOCK (1<<1)
3067 #define PIN_GLOBAL (1<<2)
3068 #define PIN_OFFSET_BIAS (1<<3)
3069 #define PIN_USER (1<<4)
3070 #define PIN_UPDATE (1<<5)
3071 #define PIN_ZONE_4G (1<<6)
3072 #define PIN_HIGH (1<<7)
3073 #define PIN_OFFSET_FIXED (1<<8)
3074 #define PIN_OFFSET_MASK (~4095)
3076 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3077 struct i915_address_space *vm,
3081 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3082 const struct i915_ggtt_view *view,
3086 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3088 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3089 int __must_check i915_vma_unbind(struct i915_vma *vma);
3091 * BEWARE: Do not use the function below unless you can _absolutely_
3092 * _guarantee_ VMA in question is _not in use_ anywhere.
3094 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3095 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3096 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3097 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3099 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3100 int *needs_clflush);
3102 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3104 static inline int __sg_page_count(struct scatterlist *sg)
3106 return sg->length >> PAGE_SHIFT;
3110 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3112 static inline struct page *
3113 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3115 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3118 if (n < obj->get_page.last) {
3119 obj->get_page.sg = obj->pages->sgl;
3120 obj->get_page.last = 0;
3123 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3124 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3125 if (unlikely(sg_is_chain(obj->get_page.sg)))
3126 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3129 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3132 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3134 BUG_ON(obj->pages == NULL);
3135 obj->pages_pin_count++;
3138 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3140 BUG_ON(obj->pages_pin_count == 0);
3141 obj->pages_pin_count--;
3145 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3146 * @obj - the object to map into kernel address space
3148 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3149 * pages and then returns a contiguous mapping of the backing storage into
3150 * the kernel address space.
3152 * The caller must hold the struct_mutex, and is responsible for calling
3153 * i915_gem_object_unpin_map() when the mapping is no longer required.
3155 * Returns the pointer through which to access the mapped object, or an
3156 * ERR_PTR() on error.
3158 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3161 * i915_gem_object_unpin_map - releases an earlier mapping
3162 * @obj - the object to unmap
3164 * After pinning the object and mapping its pages, once you are finished
3165 * with your access, call i915_gem_object_unpin_map() to release the pin
3166 * upon the mapping. Once the pin count reaches zero, that mapping may be
3169 * The caller must hold the struct_mutex.
3171 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3173 lockdep_assert_held(&obj->base.dev->struct_mutex);
3174 i915_gem_object_unpin_pages(obj);
3177 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3178 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3179 struct intel_engine_cs *to,
3180 struct drm_i915_gem_request **to_req);
3181 void i915_vma_move_to_active(struct i915_vma *vma,
3182 struct drm_i915_gem_request *req);
3183 int i915_gem_dumb_create(struct drm_file *file_priv,
3184 struct drm_device *dev,
3185 struct drm_mode_create_dumb *args);
3186 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3187 uint32_t handle, uint64_t *offset);
3189 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3190 struct drm_i915_gem_object *new,
3191 unsigned frontbuffer_bits);
3194 * Returns true if seq1 is later than seq2.
3197 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3199 return (int32_t)(seq1 - seq2) >= 0;
3202 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3203 bool lazy_coherency)
3205 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3206 req->engine->irq_seqno_barrier(req->engine);
3207 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3208 req->previous_seqno);
3211 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3212 bool lazy_coherency)
3214 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3215 req->engine->irq_seqno_barrier(req->engine);
3216 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3220 int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
3221 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3223 struct drm_i915_gem_request *
3224 i915_gem_find_active_request(struct intel_engine_cs *engine);
3226 bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3227 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3229 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3231 return atomic_read(&error->reset_counter);
3234 static inline bool __i915_reset_in_progress(u32 reset)
3236 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3239 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3241 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3244 static inline bool __i915_terminally_wedged(u32 reset)
3246 return unlikely(reset & I915_WEDGED);
3249 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3251 return __i915_reset_in_progress(i915_reset_counter(error));
3254 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3256 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3259 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3261 return __i915_terminally_wedged(i915_reset_counter(error));
3264 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3266 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3269 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3271 return dev_priv->gpu_error.stop_rings == 0 ||
3272 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3275 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3277 return dev_priv->gpu_error.stop_rings == 0 ||
3278 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3281 void i915_gem_reset(struct drm_device *dev);
3282 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3283 int __must_check i915_gem_init(struct drm_device *dev);
3284 int i915_gem_init_engines(struct drm_device *dev);
3285 int __must_check i915_gem_init_hw(struct drm_device *dev);
3286 void i915_gem_init_swizzling(struct drm_device *dev);
3287 void i915_gem_cleanup_engines(struct drm_device *dev);
3288 int __must_check i915_gpu_idle(struct drm_device *dev);
3289 int __must_check i915_gem_suspend(struct drm_device *dev);
3290 void __i915_add_request(struct drm_i915_gem_request *req,
3291 struct drm_i915_gem_object *batch_obj,
3293 #define i915_add_request(req) \
3294 __i915_add_request(req, NULL, true)
3295 #define i915_add_request_no_flush(req) \
3296 __i915_add_request(req, NULL, false)
3297 int __i915_wait_request(struct drm_i915_gem_request *req,
3300 struct intel_rps_client *rps);
3301 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3302 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3304 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3307 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3310 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3312 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3314 const struct i915_ggtt_view *view);
3315 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3316 const struct i915_ggtt_view *view);
3317 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3319 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3320 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3323 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3325 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3326 int tiling_mode, bool fenced);
3328 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3329 enum i915_cache_level cache_level);
3331 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3332 struct dma_buf *dma_buf);
3334 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3335 struct drm_gem_object *gem_obj, int flags);
3337 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3338 const struct i915_ggtt_view *view);
3339 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3340 struct i915_address_space *vm);
3342 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3344 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3347 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3348 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3349 const struct i915_ggtt_view *view);
3350 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3351 struct i915_address_space *vm);
3354 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3355 struct i915_address_space *vm);
3357 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3358 const struct i915_ggtt_view *view);
3361 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3362 struct i915_address_space *vm);
3364 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3365 const struct i915_ggtt_view *view);
3367 static inline struct i915_vma *
3368 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3370 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3372 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3374 /* Some GGTT VM helpers */
3375 static inline struct i915_hw_ppgtt *
3376 i915_vm_to_ppgtt(struct i915_address_space *vm)
3378 return container_of(vm, struct i915_hw_ppgtt, base);
3382 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3384 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3388 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
3390 static inline int __must_check
3391 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3395 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3396 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3398 return i915_gem_object_pin(obj, &ggtt->base,
3399 alignment, flags | PIN_GLOBAL);
3402 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3403 const struct i915_ggtt_view *view);
3405 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3407 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3410 /* i915_gem_fence.c */
3411 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3412 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3414 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3415 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3417 void i915_gem_restore_fences(struct drm_device *dev);
3419 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3420 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3421 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3423 /* i915_gem_context.c */
3424 int __must_check i915_gem_context_init(struct drm_device *dev);
3425 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3426 void i915_gem_context_fini(struct drm_device *dev);
3427 void i915_gem_context_reset(struct drm_device *dev);
3428 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3429 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3430 int i915_switch_context(struct drm_i915_gem_request *req);
3431 void i915_gem_context_free(struct kref *ctx_ref);
3432 struct drm_i915_gem_object *
3433 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3435 static inline struct i915_gem_context *
3436 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3438 struct i915_gem_context *ctx;
3440 lockdep_assert_held(&file_priv->dev_priv->dev->struct_mutex);
3442 ctx = idr_find(&file_priv->context_idr, id);
3444 return ERR_PTR(-ENOENT);
3449 static inline void i915_gem_context_reference(struct i915_gem_context *ctx)
3451 kref_get(&ctx->ref);
3454 static inline void i915_gem_context_unreference(struct i915_gem_context *ctx)
3456 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
3457 kref_put(&ctx->ref, i915_gem_context_free);
3460 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3462 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3465 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3466 struct drm_file *file);
3467 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3468 struct drm_file *file);
3469 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3470 struct drm_file *file_priv);
3471 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3472 struct drm_file *file_priv);
3473 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3474 struct drm_file *file);
3476 /* i915_gem_evict.c */
3477 int __must_check i915_gem_evict_something(struct drm_device *dev,
3478 struct i915_address_space *vm,
3481 unsigned cache_level,
3482 unsigned long start,
3485 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3486 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3488 /* belongs in i915_gem_gtt.h */
3489 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3491 if (INTEL_GEN(dev_priv) < 6)
3492 intel_gtt_chipset_flush();
3495 /* i915_gem_stolen.c */
3496 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3497 struct drm_mm_node *node, u64 size,
3498 unsigned alignment);
3499 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3500 struct drm_mm_node *node, u64 size,
3501 unsigned alignment, u64 start,
3503 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3504 struct drm_mm_node *node);
3505 int i915_gem_init_stolen(struct drm_device *dev);
3506 void i915_gem_cleanup_stolen(struct drm_device *dev);
3507 struct drm_i915_gem_object *
3508 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3509 struct drm_i915_gem_object *
3510 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3515 /* i915_gem_shrinker.c */
3516 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3517 unsigned long target,
3519 #define I915_SHRINK_PURGEABLE 0x1
3520 #define I915_SHRINK_UNBOUND 0x2
3521 #define I915_SHRINK_BOUND 0x4
3522 #define I915_SHRINK_ACTIVE 0x8
3523 #define I915_SHRINK_VMAPS 0x10
3524 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3525 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3526 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3529 /* i915_gem_tiling.c */
3530 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3532 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3534 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3535 obj->tiling_mode != I915_TILING_NONE;
3538 /* i915_gem_debug.c */
3540 int i915_verify_lists(struct drm_device *dev);
3542 #define i915_verify_lists(dev) 0
3545 /* i915_debugfs.c */
3546 int i915_debugfs_init(struct drm_minor *minor);
3547 void i915_debugfs_cleanup(struct drm_minor *minor);
3548 #ifdef CONFIG_DEBUG_FS
3549 int i915_debugfs_connector_add(struct drm_connector *connector);
3550 void intel_display_crc_init(struct drm_device *dev);
3552 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3554 static inline void intel_display_crc_init(struct drm_device *dev) {}
3557 /* i915_gpu_error.c */
3559 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3560 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3561 const struct i915_error_state_file_priv *error);
3562 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3563 struct drm_i915_private *i915,
3564 size_t count, loff_t pos);
3565 static inline void i915_error_state_buf_release(
3566 struct drm_i915_error_state_buf *eb)
3570 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3572 const char *error_msg);
3573 void i915_error_state_get(struct drm_device *dev,
3574 struct i915_error_state_file_priv *error_priv);
3575 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3576 void i915_destroy_error_state(struct drm_device *dev);
3578 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3579 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3581 /* i915_cmd_parser.c */
3582 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3583 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3584 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3585 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3586 int i915_parse_cmds(struct intel_engine_cs *engine,
3587 struct drm_i915_gem_object *batch_obj,
3588 struct drm_i915_gem_object *shadow_batch_obj,
3589 u32 batch_start_offset,
3593 /* i915_suspend.c */
3594 extern int i915_save_state(struct drm_device *dev);
3595 extern int i915_restore_state(struct drm_device *dev);
3598 void i915_setup_sysfs(struct drm_device *dev_priv);
3599 void i915_teardown_sysfs(struct drm_device *dev_priv);
3602 extern int intel_setup_gmbus(struct drm_device *dev);
3603 extern void intel_teardown_gmbus(struct drm_device *dev);
3604 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3607 extern struct i2c_adapter *
3608 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3609 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3610 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3611 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3613 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3615 extern void intel_i2c_reset(struct drm_device *dev);
3618 int intel_bios_init(struct drm_i915_private *dev_priv);
3619 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3620 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3621 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3622 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3623 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3624 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3625 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3628 /* intel_opregion.c */
3630 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3631 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3632 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3633 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3634 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3636 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3638 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3640 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3641 static inline void intel_opregion_init(struct drm_i915_private *dev) { }
3642 static inline void intel_opregion_fini(struct drm_i915_private *dev) { }
3643 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3647 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3652 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3656 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3664 extern void intel_register_dsm_handler(void);
3665 extern void intel_unregister_dsm_handler(void);
3667 static inline void intel_register_dsm_handler(void) { return; }
3668 static inline void intel_unregister_dsm_handler(void) { return; }
3669 #endif /* CONFIG_ACPI */
3672 extern void intel_modeset_init_hw(struct drm_device *dev);
3673 extern void intel_modeset_init(struct drm_device *dev);
3674 extern void intel_modeset_gem_init(struct drm_device *dev);
3675 extern void intel_modeset_cleanup(struct drm_device *dev);
3676 extern void intel_connector_unregister(struct intel_connector *);
3677 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3678 extern void intel_display_resume(struct drm_device *dev);
3679 extern void i915_redisable_vga(struct drm_device *dev);
3680 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3681 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3682 extern void intel_init_pch_refclk(struct drm_device *dev);
3683 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3684 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3686 extern void intel_detect_pch(struct drm_device *dev);
3688 extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
3689 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3690 struct drm_file *file);
3693 extern struct intel_overlay_error_state *
3694 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3695 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3696 struct intel_overlay_error_state *error);
3698 extern struct intel_display_error_state *
3699 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3700 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3701 struct drm_device *dev,
3702 struct intel_display_error_state *error);
3704 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3705 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3707 /* intel_sideband.c */
3708 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3709 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3710 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3711 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3712 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3713 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3714 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3715 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3716 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3717 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3718 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3719 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3720 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3721 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3722 enum intel_sbi_destination destination);
3723 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3724 enum intel_sbi_destination destination);
3725 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3726 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3728 /* intel_dpio_phy.c */
3729 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3730 u32 deemph_reg_value, u32 margin_reg_value,
3731 bool uniq_trans_scale);
3732 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3734 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3735 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3736 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3737 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3739 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3740 u32 demph_reg_value, u32 preemph_reg_value,
3741 u32 uniqtranscale_reg_value, u32 tx3_demph);
3742 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3743 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3744 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3746 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3747 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3749 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3750 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3752 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3753 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3754 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3755 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3757 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3758 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3759 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3760 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3762 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3763 * will be implemented using 2 32-bit writes in an arbitrary order with
3764 * an arbitrary delay between them. This can cause the hardware to
3765 * act upon the intermediate value, possibly leading to corruption and
3766 * machine death. You have been warned.
3768 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3769 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3771 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3772 u32 upper, lower, old_upper, loop = 0; \
3773 upper = I915_READ(upper_reg); \
3775 old_upper = upper; \
3776 lower = I915_READ(lower_reg); \
3777 upper = I915_READ(upper_reg); \
3778 } while (upper != old_upper && loop++ < 2); \
3779 (u64)upper << 32 | lower; })
3781 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3782 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3784 #define __raw_read(x, s) \
3785 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3788 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3791 #define __raw_write(x, s) \
3792 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3793 i915_reg_t reg, uint##x##_t val) \
3795 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3810 /* These are untraced mmio-accessors that are only valid to be used inside
3811 * criticial sections inside IRQ handlers where forcewake is explicitly
3813 * Think twice, and think again, before using these.
3814 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3815 * intel_uncore_forcewake_irqunlock().
3817 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3818 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3819 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3821 /* "Broadcast RGB" property */
3822 #define INTEL_BROADCAST_RGB_AUTO 0
3823 #define INTEL_BROADCAST_RGB_FULL 1
3824 #define INTEL_BROADCAST_RGB_LIMITED 2
3826 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3828 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3829 return VLV_VGACNTRL;
3830 else if (INTEL_INFO(dev)->gen >= 5)
3831 return CPU_VGACNTRL;
3836 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3838 unsigned long j = msecs_to_jiffies(m);
3840 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3843 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3845 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3848 static inline unsigned long
3849 timespec_to_jiffies_timeout(const struct timespec *value)
3851 unsigned long j = timespec_to_jiffies(value);
3853 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3857 * If you need to wait X milliseconds between events A and B, but event B
3858 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3859 * when event A happened, then just before event B you call this function and
3860 * pass the timestamp as the first argument, and X as the second argument.
3863 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3865 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3868 * Don't re-read the value of "jiffies" every time since it may change
3869 * behind our back and break the math.
3871 tmp_jiffies = jiffies;
3872 target_jiffies = timestamp_jiffies +
3873 msecs_to_jiffies_timeout(to_wait_ms);
3875 if (time_after(target_jiffies, tmp_jiffies)) {
3876 remaining_jiffies = target_jiffies - tmp_jiffies;
3877 while (remaining_jiffies)
3879 schedule_timeout_uninterruptible(remaining_jiffies);
3883 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3884 struct drm_i915_gem_request *req)
3886 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3887 i915_gem_request_assign(&engine->trace_irq_req, req);