1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
38 #include "intel_bios.h"
39 #include "intel_ringbuffer.h"
40 #include "intel_lrc.h"
41 #include "i915_gem_gtt.h"
42 #include "i915_gem_render_state.h"
43 #include <linux/io-mapping.h>
44 #include <linux/i2c.h>
45 #include <linux/i2c-algo-bit.h>
46 #include <drm/intel-gtt.h>
47 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
48 #include <drm/drm_gem.h>
49 #include <linux/backlight.h>
50 #include <linux/hashtable.h>
51 #include <linux/intel-iommu.h>
52 #include <linux/kref.h>
53 #include <linux/pm_qos.h>
54 #include "intel_guc.h"
56 /* General customization:
59 #define DRIVER_NAME "i915"
60 #define DRIVER_DESC "Intel Graphics"
61 #define DRIVER_DATE "20151218"
64 /* Many gcc seem to no see through this and fall over :( */
66 #define WARN_ON(x) ({ \
67 bool __i915_warn_cond = (x); \
68 if (__builtin_constant_p(__i915_warn_cond)) \
69 BUILD_BUG_ON(__i915_warn_cond); \
70 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
72 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
76 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
78 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
79 (long) (x), __func__);
81 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
82 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
83 * which may not necessarily be a user visible problem. This will either
84 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
85 * enable distros and users to tailor their preferred amount of i915 abrt
88 #define I915_STATE_WARN(condition, format...) ({ \
89 int __ret_warn_on = !!(condition); \
90 if (unlikely(__ret_warn_on)) { \
91 if (i915.verbose_state_checks) \
96 unlikely(__ret_warn_on); \
99 #define I915_STATE_WARN_ON(condition) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) { \
102 if (i915.verbose_state_checks) \
103 WARN(1, "WARN_ON(" #condition ")\n"); \
105 DRM_ERROR("WARN_ON(" #condition ")\n"); \
107 unlikely(__ret_warn_on); \
110 static inline const char *yesno(bool v)
112 return v ? "yes" : "no";
121 I915_MAX_PIPES = _PIPE_EDP
123 #define pipe_name(p) ((p) + 'A')
132 #define transcoder_name(t) ((t) + 'A')
135 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
136 * number of planes per CRTC. Not all platforms really have this many planes,
137 * which means some arrays of size I915_MAX_PLANES may have unused entries
138 * between the topmost sprite plane and the cursor plane.
147 #define plane_name(p) ((p) + 'A')
149 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
159 #define port_name(p) ((p) + 'A')
161 #define I915_NUM_PHYS_VLV 2
173 enum intel_display_power_domain {
177 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
178 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
179 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
180 POWER_DOMAIN_TRANSCODER_A,
181 POWER_DOMAIN_TRANSCODER_B,
182 POWER_DOMAIN_TRANSCODER_C,
183 POWER_DOMAIN_TRANSCODER_EDP,
184 POWER_DOMAIN_PORT_DDI_A_LANES,
185 POWER_DOMAIN_PORT_DDI_B_LANES,
186 POWER_DOMAIN_PORT_DDI_C_LANES,
187 POWER_DOMAIN_PORT_DDI_D_LANES,
188 POWER_DOMAIN_PORT_DDI_E_LANES,
189 POWER_DOMAIN_PORT_DSI,
190 POWER_DOMAIN_PORT_CRT,
191 POWER_DOMAIN_PORT_OTHER,
200 POWER_DOMAIN_MODESET,
206 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
207 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
208 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
209 #define POWER_DOMAIN_TRANSCODER(tran) \
210 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
211 (tran) + POWER_DOMAIN_TRANSCODER_A)
215 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
227 #define for_each_hpd_pin(__pin) \
228 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
230 struct i915_hotplug {
231 struct work_struct hotplug_work;
234 unsigned long last_jiffies;
239 HPD_MARK_DISABLED = 2
241 } stats[HPD_NUM_PINS];
243 struct delayed_work reenable_work;
245 struct intel_digital_port *irq_port[I915_MAX_PORTS];
248 struct work_struct dig_port_work;
251 * if we get a HPD irq from DP and a HPD irq from non-DP
252 * the non-DP HPD could block the workqueue on a mode config
253 * mutex getting, that userspace may have taken. However
254 * userspace is waiting on the DP workqueue to run which is
255 * blocked behind the non-DP one.
257 struct workqueue_struct *dp_wq;
260 #define I915_GEM_GPU_DOMAINS \
261 (I915_GEM_DOMAIN_RENDER | \
262 I915_GEM_DOMAIN_SAMPLER | \
263 I915_GEM_DOMAIN_COMMAND | \
264 I915_GEM_DOMAIN_INSTRUCTION | \
265 I915_GEM_DOMAIN_VERTEX)
267 #define for_each_pipe(__dev_priv, __p) \
268 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
269 #define for_each_plane(__dev_priv, __pipe, __p) \
271 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
273 #define for_each_sprite(__dev_priv, __p, __s) \
275 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
278 #define for_each_crtc(dev, crtc) \
279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
281 #define for_each_intel_plane(dev, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &dev->mode_config.plane_list, \
286 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
287 list_for_each_entry(intel_plane, \
288 &(dev)->mode_config.plane_list, \
290 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
292 #define for_each_intel_crtc(dev, intel_crtc) \
293 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
295 #define for_each_intel_encoder(dev, intel_encoder) \
296 list_for_each_entry(intel_encoder, \
297 &(dev)->mode_config.encoder_list, \
300 #define for_each_intel_connector(dev, intel_connector) \
301 list_for_each_entry(intel_connector, \
302 &dev->mode_config.connector_list, \
305 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
306 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
307 for_each_if ((intel_encoder)->base.crtc == (__crtc))
309 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
310 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
311 for_each_if ((intel_connector)->base.encoder == (__encoder))
313 #define for_each_power_domain(domain, mask) \
314 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
315 for_each_if ((1 << (domain)) & (mask))
317 struct drm_i915_private;
318 struct i915_mm_struct;
319 struct i915_mmu_object;
321 struct drm_i915_file_private {
322 struct drm_i915_private *dev_priv;
323 struct drm_file *file;
327 struct list_head request_list;
328 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
329 * chosen to prevent the CPU getting more than a frame ahead of the GPU
330 * (when using lax throttling for the frontbuffer). We also use it to
331 * offer free GPU waitboosts for severely congested workloads.
333 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
335 struct idr context_idr;
337 struct intel_rps_client {
338 struct list_head link;
342 struct intel_engine_cs *bsd_ring;
346 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
347 /* real shared dpll ids must be >= 0 */
348 DPLL_ID_PCH_PLL_A = 0,
349 DPLL_ID_PCH_PLL_B = 1,
356 DPLL_ID_SKL_DPLL1 = 0,
357 DPLL_ID_SKL_DPLL2 = 1,
358 DPLL_ID_SKL_DPLL3 = 2,
360 #define I915_NUM_PLLS 3
362 struct intel_dpll_hw_state {
375 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
376 * lower part of ctrl1 and they get shifted into position when writing
377 * the register. This allows us to easily compare the state to share
381 /* HDMI only, 0 when used for DP */
382 uint32_t cfgcr1, cfgcr2;
385 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
389 struct intel_shared_dpll_config {
390 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
391 struct intel_dpll_hw_state hw_state;
394 struct intel_shared_dpll {
395 struct intel_shared_dpll_config config;
397 int active; /* count of number of active CRTCs (i.e. DPMS on) */
398 bool on; /* is the PLL actually active? Disabled during modeset */
400 /* should match the index in the dev_priv->shared_dplls array */
401 enum intel_dpll_id id;
402 /* The mode_set hook is optional and should be used together with the
403 * intel_prepare_shared_dpll function. */
404 void (*mode_set)(struct drm_i915_private *dev_priv,
405 struct intel_shared_dpll *pll);
406 void (*enable)(struct drm_i915_private *dev_priv,
407 struct intel_shared_dpll *pll);
408 void (*disable)(struct drm_i915_private *dev_priv,
409 struct intel_shared_dpll *pll);
410 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
411 struct intel_shared_dpll *pll,
412 struct intel_dpll_hw_state *hw_state);
420 /* Used by dp and fdi links */
421 struct intel_link_m_n {
429 void intel_link_compute_m_n(int bpp, int nlanes,
430 int pixel_clock, int link_clock,
431 struct intel_link_m_n *m_n);
433 /* Interface history:
436 * 1.2: Add Power Management
437 * 1.3: Add vblank support
438 * 1.4: Fix cmdbuffer path, add heap destroy
439 * 1.5: Add vblank pipe configuration
440 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
441 * - Support vertical blank on secondary display pipe
443 #define DRIVER_MAJOR 1
444 #define DRIVER_MINOR 6
445 #define DRIVER_PATCHLEVEL 0
447 #define WATCH_LISTS 0
449 struct opregion_header;
450 struct opregion_acpi;
451 struct opregion_swsci;
452 struct opregion_asle;
454 struct intel_opregion {
455 struct opregion_header *header;
456 struct opregion_acpi *acpi;
457 struct opregion_swsci *swsci;
458 u32 swsci_gbda_sub_functions;
459 u32 swsci_sbcb_sub_functions;
460 struct opregion_asle *asle;
465 struct work_struct asle_work;
467 #define OPREGION_SIZE (8*1024)
469 struct intel_overlay;
470 struct intel_overlay_error_state;
472 #define I915_FENCE_REG_NONE -1
473 #define I915_MAX_NUM_FENCES 32
474 /* 32 fences + sign bit for FENCE_REG_NONE */
475 #define I915_MAX_NUM_FENCE_BITS 6
477 struct drm_i915_fence_reg {
478 struct list_head lru_list;
479 struct drm_i915_gem_object *obj;
483 struct sdvo_device_mapping {
492 struct intel_display_error_state;
494 struct drm_i915_error_state {
503 /* Generic register state */
511 u32 error; /* gen6+ */
512 u32 err_int; /* gen7 */
513 u32 fault_data0; /* gen8, gen9 */
514 u32 fault_data1; /* gen8, gen9 */
520 u32 extra_instdone[I915_NUM_INSTDONE_REG];
521 u64 fence[I915_MAX_NUM_FENCES];
522 struct intel_overlay_error_state *overlay;
523 struct intel_display_error_state *display;
524 struct drm_i915_error_object *semaphore_obj;
526 struct drm_i915_error_ring {
528 /* Software tracked state */
531 enum intel_ring_hangcheck_action hangcheck_action;
534 /* our own tracking of ring head and tail */
538 u32 semaphore_seqno[I915_NUM_RINGS - 1];
557 u32 rc_psmi; /* sleep state */
558 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
560 struct drm_i915_error_object {
564 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
566 struct drm_i915_error_request {
581 char comm[TASK_COMM_LEN];
582 } ring[I915_NUM_RINGS];
584 struct drm_i915_error_buffer {
587 u32 rseqno[I915_NUM_RINGS], wseqno;
591 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
599 } **active_bo, **pinned_bo;
601 u32 *active_bo_count, *pinned_bo_count;
605 struct intel_connector;
606 struct intel_encoder;
607 struct intel_crtc_state;
608 struct intel_initial_plane_config;
613 struct drm_i915_display_funcs {
614 int (*get_display_clock_speed)(struct drm_device *dev);
615 int (*get_fifo_size)(struct drm_device *dev, int plane);
617 * find_dpll() - Find the best values for the PLL
618 * @limit: limits for the PLL
619 * @crtc: current CRTC
620 * @target: target frequency in kHz
621 * @refclk: reference clock frequency in kHz
622 * @match_clock: if provided, @best_clock P divider must
623 * match the P divider from @match_clock
624 * used for LVDS downclocking
625 * @best_clock: best PLL values found
627 * Returns true on success, false on failure.
629 bool (*find_dpll)(const struct intel_limit *limit,
630 struct intel_crtc_state *crtc_state,
631 int target, int refclk,
632 struct dpll *match_clock,
633 struct dpll *best_clock);
634 int (*compute_pipe_wm)(struct intel_crtc *crtc,
635 struct drm_atomic_state *state);
636 void (*update_wm)(struct drm_crtc *crtc);
637 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
638 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
639 /* Returns the active state of the crtc, and if the crtc is active,
640 * fills out the pipe-config with the hw state. */
641 bool (*get_pipe_config)(struct intel_crtc *,
642 struct intel_crtc_state *);
643 void (*get_initial_plane_config)(struct intel_crtc *,
644 struct intel_initial_plane_config *);
645 int (*crtc_compute_clock)(struct intel_crtc *crtc,
646 struct intel_crtc_state *crtc_state);
647 void (*crtc_enable)(struct drm_crtc *crtc);
648 void (*crtc_disable)(struct drm_crtc *crtc);
649 void (*audio_codec_enable)(struct drm_connector *connector,
650 struct intel_encoder *encoder,
651 const struct drm_display_mode *adjusted_mode);
652 void (*audio_codec_disable)(struct intel_encoder *encoder);
653 void (*fdi_link_train)(struct drm_crtc *crtc);
654 void (*init_clock_gating)(struct drm_device *dev);
655 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
656 struct drm_framebuffer *fb,
657 struct drm_i915_gem_object *obj,
658 struct drm_i915_gem_request *req,
660 void (*update_primary_plane)(struct drm_crtc *crtc,
661 struct drm_framebuffer *fb,
663 void (*hpd_irq_setup)(struct drm_device *dev);
664 /* clock updates for mode set */
666 /* render clock increase/decrease */
667 /* display clock increase/decrease */
668 /* pll clock increase/decrease */
671 enum forcewake_domain_id {
672 FW_DOMAIN_ID_RENDER = 0,
673 FW_DOMAIN_ID_BLITTER,
679 enum forcewake_domains {
680 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
681 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
682 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
683 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
688 struct intel_uncore_funcs {
689 void (*force_wake_get)(struct drm_i915_private *dev_priv,
690 enum forcewake_domains domains);
691 void (*force_wake_put)(struct drm_i915_private *dev_priv,
692 enum forcewake_domains domains);
694 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
695 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
696 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
697 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
699 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
700 uint8_t val, bool trace);
701 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
702 uint16_t val, bool trace);
703 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
704 uint32_t val, bool trace);
705 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
706 uint64_t val, bool trace);
709 struct intel_uncore {
710 spinlock_t lock; /** lock is also taken in irq contexts. */
712 struct intel_uncore_funcs funcs;
715 enum forcewake_domains fw_domains;
717 struct intel_uncore_forcewake_domain {
718 struct drm_i915_private *i915;
719 enum forcewake_domain_id id;
721 struct timer_list timer;
728 } fw_domain[FW_DOMAIN_ID_COUNT];
731 /* Iterate over initialised fw domains */
732 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
733 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
734 (i__) < FW_DOMAIN_ID_COUNT; \
735 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
736 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
738 #define for_each_fw_domain(domain__, dev_priv__, i__) \
739 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
741 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
742 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
743 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
746 struct work_struct work;
748 uint32_t *dmc_payload;
749 uint32_t dmc_fw_size;
752 i915_reg_t mmioaddr[8];
753 uint32_t mmiodata[8];
756 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
757 func(is_mobile) sep \
760 func(is_i945gm) sep \
762 func(need_gfx_hws) sep \
764 func(is_pineview) sep \
765 func(is_broadwater) sep \
766 func(is_crestline) sep \
767 func(is_ivybridge) sep \
768 func(is_valleyview) sep \
769 func(is_cherryview) sep \
770 func(is_haswell) sep \
771 func(is_skylake) sep \
772 func(is_broxton) sep \
773 func(is_kabylake) sep \
774 func(is_preliminary) sep \
776 func(has_pipe_cxsr) sep \
777 func(has_hotplug) sep \
778 func(cursor_needs_physical) sep \
779 func(has_overlay) sep \
780 func(overlay_needs_physical) sep \
781 func(supports_tv) sep \
786 #define DEFINE_FLAG(name) u8 name:1
787 #define SEP_SEMICOLON ;
789 struct intel_device_info {
790 u32 display_mmio_offset;
793 u8 num_sprites[I915_MAX_PIPES];
795 u8 ring_mask; /* Rings supported by the HW */
796 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
797 /* Register offsets for the various display pipes and transcoders */
798 int pipe_offsets[I915_MAX_TRANSCODERS];
799 int trans_offsets[I915_MAX_TRANSCODERS];
800 int palette_offsets[I915_MAX_PIPES];
801 int cursor_offsets[I915_MAX_PIPES];
803 /* Slice/subslice/EU info */
806 u8 subslice_per_slice;
809 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
812 u8 has_subslice_pg:1;
819 enum i915_cache_level {
821 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
822 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
823 caches, eg sampler/render caches, and the
824 large Last-Level-Cache. LLC is coherent with
825 the CPU, but L3 is only visible to the GPU. */
826 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
829 struct i915_ctx_hang_stats {
830 /* This context had batch pending when hang was declared */
831 unsigned batch_pending;
833 /* This context had batch active when hang was declared */
834 unsigned batch_active;
836 /* Time when this context was last blamed for a GPU reset */
837 unsigned long guilty_ts;
839 /* If the contexts causes a second GPU hang within this time,
840 * it is permanently banned from submitting any more work.
842 unsigned long ban_period_seconds;
844 /* This context is banned to submit more work */
848 /* This must match up with the value previously used for execbuf2.rsvd1. */
849 #define DEFAULT_CONTEXT_HANDLE 0
851 #define CONTEXT_NO_ZEROMAP (1<<0)
853 * struct intel_context - as the name implies, represents a context.
854 * @ref: reference count.
855 * @user_handle: userspace tracking identity for this context.
856 * @remap_slice: l3 row remapping information.
857 * @flags: context specific flags:
858 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
859 * @file_priv: filp associated with this context (NULL for global default
861 * @hang_stats: information about the role of this context in possible GPU
863 * @ppgtt: virtual memory space used by this context.
864 * @legacy_hw_ctx: render context backing object and whether it is correctly
865 * initialized (legacy ring submission mechanism only).
866 * @link: link in the global list of contexts.
868 * Contexts are memory images used by the hardware to store copies of their
871 struct intel_context {
875 struct drm_i915_private *i915;
877 struct drm_i915_file_private *file_priv;
878 struct i915_ctx_hang_stats hang_stats;
879 struct i915_hw_ppgtt *ppgtt;
881 /* Legacy ring buffer submission */
883 struct drm_i915_gem_object *rcs_state;
889 struct drm_i915_gem_object *state;
890 struct intel_ringbuffer *ringbuf;
892 } engine[I915_NUM_RINGS];
894 struct list_head link;
906 /* This is always the inner lock when overlapping with struct_mutex and
907 * it's the outer lock when overlapping with stolen_lock. */
911 unsigned int possible_framebuffer_bits;
912 unsigned int busy_bits;
913 struct intel_crtc *crtc;
916 struct drm_mm_node compressed_fb;
917 struct drm_mm_node *compressed_llb;
924 struct intel_fbc_work {
926 struct work_struct work;
927 struct drm_framebuffer *fb;
928 unsigned long enable_jiffies;
931 const char *no_fbc_reason;
933 bool (*is_active)(struct drm_i915_private *dev_priv);
934 void (*activate)(struct intel_crtc *crtc);
935 void (*deactivate)(struct drm_i915_private *dev_priv);
939 * HIGH_RR is the highest eDP panel refresh rate read from EDID
940 * LOW_RR is the lowest eDP panel refresh rate found from EDID
941 * parsing for same resolution.
943 enum drrs_refresh_rate_type {
946 DRRS_MAX_RR, /* RR count */
949 enum drrs_support_type {
950 DRRS_NOT_SUPPORTED = 0,
951 STATIC_DRRS_SUPPORT = 1,
952 SEAMLESS_DRRS_SUPPORT = 2
958 struct delayed_work work;
960 unsigned busy_frontbuffer_bits;
961 enum drrs_refresh_rate_type refresh_rate_type;
962 enum drrs_support_type type;
969 struct intel_dp *enabled;
971 struct delayed_work work;
972 unsigned busy_frontbuffer_bits;
978 PCH_NONE = 0, /* No PCH present */
979 PCH_IBX, /* Ibexpeak PCH */
980 PCH_CPT, /* Cougarpoint PCH */
981 PCH_LPT, /* Lynxpoint PCH */
982 PCH_SPT, /* Sunrisepoint PCH */
986 enum intel_sbi_destination {
991 #define QUIRK_PIPEA_FORCE (1<<0)
992 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
993 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
994 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
995 #define QUIRK_PIPEB_FORCE (1<<4)
996 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
999 struct intel_fbc_work;
1001 struct intel_gmbus {
1002 struct i2c_adapter adapter;
1005 i915_reg_t gpio_reg;
1006 struct i2c_algo_bit_data bit_algo;
1007 struct drm_i915_private *dev_priv;
1010 struct i915_suspend_saved_registers {
1013 u32 savePP_ON_DELAYS;
1014 u32 savePP_OFF_DELAYS;
1019 u32 saveFBC_CONTROL;
1020 u32 saveCACHE_MODE_0;
1021 u32 saveMI_ARB_STATE;
1025 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1026 u32 savePCH_PORT_HOTPLUG;
1030 struct vlv_s0ix_state {
1037 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1038 u32 media_max_req_count;
1039 u32 gfx_max_req_count;
1065 u32 rp_down_timeout;
1071 /* Display 1 CZ domain */
1076 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1078 /* GT SA CZ domain */
1085 /* Display 2 CZ domain */
1089 u32 clock_gate_dis2;
1092 struct intel_rps_ei {
1098 struct intel_gen6_power_mgmt {
1100 * work, interrupts_enabled and pm_iir are protected by
1101 * dev_priv->irq_lock
1103 struct work_struct work;
1104 bool interrupts_enabled;
1107 /* Frequencies are stored in potentially platform dependent multiples.
1108 * In other words, *_freq needs to be multiplied by X to be interesting.
1109 * Soft limits are those which are used for the dynamic reclocking done
1110 * by the driver (raise frequencies under heavy loads, and lower for
1111 * lighter loads). Hard limits are those imposed by the hardware.
1113 * A distinction is made for overclocking, which is never enabled by
1114 * default, and is considered to be above the hard limit if it's
1117 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1118 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1119 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1120 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1121 u8 min_freq; /* AKA RPn. Minimum frequency */
1122 u8 idle_freq; /* Frequency to request when we are idle */
1123 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1124 u8 rp1_freq; /* "less than" RP0 power/freqency */
1125 u8 rp0_freq; /* Non-overclocked max frequency. */
1127 u8 up_threshold; /* Current %busy required to uplock */
1128 u8 down_threshold; /* Current %busy required to downclock */
1131 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1133 spinlock_t client_lock;
1134 struct list_head clients;
1138 struct delayed_work delayed_resume_work;
1141 struct intel_rps_client semaphores, mmioflips;
1143 /* manual wa residency calculations */
1144 struct intel_rps_ei up_ei, down_ei;
1147 * Protects RPS/RC6 register access and PCU communication.
1148 * Must be taken after struct_mutex if nested. Note that
1149 * this lock may be held for long periods of time when
1150 * talking to hw - so only take it when talking to hw!
1152 struct mutex hw_lock;
1155 /* defined intel_pm.c */
1156 extern spinlock_t mchdev_lock;
1158 struct intel_ilk_power_mgmt {
1166 unsigned long last_time1;
1167 unsigned long chipset_power;
1170 unsigned long gfx_power;
1177 struct drm_i915_private;
1178 struct i915_power_well;
1180 struct i915_power_well_ops {
1182 * Synchronize the well's hw state to match the current sw state, for
1183 * example enable/disable it based on the current refcount. Called
1184 * during driver init and resume time, possibly after first calling
1185 * the enable/disable handlers.
1187 void (*sync_hw)(struct drm_i915_private *dev_priv,
1188 struct i915_power_well *power_well);
1190 * Enable the well and resources that depend on it (for example
1191 * interrupts located on the well). Called after the 0->1 refcount
1194 void (*enable)(struct drm_i915_private *dev_priv,
1195 struct i915_power_well *power_well);
1197 * Disable the well and resources that depend on it. Called after
1198 * the 1->0 refcount transition.
1200 void (*disable)(struct drm_i915_private *dev_priv,
1201 struct i915_power_well *power_well);
1202 /* Returns the hw enabled state. */
1203 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1204 struct i915_power_well *power_well);
1207 /* Power well structure for haswell */
1208 struct i915_power_well {
1211 /* power well enable/disable usage count */
1213 /* cached hw enabled state */
1215 unsigned long domains;
1217 const struct i915_power_well_ops *ops;
1220 struct i915_power_domains {
1222 * Power wells needed for initialization at driver init and suspend
1223 * time are on. They are kept on until after the first modeset.
1227 int power_well_count;
1230 int domain_use_count[POWER_DOMAIN_NUM];
1231 struct i915_power_well *power_wells;
1234 #define MAX_L3_SLICES 2
1235 struct intel_l3_parity {
1236 u32 *remap_info[MAX_L3_SLICES];
1237 struct work_struct error_work;
1241 struct i915_gem_mm {
1242 /** Memory allocator for GTT stolen memory */
1243 struct drm_mm stolen;
1244 /** Protects the usage of the GTT stolen memory allocator. This is
1245 * always the inner lock when overlapping with struct_mutex. */
1246 struct mutex stolen_lock;
1248 /** List of all objects in gtt_space. Used to restore gtt
1249 * mappings on resume */
1250 struct list_head bound_list;
1252 * List of objects which are not bound to the GTT (thus
1253 * are idle and not used by the GPU) but still have
1254 * (presumably uncached) pages still attached.
1256 struct list_head unbound_list;
1258 /** Usable portion of the GTT for GEM */
1259 unsigned long stolen_base; /* limited to low memory (32-bit) */
1261 /** PPGTT used for aliasing the PPGTT with the GTT */
1262 struct i915_hw_ppgtt *aliasing_ppgtt;
1264 struct notifier_block oom_notifier;
1265 struct shrinker shrinker;
1266 bool shrinker_no_lock_stealing;
1268 /** LRU list of objects with fence regs on them. */
1269 struct list_head fence_list;
1272 * We leave the user IRQ off as much as possible,
1273 * but this means that requests will finish and never
1274 * be retired once the system goes idle. Set a timer to
1275 * fire periodically while the ring is running. When it
1276 * fires, go retire requests.
1278 struct delayed_work retire_work;
1281 * When we detect an idle GPU, we want to turn on
1282 * powersaving features. So once we see that there
1283 * are no more requests outstanding and no more
1284 * arrive within a small period of time, we fire
1285 * off the idle_work.
1287 struct delayed_work idle_work;
1290 * Are we in a non-interruptible section of code like
1296 * Is the GPU currently considered idle, or busy executing userspace
1297 * requests? Whilst idle, we attempt to power down the hardware and
1298 * display clocks. In order to reduce the effect on performance, there
1299 * is a slight delay before we do so.
1303 /* the indicator for dispatch video commands on two BSD rings */
1304 int bsd_ring_dispatch_index;
1306 /** Bit 6 swizzling required for X tiling */
1307 uint32_t bit_6_swizzle_x;
1308 /** Bit 6 swizzling required for Y tiling */
1309 uint32_t bit_6_swizzle_y;
1311 /* accounting, useful for userland debugging */
1312 spinlock_t object_stat_lock;
1313 size_t object_memory;
1317 struct drm_i915_error_state_buf {
1318 struct drm_i915_private *i915;
1327 struct i915_error_state_file_priv {
1328 struct drm_device *dev;
1329 struct drm_i915_error_state *error;
1332 struct i915_gpu_error {
1333 /* For hangcheck timer */
1334 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1335 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1336 /* Hang gpu twice in this window and your context gets banned */
1337 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1339 struct workqueue_struct *hangcheck_wq;
1340 struct delayed_work hangcheck_work;
1342 /* For reset and error_state handling. */
1344 /* Protected by the above dev->gpu_error.lock. */
1345 struct drm_i915_error_state *first_error;
1347 unsigned long missed_irq_rings;
1350 * State variable controlling the reset flow and count
1352 * This is a counter which gets incremented when reset is triggered,
1353 * and again when reset has been handled. So odd values (lowest bit set)
1354 * means that reset is in progress and even values that
1355 * (reset_counter >> 1):th reset was successfully completed.
1357 * If reset is not completed succesfully, the I915_WEDGE bit is
1358 * set meaning that hardware is terminally sour and there is no
1359 * recovery. All waiters on the reset_queue will be woken when
1362 * This counter is used by the wait_seqno code to notice that reset
1363 * event happened and it needs to restart the entire ioctl (since most
1364 * likely the seqno it waited for won't ever signal anytime soon).
1366 * This is important for lock-free wait paths, where no contended lock
1367 * naturally enforces the correct ordering between the bail-out of the
1368 * waiter and the gpu reset work code.
1370 atomic_t reset_counter;
1372 #define I915_RESET_IN_PROGRESS_FLAG 1
1373 #define I915_WEDGED (1 << 31)
1376 * Waitqueue to signal when the reset has completed. Used by clients
1377 * that wait for dev_priv->mm.wedged to settle.
1379 wait_queue_head_t reset_queue;
1381 /* Userspace knobs for gpu hang simulation;
1382 * combines both a ring mask, and extra flags
1385 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1386 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1388 /* For missed irq/seqno simulation. */
1389 unsigned int test_irq_rings;
1391 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1392 bool reload_in_reset;
1395 enum modeset_restore {
1396 MODESET_ON_LID_OPEN,
1401 #define DP_AUX_A 0x40
1402 #define DP_AUX_B 0x10
1403 #define DP_AUX_C 0x20
1404 #define DP_AUX_D 0x30
1406 #define DDC_PIN_B 0x05
1407 #define DDC_PIN_C 0x04
1408 #define DDC_PIN_D 0x06
1410 struct ddi_vbt_port_info {
1412 * This is an index in the HDMI/DVI DDI buffer translation table.
1413 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1414 * populate this field.
1416 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1417 uint8_t hdmi_level_shift;
1419 uint8_t supports_dvi:1;
1420 uint8_t supports_hdmi:1;
1421 uint8_t supports_dp:1;
1423 uint8_t alternate_aux_channel;
1424 uint8_t alternate_ddc_pin;
1426 uint8_t dp_boost_level;
1427 uint8_t hdmi_boost_level;
1430 enum psr_lines_to_wait {
1431 PSR_0_LINES_TO_WAIT = 0,
1433 PSR_4_LINES_TO_WAIT,
1437 struct intel_vbt_data {
1438 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1439 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1442 unsigned int int_tv_support:1;
1443 unsigned int lvds_dither:1;
1444 unsigned int lvds_vbt:1;
1445 unsigned int int_crt_support:1;
1446 unsigned int lvds_use_ssc:1;
1447 unsigned int display_clock_mode:1;
1448 unsigned int fdi_rx_polarity_inverted:1;
1449 unsigned int has_mipi:1;
1451 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1453 enum drrs_support_type drrs_type;
1458 int edp_preemphasis;
1460 bool edp_initialized;
1463 struct edp_power_seq edp_pps;
1467 bool require_aux_wakeup;
1469 enum psr_lines_to_wait lines_to_wait;
1470 int tp1_wakeup_time;
1471 int tp2_tp3_wakeup_time;
1477 bool active_low_pwm;
1478 u8 min_brightness; /* min_brightness/255 of max */
1485 struct mipi_config *config;
1486 struct mipi_pps_data *pps;
1490 u8 *sequence[MIPI_SEQ_MAX];
1496 union child_device_config *child_dev;
1498 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1501 enum intel_ddb_partitioning {
1503 INTEL_DDB_PART_5_6, /* IVB+ */
1506 struct intel_wm_level {
1514 struct ilk_wm_values {
1515 uint32_t wm_pipe[3];
1517 uint32_t wm_lp_spr[3];
1518 uint32_t wm_linetime[3];
1520 enum intel_ddb_partitioning partitioning;
1523 struct vlv_pipe_wm {
1534 struct vlv_wm_values {
1535 struct vlv_pipe_wm pipe[3];
1536 struct vlv_sr_wm sr;
1546 struct skl_ddb_entry {
1547 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1550 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1552 return entry->end - entry->start;
1555 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1556 const struct skl_ddb_entry *e2)
1558 if (e1->start == e2->start && e1->end == e2->end)
1564 struct skl_ddb_allocation {
1565 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1566 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1567 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1570 struct skl_wm_values {
1571 bool dirty[I915_MAX_PIPES];
1572 struct skl_ddb_allocation ddb;
1573 uint32_t wm_linetime[I915_MAX_PIPES];
1574 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1575 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1578 struct skl_wm_level {
1579 bool plane_en[I915_MAX_PLANES];
1580 uint16_t plane_res_b[I915_MAX_PLANES];
1581 uint8_t plane_res_l[I915_MAX_PLANES];
1585 * This struct helps tracking the state needed for runtime PM, which puts the
1586 * device in PCI D3 state. Notice that when this happens, nothing on the
1587 * graphics device works, even register access, so we don't get interrupts nor
1590 * Every piece of our code that needs to actually touch the hardware needs to
1591 * either call intel_runtime_pm_get or call intel_display_power_get with the
1592 * appropriate power domain.
1594 * Our driver uses the autosuspend delay feature, which means we'll only really
1595 * suspend if we stay with zero refcount for a certain amount of time. The
1596 * default value is currently very conservative (see intel_runtime_pm_enable), but
1597 * it can be changed with the standard runtime PM files from sysfs.
1599 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1600 * goes back to false exactly before we reenable the IRQs. We use this variable
1601 * to check if someone is trying to enable/disable IRQs while they're supposed
1602 * to be disabled. This shouldn't happen and we'll print some error messages in
1605 * For more, read the Documentation/power/runtime_pm.txt.
1607 struct i915_runtime_pm {
1608 atomic_t wakeref_count;
1609 atomic_t atomic_seq;
1614 enum intel_pipe_crc_source {
1615 INTEL_PIPE_CRC_SOURCE_NONE,
1616 INTEL_PIPE_CRC_SOURCE_PLANE1,
1617 INTEL_PIPE_CRC_SOURCE_PLANE2,
1618 INTEL_PIPE_CRC_SOURCE_PF,
1619 INTEL_PIPE_CRC_SOURCE_PIPE,
1620 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1621 INTEL_PIPE_CRC_SOURCE_TV,
1622 INTEL_PIPE_CRC_SOURCE_DP_B,
1623 INTEL_PIPE_CRC_SOURCE_DP_C,
1624 INTEL_PIPE_CRC_SOURCE_DP_D,
1625 INTEL_PIPE_CRC_SOURCE_AUTO,
1626 INTEL_PIPE_CRC_SOURCE_MAX,
1629 struct intel_pipe_crc_entry {
1634 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1635 struct intel_pipe_crc {
1637 bool opened; /* exclusive access to the result file */
1638 struct intel_pipe_crc_entry *entries;
1639 enum intel_pipe_crc_source source;
1641 wait_queue_head_t wq;
1644 struct i915_frontbuffer_tracking {
1648 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1655 struct i915_wa_reg {
1658 /* bitmask representing WA bits */
1662 #define I915_MAX_WA_REGS 16
1664 struct i915_workarounds {
1665 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1669 struct i915_virtual_gpu {
1673 struct i915_execbuffer_params {
1674 struct drm_device *dev;
1675 struct drm_file *file;
1676 uint32_t dispatch_flags;
1677 uint32_t args_batch_start_offset;
1678 uint64_t batch_obj_vm_offset;
1679 struct intel_engine_cs *ring;
1680 struct drm_i915_gem_object *batch_obj;
1681 struct intel_context *ctx;
1682 struct drm_i915_gem_request *request;
1685 /* used in computing the new watermarks state */
1686 struct intel_wm_config {
1687 unsigned int num_pipes_active;
1688 bool sprites_enabled;
1689 bool sprites_scaled;
1692 struct drm_i915_private {
1693 struct drm_device *dev;
1694 struct kmem_cache *objects;
1695 struct kmem_cache *vmas;
1696 struct kmem_cache *requests;
1698 const struct intel_device_info info;
1700 int relative_constants_mode;
1704 struct intel_uncore uncore;
1706 struct i915_virtual_gpu vgpu;
1708 struct intel_guc guc;
1710 struct intel_csr csr;
1712 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1714 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1715 * controller on different i2c buses. */
1716 struct mutex gmbus_mutex;
1719 * Base address of the gmbus and gpio block.
1721 uint32_t gpio_mmio_base;
1723 /* MMIO base address for MIPI regs */
1724 uint32_t mipi_mmio_base;
1726 uint32_t psr_mmio_base;
1728 wait_queue_head_t gmbus_wait_queue;
1730 struct pci_dev *bridge_dev;
1731 struct intel_engine_cs ring[I915_NUM_RINGS];
1732 struct drm_i915_gem_object *semaphore_obj;
1733 uint32_t last_seqno, next_seqno;
1735 struct drm_dma_handle *status_page_dmah;
1736 struct resource mch_res;
1738 /* protects the irq masks */
1739 spinlock_t irq_lock;
1741 /* protects the mmio flip data */
1742 spinlock_t mmio_flip_lock;
1744 bool display_irqs_enabled;
1746 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1747 struct pm_qos_request pm_qos;
1749 /* Sideband mailbox protection */
1750 struct mutex sb_lock;
1752 /** Cached value of IMR to avoid reads in updating the bitfield */
1755 u32 de_irq_mask[I915_MAX_PIPES];
1760 u32 pipestat_irq_mask[I915_MAX_PIPES];
1762 struct i915_hotplug hotplug;
1763 struct i915_fbc fbc;
1764 struct i915_drrs drrs;
1765 struct intel_opregion opregion;
1766 struct intel_vbt_data vbt;
1768 bool preserve_bios_swizzle;
1771 struct intel_overlay *overlay;
1773 /* backlight registers and fields in struct intel_panel */
1774 struct mutex backlight_lock;
1777 bool no_aux_handshake;
1779 /* protects panel power sequencer state */
1780 struct mutex pps_mutex;
1782 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1783 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1785 unsigned int fsb_freq, mem_freq, is_ddr3;
1786 unsigned int skl_boot_cdclk;
1787 unsigned int cdclk_freq, max_cdclk_freq;
1788 unsigned int max_dotclk_freq;
1789 unsigned int hpll_freq;
1790 unsigned int czclk_freq;
1793 * wq - Driver workqueue for GEM.
1795 * NOTE: Work items scheduled here are not allowed to grab any modeset
1796 * locks, for otherwise the flushing done in the pageflip code will
1797 * result in deadlocks.
1799 struct workqueue_struct *wq;
1801 /* Display functions */
1802 struct drm_i915_display_funcs display;
1804 /* PCH chipset type */
1805 enum intel_pch pch_type;
1806 unsigned short pch_id;
1808 unsigned long quirks;
1810 enum modeset_restore modeset_restore;
1811 struct mutex modeset_restore_lock;
1813 struct list_head vm_list; /* Global list of all address spaces */
1814 struct i915_gtt gtt; /* VM representing the global address space */
1816 struct i915_gem_mm mm;
1817 DECLARE_HASHTABLE(mm_structs, 7);
1818 struct mutex mm_lock;
1820 /* Kernel Modesetting */
1822 struct sdvo_device_mapping sdvo_mappings[2];
1824 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1825 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1826 wait_queue_head_t pending_flip_queue;
1828 #ifdef CONFIG_DEBUG_FS
1829 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1832 int num_shared_dpll;
1833 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1834 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1836 struct i915_workarounds workarounds;
1838 /* Reclocking support */
1839 bool render_reclock_avail;
1841 struct i915_frontbuffer_tracking fb_tracking;
1845 bool mchbar_need_disable;
1847 struct intel_l3_parity l3_parity;
1849 /* Cannot be determined by PCIID. You must always read a register. */
1852 /* gen6+ rps state */
1853 struct intel_gen6_power_mgmt rps;
1855 /* ilk-only ips/rps state. Everything in here is protected by the global
1856 * mchdev_lock in intel_pm.c */
1857 struct intel_ilk_power_mgmt ips;
1859 struct i915_power_domains power_domains;
1861 struct i915_psr psr;
1863 struct i915_gpu_error gpu_error;
1865 struct drm_i915_gem_object *vlv_pctx;
1867 #ifdef CONFIG_DRM_FBDEV_EMULATION
1868 /* list of fbdev register on this device */
1869 struct intel_fbdev *fbdev;
1870 struct work_struct fbdev_suspend_work;
1873 struct drm_property *broadcast_rgb_property;
1874 struct drm_property *force_audio_property;
1876 /* hda/i915 audio component */
1877 struct i915_audio_component *audio_component;
1878 bool audio_component_registered;
1880 * av_mutex - mutex for audio/video sync
1883 struct mutex av_mutex;
1885 uint32_t hw_context_size;
1886 struct list_head context_list;
1890 u32 chv_phy_control;
1893 bool suspended_to_idle;
1894 struct i915_suspend_saved_registers regfile;
1895 struct vlv_s0ix_state vlv_s0ix_state;
1899 * Raw watermark latency values:
1900 * in 0.1us units for WM0,
1901 * in 0.5us units for WM1+.
1904 uint16_t pri_latency[5];
1906 uint16_t spr_latency[5];
1908 uint16_t cur_latency[5];
1910 * Raw watermark memory latency values
1911 * for SKL for all 8 levels
1914 uint16_t skl_latency[8];
1916 /* Committed wm config */
1917 struct intel_wm_config config;
1920 * The skl_wm_values structure is a bit too big for stack
1921 * allocation, so we keep the staging struct where we store
1922 * intermediate results here instead.
1924 struct skl_wm_values skl_results;
1926 /* current hardware state */
1928 struct ilk_wm_values hw;
1929 struct skl_wm_values skl_hw;
1930 struct vlv_wm_values vlv;
1936 struct i915_runtime_pm pm;
1938 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1940 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1941 struct drm_i915_gem_execbuffer2 *args,
1942 struct list_head *vmas);
1943 int (*init_rings)(struct drm_device *dev);
1944 void (*cleanup_ring)(struct intel_engine_cs *ring);
1945 void (*stop_ring)(struct intel_engine_cs *ring);
1948 bool edp_low_vswing;
1950 /* perform PHY state sanity checks? */
1951 bool chv_phy_assert[2];
1953 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1956 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1957 * will be rejected. Instead look for a better place.
1961 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1963 return dev->dev_private;
1966 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1968 return to_i915(dev_get_drvdata(dev));
1971 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1973 return container_of(guc, struct drm_i915_private, guc);
1976 /* Iterate over initialised rings */
1977 #define for_each_ring(ring__, dev_priv__, i__) \
1978 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1979 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
1981 enum hdmi_force_audio {
1982 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1983 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1984 HDMI_AUDIO_AUTO, /* trust EDID */
1985 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1988 #define I915_GTT_OFFSET_NONE ((u32)-1)
1990 struct drm_i915_gem_object_ops {
1992 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
1994 /* Interface between the GEM object and its backing storage.
1995 * get_pages() is called once prior to the use of the associated set
1996 * of pages before to binding them into the GTT, and put_pages() is
1997 * called after we no longer need them. As we expect there to be
1998 * associated cost with migrating pages between the backing storage
1999 * and making them available for the GPU (e.g. clflush), we may hold
2000 * onto the pages after they are no longer referenced by the GPU
2001 * in case they may be used again shortly (for example migrating the
2002 * pages to a different memory domain within the GTT). put_pages()
2003 * will therefore most likely be called when the object itself is
2004 * being released or under memory pressure (where we attempt to
2005 * reap pages for the shrinker).
2007 int (*get_pages)(struct drm_i915_gem_object *);
2008 void (*put_pages)(struct drm_i915_gem_object *);
2010 int (*dmabuf_export)(struct drm_i915_gem_object *);
2011 void (*release)(struct drm_i915_gem_object *);
2015 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2016 * considered to be the frontbuffer for the given plane interface-wise. This
2017 * doesn't mean that the hw necessarily already scans it out, but that any
2018 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2020 * We have one bit per pipe and per scanout plane type.
2022 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2023 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2024 #define INTEL_FRONTBUFFER_BITS \
2025 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2026 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2027 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2028 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2029 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2030 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2031 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2032 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2033 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2034 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2035 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2037 struct drm_i915_gem_object {
2038 struct drm_gem_object base;
2040 const struct drm_i915_gem_object_ops *ops;
2042 /** List of VMAs backed by this object */
2043 struct list_head vma_list;
2045 /** Stolen memory for this object, instead of being backed by shmem. */
2046 struct drm_mm_node *stolen;
2047 struct list_head global_list;
2049 struct list_head ring_list[I915_NUM_RINGS];
2050 /** Used in execbuf to temporarily hold a ref */
2051 struct list_head obj_exec_link;
2053 struct list_head batch_pool_link;
2056 * This is set if the object is on the active lists (has pending
2057 * rendering and so a non-zero seqno), and is not set if it i s on
2058 * inactive (ready to be unbound) list.
2060 unsigned int active:I915_NUM_RINGS;
2063 * This is set if the object has been written to since last bound
2066 unsigned int dirty:1;
2069 * Fence register bits (if any) for this object. Will be set
2070 * as needed when mapped into the GTT.
2071 * Protected by dev->struct_mutex.
2073 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2076 * Advice: are the backing pages purgeable?
2078 unsigned int madv:2;
2081 * Current tiling mode for the object.
2083 unsigned int tiling_mode:2;
2085 * Whether the tiling parameters for the currently associated fence
2086 * register have changed. Note that for the purposes of tracking
2087 * tiling changes we also treat the unfenced register, the register
2088 * slot that the object occupies whilst it executes a fenced
2089 * command (such as BLT on gen2/3), as a "fence".
2091 unsigned int fence_dirty:1;
2094 * Is the object at the current location in the gtt mappable and
2095 * fenceable? Used to avoid costly recalculations.
2097 unsigned int map_and_fenceable:1;
2100 * Whether the current gtt mapping needs to be mappable (and isn't just
2101 * mappable by accident). Track pin and fault separate for a more
2102 * accurate mappable working set.
2104 unsigned int fault_mappable:1;
2107 * Is the object to be mapped as read-only to the GPU
2108 * Only honoured if hardware has relevant pte bit
2110 unsigned long gt_ro:1;
2111 unsigned int cache_level:3;
2112 unsigned int cache_dirty:1;
2114 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2116 unsigned int pin_display;
2118 struct sg_table *pages;
2119 int pages_pin_count;
2121 struct scatterlist *sg;
2125 /* prime dma-buf support */
2126 void *dma_buf_vmapping;
2129 /** Breadcrumb of last rendering to the buffer.
2130 * There can only be one writer, but we allow for multiple readers.
2131 * If there is a writer that necessarily implies that all other
2132 * read requests are complete - but we may only be lazily clearing
2133 * the read requests. A read request is naturally the most recent
2134 * request on a ring, so we may have two different write and read
2135 * requests on one ring where the write request is older than the
2136 * read request. This allows for the CPU to read from an active
2137 * buffer by only waiting for the write to complete.
2139 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2140 struct drm_i915_gem_request *last_write_req;
2141 /** Breadcrumb of last fenced GPU access to the buffer. */
2142 struct drm_i915_gem_request *last_fenced_req;
2144 /** Current tiling stride for the object, if it's tiled. */
2147 /** References from framebuffers, locks out tiling changes. */
2148 unsigned long framebuffer_references;
2150 /** Record of address bit 17 of each page at last unbind. */
2151 unsigned long *bit_17;
2154 /** for phy allocated objects */
2155 struct drm_dma_handle *phys_handle;
2157 struct i915_gem_userptr {
2159 unsigned read_only :1;
2160 unsigned workers :4;
2161 #define I915_GEM_USERPTR_MAX_WORKERS 15
2163 struct i915_mm_struct *mm;
2164 struct i915_mmu_object *mmu_object;
2165 struct work_struct *work;
2169 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2171 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2172 struct drm_i915_gem_object *new,
2173 unsigned frontbuffer_bits);
2176 * Request queue structure.
2178 * The request queue allows us to note sequence numbers that have been emitted
2179 * and may be associated with active buffers to be retired.
2181 * By keeping this list, we can avoid having to do questionable sequence
2182 * number comparisons on buffer last_read|write_seqno. It also allows an
2183 * emission time to be associated with the request for tracking how far ahead
2184 * of the GPU the submission is.
2186 * The requests are reference counted, so upon creation they should have an
2187 * initial reference taken using kref_init
2189 struct drm_i915_gem_request {
2192 /** On Which ring this request was generated */
2193 struct drm_i915_private *i915;
2194 struct intel_engine_cs *ring;
2196 /** GEM sequence number associated with the previous request,
2197 * when the HWS breadcrumb is equal to this the GPU is processing
2202 /** GEM sequence number associated with this request,
2203 * when the HWS breadcrumb is equal or greater than this the GPU
2204 * has finished processing this request.
2208 /** Position in the ringbuffer of the start of the request */
2212 * Position in the ringbuffer of the start of the postfix.
2213 * This is required to calculate the maximum available ringbuffer
2214 * space without overwriting the postfix.
2218 /** Position in the ringbuffer of the end of the whole request */
2222 * Context and ring buffer related to this request
2223 * Contexts are refcounted, so when this request is associated with a
2224 * context, we must increment the context's refcount, to guarantee that
2225 * it persists while any request is linked to it. Requests themselves
2226 * are also refcounted, so the request will only be freed when the last
2227 * reference to it is dismissed, and the code in
2228 * i915_gem_request_free() will then decrement the refcount on the
2231 struct intel_context *ctx;
2232 struct intel_ringbuffer *ringbuf;
2234 /** Batch buffer related to this request if any (used for
2235 error state dump only) */
2236 struct drm_i915_gem_object *batch_obj;
2238 /** Time at which this request was emitted, in jiffies. */
2239 unsigned long emitted_jiffies;
2241 /** global list entry for this request */
2242 struct list_head list;
2244 struct drm_i915_file_private *file_priv;
2245 /** file_priv list entry for this request */
2246 struct list_head client_list;
2248 /** process identifier submitting this request */
2252 * The ELSP only accepts two elements at a time, so we queue
2253 * context/tail pairs on a given queue (ring->execlist_queue) until the
2254 * hardware is available. The queue serves a double purpose: we also use
2255 * it to keep track of the up to 2 contexts currently in the hardware
2256 * (usually one in execution and the other queued up by the GPU): We
2257 * only remove elements from the head of the queue when the hardware
2258 * informs us that an element has been completed.
2260 * All accesses to the queue are mediated by a spinlock
2261 * (ring->execlist_lock).
2264 /** Execlist link in the submission queue.*/
2265 struct list_head execlist_link;
2267 /** Execlists no. of times this request has been sent to the ELSP */
2272 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2273 struct intel_context *ctx,
2274 struct drm_i915_gem_request **req_out);
2275 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2276 void i915_gem_request_free(struct kref *req_ref);
2277 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2278 struct drm_file *file);
2280 static inline uint32_t
2281 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2283 return req ? req->seqno : 0;
2286 static inline struct intel_engine_cs *
2287 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2289 return req ? req->ring : NULL;
2292 static inline struct drm_i915_gem_request *
2293 i915_gem_request_reference(struct drm_i915_gem_request *req)
2296 kref_get(&req->ref);
2301 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2303 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2304 kref_put(&req->ref, i915_gem_request_free);
2308 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2310 struct drm_device *dev;
2315 dev = req->ring->dev;
2316 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2317 mutex_unlock(&dev->struct_mutex);
2320 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2321 struct drm_i915_gem_request *src)
2324 i915_gem_request_reference(src);
2327 i915_gem_request_unreference(*pdst);
2333 * XXX: i915_gem_request_completed should be here but currently needs the
2334 * definition of i915_seqno_passed() which is below. It will be moved in
2335 * a later patch when the call to i915_seqno_passed() is obsoleted...
2339 * A command that requires special handling by the command parser.
2341 struct drm_i915_cmd_descriptor {
2343 * Flags describing how the command parser processes the command.
2345 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2346 * a length mask if not set
2347 * CMD_DESC_SKIP: The command is allowed but does not follow the
2348 * standard length encoding for the opcode range in
2350 * CMD_DESC_REJECT: The command is never allowed
2351 * CMD_DESC_REGISTER: The command should be checked against the
2352 * register whitelist for the appropriate ring
2353 * CMD_DESC_MASTER: The command is allowed if the submitting process
2357 #define CMD_DESC_FIXED (1<<0)
2358 #define CMD_DESC_SKIP (1<<1)
2359 #define CMD_DESC_REJECT (1<<2)
2360 #define CMD_DESC_REGISTER (1<<3)
2361 #define CMD_DESC_BITMASK (1<<4)
2362 #define CMD_DESC_MASTER (1<<5)
2365 * The command's unique identification bits and the bitmask to get them.
2366 * This isn't strictly the opcode field as defined in the spec and may
2367 * also include type, subtype, and/or subop fields.
2375 * The command's length. The command is either fixed length (i.e. does
2376 * not include a length field) or has a length field mask. The flag
2377 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2378 * a length mask. All command entries in a command table must include
2379 * length information.
2387 * Describes where to find a register address in the command to check
2388 * against the ring's register whitelist. Only valid if flags has the
2389 * CMD_DESC_REGISTER bit set.
2391 * A non-zero step value implies that the command may access multiple
2392 * registers in sequence (e.g. LRI), in that case step gives the
2393 * distance in dwords between individual offset fields.
2401 #define MAX_CMD_DESC_BITMASKS 3
2403 * Describes command checks where a particular dword is masked and
2404 * compared against an expected value. If the command does not match
2405 * the expected value, the parser rejects it. Only valid if flags has
2406 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2409 * If the check specifies a non-zero condition_mask then the parser
2410 * only performs the check when the bits specified by condition_mask
2417 u32 condition_offset;
2419 } bits[MAX_CMD_DESC_BITMASKS];
2423 * A table of commands requiring special handling by the command parser.
2425 * Each ring has an array of tables. Each table consists of an array of command
2426 * descriptors, which must be sorted with command opcodes in ascending order.
2428 struct drm_i915_cmd_table {
2429 const struct drm_i915_cmd_descriptor *table;
2433 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2434 #define __I915__(p) ({ \
2435 struct drm_i915_private *__p; \
2436 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2437 __p = (struct drm_i915_private *)p; \
2438 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2439 __p = to_i915((struct drm_device *)p); \
2444 #define INTEL_INFO(p) (&__I915__(p)->info)
2445 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2446 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2448 #define REVID_FOREVER 0xff
2450 * Return true if revision is in range [since,until] inclusive.
2452 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2454 #define IS_REVID(p, since, until) \
2455 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2457 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2458 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2459 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2460 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2461 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2462 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2463 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2464 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2465 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2466 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2467 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2468 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2469 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2470 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2471 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2472 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2473 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2474 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2475 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2476 INTEL_DEVID(dev) == 0x0152 || \
2477 INTEL_DEVID(dev) == 0x015a)
2478 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2479 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2480 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2481 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2482 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2483 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2484 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2485 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2486 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2487 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2488 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2489 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2490 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2491 (INTEL_DEVID(dev) & 0xf) == 0xe))
2492 /* ULX machines are also considered ULT. */
2493 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2494 (INTEL_DEVID(dev) & 0xf) == 0xe)
2495 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2496 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2497 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2498 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2499 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2500 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2501 /* ULX machines are also considered ULT. */
2502 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2503 INTEL_DEVID(dev) == 0x0A1E)
2504 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2505 INTEL_DEVID(dev) == 0x1913 || \
2506 INTEL_DEVID(dev) == 0x1916 || \
2507 INTEL_DEVID(dev) == 0x1921 || \
2508 INTEL_DEVID(dev) == 0x1926)
2509 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2510 INTEL_DEVID(dev) == 0x1915 || \
2511 INTEL_DEVID(dev) == 0x191E)
2512 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2513 INTEL_DEVID(dev) == 0x5913 || \
2514 INTEL_DEVID(dev) == 0x5916 || \
2515 INTEL_DEVID(dev) == 0x5921 || \
2516 INTEL_DEVID(dev) == 0x5926)
2517 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2518 INTEL_DEVID(dev) == 0x5915 || \
2519 INTEL_DEVID(dev) == 0x591E)
2520 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2521 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2522 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2523 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2525 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2527 #define SKL_REVID_A0 0x0
2528 #define SKL_REVID_B0 0x1
2529 #define SKL_REVID_C0 0x2
2530 #define SKL_REVID_D0 0x3
2531 #define SKL_REVID_E0 0x4
2532 #define SKL_REVID_F0 0x5
2534 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2536 #define BXT_REVID_A0 0x0
2537 #define BXT_REVID_A1 0x1
2538 #define BXT_REVID_B0 0x3
2539 #define BXT_REVID_C0 0x9
2541 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2544 * The genX designation typically refers to the render engine, so render
2545 * capability related checks should use IS_GEN, while display and other checks
2546 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2549 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2550 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2551 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2552 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2553 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2554 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2555 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2556 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2558 #define RENDER_RING (1<<RCS)
2559 #define BSD_RING (1<<VCS)
2560 #define BLT_RING (1<<BCS)
2561 #define VEBOX_RING (1<<VECS)
2562 #define BSD2_RING (1<<VCS2)
2563 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2564 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2565 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2566 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2567 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2568 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2569 __I915__(dev)->ellc_size)
2570 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2572 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2573 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2574 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2575 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2576 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2578 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2579 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2581 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2582 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2584 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2585 * even when in MSI mode. This results in spurious interrupt warnings if the
2586 * legacy irq no. is shared with another device. The kernel then disables that
2587 * interrupt source and so prevents the other device from working properly.
2589 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2590 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2592 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2593 * rows, which changed the alignment requirements and fence programming.
2595 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2597 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2598 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2600 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2601 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2602 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2604 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2606 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2607 INTEL_INFO(dev)->gen >= 9)
2609 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2610 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2611 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2612 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2613 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2614 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2615 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2616 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2618 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2619 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2621 #define HAS_CSR(dev) (IS_GEN9(dev))
2623 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2624 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2626 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2627 INTEL_INFO(dev)->gen >= 8)
2629 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2630 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2633 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2634 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2635 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2636 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2637 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2638 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2639 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2640 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2641 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2642 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2644 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2645 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2646 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2647 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2648 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2649 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2650 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2651 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2652 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2654 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2655 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2657 /* DPF == dynamic parity feature */
2658 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2659 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2661 #define GT_FREQUENCY_MULTIPLIER 50
2662 #define GEN9_FREQ_SCALER 3
2664 #include "i915_trace.h"
2666 extern const struct drm_ioctl_desc i915_ioctls[];
2667 extern int i915_max_ioctl;
2669 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2670 extern int i915_resume_switcheroo(struct drm_device *dev);
2673 struct i915_params {
2675 int panel_ignore_lid;
2677 int lvds_channel_mode;
2679 int vbt_sdvo_panel_type;
2684 int enable_execlists;
2686 unsigned int preliminary_hw_support;
2687 int disable_power_well;
2689 int invert_brightness;
2690 int enable_cmd_parser;
2691 /* leave bools at the end to not create holes */
2692 bool enable_hangcheck;
2694 bool prefault_disable;
2695 bool load_detect_test;
2697 bool disable_display;
2698 bool disable_vtd_wa;
2699 bool enable_guc_submission;
2703 bool verbose_state_checks;
2704 bool nuclear_pageflip;
2707 extern struct i915_params i915 __read_mostly;
2710 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2711 extern int i915_driver_unload(struct drm_device *);
2712 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2713 extern void i915_driver_lastclose(struct drm_device * dev);
2714 extern void i915_driver_preclose(struct drm_device *dev,
2715 struct drm_file *file);
2716 extern void i915_driver_postclose(struct drm_device *dev,
2717 struct drm_file *file);
2718 #ifdef CONFIG_COMPAT
2719 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2722 extern int intel_gpu_reset(struct drm_device *dev);
2723 extern bool intel_has_gpu_reset(struct drm_device *dev);
2724 extern int i915_reset(struct drm_device *dev);
2725 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2726 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2727 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2728 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2729 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2731 /* intel_hotplug.c */
2732 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2733 void intel_hpd_init(struct drm_i915_private *dev_priv);
2734 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2735 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2736 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2739 void i915_queue_hangcheck(struct drm_device *dev);
2741 void i915_handle_error(struct drm_device *dev, bool wedged,
2742 const char *fmt, ...);
2744 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2745 int intel_irq_install(struct drm_i915_private *dev_priv);
2746 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2748 extern void intel_uncore_sanitize(struct drm_device *dev);
2749 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2750 bool restore_forcewake);
2751 extern void intel_uncore_init(struct drm_device *dev);
2752 extern void intel_uncore_check_errors(struct drm_device *dev);
2753 extern void intel_uncore_fini(struct drm_device *dev);
2754 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2755 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2756 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2757 enum forcewake_domains domains);
2758 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2759 enum forcewake_domains domains);
2760 /* Like above but the caller must manage the uncore.lock itself.
2761 * Must be used with I915_READ_FW and friends.
2763 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2764 enum forcewake_domains domains);
2765 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2766 enum forcewake_domains domains);
2767 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2768 static inline bool intel_vgpu_active(struct drm_device *dev)
2770 return to_i915(dev)->vgpu.active;
2774 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2778 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2781 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2782 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2783 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2786 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2787 uint32_t interrupt_mask,
2788 uint32_t enabled_irq_mask);
2790 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2792 ilk_update_display_irq(dev_priv, bits, bits);
2795 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2797 ilk_update_display_irq(dev_priv, bits, 0);
2799 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2801 uint32_t interrupt_mask,
2802 uint32_t enabled_irq_mask);
2803 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2804 enum pipe pipe, uint32_t bits)
2806 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2808 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2809 enum pipe pipe, uint32_t bits)
2811 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2813 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2814 uint32_t interrupt_mask,
2815 uint32_t enabled_irq_mask);
2817 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2819 ibx_display_interrupt_update(dev_priv, bits, bits);
2822 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2824 ibx_display_interrupt_update(dev_priv, bits, 0);
2829 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv);
2831 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2832 struct drm_file *file_priv);
2833 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2834 struct drm_file *file_priv);
2835 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2836 struct drm_file *file_priv);
2837 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2838 struct drm_file *file_priv);
2839 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2840 struct drm_file *file_priv);
2841 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2842 struct drm_file *file_priv);
2843 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2844 struct drm_i915_gem_request *req);
2845 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2846 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2847 struct drm_i915_gem_execbuffer2 *args,
2848 struct list_head *vmas);
2849 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2850 struct drm_file *file_priv);
2851 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2852 struct drm_file *file_priv);
2853 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2854 struct drm_file *file_priv);
2855 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2856 struct drm_file *file);
2857 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2858 struct drm_file *file);
2859 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2860 struct drm_file *file_priv);
2861 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2864 struct drm_file *file_priv);
2865 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2866 struct drm_file *file_priv);
2867 int i915_gem_init_userptr(struct drm_device *dev);
2868 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2869 struct drm_file *file);
2870 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2871 struct drm_file *file_priv);
2872 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2873 struct drm_file *file_priv);
2874 void i915_gem_load(struct drm_device *dev);
2875 void *i915_gem_object_alloc(struct drm_device *dev);
2876 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2877 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2878 const struct drm_i915_gem_object_ops *ops);
2879 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2881 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2882 struct drm_device *dev, const void *data, size_t size);
2883 void i915_gem_free_object(struct drm_gem_object *obj);
2884 void i915_gem_vma_destroy(struct i915_vma *vma);
2886 /* Flags used by pin/bind&friends. */
2887 #define PIN_MAPPABLE (1<<0)
2888 #define PIN_NONBLOCK (1<<1)
2889 #define PIN_GLOBAL (1<<2)
2890 #define PIN_OFFSET_BIAS (1<<3)
2891 #define PIN_USER (1<<4)
2892 #define PIN_UPDATE (1<<5)
2893 #define PIN_ZONE_4G (1<<6)
2894 #define PIN_HIGH (1<<7)
2895 #define PIN_OFFSET_FIXED (1<<8)
2896 #define PIN_OFFSET_MASK (~4095)
2898 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2899 struct i915_address_space *vm,
2903 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2904 const struct i915_ggtt_view *view,
2908 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2910 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2911 int __must_check i915_vma_unbind(struct i915_vma *vma);
2913 * BEWARE: Do not use the function below unless you can _absolutely_
2914 * _guarantee_ VMA in question is _not in use_ anywhere.
2916 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2917 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2918 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2919 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2921 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2922 int *needs_clflush);
2924 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2926 static inline int __sg_page_count(struct scatterlist *sg)
2928 return sg->length >> PAGE_SHIFT;
2932 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2934 static inline struct page *
2935 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2937 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2940 if (n < obj->get_page.last) {
2941 obj->get_page.sg = obj->pages->sgl;
2942 obj->get_page.last = 0;
2945 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2946 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2947 if (unlikely(sg_is_chain(obj->get_page.sg)))
2948 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2951 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2954 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2956 BUG_ON(obj->pages == NULL);
2957 obj->pages_pin_count++;
2959 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2961 BUG_ON(obj->pages_pin_count == 0);
2962 obj->pages_pin_count--;
2965 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2966 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2967 struct intel_engine_cs *to,
2968 struct drm_i915_gem_request **to_req);
2969 void i915_vma_move_to_active(struct i915_vma *vma,
2970 struct drm_i915_gem_request *req);
2971 int i915_gem_dumb_create(struct drm_file *file_priv,
2972 struct drm_device *dev,
2973 struct drm_mode_create_dumb *args);
2974 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2975 uint32_t handle, uint64_t *offset);
2977 * Returns true if seq1 is later than seq2.
2980 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2982 return (int32_t)(seq1 - seq2) >= 0;
2985 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2986 bool lazy_coherency)
2988 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2989 return i915_seqno_passed(seqno, req->previous_seqno);
2992 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2993 bool lazy_coherency)
2995 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2996 return i915_seqno_passed(seqno, req->seqno);
2999 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3000 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3002 struct drm_i915_gem_request *
3003 i915_gem_find_active_request(struct intel_engine_cs *ring);
3005 bool i915_gem_retire_requests(struct drm_device *dev);
3006 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3007 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3008 bool interruptible);
3010 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3012 return unlikely(atomic_read(&error->reset_counter)
3013 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3016 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3018 return atomic_read(&error->reset_counter) & I915_WEDGED;
3021 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3023 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3026 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3028 return dev_priv->gpu_error.stop_rings == 0 ||
3029 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3032 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3034 return dev_priv->gpu_error.stop_rings == 0 ||
3035 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3038 void i915_gem_reset(struct drm_device *dev);
3039 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3040 int __must_check i915_gem_init(struct drm_device *dev);
3041 int i915_gem_init_rings(struct drm_device *dev);
3042 int __must_check i915_gem_init_hw(struct drm_device *dev);
3043 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3044 void i915_gem_init_swizzling(struct drm_device *dev);
3045 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3046 int __must_check i915_gpu_idle(struct drm_device *dev);
3047 int __must_check i915_gem_suspend(struct drm_device *dev);
3048 void __i915_add_request(struct drm_i915_gem_request *req,
3049 struct drm_i915_gem_object *batch_obj,
3051 #define i915_add_request(req) \
3052 __i915_add_request(req, NULL, true)
3053 #define i915_add_request_no_flush(req) \
3054 __i915_add_request(req, NULL, false)
3055 int __i915_wait_request(struct drm_i915_gem_request *req,
3056 unsigned reset_counter,
3059 struct intel_rps_client *rps);
3060 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3061 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3063 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3066 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3069 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3071 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3073 const struct i915_ggtt_view *view);
3074 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3075 const struct i915_ggtt_view *view);
3076 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3078 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3079 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3082 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3084 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3085 int tiling_mode, bool fenced);
3087 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3088 enum i915_cache_level cache_level);
3090 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3091 struct dma_buf *dma_buf);
3093 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3094 struct drm_gem_object *gem_obj, int flags);
3096 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3097 const struct i915_ggtt_view *view);
3098 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3099 struct i915_address_space *vm);
3101 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3103 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3106 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3107 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3108 const struct i915_ggtt_view *view);
3109 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3110 struct i915_address_space *vm);
3112 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3113 struct i915_address_space *vm);
3115 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3116 struct i915_address_space *vm);
3118 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3119 const struct i915_ggtt_view *view);
3122 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3123 struct i915_address_space *vm);
3125 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3126 const struct i915_ggtt_view *view);
3128 static inline struct i915_vma *
3129 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3131 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3133 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3135 /* Some GGTT VM helpers */
3136 #define i915_obj_to_ggtt(obj) \
3137 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3138 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3140 struct i915_address_space *ggtt =
3141 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3145 static inline struct i915_hw_ppgtt *
3146 i915_vm_to_ppgtt(struct i915_address_space *vm)
3148 WARN_ON(i915_is_ggtt(vm));
3150 return container_of(vm, struct i915_hw_ppgtt, base);
3154 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3156 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3159 static inline unsigned long
3160 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3162 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3165 static inline int __must_check
3166 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3170 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3171 alignment, flags | PIN_GLOBAL);
3175 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3177 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3180 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3181 const struct i915_ggtt_view *view);
3183 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3185 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3188 /* i915_gem_fence.c */
3189 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3190 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3192 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3193 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3195 void i915_gem_restore_fences(struct drm_device *dev);
3197 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3198 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3199 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3201 /* i915_gem_context.c */
3202 int __must_check i915_gem_context_init(struct drm_device *dev);
3203 void i915_gem_context_fini(struct drm_device *dev);
3204 void i915_gem_context_reset(struct drm_device *dev);
3205 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3206 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3207 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3208 int i915_switch_context(struct drm_i915_gem_request *req);
3209 struct intel_context *
3210 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3211 void i915_gem_context_free(struct kref *ctx_ref);
3212 struct drm_i915_gem_object *
3213 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3214 static inline void i915_gem_context_reference(struct intel_context *ctx)
3216 kref_get(&ctx->ref);
3219 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3221 kref_put(&ctx->ref, i915_gem_context_free);
3224 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3226 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3229 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3230 struct drm_file *file);
3231 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3232 struct drm_file *file);
3233 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3234 struct drm_file *file_priv);
3235 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3236 struct drm_file *file_priv);
3238 /* i915_gem_evict.c */
3239 int __must_check i915_gem_evict_something(struct drm_device *dev,
3240 struct i915_address_space *vm,
3243 unsigned cache_level,
3244 unsigned long start,
3247 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3248 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3250 /* belongs in i915_gem_gtt.h */
3251 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3253 if (INTEL_INFO(dev)->gen < 6)
3254 intel_gtt_chipset_flush();
3257 /* i915_gem_stolen.c */
3258 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3259 struct drm_mm_node *node, u64 size,
3260 unsigned alignment);
3261 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3262 struct drm_mm_node *node, u64 size,
3263 unsigned alignment, u64 start,
3265 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3266 struct drm_mm_node *node);
3267 int i915_gem_init_stolen(struct drm_device *dev);
3268 void i915_gem_cleanup_stolen(struct drm_device *dev);
3269 struct drm_i915_gem_object *
3270 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3271 struct drm_i915_gem_object *
3272 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3277 /* i915_gem_shrinker.c */
3278 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3279 unsigned long target,
3281 #define I915_SHRINK_PURGEABLE 0x1
3282 #define I915_SHRINK_UNBOUND 0x2
3283 #define I915_SHRINK_BOUND 0x4
3284 #define I915_SHRINK_ACTIVE 0x8
3285 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3286 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3289 /* i915_gem_tiling.c */
3290 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3292 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3294 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3295 obj->tiling_mode != I915_TILING_NONE;
3298 /* i915_gem_debug.c */
3300 int i915_verify_lists(struct drm_device *dev);
3302 #define i915_verify_lists(dev) 0
3305 /* i915_debugfs.c */
3306 int i915_debugfs_init(struct drm_minor *minor);
3307 void i915_debugfs_cleanup(struct drm_minor *minor);
3308 #ifdef CONFIG_DEBUG_FS
3309 int i915_debugfs_connector_add(struct drm_connector *connector);
3310 void intel_display_crc_init(struct drm_device *dev);
3312 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3314 static inline void intel_display_crc_init(struct drm_device *dev) {}
3317 /* i915_gpu_error.c */
3319 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3320 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3321 const struct i915_error_state_file_priv *error);
3322 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3323 struct drm_i915_private *i915,
3324 size_t count, loff_t pos);
3325 static inline void i915_error_state_buf_release(
3326 struct drm_i915_error_state_buf *eb)
3330 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3331 const char *error_msg);
3332 void i915_error_state_get(struct drm_device *dev,
3333 struct i915_error_state_file_priv *error_priv);
3334 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3335 void i915_destroy_error_state(struct drm_device *dev);
3337 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3338 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3340 /* i915_cmd_parser.c */
3341 int i915_cmd_parser_get_version(void);
3342 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3343 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3344 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3345 int i915_parse_cmds(struct intel_engine_cs *ring,
3346 struct drm_i915_gem_object *batch_obj,
3347 struct drm_i915_gem_object *shadow_batch_obj,
3348 u32 batch_start_offset,
3352 /* i915_suspend.c */
3353 extern int i915_save_state(struct drm_device *dev);
3354 extern int i915_restore_state(struct drm_device *dev);
3357 void i915_setup_sysfs(struct drm_device *dev_priv);
3358 void i915_teardown_sysfs(struct drm_device *dev_priv);
3361 extern int intel_setup_gmbus(struct drm_device *dev);
3362 extern void intel_teardown_gmbus(struct drm_device *dev);
3363 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3366 extern struct i2c_adapter *
3367 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3368 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3369 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3370 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3372 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3374 extern void intel_i2c_reset(struct drm_device *dev);
3377 int intel_bios_init(struct drm_i915_private *dev_priv);
3378 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3380 /* intel_opregion.c */
3382 extern int intel_opregion_setup(struct drm_device *dev);
3383 extern void intel_opregion_init(struct drm_device *dev);
3384 extern void intel_opregion_fini(struct drm_device *dev);
3385 extern void intel_opregion_asle_intr(struct drm_device *dev);
3386 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3388 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3391 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3392 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3393 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3394 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3396 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3401 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3409 extern void intel_register_dsm_handler(void);
3410 extern void intel_unregister_dsm_handler(void);
3412 static inline void intel_register_dsm_handler(void) { return; }
3413 static inline void intel_unregister_dsm_handler(void) { return; }
3414 #endif /* CONFIG_ACPI */
3417 extern void intel_modeset_init_hw(struct drm_device *dev);
3418 extern void intel_modeset_init(struct drm_device *dev);
3419 extern void intel_modeset_gem_init(struct drm_device *dev);
3420 extern void intel_modeset_cleanup(struct drm_device *dev);
3421 extern void intel_connector_unregister(struct intel_connector *);
3422 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3423 extern void intel_display_resume(struct drm_device *dev);
3424 extern void i915_redisable_vga(struct drm_device *dev);
3425 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3426 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3427 extern void intel_init_pch_refclk(struct drm_device *dev);
3428 extern void intel_set_rps(struct drm_device *dev, u8 val);
3429 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3431 extern void intel_detect_pch(struct drm_device *dev);
3432 extern int intel_enable_rc6(const struct drm_device *dev);
3434 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3435 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3436 struct drm_file *file);
3437 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3438 struct drm_file *file);
3441 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3442 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3443 struct intel_overlay_error_state *error);
3445 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3446 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3447 struct drm_device *dev,
3448 struct intel_display_error_state *error);
3450 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3451 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3453 /* intel_sideband.c */
3454 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3455 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3456 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3457 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3458 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3459 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3460 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3461 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3462 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3463 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3464 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3465 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3466 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3467 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3468 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3469 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3470 enum intel_sbi_destination destination);
3471 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3472 enum intel_sbi_destination destination);
3473 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3474 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3476 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3477 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3479 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3480 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3482 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3483 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3484 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3485 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3487 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3488 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3489 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3490 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3492 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3493 * will be implemented using 2 32-bit writes in an arbitrary order with
3494 * an arbitrary delay between them. This can cause the hardware to
3495 * act upon the intermediate value, possibly leading to corruption and
3496 * machine death. You have been warned.
3498 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3499 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3501 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3502 u32 upper, lower, old_upper, loop = 0; \
3503 upper = I915_READ(upper_reg); \
3505 old_upper = upper; \
3506 lower = I915_READ(lower_reg); \
3507 upper = I915_READ(upper_reg); \
3508 } while (upper != old_upper && loop++ < 2); \
3509 (u64)upper << 32 | lower; })
3511 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3512 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3514 #define __raw_read(x, s) \
3515 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3518 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3521 #define __raw_write(x, s) \
3522 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3523 i915_reg_t reg, uint##x##_t val) \
3525 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3540 /* These are untraced mmio-accessors that are only valid to be used inside
3541 * criticial sections inside IRQ handlers where forcewake is explicitly
3543 * Think twice, and think again, before using these.
3544 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3545 * intel_uncore_forcewake_irqunlock().
3547 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3548 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3549 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3551 /* "Broadcast RGB" property */
3552 #define INTEL_BROADCAST_RGB_AUTO 0
3553 #define INTEL_BROADCAST_RGB_FULL 1
3554 #define INTEL_BROADCAST_RGB_LIMITED 2
3556 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3558 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3559 return VLV_VGACNTRL;
3560 else if (INTEL_INFO(dev)->gen >= 5)
3561 return CPU_VGACNTRL;
3566 static inline void __user *to_user_ptr(u64 address)
3568 return (void __user *)(uintptr_t)address;
3571 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3573 unsigned long j = msecs_to_jiffies(m);
3575 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3578 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3580 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3583 static inline unsigned long
3584 timespec_to_jiffies_timeout(const struct timespec *value)
3586 unsigned long j = timespec_to_jiffies(value);
3588 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3592 * If you need to wait X milliseconds between events A and B, but event B
3593 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3594 * when event A happened, then just before event B you call this function and
3595 * pass the timestamp as the first argument, and X as the second argument.
3598 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3600 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3603 * Don't re-read the value of "jiffies" every time since it may change
3604 * behind our back and break the math.
3606 tmp_jiffies = jiffies;
3607 target_jiffies = timestamp_jiffies +
3608 msecs_to_jiffies_timeout(to_wait_ms);
3610 if (time_after(target_jiffies, tmp_jiffies)) {
3611 remaining_jiffies = target_jiffies - tmp_jiffies;
3612 while (remaining_jiffies)
3614 schedule_timeout_uninterruptible(remaining_jiffies);
3618 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3619 struct drm_i915_gem_request *req)
3621 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3622 i915_gem_request_assign(&ring->trace_irq_req, req);