1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150327"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 3
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_crtc(dev, intel_crtc) \
242 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
244 #define for_each_intel_encoder(dev, intel_encoder) \
245 list_for_each_entry(intel_encoder, \
246 &(dev)->mode_config.encoder_list, \
249 #define for_each_intel_connector(dev, intel_connector) \
250 list_for_each_entry(intel_connector, \
251 &dev->mode_config.connector_list, \
255 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
256 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
257 if ((intel_encoder)->base.crtc == (__crtc))
259 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
260 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
261 if ((intel_connector)->base.encoder == (__encoder))
263 #define for_each_power_domain(domain, mask) \
264 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
265 if ((1 << (domain)) & (mask))
267 struct drm_i915_private;
268 struct i915_mm_struct;
269 struct i915_mmu_object;
272 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
273 /* real shared dpll ids must be >= 0 */
274 DPLL_ID_PCH_PLL_A = 0,
275 DPLL_ID_PCH_PLL_B = 1,
280 DPLL_ID_SKL_DPLL1 = 0,
281 DPLL_ID_SKL_DPLL2 = 1,
282 DPLL_ID_SKL_DPLL3 = 2,
284 #define I915_NUM_PLLS 3
286 struct intel_dpll_hw_state {
298 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
299 * lower part of crtl1 and they get shifted into position when writing
300 * the register. This allows us to easily compare the state to share
304 /* HDMI only, 0 when used for DP */
305 uint32_t cfgcr1, cfgcr2;
308 struct intel_shared_dpll_config {
309 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
310 struct intel_dpll_hw_state hw_state;
313 struct intel_shared_dpll {
314 struct intel_shared_dpll_config config;
315 struct intel_shared_dpll_config *new_config;
317 int active; /* count of number of active CRTCs (i.e. DPMS on) */
318 bool on; /* is the PLL actually active? Disabled during modeset */
320 /* should match the index in the dev_priv->shared_dplls array */
321 enum intel_dpll_id id;
322 /* The mode_set hook is optional and should be used together with the
323 * intel_prepare_shared_dpll function. */
324 void (*mode_set)(struct drm_i915_private *dev_priv,
325 struct intel_shared_dpll *pll);
326 void (*enable)(struct drm_i915_private *dev_priv,
327 struct intel_shared_dpll *pll);
328 void (*disable)(struct drm_i915_private *dev_priv,
329 struct intel_shared_dpll *pll);
330 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
331 struct intel_shared_dpll *pll,
332 struct intel_dpll_hw_state *hw_state);
340 /* Used by dp and fdi links */
341 struct intel_link_m_n {
349 void intel_link_compute_m_n(int bpp, int nlanes,
350 int pixel_clock, int link_clock,
351 struct intel_link_m_n *m_n);
353 /* Interface history:
356 * 1.2: Add Power Management
357 * 1.3: Add vblank support
358 * 1.4: Fix cmdbuffer path, add heap destroy
359 * 1.5: Add vblank pipe configuration
360 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
361 * - Support vertical blank on secondary display pipe
363 #define DRIVER_MAJOR 1
364 #define DRIVER_MINOR 6
365 #define DRIVER_PATCHLEVEL 0
367 #define WATCH_LISTS 0
369 struct opregion_header;
370 struct opregion_acpi;
371 struct opregion_swsci;
372 struct opregion_asle;
374 struct intel_opregion {
375 struct opregion_header __iomem *header;
376 struct opregion_acpi __iomem *acpi;
377 struct opregion_swsci __iomem *swsci;
378 u32 swsci_gbda_sub_functions;
379 u32 swsci_sbcb_sub_functions;
380 struct opregion_asle __iomem *asle;
382 u32 __iomem *lid_state;
383 struct work_struct asle_work;
385 #define OPREGION_SIZE (8*1024)
387 struct intel_overlay;
388 struct intel_overlay_error_state;
390 #define I915_FENCE_REG_NONE -1
391 #define I915_MAX_NUM_FENCES 32
392 /* 32 fences + sign bit for FENCE_REG_NONE */
393 #define I915_MAX_NUM_FENCE_BITS 6
395 struct drm_i915_fence_reg {
396 struct list_head lru_list;
397 struct drm_i915_gem_object *obj;
401 struct sdvo_device_mapping {
410 struct intel_display_error_state;
412 struct drm_i915_error_state {
420 /* Generic register state */
428 u32 error; /* gen6+ */
429 u32 err_int; /* gen7 */
430 u32 fault_data0; /* gen8, gen9 */
431 u32 fault_data1; /* gen8, gen9 */
437 u32 extra_instdone[I915_NUM_INSTDONE_REG];
438 u64 fence[I915_MAX_NUM_FENCES];
439 struct intel_overlay_error_state *overlay;
440 struct intel_display_error_state *display;
441 struct drm_i915_error_object *semaphore_obj;
443 struct drm_i915_error_ring {
445 /* Software tracked state */
448 enum intel_ring_hangcheck_action hangcheck_action;
451 /* our own tracking of ring head and tail */
455 u32 semaphore_seqno[I915_NUM_RINGS - 1];
473 u32 rc_psmi; /* sleep state */
474 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
476 struct drm_i915_error_object {
480 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
482 struct drm_i915_error_request {
497 char comm[TASK_COMM_LEN];
498 } ring[I915_NUM_RINGS];
500 struct drm_i915_error_buffer {
507 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
515 } **active_bo, **pinned_bo;
517 u32 *active_bo_count, *pinned_bo_count;
521 struct intel_connector;
522 struct intel_encoder;
523 struct intel_crtc_state;
524 struct intel_initial_plane_config;
529 struct drm_i915_display_funcs {
530 bool (*fbc_enabled)(struct drm_device *dev);
531 void (*enable_fbc)(struct drm_crtc *crtc);
532 void (*disable_fbc)(struct drm_device *dev);
533 int (*get_display_clock_speed)(struct drm_device *dev);
534 int (*get_fifo_size)(struct drm_device *dev, int plane);
536 * find_dpll() - Find the best values for the PLL
537 * @limit: limits for the PLL
538 * @crtc: current CRTC
539 * @target: target frequency in kHz
540 * @refclk: reference clock frequency in kHz
541 * @match_clock: if provided, @best_clock P divider must
542 * match the P divider from @match_clock
543 * used for LVDS downclocking
544 * @best_clock: best PLL values found
546 * Returns true on success, false on failure.
548 bool (*find_dpll)(const struct intel_limit *limit,
549 struct intel_crtc_state *crtc_state,
550 int target, int refclk,
551 struct dpll *match_clock,
552 struct dpll *best_clock);
553 void (*update_wm)(struct drm_crtc *crtc);
554 void (*update_sprite_wm)(struct drm_plane *plane,
555 struct drm_crtc *crtc,
556 uint32_t sprite_width, uint32_t sprite_height,
557 int pixel_size, bool enable, bool scaled);
558 void (*modeset_global_resources)(struct drm_atomic_state *state);
559 /* Returns the active state of the crtc, and if the crtc is active,
560 * fills out the pipe-config with the hw state. */
561 bool (*get_pipe_config)(struct intel_crtc *,
562 struct intel_crtc_state *);
563 void (*get_initial_plane_config)(struct intel_crtc *,
564 struct intel_initial_plane_config *);
565 int (*crtc_compute_clock)(struct intel_crtc *crtc,
566 struct intel_crtc_state *crtc_state);
567 void (*crtc_enable)(struct drm_crtc *crtc);
568 void (*crtc_disable)(struct drm_crtc *crtc);
569 void (*off)(struct drm_crtc *crtc);
570 void (*audio_codec_enable)(struct drm_connector *connector,
571 struct intel_encoder *encoder,
572 struct drm_display_mode *mode);
573 void (*audio_codec_disable)(struct intel_encoder *encoder);
574 void (*fdi_link_train)(struct drm_crtc *crtc);
575 void (*init_clock_gating)(struct drm_device *dev);
576 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
577 struct drm_framebuffer *fb,
578 struct drm_i915_gem_object *obj,
579 struct intel_engine_cs *ring,
581 void (*update_primary_plane)(struct drm_crtc *crtc,
582 struct drm_framebuffer *fb,
584 void (*hpd_irq_setup)(struct drm_device *dev);
585 /* clock updates for mode set */
587 /* render clock increase/decrease */
588 /* display clock increase/decrease */
589 /* pll clock increase/decrease */
591 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
592 uint32_t (*get_backlight)(struct intel_connector *connector);
593 void (*set_backlight)(struct intel_connector *connector,
595 void (*disable_backlight)(struct intel_connector *connector);
596 void (*enable_backlight)(struct intel_connector *connector);
599 enum forcewake_domain_id {
600 FW_DOMAIN_ID_RENDER = 0,
601 FW_DOMAIN_ID_BLITTER,
607 enum forcewake_domains {
608 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
609 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
610 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
611 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
616 struct intel_uncore_funcs {
617 void (*force_wake_get)(struct drm_i915_private *dev_priv,
618 enum forcewake_domains domains);
619 void (*force_wake_put)(struct drm_i915_private *dev_priv,
620 enum forcewake_domains domains);
622 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
623 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
624 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
625 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
627 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
628 uint8_t val, bool trace);
629 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
630 uint16_t val, bool trace);
631 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
632 uint32_t val, bool trace);
633 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
634 uint64_t val, bool trace);
637 struct intel_uncore {
638 spinlock_t lock; /** lock is also taken in irq contexts. */
640 struct intel_uncore_funcs funcs;
643 enum forcewake_domains fw_domains;
645 struct intel_uncore_forcewake_domain {
646 struct drm_i915_private *i915;
647 enum forcewake_domain_id id;
649 struct timer_list timer;
656 } fw_domain[FW_DOMAIN_ID_COUNT];
659 /* Iterate over initialised fw domains */
660 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
661 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
662 (i__) < FW_DOMAIN_ID_COUNT; \
663 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
664 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
666 #define for_each_fw_domain(domain__, dev_priv__, i__) \
667 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
669 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
670 func(is_mobile) sep \
673 func(is_i945gm) sep \
675 func(need_gfx_hws) sep \
677 func(is_pineview) sep \
678 func(is_broadwater) sep \
679 func(is_crestline) sep \
680 func(is_ivybridge) sep \
681 func(is_valleyview) sep \
682 func(is_haswell) sep \
683 func(is_skylake) sep \
684 func(is_preliminary) sep \
686 func(has_pipe_cxsr) sep \
687 func(has_hotplug) sep \
688 func(cursor_needs_physical) sep \
689 func(has_overlay) sep \
690 func(overlay_needs_physical) sep \
691 func(supports_tv) sep \
696 #define DEFINE_FLAG(name) u8 name:1
697 #define SEP_SEMICOLON ;
699 struct intel_device_info {
700 u32 display_mmio_offset;
703 u8 num_sprites[I915_MAX_PIPES];
705 u8 ring_mask; /* Rings supported by the HW */
706 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
707 /* Register offsets for the various display pipes and transcoders */
708 int pipe_offsets[I915_MAX_TRANSCODERS];
709 int trans_offsets[I915_MAX_TRANSCODERS];
710 int palette_offsets[I915_MAX_PIPES];
711 int cursor_offsets[I915_MAX_PIPES];
713 /* Slice/subslice/EU info */
716 u8 subslice_per_slice;
719 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
722 u8 has_subslice_pg:1;
729 enum i915_cache_level {
731 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
732 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
733 caches, eg sampler/render caches, and the
734 large Last-Level-Cache. LLC is coherent with
735 the CPU, but L3 is only visible to the GPU. */
736 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
739 struct i915_ctx_hang_stats {
740 /* This context had batch pending when hang was declared */
741 unsigned batch_pending;
743 /* This context had batch active when hang was declared */
744 unsigned batch_active;
746 /* Time when this context was last blamed for a GPU reset */
747 unsigned long guilty_ts;
749 /* If the contexts causes a second GPU hang within this time,
750 * it is permanently banned from submitting any more work.
752 unsigned long ban_period_seconds;
754 /* This context is banned to submit more work */
758 /* This must match up with the value previously used for execbuf2.rsvd1. */
759 #define DEFAULT_CONTEXT_HANDLE 0
761 * struct intel_context - as the name implies, represents a context.
762 * @ref: reference count.
763 * @user_handle: userspace tracking identity for this context.
764 * @remap_slice: l3 row remapping information.
765 * @file_priv: filp associated with this context (NULL for global default
767 * @hang_stats: information about the role of this context in possible GPU
769 * @vm: virtual memory space used by this context.
770 * @legacy_hw_ctx: render context backing object and whether it is correctly
771 * initialized (legacy ring submission mechanism only).
772 * @link: link in the global list of contexts.
774 * Contexts are memory images used by the hardware to store copies of their
777 struct intel_context {
781 struct drm_i915_file_private *file_priv;
782 struct i915_ctx_hang_stats hang_stats;
783 struct i915_hw_ppgtt *ppgtt;
785 /* Legacy ring buffer submission */
787 struct drm_i915_gem_object *rcs_state;
792 bool rcs_initialized;
794 struct drm_i915_gem_object *state;
795 struct intel_ringbuffer *ringbuf;
797 } engine[I915_NUM_RINGS];
799 struct list_head link;
810 unsigned long uncompressed_size;
813 unsigned int possible_framebuffer_bits;
814 unsigned int busy_bits;
815 struct intel_crtc *crtc;
818 struct drm_mm_node compressed_fb;
819 struct drm_mm_node *compressed_llb;
823 /* Tracks whether the HW is actually enabled, not whether the feature is
827 struct intel_fbc_work {
828 struct delayed_work work;
829 struct drm_crtc *crtc;
830 struct drm_framebuffer *fb;
834 FBC_OK, /* FBC is enabled */
835 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
836 FBC_NO_OUTPUT, /* no outputs enabled to compress */
837 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
838 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
839 FBC_MODE_TOO_LARGE, /* mode too large for compression */
840 FBC_BAD_PLANE, /* fbc not supported on plane */
841 FBC_NOT_TILED, /* buffer not tiled */
842 FBC_MULTIPLE_PIPES, /* more than one pipe active */
844 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
849 * HIGH_RR is the highest eDP panel refresh rate read from EDID
850 * LOW_RR is the lowest eDP panel refresh rate found from EDID
851 * parsing for same resolution.
853 enum drrs_refresh_rate_type {
856 DRRS_MAX_RR, /* RR count */
859 enum drrs_support_type {
860 DRRS_NOT_SUPPORTED = 0,
861 STATIC_DRRS_SUPPORT = 1,
862 SEAMLESS_DRRS_SUPPORT = 2
868 struct delayed_work work;
870 unsigned busy_frontbuffer_bits;
871 enum drrs_refresh_rate_type refresh_rate_type;
872 enum drrs_support_type type;
879 struct intel_dp *enabled;
881 struct delayed_work work;
882 unsigned busy_frontbuffer_bits;
887 PCH_NONE = 0, /* No PCH present */
888 PCH_IBX, /* Ibexpeak PCH */
889 PCH_CPT, /* Cougarpoint PCH */
890 PCH_LPT, /* Lynxpoint PCH */
891 PCH_SPT, /* Sunrisepoint PCH */
895 enum intel_sbi_destination {
900 #define QUIRK_PIPEA_FORCE (1<<0)
901 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
902 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
903 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
904 #define QUIRK_PIPEB_FORCE (1<<4)
905 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
908 struct intel_fbc_work;
911 struct i2c_adapter adapter;
915 struct i2c_algo_bit_data bit_algo;
916 struct drm_i915_private *dev_priv;
919 struct i915_suspend_saved_registers {
922 u32 savePP_ON_DELAYS;
923 u32 savePP_OFF_DELAYS;
929 u32 saveCACHE_MODE_0;
930 u32 saveMI_ARB_STATE;
934 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
935 u32 savePCH_PORT_HOTPLUG;
939 struct vlv_s0ix_state {
946 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
947 u32 media_max_req_count;
948 u32 gfx_max_req_count;
980 /* Display 1 CZ domain */
985 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
987 /* GT SA CZ domain */
994 /* Display 2 CZ domain */
1000 struct intel_rps_ei {
1006 struct intel_gen6_power_mgmt {
1008 * work, interrupts_enabled and pm_iir are protected by
1009 * dev_priv->irq_lock
1011 struct work_struct work;
1012 bool interrupts_enabled;
1015 /* Frequencies are stored in potentially platform dependent multiples.
1016 * In other words, *_freq needs to be multiplied by X to be interesting.
1017 * Soft limits are those which are used for the dynamic reclocking done
1018 * by the driver (raise frequencies under heavy loads, and lower for
1019 * lighter loads). Hard limits are those imposed by the hardware.
1021 * A distinction is made for overclocking, which is never enabled by
1022 * default, and is considered to be above the hard limit if it's
1025 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1026 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1027 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1028 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1029 u8 min_freq; /* AKA RPn. Minimum frequency */
1030 u8 idle_freq; /* Frequency to request when we are idle */
1031 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1032 u8 rp1_freq; /* "less than" RP0 power/freqency */
1033 u8 rp0_freq; /* Non-overclocked max frequency. */
1037 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1040 struct delayed_work delayed_resume_work;
1042 /* manual wa residency calculations */
1043 struct intel_rps_ei up_ei, down_ei;
1046 * Protects RPS/RC6 register access and PCU communication.
1047 * Must be taken after struct_mutex if nested.
1049 struct mutex hw_lock;
1052 /* defined intel_pm.c */
1053 extern spinlock_t mchdev_lock;
1055 struct intel_ilk_power_mgmt {
1063 unsigned long last_time1;
1064 unsigned long chipset_power;
1067 unsigned long gfx_power;
1074 struct drm_i915_private;
1075 struct i915_power_well;
1077 struct i915_power_well_ops {
1079 * Synchronize the well's hw state to match the current sw state, for
1080 * example enable/disable it based on the current refcount. Called
1081 * during driver init and resume time, possibly after first calling
1082 * the enable/disable handlers.
1084 void (*sync_hw)(struct drm_i915_private *dev_priv,
1085 struct i915_power_well *power_well);
1087 * Enable the well and resources that depend on it (for example
1088 * interrupts located on the well). Called after the 0->1 refcount
1091 void (*enable)(struct drm_i915_private *dev_priv,
1092 struct i915_power_well *power_well);
1094 * Disable the well and resources that depend on it. Called after
1095 * the 1->0 refcount transition.
1097 void (*disable)(struct drm_i915_private *dev_priv,
1098 struct i915_power_well *power_well);
1099 /* Returns the hw enabled state. */
1100 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1101 struct i915_power_well *power_well);
1104 /* Power well structure for haswell */
1105 struct i915_power_well {
1108 /* power well enable/disable usage count */
1110 /* cached hw enabled state */
1112 unsigned long domains;
1114 const struct i915_power_well_ops *ops;
1117 struct i915_power_domains {
1119 * Power wells needed for initialization at driver init and suspend
1120 * time are on. They are kept on until after the first modeset.
1124 int power_well_count;
1127 int domain_use_count[POWER_DOMAIN_NUM];
1128 struct i915_power_well *power_wells;
1131 #define MAX_L3_SLICES 2
1132 struct intel_l3_parity {
1133 u32 *remap_info[MAX_L3_SLICES];
1134 struct work_struct error_work;
1138 struct i915_gem_batch_pool {
1139 struct drm_device *dev;
1140 struct list_head cache_list;
1143 struct i915_gem_mm {
1144 /** Memory allocator for GTT stolen memory */
1145 struct drm_mm stolen;
1146 /** List of all objects in gtt_space. Used to restore gtt
1147 * mappings on resume */
1148 struct list_head bound_list;
1150 * List of objects which are not bound to the GTT (thus
1151 * are idle and not used by the GPU) but still have
1152 * (presumably uncached) pages still attached.
1154 struct list_head unbound_list;
1157 * A pool of objects to use as shadow copies of client batch buffers
1158 * when the command parser is enabled. Prevents the client from
1159 * modifying the batch contents after software parsing.
1161 struct i915_gem_batch_pool batch_pool;
1163 /** Usable portion of the GTT for GEM */
1164 unsigned long stolen_base; /* limited to low memory (32-bit) */
1166 /** PPGTT used for aliasing the PPGTT with the GTT */
1167 struct i915_hw_ppgtt *aliasing_ppgtt;
1169 struct notifier_block oom_notifier;
1170 struct shrinker shrinker;
1171 bool shrinker_no_lock_stealing;
1173 /** LRU list of objects with fence regs on them. */
1174 struct list_head fence_list;
1177 * We leave the user IRQ off as much as possible,
1178 * but this means that requests will finish and never
1179 * be retired once the system goes idle. Set a timer to
1180 * fire periodically while the ring is running. When it
1181 * fires, go retire requests.
1183 struct delayed_work retire_work;
1186 * When we detect an idle GPU, we want to turn on
1187 * powersaving features. So once we see that there
1188 * are no more requests outstanding and no more
1189 * arrive within a small period of time, we fire
1190 * off the idle_work.
1192 struct delayed_work idle_work;
1195 * Are we in a non-interruptible section of code like
1201 * Is the GPU currently considered idle, or busy executing userspace
1202 * requests? Whilst idle, we attempt to power down the hardware and
1203 * display clocks. In order to reduce the effect on performance, there
1204 * is a slight delay before we do so.
1208 /* the indicator for dispatch video commands on two BSD rings */
1209 int bsd_ring_dispatch_index;
1211 /** Bit 6 swizzling required for X tiling */
1212 uint32_t bit_6_swizzle_x;
1213 /** Bit 6 swizzling required for Y tiling */
1214 uint32_t bit_6_swizzle_y;
1216 /* accounting, useful for userland debugging */
1217 spinlock_t object_stat_lock;
1218 size_t object_memory;
1222 struct drm_i915_error_state_buf {
1223 struct drm_i915_private *i915;
1232 struct i915_error_state_file_priv {
1233 struct drm_device *dev;
1234 struct drm_i915_error_state *error;
1237 struct i915_gpu_error {
1238 /* For hangcheck timer */
1239 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1240 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1241 /* Hang gpu twice in this window and your context gets banned */
1242 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1244 struct workqueue_struct *hangcheck_wq;
1245 struct delayed_work hangcheck_work;
1247 /* For reset and error_state handling. */
1249 /* Protected by the above dev->gpu_error.lock. */
1250 struct drm_i915_error_state *first_error;
1252 unsigned long missed_irq_rings;
1255 * State variable controlling the reset flow and count
1257 * This is a counter which gets incremented when reset is triggered,
1258 * and again when reset has been handled. So odd values (lowest bit set)
1259 * means that reset is in progress and even values that
1260 * (reset_counter >> 1):th reset was successfully completed.
1262 * If reset is not completed succesfully, the I915_WEDGE bit is
1263 * set meaning that hardware is terminally sour and there is no
1264 * recovery. All waiters on the reset_queue will be woken when
1267 * This counter is used by the wait_seqno code to notice that reset
1268 * event happened and it needs to restart the entire ioctl (since most
1269 * likely the seqno it waited for won't ever signal anytime soon).
1271 * This is important for lock-free wait paths, where no contended lock
1272 * naturally enforces the correct ordering between the bail-out of the
1273 * waiter and the gpu reset work code.
1275 atomic_t reset_counter;
1277 #define I915_RESET_IN_PROGRESS_FLAG 1
1278 #define I915_WEDGED (1 << 31)
1281 * Waitqueue to signal when the reset has completed. Used by clients
1282 * that wait for dev_priv->mm.wedged to settle.
1284 wait_queue_head_t reset_queue;
1286 /* Userspace knobs for gpu hang simulation;
1287 * combines both a ring mask, and extra flags
1290 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1291 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1293 /* For missed irq/seqno simulation. */
1294 unsigned int test_irq_rings;
1296 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1297 bool reload_in_reset;
1300 enum modeset_restore {
1301 MODESET_ON_LID_OPEN,
1306 struct ddi_vbt_port_info {
1308 * This is an index in the HDMI/DVI DDI buffer translation table.
1309 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1310 * populate this field.
1312 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1313 uint8_t hdmi_level_shift;
1315 uint8_t supports_dvi:1;
1316 uint8_t supports_hdmi:1;
1317 uint8_t supports_dp:1;
1320 enum psr_lines_to_wait {
1321 PSR_0_LINES_TO_WAIT = 0,
1323 PSR_4_LINES_TO_WAIT,
1327 struct intel_vbt_data {
1328 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1329 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1332 unsigned int int_tv_support:1;
1333 unsigned int lvds_dither:1;
1334 unsigned int lvds_vbt:1;
1335 unsigned int int_crt_support:1;
1336 unsigned int lvds_use_ssc:1;
1337 unsigned int display_clock_mode:1;
1338 unsigned int fdi_rx_polarity_inverted:1;
1339 unsigned int has_mipi:1;
1341 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1343 enum drrs_support_type drrs_type;
1348 int edp_preemphasis;
1350 bool edp_initialized;
1353 bool edp_low_vswing;
1354 struct edp_power_seq edp_pps;
1358 bool require_aux_wakeup;
1360 enum psr_lines_to_wait lines_to_wait;
1361 int tp1_wakeup_time;
1362 int tp2_tp3_wakeup_time;
1368 bool active_low_pwm;
1369 u8 min_brightness; /* min_brightness/255 of max */
1376 struct mipi_config *config;
1377 struct mipi_pps_data *pps;
1381 u8 *sequence[MIPI_SEQ_MAX];
1387 union child_device_config *child_dev;
1389 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1392 enum intel_ddb_partitioning {
1394 INTEL_DDB_PART_5_6, /* IVB+ */
1397 struct intel_wm_level {
1405 struct ilk_wm_values {
1406 uint32_t wm_pipe[3];
1408 uint32_t wm_lp_spr[3];
1409 uint32_t wm_linetime[3];
1411 enum intel_ddb_partitioning partitioning;
1414 struct vlv_wm_values {
1433 struct skl_ddb_entry {
1434 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1437 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1439 return entry->end - entry->start;
1442 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1443 const struct skl_ddb_entry *e2)
1445 if (e1->start == e2->start && e1->end == e2->end)
1451 struct skl_ddb_allocation {
1452 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1453 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1454 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1457 struct skl_wm_values {
1458 bool dirty[I915_MAX_PIPES];
1459 struct skl_ddb_allocation ddb;
1460 uint32_t wm_linetime[I915_MAX_PIPES];
1461 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1462 uint32_t cursor[I915_MAX_PIPES][8];
1463 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1464 uint32_t cursor_trans[I915_MAX_PIPES];
1467 struct skl_wm_level {
1468 bool plane_en[I915_MAX_PLANES];
1470 uint16_t plane_res_b[I915_MAX_PLANES];
1471 uint8_t plane_res_l[I915_MAX_PLANES];
1472 uint16_t cursor_res_b;
1473 uint8_t cursor_res_l;
1477 * This struct helps tracking the state needed for runtime PM, which puts the
1478 * device in PCI D3 state. Notice that when this happens, nothing on the
1479 * graphics device works, even register access, so we don't get interrupts nor
1482 * Every piece of our code that needs to actually touch the hardware needs to
1483 * either call intel_runtime_pm_get or call intel_display_power_get with the
1484 * appropriate power domain.
1486 * Our driver uses the autosuspend delay feature, which means we'll only really
1487 * suspend if we stay with zero refcount for a certain amount of time. The
1488 * default value is currently very conservative (see intel_runtime_pm_enable), but
1489 * it can be changed with the standard runtime PM files from sysfs.
1491 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1492 * goes back to false exactly before we reenable the IRQs. We use this variable
1493 * to check if someone is trying to enable/disable IRQs while they're supposed
1494 * to be disabled. This shouldn't happen and we'll print some error messages in
1497 * For more, read the Documentation/power/runtime_pm.txt.
1499 struct i915_runtime_pm {
1504 enum intel_pipe_crc_source {
1505 INTEL_PIPE_CRC_SOURCE_NONE,
1506 INTEL_PIPE_CRC_SOURCE_PLANE1,
1507 INTEL_PIPE_CRC_SOURCE_PLANE2,
1508 INTEL_PIPE_CRC_SOURCE_PF,
1509 INTEL_PIPE_CRC_SOURCE_PIPE,
1510 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1511 INTEL_PIPE_CRC_SOURCE_TV,
1512 INTEL_PIPE_CRC_SOURCE_DP_B,
1513 INTEL_PIPE_CRC_SOURCE_DP_C,
1514 INTEL_PIPE_CRC_SOURCE_DP_D,
1515 INTEL_PIPE_CRC_SOURCE_AUTO,
1516 INTEL_PIPE_CRC_SOURCE_MAX,
1519 struct intel_pipe_crc_entry {
1524 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1525 struct intel_pipe_crc {
1527 bool opened; /* exclusive access to the result file */
1528 struct intel_pipe_crc_entry *entries;
1529 enum intel_pipe_crc_source source;
1531 wait_queue_head_t wq;
1534 struct i915_frontbuffer_tracking {
1538 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1545 struct i915_wa_reg {
1548 /* bitmask representing WA bits */
1552 #define I915_MAX_WA_REGS 16
1554 struct i915_workarounds {
1555 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1559 struct i915_virtual_gpu {
1563 struct drm_i915_private {
1564 struct drm_device *dev;
1565 struct kmem_cache *slab;
1567 const struct intel_device_info info;
1569 int relative_constants_mode;
1573 struct intel_uncore uncore;
1575 struct i915_virtual_gpu vgpu;
1577 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1579 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1580 * controller on different i2c buses. */
1581 struct mutex gmbus_mutex;
1584 * Base address of the gmbus and gpio block.
1586 uint32_t gpio_mmio_base;
1588 /* MMIO base address for MIPI regs */
1589 uint32_t mipi_mmio_base;
1591 wait_queue_head_t gmbus_wait_queue;
1593 struct pci_dev *bridge_dev;
1594 struct intel_engine_cs ring[I915_NUM_RINGS];
1595 struct drm_i915_gem_object *semaphore_obj;
1596 uint32_t last_seqno, next_seqno;
1598 struct drm_dma_handle *status_page_dmah;
1599 struct resource mch_res;
1601 /* protects the irq masks */
1602 spinlock_t irq_lock;
1604 /* protects the mmio flip data */
1605 spinlock_t mmio_flip_lock;
1607 bool display_irqs_enabled;
1609 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1610 struct pm_qos_request pm_qos;
1612 /* DPIO indirect register protection */
1613 struct mutex dpio_lock;
1615 /** Cached value of IMR to avoid reads in updating the bitfield */
1618 u32 de_irq_mask[I915_MAX_PIPES];
1623 u32 pipestat_irq_mask[I915_MAX_PIPES];
1625 struct work_struct hotplug_work;
1627 unsigned long hpd_last_jiffies;
1632 HPD_MARK_DISABLED = 2
1634 } hpd_stats[HPD_NUM_PINS];
1636 struct delayed_work hotplug_reenable_work;
1638 struct i915_fbc fbc;
1639 struct i915_drrs drrs;
1640 struct intel_opregion opregion;
1641 struct intel_vbt_data vbt;
1643 bool preserve_bios_swizzle;
1646 struct intel_overlay *overlay;
1648 /* backlight registers and fields in struct intel_panel */
1649 struct mutex backlight_lock;
1652 bool no_aux_handshake;
1654 /* protects panel power sequencer state */
1655 struct mutex pps_mutex;
1657 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1658 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1659 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1661 unsigned int fsb_freq, mem_freq, is_ddr3;
1662 unsigned int vlv_cdclk_freq;
1663 unsigned int hpll_freq;
1666 * wq - Driver workqueue for GEM.
1668 * NOTE: Work items scheduled here are not allowed to grab any modeset
1669 * locks, for otherwise the flushing done in the pageflip code will
1670 * result in deadlocks.
1672 struct workqueue_struct *wq;
1674 /* Display functions */
1675 struct drm_i915_display_funcs display;
1677 /* PCH chipset type */
1678 enum intel_pch pch_type;
1679 unsigned short pch_id;
1681 unsigned long quirks;
1683 enum modeset_restore modeset_restore;
1684 struct mutex modeset_restore_lock;
1686 struct list_head vm_list; /* Global list of all address spaces */
1687 struct i915_gtt gtt; /* VM representing the global address space */
1689 struct i915_gem_mm mm;
1690 DECLARE_HASHTABLE(mm_structs, 7);
1691 struct mutex mm_lock;
1693 /* Kernel Modesetting */
1695 struct sdvo_device_mapping sdvo_mappings[2];
1697 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1698 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1699 wait_queue_head_t pending_flip_queue;
1701 #ifdef CONFIG_DEBUG_FS
1702 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1705 int num_shared_dpll;
1706 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1707 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1709 struct i915_workarounds workarounds;
1711 /* Reclocking support */
1712 bool render_reclock_avail;
1713 bool lvds_downclock_avail;
1714 /* indicates the reduced downclock for LVDS*/
1717 struct i915_frontbuffer_tracking fb_tracking;
1721 bool mchbar_need_disable;
1723 struct intel_l3_parity l3_parity;
1725 /* Cannot be determined by PCIID. You must always read a register. */
1728 /* gen6+ rps state */
1729 struct intel_gen6_power_mgmt rps;
1731 /* ilk-only ips/rps state. Everything in here is protected by the global
1732 * mchdev_lock in intel_pm.c */
1733 struct intel_ilk_power_mgmt ips;
1735 struct i915_power_domains power_domains;
1737 struct i915_psr psr;
1739 struct i915_gpu_error gpu_error;
1741 struct drm_i915_gem_object *vlv_pctx;
1743 #ifdef CONFIG_DRM_I915_FBDEV
1744 /* list of fbdev register on this device */
1745 struct intel_fbdev *fbdev;
1746 struct work_struct fbdev_suspend_work;
1749 struct drm_property *broadcast_rgb_property;
1750 struct drm_property *force_audio_property;
1752 /* hda/i915 audio component */
1753 bool audio_component_registered;
1755 uint32_t hw_context_size;
1756 struct list_head context_list;
1761 struct i915_suspend_saved_registers regfile;
1762 struct vlv_s0ix_state vlv_s0ix_state;
1766 * Raw watermark latency values:
1767 * in 0.1us units for WM0,
1768 * in 0.5us units for WM1+.
1771 uint16_t pri_latency[5];
1773 uint16_t spr_latency[5];
1775 uint16_t cur_latency[5];
1777 * Raw watermark memory latency values
1778 * for SKL for all 8 levels
1781 uint16_t skl_latency[8];
1784 * The skl_wm_values structure is a bit too big for stack
1785 * allocation, so we keep the staging struct where we store
1786 * intermediate results here instead.
1788 struct skl_wm_values skl_results;
1790 /* current hardware state */
1792 struct ilk_wm_values hw;
1793 struct skl_wm_values skl_hw;
1794 struct vlv_wm_values vlv;
1798 struct i915_runtime_pm pm;
1800 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1801 u32 long_hpd_port_mask;
1802 u32 short_hpd_port_mask;
1803 struct work_struct dig_port_work;
1806 * if we get a HPD irq from DP and a HPD irq from non-DP
1807 * the non-DP HPD could block the workqueue on a mode config
1808 * mutex getting, that userspace may have taken. However
1809 * userspace is waiting on the DP workqueue to run which is
1810 * blocked behind the non-DP one.
1812 struct workqueue_struct *dp_wq;
1814 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1816 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1817 struct intel_engine_cs *ring,
1818 struct intel_context *ctx,
1819 struct drm_i915_gem_execbuffer2 *args,
1820 struct list_head *vmas,
1821 struct drm_i915_gem_object *batch_obj,
1822 u64 exec_start, u32 flags);
1823 int (*init_rings)(struct drm_device *dev);
1824 void (*cleanup_ring)(struct intel_engine_cs *ring);
1825 void (*stop_ring)(struct intel_engine_cs *ring);
1828 uint32_t request_uniq;
1831 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1832 * will be rejected. Instead look for a better place.
1836 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1838 return dev->dev_private;
1841 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1843 return to_i915(dev_get_drvdata(dev));
1846 /* Iterate over initialised rings */
1847 #define for_each_ring(ring__, dev_priv__, i__) \
1848 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1849 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1851 enum hdmi_force_audio {
1852 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1853 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1854 HDMI_AUDIO_AUTO, /* trust EDID */
1855 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1858 #define I915_GTT_OFFSET_NONE ((u32)-1)
1860 struct drm_i915_gem_object_ops {
1861 /* Interface between the GEM object and its backing storage.
1862 * get_pages() is called once prior to the use of the associated set
1863 * of pages before to binding them into the GTT, and put_pages() is
1864 * called after we no longer need them. As we expect there to be
1865 * associated cost with migrating pages between the backing storage
1866 * and making them available for the GPU (e.g. clflush), we may hold
1867 * onto the pages after they are no longer referenced by the GPU
1868 * in case they may be used again shortly (for example migrating the
1869 * pages to a different memory domain within the GTT). put_pages()
1870 * will therefore most likely be called when the object itself is
1871 * being released or under memory pressure (where we attempt to
1872 * reap pages for the shrinker).
1874 int (*get_pages)(struct drm_i915_gem_object *);
1875 void (*put_pages)(struct drm_i915_gem_object *);
1876 int (*dmabuf_export)(struct drm_i915_gem_object *);
1877 void (*release)(struct drm_i915_gem_object *);
1881 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1882 * considered to be the frontbuffer for the given plane interface-vise. This
1883 * doesn't mean that the hw necessarily already scans it out, but that any
1884 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1886 * We have one bit per pipe and per scanout plane type.
1888 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1889 #define INTEL_FRONTBUFFER_BITS \
1890 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1891 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1892 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1893 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1894 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1895 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1896 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1897 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1898 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1899 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1900 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1902 struct drm_i915_gem_object {
1903 struct drm_gem_object base;
1905 const struct drm_i915_gem_object_ops *ops;
1907 /** List of VMAs backed by this object */
1908 struct list_head vma_list;
1910 /** Stolen memory for this object, instead of being backed by shmem. */
1911 struct drm_mm_node *stolen;
1912 struct list_head global_list;
1914 struct list_head ring_list;
1915 /** Used in execbuf to temporarily hold a ref */
1916 struct list_head obj_exec_link;
1918 struct list_head batch_pool_list;
1921 * This is set if the object is on the active lists (has pending
1922 * rendering and so a non-zero seqno), and is not set if it i s on
1923 * inactive (ready to be unbound) list.
1925 unsigned int active:1;
1928 * This is set if the object has been written to since last bound
1931 unsigned int dirty:1;
1934 * Fence register bits (if any) for this object. Will be set
1935 * as needed when mapped into the GTT.
1936 * Protected by dev->struct_mutex.
1938 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1941 * Advice: are the backing pages purgeable?
1943 unsigned int madv:2;
1946 * Current tiling mode for the object.
1948 unsigned int tiling_mode:2;
1950 * Whether the tiling parameters for the currently associated fence
1951 * register have changed. Note that for the purposes of tracking
1952 * tiling changes we also treat the unfenced register, the register
1953 * slot that the object occupies whilst it executes a fenced
1954 * command (such as BLT on gen2/3), as a "fence".
1956 unsigned int fence_dirty:1;
1959 * Is the object at the current location in the gtt mappable and
1960 * fenceable? Used to avoid costly recalculations.
1962 unsigned int map_and_fenceable:1;
1965 * Whether the current gtt mapping needs to be mappable (and isn't just
1966 * mappable by accident). Track pin and fault separate for a more
1967 * accurate mappable working set.
1969 unsigned int fault_mappable:1;
1970 unsigned int pin_mappable:1;
1971 unsigned int pin_display:1;
1974 * Is the object to be mapped as read-only to the GPU
1975 * Only honoured if hardware has relevant pte bit
1977 unsigned long gt_ro:1;
1978 unsigned int cache_level:3;
1979 unsigned int cache_dirty:1;
1981 unsigned int has_dma_mapping:1;
1983 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1985 struct sg_table *pages;
1986 int pages_pin_count;
1988 /* prime dma-buf support */
1989 void *dma_buf_vmapping;
1992 /** Breadcrumb of last rendering to the buffer. */
1993 struct drm_i915_gem_request *last_read_req;
1994 struct drm_i915_gem_request *last_write_req;
1995 /** Breadcrumb of last fenced GPU access to the buffer. */
1996 struct drm_i915_gem_request *last_fenced_req;
1998 /** Current tiling stride for the object, if it's tiled. */
2001 /** References from framebuffers, locks out tiling changes. */
2002 unsigned long framebuffer_references;
2004 /** Record of address bit 17 of each page at last unbind. */
2005 unsigned long *bit_17;
2008 /** for phy allocated objects */
2009 struct drm_dma_handle *phys_handle;
2011 struct i915_gem_userptr {
2013 unsigned read_only :1;
2014 unsigned workers :4;
2015 #define I915_GEM_USERPTR_MAX_WORKERS 15
2017 struct i915_mm_struct *mm;
2018 struct i915_mmu_object *mmu_object;
2019 struct work_struct *work;
2023 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2025 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2026 struct drm_i915_gem_object *new,
2027 unsigned frontbuffer_bits);
2030 * Request queue structure.
2032 * The request queue allows us to note sequence numbers that have been emitted
2033 * and may be associated with active buffers to be retired.
2035 * By keeping this list, we can avoid having to do questionable sequence
2036 * number comparisons on buffer last_read|write_seqno. It also allows an
2037 * emission time to be associated with the request for tracking how far ahead
2038 * of the GPU the submission is.
2040 * The requests are reference counted, so upon creation they should have an
2041 * initial reference taken using kref_init
2043 struct drm_i915_gem_request {
2046 /** On Which ring this request was generated */
2047 struct intel_engine_cs *ring;
2049 /** GEM sequence number associated with this request. */
2052 /** Position in the ringbuffer of the start of the request */
2056 * Position in the ringbuffer of the start of the postfix.
2057 * This is required to calculate the maximum available ringbuffer
2058 * space without overwriting the postfix.
2062 /** Position in the ringbuffer of the end of the whole request */
2066 * Context and ring buffer related to this request
2067 * Contexts are refcounted, so when this request is associated with a
2068 * context, we must increment the context's refcount, to guarantee that
2069 * it persists while any request is linked to it. Requests themselves
2070 * are also refcounted, so the request will only be freed when the last
2071 * reference to it is dismissed, and the code in
2072 * i915_gem_request_free() will then decrement the refcount on the
2075 struct intel_context *ctx;
2076 struct intel_ringbuffer *ringbuf;
2078 /** Batch buffer related to this request if any */
2079 struct drm_i915_gem_object *batch_obj;
2081 /** Time at which this request was emitted, in jiffies. */
2082 unsigned long emitted_jiffies;
2084 /** global list entry for this request */
2085 struct list_head list;
2087 struct drm_i915_file_private *file_priv;
2088 /** file_priv list entry for this request */
2089 struct list_head client_list;
2091 /** process identifier submitting this request */
2097 * The ELSP only accepts two elements at a time, so we queue
2098 * context/tail pairs on a given queue (ring->execlist_queue) until the
2099 * hardware is available. The queue serves a double purpose: we also use
2100 * it to keep track of the up to 2 contexts currently in the hardware
2101 * (usually one in execution and the other queued up by the GPU): We
2102 * only remove elements from the head of the queue when the hardware
2103 * informs us that an element has been completed.
2105 * All accesses to the queue are mediated by a spinlock
2106 * (ring->execlist_lock).
2109 /** Execlist link in the submission queue.*/
2110 struct list_head execlist_link;
2112 /** Execlists no. of times this request has been sent to the ELSP */
2117 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2118 struct intel_context *ctx);
2119 void i915_gem_request_free(struct kref *req_ref);
2121 static inline uint32_t
2122 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2124 return req ? req->seqno : 0;
2127 static inline struct intel_engine_cs *
2128 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2130 return req ? req->ring : NULL;
2134 i915_gem_request_reference(struct drm_i915_gem_request *req)
2136 kref_get(&req->ref);
2140 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2142 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2143 kref_put(&req->ref, i915_gem_request_free);
2147 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2149 if (req && !atomic_add_unless(&req->ref.refcount, -1, 1)) {
2150 struct drm_device *dev = req->ring->dev;
2152 mutex_lock(&dev->struct_mutex);
2153 if (likely(atomic_dec_and_test(&req->ref.refcount)))
2154 i915_gem_request_free(&req->ref);
2155 mutex_unlock(&dev->struct_mutex);
2159 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2160 struct drm_i915_gem_request *src)
2163 i915_gem_request_reference(src);
2166 i915_gem_request_unreference(*pdst);
2172 * XXX: i915_gem_request_completed should be here but currently needs the
2173 * definition of i915_seqno_passed() which is below. It will be moved in
2174 * a later patch when the call to i915_seqno_passed() is obsoleted...
2177 struct drm_i915_file_private {
2178 struct drm_i915_private *dev_priv;
2179 struct drm_file *file;
2183 struct list_head request_list;
2184 struct delayed_work idle_work;
2186 struct idr context_idr;
2188 atomic_t rps_wait_boost;
2189 struct intel_engine_cs *bsd_ring;
2193 * A command that requires special handling by the command parser.
2195 struct drm_i915_cmd_descriptor {
2197 * Flags describing how the command parser processes the command.
2199 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2200 * a length mask if not set
2201 * CMD_DESC_SKIP: The command is allowed but does not follow the
2202 * standard length encoding for the opcode range in
2204 * CMD_DESC_REJECT: The command is never allowed
2205 * CMD_DESC_REGISTER: The command should be checked against the
2206 * register whitelist for the appropriate ring
2207 * CMD_DESC_MASTER: The command is allowed if the submitting process
2211 #define CMD_DESC_FIXED (1<<0)
2212 #define CMD_DESC_SKIP (1<<1)
2213 #define CMD_DESC_REJECT (1<<2)
2214 #define CMD_DESC_REGISTER (1<<3)
2215 #define CMD_DESC_BITMASK (1<<4)
2216 #define CMD_DESC_MASTER (1<<5)
2219 * The command's unique identification bits and the bitmask to get them.
2220 * This isn't strictly the opcode field as defined in the spec and may
2221 * also include type, subtype, and/or subop fields.
2229 * The command's length. The command is either fixed length (i.e. does
2230 * not include a length field) or has a length field mask. The flag
2231 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2232 * a length mask. All command entries in a command table must include
2233 * length information.
2241 * Describes where to find a register address in the command to check
2242 * against the ring's register whitelist. Only valid if flags has the
2243 * CMD_DESC_REGISTER bit set.
2250 #define MAX_CMD_DESC_BITMASKS 3
2252 * Describes command checks where a particular dword is masked and
2253 * compared against an expected value. If the command does not match
2254 * the expected value, the parser rejects it. Only valid if flags has
2255 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2258 * If the check specifies a non-zero condition_mask then the parser
2259 * only performs the check when the bits specified by condition_mask
2266 u32 condition_offset;
2268 } bits[MAX_CMD_DESC_BITMASKS];
2272 * A table of commands requiring special handling by the command parser.
2274 * Each ring has an array of tables. Each table consists of an array of command
2275 * descriptors, which must be sorted with command opcodes in ascending order.
2277 struct drm_i915_cmd_table {
2278 const struct drm_i915_cmd_descriptor *table;
2282 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2283 #define __I915__(p) ({ \
2284 struct drm_i915_private *__p; \
2285 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2286 __p = (struct drm_i915_private *)p; \
2287 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2288 __p = to_i915((struct drm_device *)p); \
2293 #define INTEL_INFO(p) (&__I915__(p)->info)
2294 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2295 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2297 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2298 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2299 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2300 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2301 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2302 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2303 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2304 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2305 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2306 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2307 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2308 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2309 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2310 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2311 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2312 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2313 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2314 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2315 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2316 INTEL_DEVID(dev) == 0x0152 || \
2317 INTEL_DEVID(dev) == 0x015a)
2318 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2319 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2320 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2321 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2322 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2323 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2324 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2325 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2326 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2327 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2328 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2329 (INTEL_DEVID(dev) & 0xf) == 0xe))
2330 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2331 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2332 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2333 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2334 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2335 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2336 /* ULX machines are also considered ULT. */
2337 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2338 INTEL_DEVID(dev) == 0x0A1E)
2339 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2341 #define SKL_REVID_A0 (0x0)
2342 #define SKL_REVID_B0 (0x1)
2343 #define SKL_REVID_C0 (0x2)
2344 #define SKL_REVID_D0 (0x3)
2345 #define SKL_REVID_E0 (0x4)
2348 * The genX designation typically refers to the render engine, so render
2349 * capability related checks should use IS_GEN, while display and other checks
2350 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2353 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2354 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2355 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2356 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2357 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2358 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2359 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2360 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2362 #define RENDER_RING (1<<RCS)
2363 #define BSD_RING (1<<VCS)
2364 #define BLT_RING (1<<BCS)
2365 #define VEBOX_RING (1<<VECS)
2366 #define BSD2_RING (1<<VCS2)
2367 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2368 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2369 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2370 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2371 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2372 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2373 __I915__(dev)->ellc_size)
2374 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2376 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2377 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2378 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2379 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2381 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2382 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2384 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2385 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2387 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2388 * even when in MSI mode. This results in spurious interrupt warnings if the
2389 * legacy irq no. is shared with another device. The kernel then disables that
2390 * interrupt source and so prevents the other device from working properly.
2392 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2393 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2395 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2396 * rows, which changed the alignment requirements and fence programming.
2398 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2400 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2401 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2402 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2403 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2404 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2406 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2407 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2408 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2410 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2412 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2413 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2414 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2415 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2417 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2418 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2419 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2420 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2422 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2423 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2424 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2425 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2426 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2427 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2428 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2429 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2431 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2432 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2433 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2434 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2435 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2436 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2437 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2439 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2441 /* DPF == dynamic parity feature */
2442 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2443 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2445 #define GT_FREQUENCY_MULTIPLIER 50
2446 #define GEN9_FREQ_SCALER 3
2448 #include "i915_trace.h"
2450 extern const struct drm_ioctl_desc i915_ioctls[];
2451 extern int i915_max_ioctl;
2453 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2454 extern int i915_resume_legacy(struct drm_device *dev);
2457 struct i915_params {
2459 int panel_ignore_lid;
2461 unsigned int lvds_downclock;
2462 int lvds_channel_mode;
2464 int vbt_sdvo_panel_type;
2468 int enable_execlists;
2470 unsigned int preliminary_hw_support;
2471 int disable_power_well;
2473 int invert_brightness;
2474 int enable_cmd_parser;
2475 /* leave bools at the end to not create holes */
2476 bool enable_hangcheck;
2478 bool prefault_disable;
2479 bool load_detect_test;
2481 bool disable_display;
2482 bool disable_vtd_wa;
2485 bool verbose_state_checks;
2486 bool nuclear_pageflip;
2488 extern struct i915_params i915 __read_mostly;
2491 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2492 extern int i915_driver_unload(struct drm_device *);
2493 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2494 extern void i915_driver_lastclose(struct drm_device * dev);
2495 extern void i915_driver_preclose(struct drm_device *dev,
2496 struct drm_file *file);
2497 extern void i915_driver_postclose(struct drm_device *dev,
2498 struct drm_file *file);
2499 extern int i915_driver_device_is_agp(struct drm_device * dev);
2500 #ifdef CONFIG_COMPAT
2501 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2504 extern int intel_gpu_reset(struct drm_device *dev);
2505 extern int i915_reset(struct drm_device *dev);
2506 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2507 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2508 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2509 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2510 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2511 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2514 void i915_queue_hangcheck(struct drm_device *dev);
2516 void i915_handle_error(struct drm_device *dev, bool wedged,
2517 const char *fmt, ...);
2519 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2520 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2521 int intel_irq_install(struct drm_i915_private *dev_priv);
2522 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2524 extern void intel_uncore_sanitize(struct drm_device *dev);
2525 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2526 bool restore_forcewake);
2527 extern void intel_uncore_init(struct drm_device *dev);
2528 extern void intel_uncore_check_errors(struct drm_device *dev);
2529 extern void intel_uncore_fini(struct drm_device *dev);
2530 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2531 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2532 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2533 enum forcewake_domains domains);
2534 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2535 enum forcewake_domains domains);
2536 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2537 static inline bool intel_vgpu_active(struct drm_device *dev)
2539 return to_i915(dev)->vgpu.active;
2543 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2547 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2550 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2551 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2553 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2555 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2556 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2557 uint32_t interrupt_mask,
2558 uint32_t enabled_irq_mask);
2559 #define ibx_enable_display_interrupt(dev_priv, bits) \
2560 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2561 #define ibx_disable_display_interrupt(dev_priv, bits) \
2562 ibx_display_interrupt_update((dev_priv), (bits), 0)
2565 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2566 struct drm_file *file_priv);
2567 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2568 struct drm_file *file_priv);
2569 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2570 struct drm_file *file_priv);
2571 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2572 struct drm_file *file_priv);
2573 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2574 struct drm_file *file_priv);
2575 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2576 struct drm_file *file_priv);
2577 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2578 struct drm_file *file_priv);
2579 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2580 struct intel_engine_cs *ring);
2581 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2582 struct drm_file *file,
2583 struct intel_engine_cs *ring,
2584 struct drm_i915_gem_object *obj);
2585 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2586 struct drm_file *file,
2587 struct intel_engine_cs *ring,
2588 struct intel_context *ctx,
2589 struct drm_i915_gem_execbuffer2 *args,
2590 struct list_head *vmas,
2591 struct drm_i915_gem_object *batch_obj,
2592 u64 exec_start, u32 flags);
2593 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2594 struct drm_file *file_priv);
2595 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2596 struct drm_file *file_priv);
2597 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2598 struct drm_file *file_priv);
2599 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2600 struct drm_file *file);
2601 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2602 struct drm_file *file);
2603 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2604 struct drm_file *file_priv);
2605 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2606 struct drm_file *file_priv);
2607 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2608 struct drm_file *file_priv);
2609 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2610 struct drm_file *file_priv);
2611 int i915_gem_init_userptr(struct drm_device *dev);
2612 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2613 struct drm_file *file);
2614 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2615 struct drm_file *file_priv);
2616 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2617 struct drm_file *file_priv);
2618 void i915_gem_load(struct drm_device *dev);
2619 void *i915_gem_object_alloc(struct drm_device *dev);
2620 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2621 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2622 const struct drm_i915_gem_object_ops *ops);
2623 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2625 void i915_init_vm(struct drm_i915_private *dev_priv,
2626 struct i915_address_space *vm);
2627 void i915_gem_free_object(struct drm_gem_object *obj);
2628 void i915_gem_vma_destroy(struct i915_vma *vma);
2630 #define PIN_MAPPABLE 0x1
2631 #define PIN_NONBLOCK 0x2
2632 #define PIN_GLOBAL 0x4
2633 #define PIN_OFFSET_BIAS 0x8
2634 #define PIN_OFFSET_MASK (~4095)
2636 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2637 struct i915_address_space *vm,
2641 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2642 const struct i915_ggtt_view *view,
2646 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2648 int __must_check i915_vma_unbind(struct i915_vma *vma);
2649 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2650 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2651 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2653 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2654 int *needs_clflush);
2656 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2657 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2659 struct sg_page_iter sg_iter;
2661 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2662 return sg_page_iter_page(&sg_iter);
2666 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2668 BUG_ON(obj->pages == NULL);
2669 obj->pages_pin_count++;
2671 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2673 BUG_ON(obj->pages_pin_count == 0);
2674 obj->pages_pin_count--;
2677 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2678 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2679 struct intel_engine_cs *to);
2680 void i915_vma_move_to_active(struct i915_vma *vma,
2681 struct intel_engine_cs *ring);
2682 int i915_gem_dumb_create(struct drm_file *file_priv,
2683 struct drm_device *dev,
2684 struct drm_mode_create_dumb *args);
2685 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2686 uint32_t handle, uint64_t *offset);
2688 * Returns true if seq1 is later than seq2.
2691 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2693 return (int32_t)(seq1 - seq2) >= 0;
2696 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2697 bool lazy_coherency)
2701 BUG_ON(req == NULL);
2703 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2705 return i915_seqno_passed(seqno, req->seqno);
2708 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2709 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2710 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2711 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2713 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2714 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2716 struct drm_i915_gem_request *
2717 i915_gem_find_active_request(struct intel_engine_cs *ring);
2719 bool i915_gem_retire_requests(struct drm_device *dev);
2720 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2721 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2722 bool interruptible);
2723 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2725 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2727 return unlikely(atomic_read(&error->reset_counter)
2728 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2731 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2733 return atomic_read(&error->reset_counter) & I915_WEDGED;
2736 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2738 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2741 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2743 return dev_priv->gpu_error.stop_rings == 0 ||
2744 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2747 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2749 return dev_priv->gpu_error.stop_rings == 0 ||
2750 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2753 void i915_gem_reset(struct drm_device *dev);
2754 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2755 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2756 int __must_check i915_gem_init(struct drm_device *dev);
2757 int i915_gem_init_rings(struct drm_device *dev);
2758 int __must_check i915_gem_init_hw(struct drm_device *dev);
2759 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2760 void i915_gem_init_swizzling(struct drm_device *dev);
2761 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2762 int __must_check i915_gpu_idle(struct drm_device *dev);
2763 int __must_check i915_gem_suspend(struct drm_device *dev);
2764 int __i915_add_request(struct intel_engine_cs *ring,
2765 struct drm_file *file,
2766 struct drm_i915_gem_object *batch_obj);
2767 #define i915_add_request(ring) \
2768 __i915_add_request(ring, NULL, NULL)
2769 int __i915_wait_request(struct drm_i915_gem_request *req,
2770 unsigned reset_counter,
2773 struct drm_i915_file_private *file_priv);
2774 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2775 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2777 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2780 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2782 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2784 struct intel_engine_cs *pipelined,
2785 const struct i915_ggtt_view *view);
2786 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2787 const struct i915_ggtt_view *view);
2788 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2790 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2791 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2794 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2796 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2797 int tiling_mode, bool fenced);
2799 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2800 enum i915_cache_level cache_level);
2802 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2803 struct dma_buf *dma_buf);
2805 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2806 struct drm_gem_object *gem_obj, int flags);
2808 void i915_gem_restore_fences(struct drm_device *dev);
2811 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2812 const struct i915_ggtt_view *view);
2814 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2815 struct i915_address_space *vm);
2816 static inline unsigned long
2817 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2819 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2822 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2823 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2824 const struct i915_ggtt_view *view);
2825 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2826 struct i915_address_space *vm);
2828 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2829 struct i915_address_space *vm);
2831 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2832 struct i915_address_space *vm);
2834 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2835 const struct i915_ggtt_view *view);
2838 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2839 struct i915_address_space *vm);
2841 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2842 const struct i915_ggtt_view *view);
2844 static inline struct i915_vma *
2845 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2847 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2849 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2851 /* Some GGTT VM helpers */
2852 #define i915_obj_to_ggtt(obj) \
2853 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2854 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2856 struct i915_address_space *ggtt =
2857 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2861 static inline struct i915_hw_ppgtt *
2862 i915_vm_to_ppgtt(struct i915_address_space *vm)
2864 WARN_ON(i915_is_ggtt(vm));
2866 return container_of(vm, struct i915_hw_ppgtt, base);
2870 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2872 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2875 static inline unsigned long
2876 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2878 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2881 static inline int __must_check
2882 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2886 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2887 alignment, flags | PIN_GLOBAL);
2891 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2893 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2896 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
2897 const struct i915_ggtt_view *view);
2899 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
2901 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
2904 /* i915_gem_context.c */
2905 int __must_check i915_gem_context_init(struct drm_device *dev);
2906 void i915_gem_context_fini(struct drm_device *dev);
2907 void i915_gem_context_reset(struct drm_device *dev);
2908 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2909 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2910 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2911 int i915_switch_context(struct intel_engine_cs *ring,
2912 struct intel_context *to);
2913 struct intel_context *
2914 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2915 void i915_gem_context_free(struct kref *ctx_ref);
2916 struct drm_i915_gem_object *
2917 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2918 static inline void i915_gem_context_reference(struct intel_context *ctx)
2920 kref_get(&ctx->ref);
2923 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2925 kref_put(&ctx->ref, i915_gem_context_free);
2928 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2930 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2933 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2934 struct drm_file *file);
2935 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2936 struct drm_file *file);
2937 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2938 struct drm_file *file_priv);
2939 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2940 struct drm_file *file_priv);
2942 /* i915_gem_evict.c */
2943 int __must_check i915_gem_evict_something(struct drm_device *dev,
2944 struct i915_address_space *vm,
2947 unsigned cache_level,
2948 unsigned long start,
2951 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2952 int i915_gem_evict_everything(struct drm_device *dev);
2954 /* belongs in i915_gem_gtt.h */
2955 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2957 if (INTEL_INFO(dev)->gen < 6)
2958 intel_gtt_chipset_flush();
2961 /* i915_gem_stolen.c */
2962 int i915_gem_init_stolen(struct drm_device *dev);
2963 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2964 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2965 void i915_gem_cleanup_stolen(struct drm_device *dev);
2966 struct drm_i915_gem_object *
2967 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2968 struct drm_i915_gem_object *
2969 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2974 /* i915_gem_shrinker.c */
2975 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2978 #define I915_SHRINK_PURGEABLE 0x1
2979 #define I915_SHRINK_UNBOUND 0x2
2980 #define I915_SHRINK_BOUND 0x4
2981 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
2982 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
2985 /* i915_gem_tiling.c */
2986 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2988 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2990 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2991 obj->tiling_mode != I915_TILING_NONE;
2994 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2995 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2996 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2998 /* i915_gem_debug.c */
3000 int i915_verify_lists(struct drm_device *dev);
3002 #define i915_verify_lists(dev) 0
3005 /* i915_debugfs.c */
3006 int i915_debugfs_init(struct drm_minor *minor);
3007 void i915_debugfs_cleanup(struct drm_minor *minor);
3008 #ifdef CONFIG_DEBUG_FS
3009 void intel_display_crc_init(struct drm_device *dev);
3011 static inline void intel_display_crc_init(struct drm_device *dev) {}
3014 /* i915_gpu_error.c */
3016 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3017 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3018 const struct i915_error_state_file_priv *error);
3019 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3020 struct drm_i915_private *i915,
3021 size_t count, loff_t pos);
3022 static inline void i915_error_state_buf_release(
3023 struct drm_i915_error_state_buf *eb)
3027 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3028 const char *error_msg);
3029 void i915_error_state_get(struct drm_device *dev,
3030 struct i915_error_state_file_priv *error_priv);
3031 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3032 void i915_destroy_error_state(struct drm_device *dev);
3034 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3035 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3037 /* i915_gem_batch_pool.c */
3038 void i915_gem_batch_pool_init(struct drm_device *dev,
3039 struct i915_gem_batch_pool *pool);
3040 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
3041 struct drm_i915_gem_object*
3042 i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
3044 /* i915_cmd_parser.c */
3045 int i915_cmd_parser_get_version(void);
3046 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3047 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3048 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3049 int i915_parse_cmds(struct intel_engine_cs *ring,
3050 struct drm_i915_gem_object *batch_obj,
3051 struct drm_i915_gem_object *shadow_batch_obj,
3052 u32 batch_start_offset,
3056 /* i915_suspend.c */
3057 extern int i915_save_state(struct drm_device *dev);
3058 extern int i915_restore_state(struct drm_device *dev);
3061 void i915_setup_sysfs(struct drm_device *dev_priv);
3062 void i915_teardown_sysfs(struct drm_device *dev_priv);
3065 extern int intel_setup_gmbus(struct drm_device *dev);
3066 extern void intel_teardown_gmbus(struct drm_device *dev);
3067 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3070 extern struct i2c_adapter *
3071 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3072 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3073 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3074 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3076 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3078 extern void intel_i2c_reset(struct drm_device *dev);
3080 /* intel_opregion.c */
3082 extern int intel_opregion_setup(struct drm_device *dev);
3083 extern void intel_opregion_init(struct drm_device *dev);
3084 extern void intel_opregion_fini(struct drm_device *dev);
3085 extern void intel_opregion_asle_intr(struct drm_device *dev);
3086 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3088 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3091 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3092 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3093 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3094 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3096 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3101 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3109 extern void intel_register_dsm_handler(void);
3110 extern void intel_unregister_dsm_handler(void);
3112 static inline void intel_register_dsm_handler(void) { return; }
3113 static inline void intel_unregister_dsm_handler(void) { return; }
3114 #endif /* CONFIG_ACPI */
3117 extern void intel_modeset_init_hw(struct drm_device *dev);
3118 extern void intel_modeset_init(struct drm_device *dev);
3119 extern void intel_modeset_gem_init(struct drm_device *dev);
3120 extern void intel_modeset_cleanup(struct drm_device *dev);
3121 extern void intel_connector_unregister(struct intel_connector *);
3122 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3123 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3124 bool force_restore);
3125 extern void i915_redisable_vga(struct drm_device *dev);
3126 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3127 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3128 extern void intel_init_pch_refclk(struct drm_device *dev);
3129 extern void intel_set_rps(struct drm_device *dev, u8 val);
3130 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3132 extern void intel_detect_pch(struct drm_device *dev);
3133 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3134 extern int intel_enable_rc6(const struct drm_device *dev);
3136 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3137 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3138 struct drm_file *file);
3139 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3140 struct drm_file *file);
3143 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3144 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3145 struct intel_overlay_error_state *error);
3147 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3148 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3149 struct drm_device *dev,
3150 struct intel_display_error_state *error);
3152 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3153 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3155 /* intel_sideband.c */
3156 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3157 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3158 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3159 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3160 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3161 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3162 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3163 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3164 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3165 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3166 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3167 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3168 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3169 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3170 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3171 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3172 enum intel_sbi_destination destination);
3173 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3174 enum intel_sbi_destination destination);
3175 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3176 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3178 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3179 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3181 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3182 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3184 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3185 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3186 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3187 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3189 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3190 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3191 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3192 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3194 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3195 * will be implemented using 2 32-bit writes in an arbitrary order with
3196 * an arbitrary delay between them. This can cause the hardware to
3197 * act upon the intermediate value, possibly leading to corruption and
3198 * machine death. You have been warned.
3200 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3201 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3203 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3204 u32 upper = I915_READ(upper_reg); \
3205 u32 lower = I915_READ(lower_reg); \
3206 u32 tmp = I915_READ(upper_reg); \
3207 if (upper != tmp) { \
3209 lower = I915_READ(lower_reg); \
3210 WARN_ON(I915_READ(upper_reg) != upper); \
3212 (u64)upper << 32 | lower; })
3214 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3215 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3217 /* "Broadcast RGB" property */
3218 #define INTEL_BROADCAST_RGB_AUTO 0
3219 #define INTEL_BROADCAST_RGB_FULL 1
3220 #define INTEL_BROADCAST_RGB_LIMITED 2
3222 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3224 if (IS_VALLEYVIEW(dev))
3225 return VLV_VGACNTRL;
3226 else if (INTEL_INFO(dev)->gen >= 5)
3227 return CPU_VGACNTRL;
3232 static inline void __user *to_user_ptr(u64 address)
3234 return (void __user *)(uintptr_t)address;
3237 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3239 unsigned long j = msecs_to_jiffies(m);
3241 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3244 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3246 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3249 static inline unsigned long
3250 timespec_to_jiffies_timeout(const struct timespec *value)
3252 unsigned long j = timespec_to_jiffies(value);
3254 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3258 * If you need to wait X milliseconds between events A and B, but event B
3259 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3260 * when event A happened, then just before event B you call this function and
3261 * pass the timestamp as the first argument, and X as the second argument.
3264 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3266 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3269 * Don't re-read the value of "jiffies" every time since it may change
3270 * behind our back and break the math.
3272 tmp_jiffies = jiffies;
3273 target_jiffies = timestamp_jiffies +
3274 msecs_to_jiffies_timeout(to_wait_ms);
3276 if (time_after(target_jiffies, tmp_jiffies)) {
3277 remaining_jiffies = target_jiffies - tmp_jiffies;
3278 while (remaining_jiffies)
3280 schedule_timeout_uninterruptible(remaining_jiffies);
3284 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3285 struct drm_i915_gem_request *req)
3287 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3288 i915_gem_request_assign(&ring->trace_irq_req, req);