drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include <linux/pm_qos.h>
  36
  37 #include <drm/ttm/ttm_device.h>
  38
  39 #include "display/intel_display.h"
  40 #include "display/intel_display_core.h"
  41
  42 #include "gem/i915_gem_context_types.h"
  43 #include "gem/i915_gem_shrinker.h"
  44 #include "gem/i915_gem_stolen.h"
  45
  46 #include "gt/intel_engine.h"
  47 #include "gt/intel_gt_types.h"
  48 #include "gt/intel_region_lmem.h"
  49 #include "gt/intel_workarounds.h"
  50 #include "gt/uc/intel_uc.h"
  51
  52 #include "i915_drm_client.h"
  53 #include "i915_gem.h"
  54 #include "i915_gpu_error.h"
  55 #include "i915_params.h"
  56 #include "i915_perf_types.h"
  57 #include "i915_scheduler.h"
  58 #include "i915_utils.h"
  59 #include "intel_device_info.h"
  60 #include "intel_memory_region.h"
  61 #include "intel_pch.h"
  62 #include "intel_runtime_pm.h"
  63 #include "intel_step.h"
  64 #include "intel_uncore.h"
  65 #include "intel_wopcm.h"
  66
  67 struct drm_i915_clock_gating_funcs;
  68 struct drm_i915_gem_object;
  69 struct drm_i915_private;
  70 struct intel_connector;
  71 struct intel_dp;
  72 struct intel_encoder;
  73 struct intel_limit;
  74 struct intel_overlay_error_state;
  75 struct vlv_s0ix_state;
  76
  77 /* Threshold == 5 for long IRQs, 50 for short */
  78 #define HPD_STORM_DEFAULT_THRESHOLD 50
  79
  80 #define I915_GEM_GPU_DOMAINS \
  81         (I915_GEM_DOMAIN_RENDER | \
  82          I915_GEM_DOMAIN_SAMPLER | \
  83          I915_GEM_DOMAIN_COMMAND | \
  84          I915_GEM_DOMAIN_INSTRUCTION | \
  85          I915_GEM_DOMAIN_VERTEX)
  86
  87 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
  88
  89 #define GEM_QUIRK_PIN_SWIZZLED_PAGES    BIT(0)
  90
  91 struct i915_suspend_saved_registers {
  92         u32 saveDSPARB;
  93         u32 saveSWF0[16];
  94         u32 saveSWF1[16];
  95         u32 saveSWF3[3];
  96         u16 saveGCDGMBUS;
  97 };
  98
  99 #define MAX_L3_SLICES 2
 100 struct intel_l3_parity {
 101         u32 *remap_info[MAX_L3_SLICES];
 102         struct work_struct error_work;
 103         int which_slice;
 104 };
 105
 106 struct i915_gem_mm {
 107         /*
 108          * Shortcut for the stolen region. This points to either
 109          * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
 110          * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
 111          * support stolen.
 112          */
 113         struct intel_memory_region *stolen_region;
 114         /** Memory allocator for GTT stolen memory */
 115         struct drm_mm stolen;
 116         /** Protects the usage of the GTT stolen memory allocator. This is
 117          * always the inner lock when overlapping with struct_mutex. */
 118         struct mutex stolen_lock;
 119
 120         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 121         spinlock_t obj_lock;
 122
 123         /**
 124          * List of objects which are purgeable.
 125          */
 126         struct list_head purge_list;
 127
 128         /**
 129          * List of objects which have allocated pages and are shrinkable.
 130          */
 131         struct list_head shrink_list;
 132
 133         /**
 134          * List of objects which are pending destruction.
 135          */
 136         struct llist_head free_list;
 137         struct work_struct free_work;
 138         /**
 139          * Count of objects pending destructions. Used to skip needlessly
 140          * waiting on an RCU barrier if no objects are waiting to be freed.
 141          */
 142         atomic_t free_count;
 143
 144         /**
 145          * tmpfs instance used for shmem backed objects
 146          */
 147         struct vfsmount *gemfs;
 148
 149         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 150
 151         struct notifier_block oom_notifier;
 152         struct notifier_block vmap_notifier;
 153         struct shrinker shrinker;
 154
 155 #ifdef CONFIG_MMU_NOTIFIER
 156         /**
 157          * notifier_lock for mmu notifiers, memory may not be allocated
 158          * while holding this lock.
 159          */
 160         rwlock_t notifier_lock;
 161 #endif
 162
 163         /* shrinker accounting, also useful for userland debugging */
 164         u64 shrink_memory;
 165         u32 shrink_count;
 166 };
 167
 168 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 169
 170 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 171                                          u64 context);
 172
 173 static inline unsigned long
 174 i915_fence_timeout(const struct drm_i915_private *i915)
 175 {
 176         return i915_fence_context_timeout(i915, U64_MAX);
 177 }
 178
 179 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 180
 181 struct i915_virtual_gpu {
 182         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 183         bool active;
 184         u32 caps;
 185         u32 *initial_mmio;
 186         u8 *initial_cfg_space;
 187         struct list_head entry;
 188 };
 189
 190 struct i915_selftest_stash {
 191         atomic_t counter;
 192         struct ida mock_region_instances;
 193 };
 194
 195 struct drm_i915_private {
 196         struct drm_device drm;
 197
 198         struct intel_display display;
 199
 200         /* FIXME: Device release actions should all be moved to drmm_ */
 201         bool do_release;
 202
 203         /* i915 device parameters */
 204         struct i915_params params;
 205
 206         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 207         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 208         struct intel_driver_caps caps;
 209
 210         /**
 211          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 212          * end of stolen which we can optionally use to create GEM objects
 213          * backed by stolen memory. Note that stolen_usable_size tells us
 214          * exactly how much of this we are actually allowed to use, given that
 215          * some portion of it is in fact reserved for use by hardware functions.
 216          */
 217         struct resource dsm;
 218         /**
 219          * Reseved portion of Data Stolen Memory
 220          */
 221         struct resource dsm_reserved;
 222
 223         /*
 224          * Stolen memory is segmented in hardware with different portions
 225          * offlimits to certain functions.
 226          *
 227          * The drm_mm is initialised to the total accessible range, as found
 228          * from the PCI config. On Broadwell+, this is further restricted to
 229          * avoid the first page! The upper end of stolen memory is reserved for
 230          * hardware functions and similarly removed from the accessible range.
 231          */
 232         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 233
 234         struct intel_uncore uncore;
 235         struct intel_uncore_mmio_debug mmio_debug;
 236
 237         struct i915_virtual_gpu vgpu;
 238
 239         struct intel_gvt *gvt;
 240
 241         struct intel_wopcm wopcm;
 242
 243         struct pci_dev *bridge_dev;
 244
 245         struct rb_root uabi_engines;
 246         unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
 247
 248         struct resource mch_res;
 249
 250         /* protects the irq masks */
 251         spinlock_t irq_lock;
 252
 253         bool display_irqs_enabled;
 254
 255         /* Sideband mailbox protection */
 256         struct mutex sb_lock;
 257         struct pm_qos_request sb_qos;
 258
 259         /** Cached value of IMR to avoid reads in updating the bitfield */
 260         union {
 261                 u32 irq_mask;
 262                 u32 de_irq_mask[I915_MAX_PIPES];
 263         };
 264         u32 pipestat_irq_mask[I915_MAX_PIPES];
 265
 266         bool preserve_bios_swizzle;
 267
 268         unsigned int fsb_freq, mem_freq, is_ddr3;
 269         unsigned int skl_preferred_vco_freq;
 270
 271         unsigned int max_dotclk_freq;
 272         unsigned int hpll_freq;
 273         unsigned int czclk_freq;
 274
 275         /**
 276          * wq - Driver workqueue for GEM.
 277          *
 278          * NOTE: Work items scheduled here are not allowed to grab any modeset
 279          * locks, for otherwise the flushing done in the pageflip code will
 280          * result in deadlocks.
 281          */
 282         struct workqueue_struct *wq;
 283
 284         /* pm private clock gating functions */
 285         const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 286
 287         /* PCH chipset type */
 288         enum intel_pch pch_type;
 289         unsigned short pch_id;
 290
 291         unsigned long gem_quirks;
 292
 293         struct drm_atomic_state *modeset_restore_state;
 294         struct drm_modeset_acquire_ctx reset_ctx;
 295
 296         struct i915_gem_mm mm;
 297
 298         /* Kernel Modesetting */
 299
 300         struct list_head global_obj_list;
 301
 302         bool mchbar_need_disable;
 303
 304         struct intel_l3_parity l3_parity;
 305
 306         /*
 307          * HTI (aka HDPORT) state read during initial hw readout.  Most
 308          * platforms don't have HTI, so this will just stay 0.  Those that do
 309          * will use this later to figure out which PLLs and PHYs are unavailable
 310          * for driver usage.
 311          */
 312         u32 hti_state;
 313
 314         /*
 315          * edram size in MB.
 316          * Cannot be determined by PCIID. You must always read a register.
 317          */
 318         u32 edram_size_mb;
 319
 320         struct i915_gpu_error gpu_error;
 321
 322         /*
 323          * Shadows for CHV DPLL_MD regs to keep the state
 324          * checker somewhat working in the presence hardware
 325          * crappiness (can't read out DPLL_MD for pipes B & C).
 326          */
 327         u32 chv_dpll_md[I915_MAX_PIPES];
 328         u32 bxt_phy_grc;
 329
 330         u32 suspend_count;
 331         struct i915_suspend_saved_registers regfile;
 332         struct vlv_s0ix_state *vlv_s0ix_state;
 333
 334         struct dram_info {
 335                 bool wm_lv_0_adjust_needed;
 336                 u8 num_channels;
 337                 bool symmetric_memory;
 338                 enum intel_dram_type {
 339                         INTEL_DRAM_UNKNOWN,
 340                         INTEL_DRAM_DDR3,
 341                         INTEL_DRAM_DDR4,
 342                         INTEL_DRAM_LPDDR3,
 343                         INTEL_DRAM_LPDDR4,
 344                         INTEL_DRAM_DDR5,
 345                         INTEL_DRAM_LPDDR5,
 346                 } type;
 347                 u8 num_qgv_points;
 348                 u8 num_psf_gv_points;
 349         } dram_info;
 350
 351         struct intel_runtime_pm runtime_pm;
 352
 353         struct i915_perf perf;
 354
 355         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
 356         struct intel_gt gt0;
 357
 358         /*
 359          * i915->gt[0] == &i915->gt0
 360          */
 361 #define I915_MAX_GT 4
 362         struct intel_gt *gt[I915_MAX_GT];
 363
 364         struct kobject *sysfs_gt;
 365
 366         /* Quick lookup of media GT (current platforms only have one) */
 367         struct intel_gt *media_gt;
 368
 369         struct {
 370                 struct i915_gem_contexts {
 371                         spinlock_t lock; /* locks list */
 372                         struct list_head list;
 373                 } contexts;
 374
 375                 /*
 376                  * We replace the local file with a global mappings as the
 377                  * backing storage for the mmap is on the device and not
 378                  * on the struct file, and we do not want to prolong the
 379                  * lifetime of the local fd. To minimise the number of
 380                  * anonymous inodes we create, we use a global singleton to
 381                  * share the global mapping.
 382                  */
 383                 struct file *mmap_singleton;
 384         } gem;
 385
 386         u8 pch_ssc_use;
 387
 388         /* For i915gm/i945gm vblank irq workaround */
 389         u8 vblank_enabled;
 390
 391         bool irq_enabled;
 392
 393         /*
 394          * DG2: Mask of PHYs that were not calibrated by the firmware
 395          * and should not be used.
 396          */
 397         u8 snps_phy_failed_calibration;
 398
 399         struct i915_pmu pmu;
 400
 401         struct i915_drm_clients clients;
 402
 403         /* The TTM device structure. */
 404         struct ttm_device bdev;
 405
 406         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 407
 408         /*
 409          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 410          * will be rejected. Instead look for a better place.
 411          */
 412 };
 413
 414 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 415 {
 416         return container_of(dev, struct drm_i915_private, drm);
 417 }
 418
 419 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 420 {
 421         return dev_get_drvdata(kdev);
 422 }
 423
 424 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 425 {
 426         return pci_get_drvdata(pdev);
 427 }
 428
 429 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 430 {
 431         return &i915->gt0;
 432 }
 433
 434 /* Simple iterator over all initialised engines */
 435 #define for_each_engine(engine__, dev_priv__, id__) \
 436         for ((id__) = 0; \
 437              (id__) < I915_NUM_ENGINES; \
 438              (id__)++) \
 439                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
 440
 441 /* Iterator over subset of engines selected by mask */
 442 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
 443         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
 444              (tmp__) ? \
 445              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
 446              0;)
 447
 448 #define rb_to_uabi_engine(rb) \
 449         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
 450
 451 #define for_each_uabi_engine(engine__, i915__) \
 452         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
 453              (engine__); \
 454              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 455
 456 #define for_each_uabi_class_engine(engine__, class__, i915__) \
 457         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
 458              (engine__) && (engine__)->uabi_class == (class__); \
 459              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 460
 461 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
 462 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
 463 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
 464
 465 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
 466
 467 #define IP_VER(ver, rel)                ((ver) << 8 | (rel))
 468
 469 #define GRAPHICS_VER(i915)              (RUNTIME_INFO(i915)->graphics.ip.ver)
 470 #define GRAPHICS_VER_FULL(i915)         IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
 471                                                RUNTIME_INFO(i915)->graphics.ip.rel)
 472 #define IS_GRAPHICS_VER(i915, from, until) \
 473         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
 474
 475 #define MEDIA_VER(i915)                 (RUNTIME_INFO(i915)->media.ip.ver)
 476 #define MEDIA_VER_FULL(i915)            IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 477                                                RUNTIME_INFO(i915)->media.ip.rel)
 478 #define IS_MEDIA_VER(i915, from, until) \
 479         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 480
 481 #define DISPLAY_VER(i915)       (RUNTIME_INFO(i915)->display.ip.ver)
 482 #define IS_DISPLAY_VER(i915, from, until) \
 483         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 484
 485 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
 486
 487 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
 488
 489 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 490 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
 491 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
 492 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
 493
 494 #define IS_DISPLAY_STEP(__i915, since, until) \
 495         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
 496          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 497
 498 #define IS_GRAPHICS_STEP(__i915, since, until) \
 499         (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
 500          INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
 501
 502 #define IS_MEDIA_STEP(__i915, since, until) \
 503         (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
 504          INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
 505
 506 #define IS_BASEDIE_STEP(__i915, since, until) \
 507         (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
 508          INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
 509
 510 static __always_inline unsigned int
 511 __platform_mask_index(const struct intel_runtime_info *info,
 512                       enum intel_platform p)
 513 {
 514         const unsigned int pbits =
 515                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 516
 517         /* Expand the platform_mask array if this fails. */
 518         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 519                      pbits * ARRAY_SIZE(info->platform_mask));
 520
 521         return p / pbits;
 522 }
 523
 524 static __always_inline unsigned int
 525 __platform_mask_bit(const struct intel_runtime_info *info,
 526                     enum intel_platform p)
 527 {
 528         const unsigned int pbits =
 529                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 530
 531         return p % pbits + INTEL_SUBPLATFORM_BITS;
 532 }
 533
 534 static inline u32
 535 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
 536 {
 537         const unsigned int pi = __platform_mask_index(info, p);
 538
 539         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
 540 }
 541
 542 static __always_inline bool
 543 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
 544 {
 545         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 546         const unsigned int pi = __platform_mask_index(info, p);
 547         const unsigned int pb = __platform_mask_bit(info, p);
 548
 549         BUILD_BUG_ON(!__builtin_constant_p(p));
 550
 551         return info->platform_mask[pi] & BIT(pb);
 552 }
 553
 554 static __always_inline bool
 555 IS_SUBPLATFORM(const struct drm_i915_private *i915,
 556                enum intel_platform p, unsigned int s)
 557 {
 558         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 559         const unsigned int pi = __platform_mask_index(info, p);
 560         const unsigned int pb = __platform_mask_bit(info, p);
 561         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
 562         const u32 mask = info->platform_mask[pi];
 563
 564         BUILD_BUG_ON(!__builtin_constant_p(p));
 565         BUILD_BUG_ON(!__builtin_constant_p(s));
 566         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
 567
 568         /* Shift and test on the MSB position so sign flag can be used. */
 569         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
 570 }
 571
 572 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
 573 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
 574
 575 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
 576 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
 577 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
 578 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
 579 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
 580 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
 581 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
 582 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
 583 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
 584 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
 585 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
 586 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
 587 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
 588 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 589 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
 590 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
 591 #define IS_IRONLAKE_M(dev_priv) \
 592         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
 593 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
 594 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 595 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
 596                                  INTEL_INFO(dev_priv)->gt == 1)
 597 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 598 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 599 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
 600 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 601 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 602 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
 603 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
 604 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 605 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 606 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 607 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 608 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
 609                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 610 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 611 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 612 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
 613 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 614 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 615 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
 616 #define IS_DG2(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG2)
 617 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 618 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
 619
 620 #define IS_METEORLAKE_M(dev_priv) \
 621         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
 622 #define IS_METEORLAKE_P(dev_priv) \
 623         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 624 #define IS_DG2_G10(dev_priv) \
 625         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 626 #define IS_DG2_G11(dev_priv) \
 627         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 628 #define IS_DG2_G12(dev_priv) \
 629         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 630 #define IS_ADLS_RPLS(dev_priv) \
 631         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 632 #define IS_ADLP_N(dev_priv) \
 633         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 634 #define IS_ADLP_RPLP(dev_priv) \
 635         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 636 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 637                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 638 #define IS_BDW_ULT(dev_priv) \
 639         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
 640 #define IS_BDW_ULX(dev_priv) \
 641         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 642 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
 643                                  INTEL_INFO(dev_priv)->gt == 3)
 644 #define IS_HSW_ULT(dev_priv) \
 645         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 646 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
 647                                  INTEL_INFO(dev_priv)->gt == 3)
 648 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
 649                                  INTEL_INFO(dev_priv)->gt == 1)
 650 /* ULX machines are also considered ULT. */
 651 #define IS_HSW_ULX(dev_priv) \
 652         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
 653 #define IS_SKL_ULT(dev_priv) \
 654         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 655 #define IS_SKL_ULX(dev_priv) \
 656         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 657 #define IS_KBL_ULT(dev_priv) \
 658         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 659 #define IS_KBL_ULX(dev_priv) \
 660         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 661 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 662                                  INTEL_INFO(dev_priv)->gt == 2)
 663 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 664                                  INTEL_INFO(dev_priv)->gt == 3)
 665 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 666                                  INTEL_INFO(dev_priv)->gt == 4)
 667 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 668                                  INTEL_INFO(dev_priv)->gt == 2)
 669 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 670                                  INTEL_INFO(dev_priv)->gt == 3)
 671 #define IS_CFL_ULT(dev_priv) \
 672         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 673 #define IS_CFL_ULX(dev_priv) \
 674         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
 675 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 676                                  INTEL_INFO(dev_priv)->gt == 2)
 677 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 678                                  INTEL_INFO(dev_priv)->gt == 3)
 679
 680 #define IS_CML_ULT(dev_priv) \
 681         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
 682 #define IS_CML_ULX(dev_priv) \
 683         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
 684 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
 685                                  INTEL_INFO(dev_priv)->gt == 2)
 686
 687 #define IS_ICL_WITH_PORT_F(dev_priv) \
 688         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 689
 690 #define IS_TGL_UY(dev_priv) \
 691         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 692
 693 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 694
 695 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
 696         (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
 697 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 698         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 699
 700 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
 701         (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
 702 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 703         (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 704
 705 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 706         (IS_TIGERLAKE(__i915) && \
 707          IS_DISPLAY_STEP(__i915, since, until))
 708
 709 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
 710         (IS_TGL_UY(__i915) && \
 711          IS_GRAPHICS_STEP(__i915, since, until))
 712
 713 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
 714         (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
 715          IS_GRAPHICS_STEP(__i915, since, until))
 716
 717 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 718         (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 719
 720 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
 721         (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
 722 #define IS_DG1_DISPLAY_STEP(p, since, until) \
 723         (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 724
 725 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 726         (IS_ALDERLAKE_S(__i915) && \
 727          IS_DISPLAY_STEP(__i915, since, until))
 728
 729 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
 730         (IS_ALDERLAKE_S(__i915) && \
 731          IS_GRAPHICS_STEP(__i915, since, until))
 732
 733 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
 734         (IS_ALDERLAKE_P(__i915) && \
 735          IS_DISPLAY_STEP(__i915, since, until))
 736
 737 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
 738         (IS_ALDERLAKE_P(__i915) && \
 739          IS_GRAPHICS_STEP(__i915, since, until))
 740
 741 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 742         (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 743
 744 /*
 745  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 746  * create three variants (G10, G11, and G12) which each have distinct
 747  * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 748  * stepping back to "A0" for their first iterations, even though they're more
 749  * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 750  * functionality and workarounds.  However the display stepping does not reset
 751  * in the same manner --- a specific stepping like "B0" has a consistent
 752  * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 753  *
 754  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 755  * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 756  * and stepping-specific logic will be applied with a general DG2-wide stepping
 757  * number.
 758  */
 759 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 760         (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 761          IS_GRAPHICS_STEP(__i915, since, until))
 762
 763 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
 764         (IS_DG2(__i915) && \
 765          IS_DISPLAY_STEP(__i915, since, until))
 766
 767 #define IS_PVC_BD_STEP(__i915, since, until) \
 768         (IS_PONTEVECCHIO(__i915) && \
 769          IS_BASEDIE_STEP(__i915, since, until))
 770
 771 #define IS_PVC_CT_STEP(__i915, since, until) \
 772         (IS_PONTEVECCHIO(__i915) && \
 773          IS_GRAPHICS_STEP(__i915, since, until))
 774
 775 #define IS_LP(dev_priv)         (INTEL_INFO(dev_priv)->is_lp)
 776 #define IS_GEN9_LP(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 777 #define IS_GEN9_BC(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
 778
 779 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 780 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
 781
 782 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
 783         unsigned int first__ = (first);                                 \
 784         unsigned int count__ = (count);                                 \
 785         ((gt)->info.engine_mask &                                               \
 786          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
 787 })
 788 #define RCS_MASK(gt) \
 789         ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 790 #define BCS_MASK(gt) \
 791         ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
 792 #define VDBOX_MASK(gt) \
 793         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 794 #define VEBOX_MASK(gt) \
 795         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
 796 #define CCS_MASK(gt) \
 797         ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 798
 799 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
 800
 801 /*
 802  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
 803  * All later gens can run the final buffer from the ppgtt
 804  */
 805 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 806
 807 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
 808 #define HAS_4TILE(dev_priv)     (INTEL_INFO(dev_priv)->has_4tile)
 809 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
 810 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
 811 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
 812 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
 813
 814 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
 815
 816 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 817                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 818 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
 819                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 820
 821 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 822
 823 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
 824 #define HAS_PPGTT(dev_priv) \
 825         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 826 #define HAS_FULL_PPGTT(dev_priv) \
 827         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
 828
 829 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 830         GEM_BUG_ON((sizes) == 0); \
 831         ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 832 })
 833
 834 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
 835 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
 836                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
 837
 838 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 839 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
 840
 841 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
 842         (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
 843
 844 /* WaRsDisableCoarsePowerGating:skl,cnl */
 845 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
 846         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 847
 848 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
 849 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
 850                                         IS_GEMINILAKE(dev_priv) || \
 851                                         IS_KABYLAKE(dev_priv))
 852
 853 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 854  * rows, which changed the alignment requirements and fence programming.
 855  */
 856 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 857                                          !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
 858 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
 859 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
 860
 861 #define HAS_FW_BLC(dev_priv)    (DISPLAY_VER(dev_priv) > 2)
 862 #define HAS_FBC(dev_priv)       (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
 863 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
 864
 865 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 866
 867 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
 868 #define HAS_DP20(dev_priv)      (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
 869
 870 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)       (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 871
 872 #define HAS_CDCLK_CRAWL(dev_priv)        (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 873 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
 874 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 875 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
 876 #define HAS_PSR_HW_TRACKING(dev_priv) \
 877         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 878 #define HAS_PSR2_SEL_FETCH(dev_priv)     (DISPLAY_VER(dev_priv) >= 12)
 879 #define HAS_TRANSCODER(dev_priv, trans)  ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 880
 881 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
 882 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
 883 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
 884
 885 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
 886
 887 #define HAS_DMC(dev_priv)       (RUNTIME_INFO(dev_priv)->has_dmc)
 888
 889 #define HAS_HECI_PXP(dev_priv) \
 890         (INTEL_INFO(dev_priv)->has_heci_pxp)
 891
 892 #define HAS_HECI_GSCFI(dev_priv) \
 893         (INTEL_INFO(dev_priv)->has_heci_gscfi)
 894
 895 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 896
 897 #define HAS_MSO(i915)           (DISPLAY_VER(i915) >= 12)
 898
 899 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 900 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 901
 902 /*
 903  * Set this flag, when platform requires 64K GTT page sizes or larger for
 904  * device local memory access.
 905  */
 906 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 907
 908 /*
 909  * Set this flag when platform doesn't allow both 64k pages and 4k pages in
 910  * the same PT. this flag means we need to support compact PT layout for the
 911  * ppGTT when using the 64K GTT pages.
 912  */
 913 #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
 914
 915 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
 916
 917 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 918 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 919
 920 #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
 921
 922 /*
 923  * Platform has the dedicated compression control state for each lmem surfaces
 924  * stored in lmem to support the 3D and media compression formats.
 925  */
 926 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 927
 928 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
 929
 930 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
 931
 932 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
 933
 934 #define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
 935                             INTEL_INFO(dev_priv)->has_pxp) && \
 936                             VDBOX_MASK(to_gt(dev_priv)))
 937
 938 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 939
 940 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 941
 942 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 943
 944 /* DPF == dynamic parity feature */
 945 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 946 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 947                                  2 : HAS_L3_DPF(dev_priv))
 948
 949 #define GT_FREQUENCY_MULTIPLIER 50
 950 #define GEN9_FREQ_SCALER 3
 951
 952 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
 953
 954 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
 955
 956 #define HAS_VRR(i915)   (DISPLAY_VER(i915) >= 11)
 957
 958 #define HAS_ASYNC_FLIPS(i915)           (DISPLAY_VER(i915) >= 5)
 959
 960 /* Only valid when HAS_DISPLAY() is true */
 961 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 962         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),         \
 963          !(dev_priv)->params.disable_display &&                         \
 964          !intel_opregion_headless_sku(dev_priv))
 965
 966 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
 967         (INTEL_INFO(dev_priv)->has_guc_deprivilege)
 968
 969 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
 970                                               IS_ALDERLAKE_S(dev_priv))
 971
 972 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 973
 974 #define HAS_3D_PIPELINE(i915)   (INTEL_INFO(i915)->has_3d_pipeline)
 975
 976 #define HAS_ONE_EU_PER_FUSE_BIT(i915)   (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
 977
 978 #define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
 979                                     GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
 980
 981 /* intel_device_info.c */
 982 static inline struct intel_device_info *
 983 mkwrite_device_info(struct drm_i915_private *dev_priv)
 984 {
 985         return (struct intel_device_info *)INTEL_INFO(dev_priv);
 986 }
 987
 988 #endif