1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/dma-resv.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_atomic.h>
58 #include <drm/drm_connector.h>
59 #include <drm/i915_mei_hdcp_interface.h>
61 #include "i915_fixed.h"
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "display/intel_bios.h"
67 #include "display/intel_display.h"
68 #include "display/intel_display_power.h"
69 #include "display/intel_dpll_mgr.h"
70 #include "display/intel_frontbuffer.h"
71 #include "display/intel_opregion.h"
73 #include "gt/intel_lrc.h"
74 #include "gt/intel_engine.h"
75 #include "gt/intel_workarounds.h"
77 #include "intel_device_info.h"
78 #include "intel_runtime_pm.h"
80 #include "intel_uncore.h"
81 #include "intel_wakeref.h"
82 #include "intel_wopcm.h"
85 #include "gem/i915_gem_context_types.h"
86 #include "i915_gem_fence_reg.h"
87 #include "i915_gem_gtt.h"
88 #include "i915_gpu_error.h"
89 #include "i915_request.h"
90 #include "i915_scheduler.h"
91 #include "i915_timeline.h"
94 #include "intel_gvt.h"
96 /* General customization:
99 #define DRIVER_NAME "i915"
100 #define DRIVER_DESC "Intel Graphics"
101 #define DRIVER_DATE "20190619"
102 #define DRIVER_TIMESTAMP 1560947544
104 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
105 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
106 * which may not necessarily be a user visible problem. This will either
107 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
108 * enable distros and users to tailor their preferred amount of i915 abrt
111 #define I915_STATE_WARN(condition, format...) ({ \
112 int __ret_warn_on = !!(condition); \
113 if (unlikely(__ret_warn_on)) \
114 if (!WARN(i915_modparams.verbose_state_checks, format)) \
116 unlikely(__ret_warn_on); \
119 #define I915_STATE_WARN_ON(x) \
120 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
122 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
124 bool __i915_inject_load_failure(const char *func, int line);
125 #define i915_inject_load_failure() \
126 __i915_inject_load_failure(__func__, __LINE__)
128 bool i915_error_injected(void);
132 #define i915_inject_load_failure() false
133 #define i915_error_injected() false
137 #define i915_load_error(i915, fmt, ...) \
138 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
141 struct drm_i915_gem_object;
145 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
158 #define for_each_hpd_pin(__pin) \
159 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
161 /* Threshold == 5 for long IRQs, 50 for short */
162 #define HPD_STORM_DEFAULT_THRESHOLD 50
164 struct i915_hotplug {
165 struct work_struct hotplug_work;
168 unsigned long last_jiffies;
173 HPD_MARK_DISABLED = 2
175 } stats[HPD_NUM_PINS];
177 struct delayed_work reenable_work;
181 struct work_struct dig_port_work;
183 struct work_struct poll_init_work;
186 unsigned int hpd_storm_threshold;
187 /* Whether or not to count short HPD IRQs in HPD storms */
188 u8 hpd_short_storm_enabled;
191 * if we get a HPD irq from DP and a HPD irq from non-DP
192 * the non-DP HPD could block the workqueue on a mode config
193 * mutex getting, that userspace may have taken. However
194 * userspace is waiting on the DP workqueue to run which is
195 * blocked behind the non-DP one.
197 struct workqueue_struct *dp_wq;
200 #define I915_GEM_GPU_DOMAINS \
201 (I915_GEM_DOMAIN_RENDER | \
202 I915_GEM_DOMAIN_SAMPLER | \
203 I915_GEM_DOMAIN_COMMAND | \
204 I915_GEM_DOMAIN_INSTRUCTION | \
205 I915_GEM_DOMAIN_VERTEX)
207 struct drm_i915_private;
208 struct i915_mm_struct;
209 struct i915_mmu_object;
211 struct drm_i915_file_private {
212 struct drm_i915_private *dev_priv;
213 struct drm_file *file;
217 struct list_head request_list;
220 struct idr context_idr;
221 struct mutex context_idr_lock; /* guards context_idr */
224 struct mutex vm_idr_lock; /* guards vm_idr */
226 unsigned int bsd_engine;
229 * Every context ban increments per client ban score. Also
230 * hangs in short succession increments ban score. If ban threshold
231 * is reached, client is considered banned and submitting more work
232 * will fail. This is a stop gap measure to limit the badly behaving
233 * clients access to gpu. Note that unbannable contexts never increment
234 * the client ban score.
236 #define I915_CLIENT_SCORE_HANG_FAST 1
237 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
238 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
239 #define I915_CLIENT_SCORE_BANNED 9
240 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
242 unsigned long hang_timestamp;
245 /* Interface history:
248 * 1.2: Add Power Management
249 * 1.3: Add vblank support
250 * 1.4: Fix cmdbuffer path, add heap destroy
251 * 1.5: Add vblank pipe configuration
252 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
253 * - Support vertical blank on secondary display pipe
255 #define DRIVER_MAJOR 1
256 #define DRIVER_MINOR 6
257 #define DRIVER_PATCHLEVEL 0
259 struct intel_overlay;
260 struct intel_overlay_error_state;
262 struct sdvo_device_mapping {
271 struct intel_connector;
272 struct intel_encoder;
273 struct intel_atomic_state;
274 struct intel_crtc_state;
275 struct intel_initial_plane_config;
279 struct intel_cdclk_state;
281 struct drm_i915_display_funcs {
282 void (*get_cdclk)(struct drm_i915_private *dev_priv,
283 struct intel_cdclk_state *cdclk_state);
284 void (*set_cdclk)(struct drm_i915_private *dev_priv,
285 const struct intel_cdclk_state *cdclk_state,
287 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
288 enum i9xx_plane_id i9xx_plane);
289 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
290 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
291 void (*initial_watermarks)(struct intel_atomic_state *state,
292 struct intel_crtc_state *cstate);
293 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
294 struct intel_crtc_state *cstate);
295 void (*optimize_watermarks)(struct intel_atomic_state *state,
296 struct intel_crtc_state *cstate);
297 int (*compute_global_watermarks)(struct intel_atomic_state *state);
298 void (*update_wm)(struct intel_crtc *crtc);
299 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
300 /* Returns the active state of the crtc, and if the crtc is active,
301 * fills out the pipe-config with the hw state. */
302 bool (*get_pipe_config)(struct intel_crtc *,
303 struct intel_crtc_state *);
304 void (*get_initial_plane_config)(struct intel_crtc *,
305 struct intel_initial_plane_config *);
306 int (*crtc_compute_clock)(struct intel_crtc *crtc,
307 struct intel_crtc_state *crtc_state);
308 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
309 struct drm_atomic_state *old_state);
310 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
311 struct drm_atomic_state *old_state);
312 void (*update_crtcs)(struct drm_atomic_state *state);
313 void (*audio_codec_enable)(struct intel_encoder *encoder,
314 const struct intel_crtc_state *crtc_state,
315 const struct drm_connector_state *conn_state);
316 void (*audio_codec_disable)(struct intel_encoder *encoder,
317 const struct intel_crtc_state *old_crtc_state,
318 const struct drm_connector_state *old_conn_state);
319 void (*fdi_link_train)(struct intel_crtc *crtc,
320 const struct intel_crtc_state *crtc_state);
321 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
322 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
323 /* clock updates for mode set */
325 /* render clock increase/decrease */
326 /* display clock increase/decrease */
327 /* pll clock increase/decrease */
329 int (*color_check)(struct intel_crtc_state *crtc_state);
331 * Program double buffered color management registers during
332 * vblank evasion. The registers should then latch during the
333 * next vblank start, alongside any other double buffered registers
334 * involved with the same commit.
336 void (*color_commit)(const struct intel_crtc_state *crtc_state);
338 * Load LUTs (and other single buffered color management
339 * registers). Will (hopefully) be called during the vblank
340 * following the latching of any double buffered registers
341 * involved with the same commit.
343 void (*load_luts)(const struct intel_crtc_state *crtc_state);
344 void (*read_luts)(struct intel_crtc_state *crtc_state);
348 struct work_struct work;
350 u32 required_version;
351 u32 max_fw_size; /* bytes */
353 u32 dmc_fw_size; /* dwords */
356 i915_reg_t mmioaddr[20];
360 intel_wakeref_t wakeref;
363 enum i915_cache_level {
365 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
366 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
367 caches, eg sampler/render caches, and the
368 large Last-Level-Cache. LLC is coherent with
369 the CPU, but L3 is only visible to the GPU. */
370 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
373 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
376 /* This is always the inner lock when overlapping with struct_mutex and
377 * it's the outer lock when overlapping with stolen_lock. */
380 unsigned int possible_framebuffer_bits;
381 unsigned int busy_bits;
382 unsigned int visible_pipes_mask;
383 struct intel_crtc *crtc;
385 struct drm_mm_node compressed_fb;
386 struct drm_mm_node *compressed_llb;
394 bool underrun_detected;
395 struct work_struct underrun_work;
398 * Due to the atomic rules we can't access some structures without the
399 * appropriate locking, so we cache information here in order to avoid
402 struct intel_fbc_state_cache {
403 struct i915_vma *vma;
407 unsigned int mode_flags;
408 u32 hsw_bdw_pixel_rate;
412 unsigned int rotation;
417 * Display surface base address adjustement for
418 * pageflips. Note that on gen4+ this only adjusts up
419 * to a tile, offsets within a tile are handled in
420 * the hw itself (with the TILEOFF register).
427 u16 pixel_blend_mode;
431 const struct drm_format_info *format;
437 * This structure contains everything that's relevant to program the
438 * hardware registers. When we want to figure out if we need to disable
439 * and re-enable FBC for a new configuration we just check if there's
440 * something different in the struct. The genx_fbc_activate functions
441 * are supposed to read from it in order to program the registers.
443 struct intel_fbc_reg_params {
444 struct i915_vma *vma;
449 enum i9xx_plane_id i9xx_plane;
450 unsigned int fence_y_offset;
454 const struct drm_format_info *format;
459 unsigned int gen9_wa_cfb_stride;
462 const char *no_fbc_reason;
466 * HIGH_RR is the highest eDP panel refresh rate read from EDID
467 * LOW_RR is the lowest eDP panel refresh rate found from EDID
468 * parsing for same resolution.
470 enum drrs_refresh_rate_type {
473 DRRS_MAX_RR, /* RR count */
476 enum drrs_support_type {
477 DRRS_NOT_SUPPORTED = 0,
478 STATIC_DRRS_SUPPORT = 1,
479 SEAMLESS_DRRS_SUPPORT = 2
485 struct delayed_work work;
487 unsigned busy_frontbuffer_bits;
488 enum drrs_refresh_rate_type refresh_rate_type;
489 enum drrs_support_type type;
495 #define I915_PSR_DEBUG_MODE_MASK 0x0f
496 #define I915_PSR_DEBUG_DEFAULT 0x00
497 #define I915_PSR_DEBUG_DISABLE 0x01
498 #define I915_PSR_DEBUG_ENABLE 0x02
499 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
500 #define I915_PSR_DEBUG_IRQ 0x10
508 struct work_struct work;
509 unsigned busy_frontbuffer_bits;
510 bool sink_psr2_support;
512 bool colorimetry_support;
514 u8 sink_sync_latency;
515 ktime_t last_entry_attempt;
517 bool sink_not_reliable;
519 u16 su_x_granularity;
523 * Sorted by south display engine compatibility.
524 * If the new PCH comes with a south display engine that is not
525 * inherited from the latest item, please do not add it to the
526 * end. Instead, add it right after its "parent" PCH.
529 PCH_NOP = -1, /* PCH without south display */
530 PCH_NONE = 0, /* No PCH present */
531 PCH_IBX, /* Ibexpeak PCH */
532 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
533 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
534 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
535 PCH_CNP, /* Cannon/Comet Lake PCH */
536 PCH_ICP, /* Ice Lake PCH */
537 PCH_MCC, /* Mule Creek Canyon PCH */
540 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
541 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
542 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
543 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
544 #define QUIRK_INCREASE_T12_DELAY (1<<6)
545 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
548 struct intel_fbc_work;
551 struct i2c_adapter adapter;
552 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
556 struct i2c_algo_bit_data bit_algo;
557 struct drm_i915_private *dev_priv;
560 struct i915_suspend_saved_registers {
563 u32 saveCACHE_MODE_0;
564 u32 saveMI_ARB_STATE;
568 u64 saveFENCE[I915_MAX_NUM_FENCES];
569 u32 savePCH_PORT_HOTPLUG;
573 struct vlv_s0ix_state {
580 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
581 u32 media_max_req_count;
582 u32 gfx_max_req_count;
614 /* Display 1 CZ domain */
619 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
621 /* GT SA CZ domain */
628 /* Display 2 CZ domain */
635 struct intel_rps_ei {
642 struct mutex lock; /* protects enabling and the worker */
645 * work, interrupts_enabled and pm_iir are protected by
648 struct work_struct work;
649 bool interrupts_enabled;
652 /* PM interrupt bits that should never be masked */
655 /* Frequencies are stored in potentially platform dependent multiples.
656 * In other words, *_freq needs to be multiplied by X to be interesting.
657 * Soft limits are those which are used for the dynamic reclocking done
658 * by the driver (raise frequencies under heavy loads, and lower for
659 * lighter loads). Hard limits are those imposed by the hardware.
661 * A distinction is made for overclocking, which is never enabled by
662 * default, and is considered to be above the hard limit if it's
665 u8 cur_freq; /* Current frequency (cached, may not == HW) */
666 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
667 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
668 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
669 u8 min_freq; /* AKA RPn. Minimum frequency */
670 u8 boost_freq; /* Frequency to request when wait boosting */
671 u8 idle_freq; /* Frequency to request when we are idle */
672 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
673 u8 rp1_freq; /* "less than" RP0 power/freqency */
674 u8 rp0_freq; /* Non-overclocked max frequency. */
675 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
682 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
683 unsigned int interactive;
685 u8 up_threshold; /* Current %busy required to uplock */
686 u8 down_threshold; /* Current %busy required to downclock */
690 atomic_t num_waiters;
693 /* manual wa residency calculations */
694 struct intel_rps_ei ei;
699 u64 prev_hw_residency[4];
700 u64 cur_residency[4];
703 struct intel_llc_pstate {
707 struct intel_gen6_power_mgmt {
708 struct intel_rps rps;
709 struct intel_rc6 rc6;
710 struct intel_llc_pstate llc_pstate;
713 /* defined intel_pm.c */
714 extern spinlock_t mchdev_lock;
716 struct intel_ilk_power_mgmt {
724 unsigned long last_time1;
725 unsigned long chipset_power;
728 unsigned long gfx_power;
735 #define MAX_L3_SLICES 2
736 struct intel_l3_parity {
737 u32 *remap_info[MAX_L3_SLICES];
738 struct work_struct error_work;
743 /** Memory allocator for GTT stolen memory */
744 struct drm_mm stolen;
745 /** Protects the usage of the GTT stolen memory allocator. This is
746 * always the inner lock when overlapping with struct_mutex. */
747 struct mutex stolen_lock;
749 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
753 * List of objects which are purgeable.
755 struct list_head purge_list;
758 * List of objects which have allocated pages and are shrinkable.
760 struct list_head shrink_list;
763 * List of objects which are pending destruction.
765 struct llist_head free_list;
766 struct work_struct free_work;
767 spinlock_t free_lock;
769 * Count of objects pending destructions. Used to skip needlessly
770 * waiting on an RCU barrier if no objects are waiting to be freed.
775 * Small stash of WC pages
777 struct pagestash wc_stash;
780 * tmpfs instance used for shmem backed objects
782 struct vfsmount *gemfs;
784 /** PPGTT used for aliasing the PPGTT with the GTT */
785 struct i915_ppgtt *aliasing_ppgtt;
787 struct notifier_block oom_notifier;
788 struct notifier_block vmap_notifier;
789 struct shrinker shrinker;
792 * Workqueue to fault in userptr pages, flushed by the execbuf
793 * when required but otherwise left to userspace to try again
796 struct workqueue_struct *userptr_wq;
798 u64 unordered_timeline;
800 /* the indicator for dispatch video commands on two BSD rings */
801 atomic_t bsd_engine_dispatch_index;
803 /** Bit 6 swizzling required for X tiling */
805 /** Bit 6 swizzling required for Y tiling */
808 /* shrinker accounting, also useful for userland debugging */
813 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
815 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
816 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
818 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
819 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
821 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
823 struct ddi_vbt_port_info {
824 /* Non-NULL if port present. */
825 const struct child_device_config *child;
830 * This is an index in the HDMI/DVI DDI buffer translation table.
831 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
832 * populate this field.
834 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
841 u8 supports_typec_usb:1;
844 u8 alternate_aux_channel;
845 u8 alternate_ddc_pin;
849 int dp_max_link_rate; /* 0 for not limited by VBT */
852 enum psr_lines_to_wait {
853 PSR_0_LINES_TO_WAIT = 0,
859 struct intel_vbt_data {
860 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
861 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
864 unsigned int int_tv_support:1;
865 unsigned int lvds_dither:1;
866 unsigned int int_crt_support:1;
867 unsigned int lvds_use_ssc:1;
868 unsigned int int_lvds_support:1;
869 unsigned int display_clock_mode:1;
870 unsigned int fdi_rx_polarity_inverted:1;
871 unsigned int panel_type:4;
873 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
874 enum drm_panel_orientation orientation;
876 enum drrs_support_type drrs_type;
886 struct edp_power_seq pps;
892 bool require_aux_wakeup;
894 enum psr_lines_to_wait lines_to_wait;
895 int tp1_wakeup_time_us;
896 int tp2_tp3_wakeup_time_us;
897 int psr2_tp2_tp3_wakeup_time_us;
904 u8 min_brightness; /* min_brightness/255 of max */
905 u8 controller; /* brightness controller number */
906 enum intel_backlight_type type;
912 struct mipi_config *config;
913 struct mipi_pps_data *pps;
919 const u8 *sequence[MIPI_SEQ_MAX];
920 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
921 enum drm_panel_orientation orientation;
927 struct child_device_config *child_dev;
929 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
930 struct sdvo_device_mapping sdvo_mappings[2];
933 enum intel_ddb_partitioning {
935 INTEL_DDB_PART_5_6, /* IVB+ */
938 struct intel_wm_level {
946 struct ilk_wm_values {
952 enum intel_ddb_partitioning partitioning;
956 u16 plane[I915_MAX_PLANES];
966 struct vlv_wm_ddl_values {
967 u8 plane[I915_MAX_PLANES];
970 struct vlv_wm_values {
971 struct g4x_pipe_wm pipe[3];
973 struct vlv_wm_ddl_values ddl[3];
978 struct g4x_wm_values {
979 struct g4x_pipe_wm pipe[2];
981 struct g4x_sr_wm hpll;
987 struct skl_ddb_entry {
988 u16 start, end; /* in number of blocks, 'end' is exclusive */
991 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
993 return entry->end - entry->start;
996 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
997 const struct skl_ddb_entry *e2)
999 if (e1->start == e2->start && e1->end == e2->end)
1005 struct skl_ddb_allocation {
1006 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1009 struct skl_ddb_values {
1010 unsigned dirty_pipes;
1011 struct skl_ddb_allocation ddb;
1014 struct skl_wm_level {
1022 /* Stores plane specific WM parameters */
1023 struct skl_wm_params {
1024 bool x_tiled, y_tiled;
1029 u32 plane_pixel_rate;
1030 u32 y_min_scanlines;
1031 u32 plane_bytes_per_line;
1032 uint_fixed_16_16_t plane_blocks_per_line;
1033 uint_fixed_16_16_t y_tile_minimum;
1035 u32 dbuf_block_size;
1038 enum intel_pipe_crc_source {
1039 INTEL_PIPE_CRC_SOURCE_NONE,
1040 INTEL_PIPE_CRC_SOURCE_PLANE1,
1041 INTEL_PIPE_CRC_SOURCE_PLANE2,
1042 INTEL_PIPE_CRC_SOURCE_PLANE3,
1043 INTEL_PIPE_CRC_SOURCE_PLANE4,
1044 INTEL_PIPE_CRC_SOURCE_PLANE5,
1045 INTEL_PIPE_CRC_SOURCE_PLANE6,
1046 INTEL_PIPE_CRC_SOURCE_PLANE7,
1047 INTEL_PIPE_CRC_SOURCE_PIPE,
1048 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1049 INTEL_PIPE_CRC_SOURCE_TV,
1050 INTEL_PIPE_CRC_SOURCE_DP_B,
1051 INTEL_PIPE_CRC_SOURCE_DP_C,
1052 INTEL_PIPE_CRC_SOURCE_DP_D,
1053 INTEL_PIPE_CRC_SOURCE_AUTO,
1054 INTEL_PIPE_CRC_SOURCE_MAX,
1057 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1058 struct intel_pipe_crc {
1061 enum intel_pipe_crc_source source;
1064 struct i915_frontbuffer_tracking {
1068 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1075 struct i915_virtual_gpu {
1080 /* used in computing the new watermarks state */
1081 struct intel_wm_config {
1082 unsigned int num_pipes_active;
1083 bool sprites_enabled;
1084 bool sprites_scaled;
1087 struct i915_oa_format {
1092 struct i915_oa_reg {
1097 struct i915_oa_config {
1098 char uuid[UUID_STRING_LEN + 1];
1101 const struct i915_oa_reg *mux_regs;
1103 const struct i915_oa_reg *b_counter_regs;
1104 u32 b_counter_regs_len;
1105 const struct i915_oa_reg *flex_regs;
1108 struct attribute_group sysfs_metric;
1109 struct attribute *attrs[2];
1110 struct device_attribute sysfs_metric_id;
1115 struct i915_perf_stream;
1118 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1120 struct i915_perf_stream_ops {
1122 * @enable: Enables the collection of HW samples, either in response to
1123 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1124 * without `I915_PERF_FLAG_DISABLED`.
1126 void (*enable)(struct i915_perf_stream *stream);
1129 * @disable: Disables the collection of HW samples, either in response
1130 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1133 void (*disable)(struct i915_perf_stream *stream);
1136 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1137 * once there is something ready to read() for the stream
1139 void (*poll_wait)(struct i915_perf_stream *stream,
1144 * @wait_unlocked: For handling a blocking read, wait until there is
1145 * something to ready to read() for the stream. E.g. wait on the same
1146 * wait queue that would be passed to poll_wait().
1148 int (*wait_unlocked)(struct i915_perf_stream *stream);
1151 * @read: Copy buffered metrics as records to userspace
1152 * **buf**: the userspace, destination buffer
1153 * **count**: the number of bytes to copy, requested by userspace
1154 * **offset**: zero at the start of the read, updated as the read
1155 * proceeds, it represents how many bytes have been copied so far and
1156 * the buffer offset for copying the next record.
1158 * Copy as many buffered i915 perf samples and records for this stream
1159 * to userspace as will fit in the given buffer.
1161 * Only write complete records; returning -%ENOSPC if there isn't room
1162 * for a complete record.
1164 * Return any error condition that results in a short read such as
1165 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1166 * returning to userspace.
1168 int (*read)(struct i915_perf_stream *stream,
1174 * @destroy: Cleanup any stream specific resources.
1176 * The stream will always be disabled before this is called.
1178 void (*destroy)(struct i915_perf_stream *stream);
1182 * struct i915_perf_stream - state for a single open stream FD
1184 struct i915_perf_stream {
1186 * @dev_priv: i915 drm device
1188 struct drm_i915_private *dev_priv;
1191 * @link: Links the stream into ``&drm_i915_private->streams``
1193 struct list_head link;
1196 * @wakeref: As we keep the device awake while the perf stream is
1197 * active, we track our runtime pm reference for later release.
1199 intel_wakeref_t wakeref;
1202 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1203 * properties given when opening a stream, representing the contents
1204 * of a single sample as read() by userspace.
1209 * @sample_size: Considering the configured contents of a sample
1210 * combined with the required header size, this is the total size
1211 * of a single sample record.
1216 * @ctx: %NULL if measuring system-wide across all contexts or a
1217 * specific context that is being monitored.
1219 struct i915_gem_context *ctx;
1222 * @enabled: Whether the stream is currently enabled, considering
1223 * whether the stream was opened in a disabled state and based
1224 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1229 * @ops: The callbacks providing the implementation of this specific
1230 * type of configured stream.
1232 const struct i915_perf_stream_ops *ops;
1235 * @oa_config: The OA configuration used by the stream.
1237 struct i915_oa_config *oa_config;
1241 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1243 struct i915_oa_ops {
1245 * @is_valid_b_counter_reg: Validates register's address for
1246 * programming boolean counters for a particular platform.
1248 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1252 * @is_valid_mux_reg: Validates register's address for programming mux
1253 * for a particular platform.
1255 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1258 * @is_valid_flex_reg: Validates register's address for programming
1259 * flex EU filtering for a particular platform.
1261 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1264 * @enable_metric_set: Selects and applies any MUX configuration to set
1265 * up the Boolean and Custom (B/C) counters that are part of the
1266 * counter reports being sampled. May apply system constraints such as
1267 * disabling EU clock gating as required.
1269 int (*enable_metric_set)(struct i915_perf_stream *stream);
1272 * @disable_metric_set: Remove system constraints associated with using
1275 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1278 * @oa_enable: Enable periodic sampling
1280 void (*oa_enable)(struct i915_perf_stream *stream);
1283 * @oa_disable: Disable periodic sampling
1285 void (*oa_disable)(struct i915_perf_stream *stream);
1288 * @read: Copy data from the circular OA buffer into a given userspace
1291 int (*read)(struct i915_perf_stream *stream,
1297 * @oa_hw_tail_read: read the OA tail pointer register
1299 * In particular this enables us to share all the fiddly code for
1300 * handling the OA unit tail pointer race that affects multiple
1303 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1306 struct intel_cdclk_state {
1307 unsigned int cdclk, vco, ref, bypass;
1311 struct drm_i915_private {
1312 struct drm_device drm;
1314 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1315 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1316 struct intel_driver_caps caps;
1319 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1320 * end of stolen which we can optionally use to create GEM objects
1321 * backed by stolen memory. Note that stolen_usable_size tells us
1322 * exactly how much of this we are actually allowed to use, given that
1323 * some portion of it is in fact reserved for use by hardware functions.
1325 struct resource dsm;
1327 * Reseved portion of Data Stolen Memory
1329 struct resource dsm_reserved;
1332 * Stolen memory is segmented in hardware with different portions
1333 * offlimits to certain functions.
1335 * The drm_mm is initialised to the total accessible range, as found
1336 * from the PCI config. On Broadwell+, this is further restricted to
1337 * avoid the first page! The upper end of stolen memory is reserved for
1338 * hardware functions and similarly removed from the accessible range.
1340 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1342 struct intel_uncore uncore;
1344 struct i915_virtual_gpu vgpu;
1346 struct intel_gvt *gvt;
1348 struct intel_wopcm wopcm;
1350 struct intel_huc huc;
1351 struct intel_guc guc;
1353 struct intel_csr csr;
1355 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1357 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1358 * controller on different i2c buses. */
1359 struct mutex gmbus_mutex;
1362 * Base address of where the gmbus and gpio blocks are located (either
1363 * on PCH or on SoC for platforms without PCH).
1367 /* MMIO base address for MIPI regs */
1374 wait_queue_head_t gmbus_wait_queue;
1376 struct pci_dev *bridge_dev;
1377 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1378 /* Context used internally to idle the GPU and setup initial state */
1379 struct i915_gem_context *kernel_context;
1380 /* Context only to be used for injecting preemption commands */
1381 struct i915_gem_context *preempt_context;
1382 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1383 [MAX_ENGINE_INSTANCE + 1];
1385 struct resource mch_res;
1387 /* protects the irq masks */
1388 spinlock_t irq_lock;
1390 bool display_irqs_enabled;
1392 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1393 struct pm_qos_request pm_qos;
1395 /* Sideband mailbox protection */
1396 struct mutex sb_lock;
1397 struct pm_qos_request sb_qos;
1399 /** Cached value of IMR to avoid reads in updating the bitfield */
1402 u32 de_irq_mask[I915_MAX_PIPES];
1409 u32 pipestat_irq_mask[I915_MAX_PIPES];
1411 struct i915_hotplug hotplug;
1412 struct intel_fbc fbc;
1413 struct i915_drrs drrs;
1414 struct intel_opregion opregion;
1415 struct intel_vbt_data vbt;
1417 bool preserve_bios_swizzle;
1420 struct intel_overlay *overlay;
1422 /* backlight registers and fields in struct intel_panel */
1423 struct mutex backlight_lock;
1426 bool no_aux_handshake;
1428 /* protects panel power sequencer state */
1429 struct mutex pps_mutex;
1431 unsigned int fsb_freq, mem_freq, is_ddr3;
1432 unsigned int skl_preferred_vco_freq;
1433 unsigned int max_cdclk_freq;
1435 unsigned int max_dotclk_freq;
1436 unsigned int rawclk_freq;
1437 unsigned int hpll_freq;
1438 unsigned int fdi_pll_freq;
1439 unsigned int czclk_freq;
1443 * The current logical cdclk state.
1444 * See intel_atomic_state.cdclk.logical
1446 * For reading holding any crtc lock is sufficient,
1447 * for writing must hold all of them.
1449 struct intel_cdclk_state logical;
1451 * The current actual cdclk state.
1452 * See intel_atomic_state.cdclk.actual
1454 struct intel_cdclk_state actual;
1455 /* The current hardware cdclk state */
1456 struct intel_cdclk_state hw;
1458 int force_min_cdclk;
1462 * wq - Driver workqueue for GEM.
1464 * NOTE: Work items scheduled here are not allowed to grab any modeset
1465 * locks, for otherwise the flushing done in the pageflip code will
1466 * result in deadlocks.
1468 struct workqueue_struct *wq;
1470 /* ordered wq for modesets */
1471 struct workqueue_struct *modeset_wq;
1473 /* Display functions */
1474 struct drm_i915_display_funcs display;
1476 /* PCH chipset type */
1477 enum intel_pch pch_type;
1478 unsigned short pch_id;
1480 unsigned long quirks;
1482 struct drm_atomic_state *modeset_restore_state;
1483 struct drm_modeset_acquire_ctx reset_ctx;
1485 struct i915_ggtt ggtt; /* VM representing the global address space */
1487 struct i915_gem_mm mm;
1488 DECLARE_HASHTABLE(mm_structs, 7);
1489 struct mutex mm_lock;
1491 struct intel_ppat ppat;
1493 /* Kernel Modesetting */
1495 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1496 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1498 #ifdef CONFIG_DEBUG_FS
1499 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1502 /* dpll and cdclk state is protected by connection_mutex */
1503 int num_shared_dpll;
1504 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1505 const struct intel_dpll_mgr *dpll_mgr;
1508 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1509 * Must be global rather than per dpll, because on some platforms
1510 * plls share registers.
1512 struct mutex dpll_lock;
1514 unsigned int active_crtcs;
1515 /* minimum acceptable cdclk for each pipe */
1516 int min_cdclk[I915_MAX_PIPES];
1517 /* minimum acceptable voltage level for each pipe */
1518 u8 min_voltage_level[I915_MAX_PIPES];
1520 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1522 struct i915_wa_list gt_wa_list;
1524 struct i915_frontbuffer_tracking fb_tracking;
1526 struct intel_atomic_helper {
1527 struct llist_head free_list;
1528 struct work_struct free_work;
1533 bool mchbar_need_disable;
1535 struct intel_l3_parity l3_parity;
1539 * Cannot be determined by PCIID. You must always read a register.
1543 /* gen6+ GT PM state */
1544 struct intel_gen6_power_mgmt gt_pm;
1546 /* ilk-only ips/rps state. Everything in here is protected by the global
1547 * mchdev_lock in intel_pm.c */
1548 struct intel_ilk_power_mgmt ips;
1550 struct i915_power_domains power_domains;
1552 struct i915_psr psr;
1554 struct i915_gpu_error gpu_error;
1556 struct drm_i915_gem_object *vlv_pctx;
1558 /* list of fbdev register on this device */
1559 struct intel_fbdev *fbdev;
1560 struct work_struct fbdev_suspend_work;
1562 struct drm_property *broadcast_rgb_property;
1563 struct drm_property *force_audio_property;
1565 /* hda/i915 audio component */
1566 struct i915_audio_component *audio_component;
1567 bool audio_component_registered;
1569 * av_mutex - mutex for audio/video sync
1572 struct mutex av_mutex;
1573 int audio_power_refcount;
1577 struct list_head list;
1578 struct llist_head free_list;
1579 struct work_struct free_work;
1581 /* The hw wants to have a stable context identifier for the
1582 * lifetime of the context (for OA, PASID, faults, etc).
1583 * This is limited in execlists to 21 bits.
1586 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1587 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1588 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1589 struct list_head hw_id_list;
1594 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1595 u32 chv_phy_control;
1597 * Shadows for CHV DPLL_MD regs to keep the state
1598 * checker somewhat working in the presence hardware
1599 * crappiness (can't read out DPLL_MD for pipes B & C).
1601 u32 chv_dpll_md[I915_MAX_PIPES];
1605 bool power_domains_suspended;
1606 struct i915_suspend_saved_registers regfile;
1607 struct vlv_s0ix_state vlv_s0ix_state;
1610 I915_SAGV_UNKNOWN = 0,
1613 I915_SAGV_NOT_CONTROLLED
1618 * Raw watermark latency values:
1619 * in 0.1us units for WM0,
1620 * in 0.5us units for WM1+.
1629 * Raw watermark memory latency values
1630 * for SKL for all 8 levels
1635 /* current hardware state */
1637 struct ilk_wm_values hw;
1638 struct skl_ddb_values skl_hw;
1639 struct vlv_wm_values vlv;
1640 struct g4x_wm_values g4x;
1646 * Should be held around atomic WM register writing; also
1647 * protects * intel_crtc->wm.active and
1648 * cstate->wm.need_postvbl_update.
1650 struct mutex wm_mutex;
1653 * Set during HW readout of watermarks/DDB. Some platforms
1654 * need to know when we're still using BIOS-provided values
1655 * (which we don't fully trust).
1657 bool distrust_bios_wm;
1666 bool symmetric_memory;
1667 enum intel_dram_type {
1676 struct intel_bw_info {
1681 struct drm_private_obj bw_obj;
1683 struct intel_runtime_pm runtime_pm;
1688 struct kobject *metrics_kobj;
1689 struct ctl_table_header *sysctl_header;
1692 * Lock associated with adding/modifying/removing OA configs
1693 * in dev_priv->perf.metrics_idr.
1695 struct mutex metrics_lock;
1698 * List of dynamic configurations, you need to hold
1699 * dev_priv->perf.metrics_lock to access it.
1701 struct idr metrics_idr;
1704 * Lock associated with anything below within this structure
1705 * except exclusive_stream.
1708 struct list_head streams;
1712 * The stream currently using the OA unit. If accessed
1713 * outside a syscall associated to its file
1714 * descriptor, you need to hold
1715 * dev_priv->drm.struct_mutex.
1717 struct i915_perf_stream *exclusive_stream;
1719 struct intel_context *pinned_ctx;
1720 u32 specific_ctx_id;
1721 u32 specific_ctx_id_mask;
1723 struct hrtimer poll_check_timer;
1724 wait_queue_head_t poll_wq;
1728 * For rate limiting any notifications of spurious
1729 * invalid OA reports
1731 struct ratelimit_state spurious_report_rs;
1734 int period_exponent;
1736 struct i915_oa_config test_config;
1739 struct i915_vma *vma;
1746 * Locks reads and writes to all head/tail state
1748 * Consider: the head and tail pointer state
1749 * needs to be read consistently from a hrtimer
1750 * callback (atomic context) and read() fop
1751 * (user context) with tail pointer updates
1752 * happening in atomic context and head updates
1753 * in user context and the (unlikely)
1754 * possibility of read() errors needing to
1755 * reset all head/tail state.
1757 * Note: Contention or performance aren't
1758 * currently a significant concern here
1759 * considering the relatively low frequency of
1760 * hrtimer callbacks (5ms period) and that
1761 * reads typically only happen in response to a
1762 * hrtimer event and likely complete before the
1765 * Note: This lock is not held *while* reading
1766 * and copying data to userspace so the value
1767 * of head observed in htrimer callbacks won't
1768 * represent any partial consumption of data.
1770 spinlock_t ptr_lock;
1773 * One 'aging' tail pointer and one 'aged'
1774 * tail pointer ready to used for reading.
1776 * Initial values of 0xffffffff are invalid
1777 * and imply that an update is required
1778 * (and should be ignored by an attempted
1786 * Index for the aged tail ready to read()
1789 unsigned int aged_tail_idx;
1792 * A monotonic timestamp for when the current
1793 * aging tail pointer was read; used to
1794 * determine when it is old enough to trust.
1796 u64 aging_timestamp;
1799 * Although we can always read back the head
1800 * pointer register, we prefer to avoid
1801 * trusting the HW state, just to avoid any
1802 * risk that some hardware condition could
1803 * somehow bump the head pointer unpredictably
1804 * and cause us to forward the wrong OA buffer
1805 * data to userspace.
1810 u32 gen7_latched_oastatus1;
1811 u32 ctx_oactxctrl_offset;
1812 u32 ctx_flexeu0_offset;
1815 * The RPT_ID/reason field for Gen8+ includes a bit
1816 * to determine if the CTX ID in the report is valid
1817 * but the specific bit differs between Gen 8 and 9
1819 u32 gen8_valid_ctx_bit;
1821 struct i915_oa_ops ops;
1822 const struct i915_oa_format *oa_formats;
1826 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1828 struct i915_gt_timelines {
1829 struct mutex mutex; /* protects list, tainted by GPU */
1830 struct list_head active_list;
1832 /* Pack multiple timelines' seqnos into the same page */
1833 spinlock_t hwsp_lock;
1834 struct list_head hwsp_free_list;
1837 struct list_head active_rings;
1839 struct intel_wakeref wakeref;
1841 struct list_head closed_vma;
1842 spinlock_t closed_lock; /* guards the list of closed_vma */
1845 * Is the GPU currently considered idle, or busy executing
1846 * userspace requests? Whilst idle, we allow runtime power
1847 * management to power down the hardware and display clocks.
1848 * In order to reduce the effect on performance, there
1849 * is a slight delay before we do so.
1851 intel_wakeref_t awake;
1853 struct blocking_notifier_head pm_notifications;
1855 ktime_t last_init_time;
1857 struct i915_vma *scratch;
1861 struct notifier_block pm_notifier;
1864 * We leave the user IRQ off as much as possible,
1865 * but this means that requests will finish and never
1866 * be retired once the system goes idle. Set a timer to
1867 * fire periodically while the ring is running. When it
1868 * fires, go retire requests.
1870 struct delayed_work retire_work;
1873 * When we detect an idle GPU, we want to turn on
1874 * powersaving features. So once we see that there
1875 * are no more requests outstanding and no more
1876 * arrive within a small period of time, we fire
1877 * off the idle_work.
1879 struct work_struct idle_work;
1882 /* For i945gm vblank irq vs. C3 workaround */
1884 struct work_struct work;
1885 struct pm_qos_request pm_qos;
1886 u8 c3_disable_latency;
1890 /* perform PHY state sanity checks? */
1891 bool chv_phy_assert[2];
1895 /* Used to save the pipe-to-encoder mapping for audio */
1896 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1898 /* necessary resource sharing with HDMI LPE audio driver. */
1900 struct platform_device *platdev;
1904 struct i915_pmu pmu;
1906 struct i915_hdcp_comp_master *hdcp_master;
1907 bool hdcp_comp_added;
1909 /* Mutex to protect the above hdcp component related values. */
1910 struct mutex hdcp_comp_mutex;
1913 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1914 * will be rejected. Instead look for a better place.
1918 struct dram_dimm_info {
1919 u8 size, width, ranks;
1922 struct dram_channel_info {
1923 struct dram_dimm_info dimm_l, dimm_s;
1928 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1930 return container_of(dev, struct drm_i915_private, drm);
1933 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1935 return to_i915(dev_get_drvdata(kdev));
1938 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
1940 return container_of(wopcm, struct drm_i915_private, wopcm);
1943 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1945 return container_of(guc, struct drm_i915_private, guc);
1948 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
1950 return container_of(huc, struct drm_i915_private, huc);
1953 static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
1955 return container_of(uncore, struct drm_i915_private, uncore);
1958 /* Simple iterator over all initialised engines */
1959 #define for_each_engine(engine__, dev_priv__, id__) \
1961 (id__) < I915_NUM_ENGINES; \
1963 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1965 /* Iterator over subset of engines selected by mask */
1966 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
1967 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
1969 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
1972 enum hdmi_force_audio {
1973 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1974 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1975 HDMI_AUDIO_AUTO, /* trust EDID */
1976 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1979 #define I915_GTT_OFFSET_NONE ((u32)-1)
1982 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1983 * considered to be the frontbuffer for the given plane interface-wise. This
1984 * doesn't mean that the hw necessarily already scans it out, but that any
1985 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1987 * We have one bit per pipe and per scanout plane type.
1989 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1990 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1991 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1992 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1993 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1995 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1996 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1997 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1998 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1999 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2001 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2002 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2003 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2005 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2006 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2008 #define REVID_FOREVER 0xff
2009 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2011 #define INTEL_GEN_MASK(s, e) ( \
2012 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2013 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2014 GENMASK((e) - 1, (s) - 1))
2016 /* Returns true if Gen is in inclusive range [Start, End] */
2017 #define IS_GEN_RANGE(dev_priv, s, e) \
2018 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2020 #define IS_GEN(dev_priv, n) \
2021 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2022 INTEL_INFO(dev_priv)->gen == (n))
2025 * Return true if revision is in range [since,until] inclusive.
2027 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2029 #define IS_REVID(p, since, until) \
2030 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2032 static __always_inline unsigned int
2033 __platform_mask_index(const struct intel_runtime_info *info,
2034 enum intel_platform p)
2036 const unsigned int pbits =
2037 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2039 /* Expand the platform_mask array if this fails. */
2040 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
2041 pbits * ARRAY_SIZE(info->platform_mask));
2046 static __always_inline unsigned int
2047 __platform_mask_bit(const struct intel_runtime_info *info,
2048 enum intel_platform p)
2050 const unsigned int pbits =
2051 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2053 return p % pbits + INTEL_SUBPLATFORM_BITS;
2057 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
2059 const unsigned int pi = __platform_mask_index(info, p);
2061 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
2064 static __always_inline bool
2065 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
2067 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2068 const unsigned int pi = __platform_mask_index(info, p);
2069 const unsigned int pb = __platform_mask_bit(info, p);
2071 BUILD_BUG_ON(!__builtin_constant_p(p));
2073 return info->platform_mask[pi] & BIT(pb);
2076 static __always_inline bool
2077 IS_SUBPLATFORM(const struct drm_i915_private *i915,
2078 enum intel_platform p, unsigned int s)
2080 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2081 const unsigned int pi = __platform_mask_index(info, p);
2082 const unsigned int pb = __platform_mask_bit(info, p);
2083 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
2084 const u32 mask = info->platform_mask[pi];
2086 BUILD_BUG_ON(!__builtin_constant_p(p));
2087 BUILD_BUG_ON(!__builtin_constant_p(s));
2088 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
2090 /* Shift and test on the MSB position so sign flag can be used. */
2091 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
2094 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2096 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2097 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2098 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2099 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2100 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2101 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2102 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2103 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2104 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2105 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2106 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2107 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2108 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2109 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2110 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2111 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
2112 #define IS_IRONLAKE_M(dev_priv) \
2113 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
2114 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2115 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2116 INTEL_INFO(dev_priv)->gt == 1)
2117 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2118 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2119 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2120 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2121 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2122 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2123 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2124 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2125 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2126 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2127 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2128 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2129 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2130 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2131 #define IS_BDW_ULT(dev_priv) \
2132 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
2133 #define IS_BDW_ULX(dev_priv) \
2134 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2135 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2136 INTEL_INFO(dev_priv)->gt == 3)
2137 #define IS_HSW_ULT(dev_priv) \
2138 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2139 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2140 INTEL_INFO(dev_priv)->gt == 3)
2141 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2142 INTEL_INFO(dev_priv)->gt == 1)
2143 /* ULX machines are also considered ULT. */
2144 #define IS_HSW_ULX(dev_priv) \
2145 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
2146 #define IS_SKL_ULT(dev_priv) \
2147 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
2148 #define IS_SKL_ULX(dev_priv) \
2149 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
2150 #define IS_KBL_ULT(dev_priv) \
2151 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
2152 #define IS_KBL_ULX(dev_priv) \
2153 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2154 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2155 INTEL_INFO(dev_priv)->gt == 2)
2156 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2157 INTEL_INFO(dev_priv)->gt == 3)
2158 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2159 INTEL_INFO(dev_priv)->gt == 4)
2160 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2161 INTEL_INFO(dev_priv)->gt == 2)
2162 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2163 INTEL_INFO(dev_priv)->gt == 3)
2164 #define IS_CFL_ULT(dev_priv) \
2165 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2166 #define IS_CFL_ULX(dev_priv) \
2167 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
2168 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2169 INTEL_INFO(dev_priv)->gt == 2)
2170 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2171 INTEL_INFO(dev_priv)->gt == 3)
2172 #define IS_CNL_WITH_PORT_F(dev_priv) \
2173 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2174 #define IS_ICL_WITH_PORT_F(dev_priv) \
2175 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2177 #define SKL_REVID_A0 0x0
2178 #define SKL_REVID_B0 0x1
2179 #define SKL_REVID_C0 0x2
2180 #define SKL_REVID_D0 0x3
2181 #define SKL_REVID_E0 0x4
2182 #define SKL_REVID_F0 0x5
2183 #define SKL_REVID_G0 0x6
2184 #define SKL_REVID_H0 0x7
2186 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2188 #define BXT_REVID_A0 0x0
2189 #define BXT_REVID_A1 0x1
2190 #define BXT_REVID_B0 0x3
2191 #define BXT_REVID_B_LAST 0x8
2192 #define BXT_REVID_C0 0x9
2194 #define IS_BXT_REVID(dev_priv, since, until) \
2195 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2197 #define KBL_REVID_A0 0x0
2198 #define KBL_REVID_B0 0x1
2199 #define KBL_REVID_C0 0x2
2200 #define KBL_REVID_D0 0x3
2201 #define KBL_REVID_E0 0x4
2203 #define IS_KBL_REVID(dev_priv, since, until) \
2204 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2206 #define GLK_REVID_A0 0x0
2207 #define GLK_REVID_A1 0x1
2209 #define IS_GLK_REVID(dev_priv, since, until) \
2210 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2212 #define CNL_REVID_A0 0x0
2213 #define CNL_REVID_B0 0x1
2214 #define CNL_REVID_C0 0x2
2216 #define IS_CNL_REVID(p, since, until) \
2217 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2219 #define ICL_REVID_A0 0x0
2220 #define ICL_REVID_A2 0x1
2221 #define ICL_REVID_B0 0x3
2222 #define ICL_REVID_B2 0x4
2223 #define ICL_REVID_C0 0x5
2225 #define IS_ICL_REVID(p, since, until) \
2226 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2228 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2229 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2230 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2232 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2234 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2235 unsigned int first__ = (first); \
2236 unsigned int count__ = (count); \
2237 (INTEL_INFO(dev_priv)->engine_mask & \
2238 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2240 #define VDBOX_MASK(dev_priv) \
2241 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2242 #define VEBOX_MASK(dev_priv) \
2243 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2245 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2246 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2247 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2248 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2249 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2251 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2253 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2254 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2255 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2256 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2257 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2258 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2260 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2262 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2263 #define HAS_PPGTT(dev_priv) \
2264 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2265 #define HAS_FULL_PPGTT(dev_priv) \
2266 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2268 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2269 GEM_BUG_ON((sizes) == 0); \
2270 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2273 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2274 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2275 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2277 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2278 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2280 /* WaRsDisableCoarsePowerGating:skl,cnl */
2281 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2282 (IS_CANNONLAKE(dev_priv) || \
2283 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2285 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2286 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2287 IS_GEMINILAKE(dev_priv) || \
2288 IS_KABYLAKE(dev_priv))
2290 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2291 * rows, which changed the alignment requirements and fence programming.
2293 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2294 !(IS_I915G(dev_priv) || \
2295 IS_I915GM(dev_priv)))
2296 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2297 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2299 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2300 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2301 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2303 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2305 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2307 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2308 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2309 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2310 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2312 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2313 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2314 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2316 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
2318 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2320 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2321 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2323 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2326 * For now, anything with a GuC requires uCode loading, and then supports
2327 * command submission once loaded. But these are logically independent
2328 * properties, so we have separate macros to test them.
2330 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2331 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2332 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2334 /* For now, anything with a GuC has also HuC */
2335 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2336 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2338 /* Having a GuC is not the same as using a GuC */
2339 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2340 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2341 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2343 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2345 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2346 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2347 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2348 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2349 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2350 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2351 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2352 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2353 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2354 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2355 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2356 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2357 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2358 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
2359 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2360 #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
2361 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2362 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2363 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2365 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2366 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2367 #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
2368 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2369 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2370 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2371 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2372 #define HAS_PCH_LPT_LP(dev_priv) \
2373 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2374 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2375 #define HAS_PCH_LPT_H(dev_priv) \
2376 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2377 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2378 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2379 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2380 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2381 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2383 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2385 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2387 /* DPF == dynamic parity feature */
2388 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2389 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2390 2 : HAS_L3_DPF(dev_priv))
2392 #define GT_FREQUENCY_MULTIPLIER 50
2393 #define GEN9_FREQ_SCALER 3
2395 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2397 #include "i915_trace.h"
2399 static inline bool intel_vtd_active(void)
2401 #ifdef CONFIG_INTEL_IOMMU
2402 if (intel_iommu_gfx_mapped)
2408 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2410 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2414 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2416 return IS_BROXTON(dev_priv) && intel_vtd_active();
2421 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2422 const char *fmt, ...);
2424 #define i915_report_error(dev_priv, fmt, ...) \
2425 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2427 #ifdef CONFIG_COMPAT
2428 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2431 #define i915_compat_ioctl NULL
2433 extern const struct dev_pm_ops i915_pm_ops;
2435 extern int i915_driver_load(struct pci_dev *pdev,
2436 const struct pci_device_id *ent);
2437 extern void i915_driver_unload(struct drm_device *dev);
2439 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2440 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2441 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2443 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2445 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2447 unsigned long delay;
2449 if (unlikely(!i915_modparams.enable_hangcheck))
2452 /* Don't continually defer the hangcheck so that it is always run at
2453 * least once after work has been scheduled on any ring. Otherwise,
2454 * we will ignore a hung ring if a second ring is kept busy.
2457 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2458 queue_delayed_work(system_long_wq,
2459 &dev_priv->gpu_error.hangcheck_work, delay);
2462 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2464 return dev_priv->gvt;
2467 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2469 return dev_priv->vgpu.active;
2473 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2474 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2475 void i915_gem_sanitize(struct drm_i915_private *i915);
2476 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2477 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2478 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2479 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2481 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2483 if (!atomic_read(&i915->mm.free_count))
2486 /* A single pass should suffice to release all the freed objects (along
2487 * most call paths) , but be a little more paranoid in that freeing
2488 * the objects does take a little amount of time, during which the rcu
2489 * callbacks could have added new objects into the freed list, and
2490 * armed the work again.
2494 } while (flush_work(&i915->mm.free_work));
2497 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2500 * Similar to objects above (see i915_gem_drain_freed-objects), in
2501 * general we have workers that are armed by RCU and then rearm
2502 * themselves in their callbacks. To be paranoid, we need to
2503 * drain the workqueue a second time after waiting for the RCU
2504 * grace period so that we catch work queued via RCU from the first
2505 * pass. As neither drain_workqueue() nor flush_workqueue() report
2506 * a result, we make an assumption that we only don't require more
2507 * than 3 passes to catch all _recursive_ RCU delayed work.
2513 i915_gem_drain_freed_objects(i915);
2515 drain_workqueue(i915->wq);
2518 struct i915_vma * __must_check
2519 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2520 const struct i915_ggtt_view *view,
2525 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2527 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2529 static inline int __must_check
2530 i915_mutex_lock_interruptible(struct drm_device *dev)
2532 return mutex_lock_interruptible(&dev->struct_mutex);
2535 int i915_gem_dumb_create(struct drm_file *file_priv,
2536 struct drm_device *dev,
2537 struct drm_mode_create_dumb *args);
2538 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2539 u32 handle, u64 *offset);
2540 int i915_gem_mmap_gtt_version(void);
2542 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2543 struct drm_i915_gem_object *new,
2544 unsigned frontbuffer_bits);
2546 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
2548 static inline bool __i915_wedged(struct i915_gpu_error *error)
2550 return unlikely(test_bit(I915_WEDGED, &error->flags));
2553 static inline bool i915_reset_failed(struct drm_i915_private *i915)
2555 return __i915_wedged(&i915->gpu_error);
2558 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2560 return READ_ONCE(error->reset_count);
2563 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
2564 struct intel_engine_cs *engine)
2566 return READ_ONCE(error->reset_engine_count[engine->id]);
2569 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
2570 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
2572 void i915_gem_init_mmio(struct drm_i915_private *i915);
2573 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
2574 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
2575 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
2576 void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
2577 void i915_gem_fini(struct drm_i915_private *dev_priv);
2578 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
2579 unsigned int flags, long timeout);
2580 void i915_gem_suspend(struct drm_i915_private *dev_priv);
2581 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
2582 void i915_gem_resume(struct drm_i915_private *dev_priv);
2583 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
2585 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
2586 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2588 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2589 enum i915_cache_level cache_level);
2591 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2592 struct dma_buf *dma_buf);
2594 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
2596 static inline struct i915_gem_context *
2597 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
2599 return idr_find(&file_priv->context_idr, id);
2602 static inline struct i915_gem_context *
2603 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2605 struct i915_gem_context *ctx;
2608 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
2609 if (ctx && !kref_get_unless_zero(&ctx->ref))
2616 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
2617 struct drm_file *file);
2618 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
2619 struct drm_file *file);
2620 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
2621 struct drm_file *file);
2622 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
2623 struct intel_context *ce,
2626 /* i915_gem_evict.c */
2627 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
2628 u64 min_size, u64 alignment,
2629 unsigned cache_level,
2632 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2633 struct drm_mm_node *node,
2634 unsigned int flags);
2635 int i915_gem_evict_vm(struct i915_address_space *vm);
2637 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
2639 /* belongs in i915_gem_gtt.h */
2640 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
2643 if (INTEL_GEN(dev_priv) < 6)
2644 intel_gtt_chipset_flush();
2647 /* i915_gem_stolen.c */
2648 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
2649 struct drm_mm_node *node, u64 size,
2650 unsigned alignment);
2651 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
2652 struct drm_mm_node *node, u64 size,
2653 unsigned alignment, u64 start,
2655 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
2656 struct drm_mm_node *node);
2657 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
2658 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
2659 struct drm_i915_gem_object *
2660 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
2661 resource_size_t size);
2662 struct drm_i915_gem_object *
2663 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
2664 resource_size_t stolen_offset,
2665 resource_size_t gtt_offset,
2666 resource_size_t size);
2668 /* i915_gem_internal.c */
2669 struct drm_i915_gem_object *
2670 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2673 /* i915_gem_shrinker.c */
2674 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
2675 unsigned long target,
2676 unsigned long *nr_scanned,
2678 #define I915_SHRINK_UNBOUND BIT(0)
2679 #define I915_SHRINK_BOUND BIT(1)
2680 #define I915_SHRINK_ACTIVE BIT(2)
2681 #define I915_SHRINK_VMAPS BIT(3)
2682 #define I915_SHRINK_WRITEBACK BIT(4)
2684 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
2685 void i915_gem_shrinker_register(struct drm_i915_private *i915);
2686 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
2687 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
2688 struct mutex *mutex);
2690 /* i915_gem_tiling.c */
2691 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2693 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2695 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2696 i915_gem_object_is_tiled(obj);
2699 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2700 unsigned int tiling, unsigned int stride);
2701 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2702 unsigned int tiling, unsigned int stride);
2704 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2706 /* i915_cmd_parser.c */
2707 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2708 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2709 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2710 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
2711 struct drm_i915_gem_object *batch_obj,
2712 struct drm_i915_gem_object *shadow_batch_obj,
2713 u32 batch_start_offset,
2718 extern void i915_perf_init(struct drm_i915_private *dev_priv);
2719 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
2720 extern void i915_perf_register(struct drm_i915_private *dev_priv);
2721 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
2723 /* i915_suspend.c */
2724 extern int i915_save_state(struct drm_i915_private *dev_priv);
2725 extern int i915_restore_state(struct drm_i915_private *dev_priv);
2728 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
2729 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
2731 /* intel_device_info.c */
2732 static inline struct intel_device_info *
2733 mkwrite_device_info(struct drm_i915_private *dev_priv)
2735 return (struct intel_device_info *)INTEL_INFO(dev_priv);
2739 extern void intel_modeset_init_hw(struct drm_device *dev);
2740 extern int intel_modeset_init(struct drm_device *dev);
2741 extern void intel_modeset_cleanup(struct drm_device *dev);
2742 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
2744 extern void intel_display_resume(struct drm_device *dev);
2745 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
2746 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
2747 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
2749 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2750 struct drm_file *file);
2752 extern struct intel_display_error_state *
2753 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
2754 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2755 struct intel_display_error_state *error);
2757 #define __I915_REG_OP(op__, dev_priv__, ...) \
2758 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2760 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
2761 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2763 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
2765 /* These are untraced mmio-accessors that are only valid to be used inside
2766 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
2769 * Think twice, and think again, before using these.
2771 * As an example, these accessors can possibly be used between:
2773 * spin_lock_irq(&dev_priv->uncore.lock);
2774 * intel_uncore_forcewake_get__locked();
2778 * intel_uncore_forcewake_put__locked();
2779 * spin_unlock_irq(&dev_priv->uncore.lock);
2782 * Note: some registers may not need forcewake held, so
2783 * intel_uncore_forcewake_{get,put} can be omitted, see
2784 * intel_uncore_forcewake_for_reg().
2786 * Certain architectures will die if the same cacheline is concurrently accessed
2787 * by different clients (e.g. on Ivybridge). Access to registers should
2788 * therefore generally be serialised, by either the dev_priv->uncore.lock or
2789 * a more localised lock guarding all access to that bank of registers.
2791 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2792 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2794 /* "Broadcast RGB" property */
2795 #define INTEL_BROADCAST_RGB_AUTO 0
2796 #define INTEL_BROADCAST_RGB_FULL 1
2797 #define INTEL_BROADCAST_RGB_LIMITED 2
2799 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
2800 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
2802 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
2803 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
2804 * perform the operation. To check beforehand, pass in the parameters to
2805 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
2806 * you only need to pass in the minor offsets, page-aligned pointers are
2809 * For just checking for SSE4.1, in the foreknowledge that the future use
2810 * will be correctly aligned, just use i915_has_memcpy_from_wc().
2812 #define i915_can_memcpy_from_wc(dst, src, len) \
2813 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
2815 #define i915_has_memcpy_from_wc() \
2816 i915_memcpy_from_wc(NULL, NULL, 0)
2819 int remap_io_mapping(struct vm_area_struct *vma,
2820 unsigned long addr, unsigned long pfn, unsigned long size,
2821 struct io_mapping *iomap);
2823 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2825 if (INTEL_GEN(i915) >= 10)
2826 return CNL_HWS_CSB_WRITE_INDEX;
2828 return I915_HWS_CSB_WRITE_INDEX;
2831 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
2833 return i915_ggtt_offset(i915->gt.scratch);
2836 static inline enum i915_map_type
2837 i915_coherent_map_type(struct drm_i915_private *i915)
2839 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2842 static inline void add_taint_for_CI(unsigned int taint)
2845 * The system is "ok", just about surviving for the user, but
2846 * CI results are now unreliable as the HW is very suspect.
2847 * CI checks the taint state after every test and will reboot
2848 * the machine if the kernel is tainted.
2850 add_taint(taint, LOCKDEP_STILL_OK);