1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_bios.h"
59 #include "intel_dpll_mgr.h"
61 #include "intel_lrc.h"
62 #include "intel_ringbuffer.h"
65 #include "i915_gem_context.h"
66 #include "i915_gem_fence_reg.h"
67 #include "i915_gem_object.h"
68 #include "i915_gem_gtt.h"
69 #include "i915_gem_render_state.h"
70 #include "i915_gem_request.h"
71 #include "i915_gem_timeline.h"
75 #include "intel_gvt.h"
77 /* General customization:
80 #define DRIVER_NAME "i915"
81 #define DRIVER_DESC "Intel Graphics"
82 #define DRIVER_DATE "20170306"
83 #define DRIVER_TIMESTAMP 1488785683
86 /* Many gcc seem to no see through this and fall over :( */
88 #define WARN_ON(x) ({ \
89 bool __i915_warn_cond = (x); \
90 if (__builtin_constant_p(__i915_warn_cond)) \
91 BUILD_BUG_ON(__i915_warn_cond); \
92 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
101 (long) (x), __func__);
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 bool __i915_inject_load_failure(const char *func, int line);
122 #define i915_inject_load_failure() \
123 __i915_inject_load_failure(__func__, __LINE__)
127 } uint_fixed_16_16_t;
129 #define FP_16_16_MAX ({ \
130 uint_fixed_16_16_t fp; \
135 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
137 uint_fixed_16_16_t fp;
145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
147 return DIV_ROUND_UP(fp.val, 1 << 16);
150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
155 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
156 uint_fixed_16_16_t min2)
158 uint_fixed_16_16_t min;
160 min.val = min(min1.val, min2.val);
164 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
165 uint_fixed_16_16_t max2)
167 uint_fixed_16_16_t max;
169 max.val = max(max1.val, max2.val);
173 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
176 uint_fixed_16_16_t fp, res;
178 fp = u32_to_fixed_16_16(val);
179 res.val = DIV_ROUND_UP(fp.val, d);
183 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
186 uint_fixed_16_16_t res;
189 interm_val = (uint64_t)val << 16;
190 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
191 WARN_ON(interm_val >> 32);
192 res.val = (uint32_t) interm_val;
197 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
198 uint_fixed_16_16_t mul)
200 uint64_t intermediate_val;
201 uint_fixed_16_16_t fp;
203 intermediate_val = (uint64_t) val * mul.val;
204 WARN_ON(intermediate_val >> 32);
205 fp.val = (uint32_t) intermediate_val;
209 static inline const char *yesno(bool v)
211 return v ? "yes" : "no";
214 static inline const char *onoff(bool v)
216 return v ? "on" : "off";
219 static inline const char *enableddisabled(bool v)
221 return v ? "enabled" : "disabled";
230 I915_MAX_PIPES = _PIPE_EDP
232 #define pipe_name(p) ((p) + 'A')
244 static inline const char *transcoder_name(enum transcoder transcoder)
246 switch (transcoder) {
255 case TRANSCODER_DSI_A:
257 case TRANSCODER_DSI_C:
264 static inline bool transcoder_is_dsi(enum transcoder transcoder)
266 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
270 * Global legacy plane identifier. Valid only for primary/sprite
271 * planes on pre-g4x, and only for primary planes on g4x+.
278 #define plane_name(p) ((p) + 'A')
280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
283 * Per-pipe plane identifier.
284 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
285 * number of planes per CRTC. Not all platforms really have this many planes,
286 * which means some arrays of size I915_MAX_PLANES may have unused entries
287 * between the topmost sprite plane and the cursor plane.
289 * This is expected to be passed to various register macros
290 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
301 #define for_each_plane_id_on_crtc(__crtc, __p) \
302 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
303 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
314 #define port_name(p) ((p) + 'A')
316 #define I915_NUM_PHYS_VLV 2
329 enum intel_display_power_domain {
333 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
334 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
335 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
336 POWER_DOMAIN_TRANSCODER_A,
337 POWER_DOMAIN_TRANSCODER_B,
338 POWER_DOMAIN_TRANSCODER_C,
339 POWER_DOMAIN_TRANSCODER_EDP,
340 POWER_DOMAIN_TRANSCODER_DSI_A,
341 POWER_DOMAIN_TRANSCODER_DSI_C,
342 POWER_DOMAIN_PORT_DDI_A_LANES,
343 POWER_DOMAIN_PORT_DDI_B_LANES,
344 POWER_DOMAIN_PORT_DDI_C_LANES,
345 POWER_DOMAIN_PORT_DDI_D_LANES,
346 POWER_DOMAIN_PORT_DDI_E_LANES,
347 POWER_DOMAIN_PORT_DDI_A_IO,
348 POWER_DOMAIN_PORT_DDI_B_IO,
349 POWER_DOMAIN_PORT_DDI_C_IO,
350 POWER_DOMAIN_PORT_DDI_D_IO,
351 POWER_DOMAIN_PORT_DDI_E_IO,
352 POWER_DOMAIN_PORT_DSI,
353 POWER_DOMAIN_PORT_CRT,
354 POWER_DOMAIN_PORT_OTHER,
363 POWER_DOMAIN_MODESET,
369 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
370 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
371 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
372 #define POWER_DOMAIN_TRANSCODER(tran) \
373 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
374 (tran) + POWER_DOMAIN_TRANSCODER_A)
378 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
390 #define for_each_hpd_pin(__pin) \
391 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
393 #define HPD_STORM_DEFAULT_THRESHOLD 5
395 struct i915_hotplug {
396 struct work_struct hotplug_work;
399 unsigned long last_jiffies;
404 HPD_MARK_DISABLED = 2
406 } stats[HPD_NUM_PINS];
408 struct delayed_work reenable_work;
410 struct intel_digital_port *irq_port[I915_MAX_PORTS];
413 struct work_struct dig_port_work;
415 struct work_struct poll_init_work;
418 unsigned int hpd_storm_threshold;
421 * if we get a HPD irq from DP and a HPD irq from non-DP
422 * the non-DP HPD could block the workqueue on a mode config
423 * mutex getting, that userspace may have taken. However
424 * userspace is waiting on the DP workqueue to run which is
425 * blocked behind the non-DP one.
427 struct workqueue_struct *dp_wq;
430 #define I915_GEM_GPU_DOMAINS \
431 (I915_GEM_DOMAIN_RENDER | \
432 I915_GEM_DOMAIN_SAMPLER | \
433 I915_GEM_DOMAIN_COMMAND | \
434 I915_GEM_DOMAIN_INSTRUCTION | \
435 I915_GEM_DOMAIN_VERTEX)
437 #define for_each_pipe(__dev_priv, __p) \
438 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
439 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
440 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
441 for_each_if ((__mask) & (1 << (__p)))
442 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
444 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
446 #define for_each_sprite(__dev_priv, __p, __s) \
448 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
451 #define for_each_port_masked(__port, __ports_mask) \
452 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
453 for_each_if ((__ports_mask) & (1 << (__port)))
455 #define for_each_crtc(dev, crtc) \
456 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
458 #define for_each_intel_plane(dev, intel_plane) \
459 list_for_each_entry(intel_plane, \
460 &(dev)->mode_config.plane_list, \
463 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
464 list_for_each_entry(intel_plane, \
465 &(dev)->mode_config.plane_list, \
467 for_each_if ((plane_mask) & \
468 (1 << drm_plane_index(&intel_plane->base)))
470 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
471 list_for_each_entry(intel_plane, \
472 &(dev)->mode_config.plane_list, \
474 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
476 #define for_each_intel_crtc(dev, intel_crtc) \
477 list_for_each_entry(intel_crtc, \
478 &(dev)->mode_config.crtc_list, \
481 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
482 list_for_each_entry(intel_crtc, \
483 &(dev)->mode_config.crtc_list, \
485 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
487 #define for_each_intel_encoder(dev, intel_encoder) \
488 list_for_each_entry(intel_encoder, \
489 &(dev)->mode_config.encoder_list, \
492 #define for_each_intel_connector(dev, intel_connector) \
493 list_for_each_entry(intel_connector, \
494 &(dev)->mode_config.connector_list, \
497 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
498 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
499 for_each_if ((intel_encoder)->base.crtc == (__crtc))
501 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
502 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
503 for_each_if ((intel_connector)->base.encoder == (__encoder))
505 #define for_each_power_domain(domain, mask) \
506 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
507 for_each_if (BIT_ULL(domain) & (mask))
509 #define for_each_power_well(__dev_priv, __power_well) \
510 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
511 (__power_well) - (__dev_priv)->power_domains.power_wells < \
512 (__dev_priv)->power_domains.power_well_count; \
515 #define for_each_power_well_rev(__dev_priv, __power_well) \
516 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
517 (__dev_priv)->power_domains.power_well_count - 1; \
518 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
521 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
522 for_each_power_well(__dev_priv, __power_well) \
523 for_each_if ((__power_well)->domains & (__domain_mask))
525 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
526 for_each_power_well_rev(__dev_priv, __power_well) \
527 for_each_if ((__power_well)->domains & (__domain_mask))
529 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
531 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
532 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
533 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
535 for_each_if (plane_state)
537 struct drm_i915_private;
538 struct i915_mm_struct;
539 struct i915_mmu_object;
541 struct drm_i915_file_private {
542 struct drm_i915_private *dev_priv;
543 struct drm_file *file;
547 struct list_head request_list;
548 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
549 * chosen to prevent the CPU getting more than a frame ahead of the GPU
550 * (when using lax throttling for the frontbuffer). We also use it to
551 * offer free GPU waitboosts for severely congested workloads.
553 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
555 struct idr context_idr;
557 struct intel_rps_client {
558 struct list_head link;
562 unsigned int bsd_engine;
564 /* Client can have a maximum of 3 contexts banned before
565 * it is denied of creating new contexts. As one context
566 * ban needs 4 consecutive hangs, and more if there is
567 * progress in between, this is a last resort stop gap measure
568 * to limit the badly behaving clients access to gpu.
570 #define I915_MAX_CLIENT_CONTEXT_BANS 3
574 /* Used by dp and fdi links */
575 struct intel_link_m_n {
583 void intel_link_compute_m_n(int bpp, int nlanes,
584 int pixel_clock, int link_clock,
585 struct intel_link_m_n *m_n);
587 /* Interface history:
590 * 1.2: Add Power Management
591 * 1.3: Add vblank support
592 * 1.4: Fix cmdbuffer path, add heap destroy
593 * 1.5: Add vblank pipe configuration
594 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
595 * - Support vertical blank on secondary display pipe
597 #define DRIVER_MAJOR 1
598 #define DRIVER_MINOR 6
599 #define DRIVER_PATCHLEVEL 0
601 struct opregion_header;
602 struct opregion_acpi;
603 struct opregion_swsci;
604 struct opregion_asle;
606 struct intel_opregion {
607 struct opregion_header *header;
608 struct opregion_acpi *acpi;
609 struct opregion_swsci *swsci;
610 u32 swsci_gbda_sub_functions;
611 u32 swsci_sbcb_sub_functions;
612 struct opregion_asle *asle;
617 struct work_struct asle_work;
619 #define OPREGION_SIZE (8*1024)
621 struct intel_overlay;
622 struct intel_overlay_error_state;
624 struct sdvo_device_mapping {
633 struct intel_connector;
634 struct intel_encoder;
635 struct intel_atomic_state;
636 struct intel_crtc_state;
637 struct intel_initial_plane_config;
641 struct intel_cdclk_state;
643 struct drm_i915_display_funcs {
644 void (*get_cdclk)(struct drm_i915_private *dev_priv,
645 struct intel_cdclk_state *cdclk_state);
646 void (*set_cdclk)(struct drm_i915_private *dev_priv,
647 const struct intel_cdclk_state *cdclk_state);
648 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
649 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
650 int (*compute_intermediate_wm)(struct drm_device *dev,
651 struct intel_crtc *intel_crtc,
652 struct intel_crtc_state *newstate);
653 void (*initial_watermarks)(struct intel_atomic_state *state,
654 struct intel_crtc_state *cstate);
655 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
656 struct intel_crtc_state *cstate);
657 void (*optimize_watermarks)(struct intel_atomic_state *state,
658 struct intel_crtc_state *cstate);
659 int (*compute_global_watermarks)(struct drm_atomic_state *state);
660 void (*update_wm)(struct intel_crtc *crtc);
661 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
662 /* Returns the active state of the crtc, and if the crtc is active,
663 * fills out the pipe-config with the hw state. */
664 bool (*get_pipe_config)(struct intel_crtc *,
665 struct intel_crtc_state *);
666 void (*get_initial_plane_config)(struct intel_crtc *,
667 struct intel_initial_plane_config *);
668 int (*crtc_compute_clock)(struct intel_crtc *crtc,
669 struct intel_crtc_state *crtc_state);
670 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
671 struct drm_atomic_state *old_state);
672 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
673 struct drm_atomic_state *old_state);
674 void (*update_crtcs)(struct drm_atomic_state *state,
675 unsigned int *crtc_vblank_mask);
676 void (*audio_codec_enable)(struct drm_connector *connector,
677 struct intel_encoder *encoder,
678 const struct drm_display_mode *adjusted_mode);
679 void (*audio_codec_disable)(struct intel_encoder *encoder);
680 void (*fdi_link_train)(struct intel_crtc *crtc,
681 const struct intel_crtc_state *crtc_state);
682 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
683 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
684 struct drm_framebuffer *fb,
685 struct drm_i915_gem_object *obj,
686 struct drm_i915_gem_request *req,
688 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
689 /* clock updates for mode set */
691 /* render clock increase/decrease */
692 /* display clock increase/decrease */
693 /* pll clock increase/decrease */
695 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
696 void (*load_luts)(struct drm_crtc_state *crtc_state);
699 enum forcewake_domain_id {
700 FW_DOMAIN_ID_RENDER = 0,
701 FW_DOMAIN_ID_BLITTER,
707 enum forcewake_domains {
708 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
709 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
710 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
711 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
716 #define FW_REG_READ (1)
717 #define FW_REG_WRITE (2)
719 enum decoupled_power_domain {
720 GEN9_DECOUPLED_PD_BLITTER = 0,
721 GEN9_DECOUPLED_PD_RENDER,
722 GEN9_DECOUPLED_PD_MEDIA,
723 GEN9_DECOUPLED_PD_ALL
727 GEN9_DECOUPLED_OP_WRITE = 0,
728 GEN9_DECOUPLED_OP_READ
731 enum forcewake_domains
732 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
733 i915_reg_t reg, unsigned int op);
735 struct intel_uncore_funcs {
736 void (*force_wake_get)(struct drm_i915_private *dev_priv,
737 enum forcewake_domains domains);
738 void (*force_wake_put)(struct drm_i915_private *dev_priv,
739 enum forcewake_domains domains);
741 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
742 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
743 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
744 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
746 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
747 uint8_t val, bool trace);
748 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
749 uint16_t val, bool trace);
750 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
751 uint32_t val, bool trace);
754 struct intel_forcewake_range {
758 enum forcewake_domains domains;
761 struct intel_uncore {
762 spinlock_t lock; /** lock is also taken in irq contexts. */
764 const struct intel_forcewake_range *fw_domains_table;
765 unsigned int fw_domains_table_entries;
767 struct intel_uncore_funcs funcs;
771 enum forcewake_domains fw_domains;
772 enum forcewake_domains fw_domains_active;
774 struct intel_uncore_forcewake_domain {
775 struct drm_i915_private *i915;
776 enum forcewake_domain_id id;
777 enum forcewake_domains mask;
779 struct hrtimer timer;
786 } fw_domain[FW_DOMAIN_ID_COUNT];
788 int unclaimed_mmio_check;
791 /* Iterate over initialised fw domains */
792 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
793 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
794 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
796 for_each_if ((mask__) & (domain__)->mask)
798 #define for_each_fw_domain(domain__, dev_priv__) \
799 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
801 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
802 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
803 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
806 struct work_struct work;
808 uint32_t *dmc_payload;
809 uint32_t dmc_fw_size;
812 i915_reg_t mmioaddr[8];
813 uint32_t mmiodata[8];
815 uint32_t allowed_dc_mask;
818 #define DEV_INFO_FOR_EACH_FLAG(func) \
821 func(is_alpha_support); \
822 /* Keep has_* in alphabetical order */ \
823 func(has_64bit_reloc); \
824 func(has_aliasing_ppgtt); \
827 func(has_decoupled_mmio); \
830 func(has_fpga_dbg); \
831 func(has_full_ppgtt); \
832 func(has_full_48bit_ppgtt); \
833 func(has_gmbus_irq); \
834 func(has_gmch_display); \
837 func(has_hw_contexts); \
840 func(has_logical_ring_contexts); \
842 func(has_pipe_cxsr); \
843 func(has_pooled_eu); \
847 func(has_resource_streamer); \
848 func(has_runtime_pm); \
850 func(cursor_needs_physical); \
851 func(hws_needs_physical); \
852 func(overlay_needs_physical); \
855 struct sseu_dev_info {
861 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
864 u8 has_subslice_pg:1;
868 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
870 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
873 /* Keep in gen based order, and chronological order within a gen */
874 enum intel_platform {
875 INTEL_PLATFORM_UNINITIALIZED = 0,
904 struct intel_device_info {
905 u32 display_mmio_offset;
908 u8 num_sprites[I915_MAX_PIPES];
909 u8 num_scalers[I915_MAX_PIPES];
912 enum intel_platform platform;
913 u8 ring_mask; /* Rings supported by the HW */
915 #define DEFINE_FLAG(name) u8 name:1
916 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
918 u16 ddb_size; /* in blocks */
919 /* Register offsets for the various display pipes and transcoders */
920 int pipe_offsets[I915_MAX_TRANSCODERS];
921 int trans_offsets[I915_MAX_TRANSCODERS];
922 int palette_offsets[I915_MAX_PIPES];
923 int cursor_offsets[I915_MAX_PIPES];
925 /* Slice/subslice/EU info */
926 struct sseu_dev_info sseu;
929 u16 degamma_lut_size;
934 struct intel_display_error_state;
936 struct i915_gpu_state {
939 struct timeval boottime;
940 struct timeval uptime;
942 struct drm_i915_private *i915;
952 struct intel_device_info device_info;
953 struct i915_params params;
955 /* Generic register state */
959 u32 gtier[4], ngtier;
963 u32 error; /* gen6+ */
964 u32 err_int; /* gen7 */
965 u32 fault_data0; /* gen8, gen9 */
966 u32 fault_data1; /* gen8, gen9 */
974 u64 fence[I915_MAX_NUM_FENCES];
975 struct intel_overlay_error_state *overlay;
976 struct intel_display_error_state *display;
977 struct drm_i915_error_object *semaphore;
978 struct drm_i915_error_object *guc_log;
980 struct drm_i915_error_engine {
982 /* Software tracked state */
985 unsigned long hangcheck_timestamp;
986 bool hangcheck_stalled;
987 enum intel_engine_hangcheck_action hangcheck_action;
988 struct i915_address_space *vm;
991 /* position of active request inside the ring */
992 u32 rq_head, rq_post, rq_tail;
994 /* our own tracking of ring head and tail */
1000 /* Register state */
1017 u32 rc_psmi; /* sleep state */
1018 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1019 struct intel_instdone instdone;
1021 struct drm_i915_error_context {
1022 char comm[TASK_COMM_LEN];
1031 struct drm_i915_error_object {
1037 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
1039 struct drm_i915_error_object *wa_ctx;
1041 struct drm_i915_error_request {
1049 } *requests, execlist[2];
1051 struct drm_i915_error_waiter {
1052 char comm[TASK_COMM_LEN];
1064 } engine[I915_NUM_ENGINES];
1066 struct drm_i915_error_buffer {
1069 u32 rseqno[I915_NUM_ENGINES], wseqno;
1073 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1080 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1081 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1082 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1085 enum i915_cache_level {
1086 I915_CACHE_NONE = 0,
1087 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1088 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1089 caches, eg sampler/render caches, and the
1090 large Last-Level-Cache. LLC is coherent with
1091 the CPU, but L3 is only visible to the GPU. */
1092 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1095 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1106 /* This is always the inner lock when overlapping with struct_mutex and
1107 * it's the outer lock when overlapping with stolen_lock. */
1110 unsigned int possible_framebuffer_bits;
1111 unsigned int busy_bits;
1112 unsigned int visible_pipes_mask;
1113 struct intel_crtc *crtc;
1115 struct drm_mm_node compressed_fb;
1116 struct drm_mm_node *compressed_llb;
1123 bool underrun_detected;
1124 struct work_struct underrun_work;
1126 struct intel_fbc_state_cache {
1127 struct i915_vma *vma;
1130 unsigned int mode_flags;
1131 uint32_t hsw_bdw_pixel_rate;
1135 unsigned int rotation;
1142 const struct drm_format_info *format;
1143 unsigned int stride;
1147 struct intel_fbc_reg_params {
1148 struct i915_vma *vma;
1153 unsigned int fence_y_offset;
1157 const struct drm_format_info *format;
1158 unsigned int stride;
1164 struct intel_fbc_work {
1166 u32 scheduled_vblank;
1167 struct work_struct work;
1170 const char *no_fbc_reason;
1174 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1175 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1176 * parsing for same resolution.
1178 enum drrs_refresh_rate_type {
1181 DRRS_MAX_RR, /* RR count */
1184 enum drrs_support_type {
1185 DRRS_NOT_SUPPORTED = 0,
1186 STATIC_DRRS_SUPPORT = 1,
1187 SEAMLESS_DRRS_SUPPORT = 2
1193 struct delayed_work work;
1194 struct intel_dp *dp;
1195 unsigned busy_frontbuffer_bits;
1196 enum drrs_refresh_rate_type refresh_rate_type;
1197 enum drrs_support_type type;
1204 struct intel_dp *enabled;
1206 struct delayed_work work;
1207 unsigned busy_frontbuffer_bits;
1209 bool aux_frame_sync;
1211 bool y_cord_support;
1212 bool colorimetry_support;
1217 PCH_NONE = 0, /* No PCH present */
1218 PCH_IBX, /* Ibexpeak PCH */
1219 PCH_CPT, /* Cougarpoint PCH */
1220 PCH_LPT, /* Lynxpoint PCH */
1221 PCH_SPT, /* Sunrisepoint PCH */
1222 PCH_KBP, /* Kabypoint PCH */
1226 enum intel_sbi_destination {
1231 #define QUIRK_PIPEA_FORCE (1<<0)
1232 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1233 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1234 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1235 #define QUIRK_PIPEB_FORCE (1<<4)
1236 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1239 struct intel_fbc_work;
1241 struct intel_gmbus {
1242 struct i2c_adapter adapter;
1243 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1246 i915_reg_t gpio_reg;
1247 struct i2c_algo_bit_data bit_algo;
1248 struct drm_i915_private *dev_priv;
1251 struct i915_suspend_saved_registers {
1253 u32 saveFBC_CONTROL;
1254 u32 saveCACHE_MODE_0;
1255 u32 saveMI_ARB_STATE;
1259 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1260 u32 savePCH_PORT_HOTPLUG;
1264 struct vlv_s0ix_state {
1271 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1272 u32 media_max_req_count;
1273 u32 gfx_max_req_count;
1299 u32 rp_down_timeout;
1305 /* Display 1 CZ domain */
1310 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1312 /* GT SA CZ domain */
1319 /* Display 2 CZ domain */
1323 u32 clock_gate_dis2;
1326 struct intel_rps_ei {
1332 struct intel_gen6_power_mgmt {
1334 * work, interrupts_enabled and pm_iir are protected by
1335 * dev_priv->irq_lock
1337 struct work_struct work;
1338 bool interrupts_enabled;
1341 /* PM interrupt bits that should never be masked */
1344 /* Frequencies are stored in potentially platform dependent multiples.
1345 * In other words, *_freq needs to be multiplied by X to be interesting.
1346 * Soft limits are those which are used for the dynamic reclocking done
1347 * by the driver (raise frequencies under heavy loads, and lower for
1348 * lighter loads). Hard limits are those imposed by the hardware.
1350 * A distinction is made for overclocking, which is never enabled by
1351 * default, and is considered to be above the hard limit if it's
1354 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1355 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1356 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1357 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1358 u8 min_freq; /* AKA RPn. Minimum frequency */
1359 u8 boost_freq; /* Frequency to request when wait boosting */
1360 u8 idle_freq; /* Frequency to request when we are idle */
1361 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1362 u8 rp1_freq; /* "less than" RP0 power/freqency */
1363 u8 rp0_freq; /* Non-overclocked max frequency. */
1364 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1366 u8 up_threshold; /* Current %busy required to uplock */
1367 u8 down_threshold; /* Current %busy required to downclock */
1370 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1372 spinlock_t client_lock;
1373 struct list_head clients;
1377 struct delayed_work autoenable_work;
1380 /* manual wa residency calculations */
1381 struct intel_rps_ei up_ei, down_ei;
1384 * Protects RPS/RC6 register access and PCU communication.
1385 * Must be taken after struct_mutex if nested. Note that
1386 * this lock may be held for long periods of time when
1387 * talking to hw - so only take it when talking to hw!
1389 struct mutex hw_lock;
1392 /* defined intel_pm.c */
1393 extern spinlock_t mchdev_lock;
1395 struct intel_ilk_power_mgmt {
1403 unsigned long last_time1;
1404 unsigned long chipset_power;
1407 unsigned long gfx_power;
1414 struct drm_i915_private;
1415 struct i915_power_well;
1417 struct i915_power_well_ops {
1419 * Synchronize the well's hw state to match the current sw state, for
1420 * example enable/disable it based on the current refcount. Called
1421 * during driver init and resume time, possibly after first calling
1422 * the enable/disable handlers.
1424 void (*sync_hw)(struct drm_i915_private *dev_priv,
1425 struct i915_power_well *power_well);
1427 * Enable the well and resources that depend on it (for example
1428 * interrupts located on the well). Called after the 0->1 refcount
1431 void (*enable)(struct drm_i915_private *dev_priv,
1432 struct i915_power_well *power_well);
1434 * Disable the well and resources that depend on it. Called after
1435 * the 1->0 refcount transition.
1437 void (*disable)(struct drm_i915_private *dev_priv,
1438 struct i915_power_well *power_well);
1439 /* Returns the hw enabled state. */
1440 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1441 struct i915_power_well *power_well);
1444 /* Power well structure for haswell */
1445 struct i915_power_well {
1448 /* power well enable/disable usage count */
1450 /* cached hw enabled state */
1453 /* unique identifier for this power well */
1456 * Arbitraty data associated with this power well. Platform and power
1460 const struct i915_power_well_ops *ops;
1463 struct i915_power_domains {
1465 * Power wells needed for initialization at driver init and suspend
1466 * time are on. They are kept on until after the first modeset.
1470 int power_well_count;
1473 int domain_use_count[POWER_DOMAIN_NUM];
1474 struct i915_power_well *power_wells;
1477 #define MAX_L3_SLICES 2
1478 struct intel_l3_parity {
1479 u32 *remap_info[MAX_L3_SLICES];
1480 struct work_struct error_work;
1484 struct i915_gem_mm {
1485 /** Memory allocator for GTT stolen memory */
1486 struct drm_mm stolen;
1487 /** Protects the usage of the GTT stolen memory allocator. This is
1488 * always the inner lock when overlapping with struct_mutex. */
1489 struct mutex stolen_lock;
1491 /** List of all objects in gtt_space. Used to restore gtt
1492 * mappings on resume */
1493 struct list_head bound_list;
1495 * List of objects which are not bound to the GTT (thus
1496 * are idle and not used by the GPU). These objects may or may
1497 * not actually have any pages attached.
1499 struct list_head unbound_list;
1501 /** List of all objects in gtt_space, currently mmaped by userspace.
1502 * All objects within this list must also be on bound_list.
1504 struct list_head userfault_list;
1507 * List of objects which are pending destruction.
1509 struct llist_head free_list;
1510 struct work_struct free_work;
1512 /** Usable portion of the GTT for GEM */
1513 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1515 /** PPGTT used for aliasing the PPGTT with the GTT */
1516 struct i915_hw_ppgtt *aliasing_ppgtt;
1518 struct notifier_block oom_notifier;
1519 struct notifier_block vmap_notifier;
1520 struct shrinker shrinker;
1522 /** LRU list of objects with fence regs on them. */
1523 struct list_head fence_list;
1526 * Are we in a non-interruptible section of code like
1531 /* the indicator for dispatch video commands on two BSD rings */
1532 atomic_t bsd_engine_dispatch_index;
1534 /** Bit 6 swizzling required for X tiling */
1535 uint32_t bit_6_swizzle_x;
1536 /** Bit 6 swizzling required for Y tiling */
1537 uint32_t bit_6_swizzle_y;
1539 /* accounting, useful for userland debugging */
1540 spinlock_t object_stat_lock;
1545 struct drm_i915_error_state_buf {
1546 struct drm_i915_private *i915;
1555 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1556 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1558 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1559 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1561 struct i915_gpu_error {
1562 /* For hangcheck timer */
1563 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1564 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1566 struct delayed_work hangcheck_work;
1568 /* For reset and error_state handling. */
1570 /* Protected by the above dev->gpu_error.lock. */
1571 struct i915_gpu_state *first_error;
1573 unsigned long missed_irq_rings;
1576 * State variable controlling the reset flow and count
1578 * This is a counter which gets incremented when reset is triggered,
1580 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1581 * meaning that any waiters holding onto the struct_mutex should
1582 * relinquish the lock immediately in order for the reset to start.
1584 * If reset is not completed succesfully, the I915_WEDGE bit is
1585 * set meaning that hardware is terminally sour and there is no
1586 * recovery. All waiters on the reset_queue will be woken when
1589 * This counter is used by the wait_seqno code to notice that reset
1590 * event happened and it needs to restart the entire ioctl (since most
1591 * likely the seqno it waited for won't ever signal anytime soon).
1593 * This is important for lock-free wait paths, where no contended lock
1594 * naturally enforces the correct ordering between the bail-out of the
1595 * waiter and the gpu reset work code.
1597 unsigned long reset_count;
1599 unsigned long flags;
1600 #define I915_RESET_IN_PROGRESS 0
1601 #define I915_WEDGED (BITS_PER_LONG - 1)
1604 * Waitqueue to signal when a hang is detected. Used to for waiters
1605 * to release the struct_mutex for the reset to procede.
1607 wait_queue_head_t wait_queue;
1610 * Waitqueue to signal when the reset has completed. Used by clients
1611 * that wait for dev_priv->mm.wedged to settle.
1613 wait_queue_head_t reset_queue;
1615 /* For missed irq/seqno simulation. */
1616 unsigned long test_irq_rings;
1619 enum modeset_restore {
1620 MODESET_ON_LID_OPEN,
1625 #define DP_AUX_A 0x40
1626 #define DP_AUX_B 0x10
1627 #define DP_AUX_C 0x20
1628 #define DP_AUX_D 0x30
1630 #define DDC_PIN_B 0x05
1631 #define DDC_PIN_C 0x04
1632 #define DDC_PIN_D 0x06
1634 struct ddi_vbt_port_info {
1636 * This is an index in the HDMI/DVI DDI buffer translation table.
1637 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1638 * populate this field.
1640 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1641 uint8_t hdmi_level_shift;
1643 uint8_t supports_dvi:1;
1644 uint8_t supports_hdmi:1;
1645 uint8_t supports_dp:1;
1646 uint8_t supports_edp:1;
1648 uint8_t alternate_aux_channel;
1649 uint8_t alternate_ddc_pin;
1651 uint8_t dp_boost_level;
1652 uint8_t hdmi_boost_level;
1655 enum psr_lines_to_wait {
1656 PSR_0_LINES_TO_WAIT = 0,
1658 PSR_4_LINES_TO_WAIT,
1662 struct intel_vbt_data {
1663 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1664 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1667 unsigned int int_tv_support:1;
1668 unsigned int lvds_dither:1;
1669 unsigned int lvds_vbt:1;
1670 unsigned int int_crt_support:1;
1671 unsigned int lvds_use_ssc:1;
1672 unsigned int display_clock_mode:1;
1673 unsigned int fdi_rx_polarity_inverted:1;
1674 unsigned int panel_type:4;
1676 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1678 enum drrs_support_type drrs_type;
1689 struct edp_power_seq pps;
1694 bool require_aux_wakeup;
1696 enum psr_lines_to_wait lines_to_wait;
1697 int tp1_wakeup_time;
1698 int tp2_tp3_wakeup_time;
1704 bool active_low_pwm;
1705 u8 min_brightness; /* min_brightness/255 of max */
1706 u8 controller; /* brightness controller number */
1707 enum intel_backlight_type type;
1713 struct mipi_config *config;
1714 struct mipi_pps_data *pps;
1718 const u8 *sequence[MIPI_SEQ_MAX];
1724 union child_device_config *child_dev;
1726 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1727 struct sdvo_device_mapping sdvo_mappings[2];
1730 enum intel_ddb_partitioning {
1732 INTEL_DDB_PART_5_6, /* IVB+ */
1735 struct intel_wm_level {
1743 struct ilk_wm_values {
1744 uint32_t wm_pipe[3];
1746 uint32_t wm_lp_spr[3];
1747 uint32_t wm_linetime[3];
1749 enum intel_ddb_partitioning partitioning;
1752 struct vlv_pipe_wm {
1753 uint16_t plane[I915_MAX_PLANES];
1761 struct vlv_wm_ddl_values {
1762 uint8_t plane[I915_MAX_PLANES];
1765 struct vlv_wm_values {
1766 struct vlv_pipe_wm pipe[3];
1767 struct vlv_sr_wm sr;
1768 struct vlv_wm_ddl_values ddl[3];
1773 struct skl_ddb_entry {
1774 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1777 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1779 return entry->end - entry->start;
1782 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1783 const struct skl_ddb_entry *e2)
1785 if (e1->start == e2->start && e1->end == e2->end)
1791 struct skl_ddb_allocation {
1792 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1793 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1796 struct skl_wm_values {
1797 unsigned dirty_pipes;
1798 struct skl_ddb_allocation ddb;
1801 struct skl_wm_level {
1803 uint16_t plane_res_b;
1804 uint8_t plane_res_l;
1808 * This struct helps tracking the state needed for runtime PM, which puts the
1809 * device in PCI D3 state. Notice that when this happens, nothing on the
1810 * graphics device works, even register access, so we don't get interrupts nor
1813 * Every piece of our code that needs to actually touch the hardware needs to
1814 * either call intel_runtime_pm_get or call intel_display_power_get with the
1815 * appropriate power domain.
1817 * Our driver uses the autosuspend delay feature, which means we'll only really
1818 * suspend if we stay with zero refcount for a certain amount of time. The
1819 * default value is currently very conservative (see intel_runtime_pm_enable), but
1820 * it can be changed with the standard runtime PM files from sysfs.
1822 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1823 * goes back to false exactly before we reenable the IRQs. We use this variable
1824 * to check if someone is trying to enable/disable IRQs while they're supposed
1825 * to be disabled. This shouldn't happen and we'll print some error messages in
1828 * For more, read the Documentation/power/runtime_pm.txt.
1830 struct i915_runtime_pm {
1831 atomic_t wakeref_count;
1836 enum intel_pipe_crc_source {
1837 INTEL_PIPE_CRC_SOURCE_NONE,
1838 INTEL_PIPE_CRC_SOURCE_PLANE1,
1839 INTEL_PIPE_CRC_SOURCE_PLANE2,
1840 INTEL_PIPE_CRC_SOURCE_PF,
1841 INTEL_PIPE_CRC_SOURCE_PIPE,
1842 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1843 INTEL_PIPE_CRC_SOURCE_TV,
1844 INTEL_PIPE_CRC_SOURCE_DP_B,
1845 INTEL_PIPE_CRC_SOURCE_DP_C,
1846 INTEL_PIPE_CRC_SOURCE_DP_D,
1847 INTEL_PIPE_CRC_SOURCE_AUTO,
1848 INTEL_PIPE_CRC_SOURCE_MAX,
1851 struct intel_pipe_crc_entry {
1856 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1857 struct intel_pipe_crc {
1859 bool opened; /* exclusive access to the result file */
1860 struct intel_pipe_crc_entry *entries;
1861 enum intel_pipe_crc_source source;
1863 wait_queue_head_t wq;
1867 struct i915_frontbuffer_tracking {
1871 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1878 struct i915_wa_reg {
1881 /* bitmask representing WA bits */
1886 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1887 * allowing it for RCS as we don't foresee any requirement of having
1888 * a whitelist for other engines. When it is really required for
1889 * other engines then the limit need to be increased.
1891 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1893 struct i915_workarounds {
1894 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1896 u32 hw_whitelist_count[I915_NUM_ENGINES];
1899 struct i915_virtual_gpu {
1903 /* used in computing the new watermarks state */
1904 struct intel_wm_config {
1905 unsigned int num_pipes_active;
1906 bool sprites_enabled;
1907 bool sprites_scaled;
1910 struct i915_oa_format {
1915 struct i915_oa_reg {
1920 struct i915_perf_stream;
1923 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1925 struct i915_perf_stream_ops {
1927 * @enable: Enables the collection of HW samples, either in response to
1928 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1929 * without `I915_PERF_FLAG_DISABLED`.
1931 void (*enable)(struct i915_perf_stream *stream);
1934 * @disable: Disables the collection of HW samples, either in response
1935 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1938 void (*disable)(struct i915_perf_stream *stream);
1941 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1942 * once there is something ready to read() for the stream
1944 void (*poll_wait)(struct i915_perf_stream *stream,
1949 * @wait_unlocked: For handling a blocking read, wait until there is
1950 * something to ready to read() for the stream. E.g. wait on the same
1951 * wait queue that would be passed to poll_wait().
1953 int (*wait_unlocked)(struct i915_perf_stream *stream);
1956 * @read: Copy buffered metrics as records to userspace
1957 * **buf**: the userspace, destination buffer
1958 * **count**: the number of bytes to copy, requested by userspace
1959 * **offset**: zero at the start of the read, updated as the read
1960 * proceeds, it represents how many bytes have been copied so far and
1961 * the buffer offset for copying the next record.
1963 * Copy as many buffered i915 perf samples and records for this stream
1964 * to userspace as will fit in the given buffer.
1966 * Only write complete records; returning -%ENOSPC if there isn't room
1967 * for a complete record.
1969 * Return any error condition that results in a short read such as
1970 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1971 * returning to userspace.
1973 int (*read)(struct i915_perf_stream *stream,
1979 * @destroy: Cleanup any stream specific resources.
1981 * The stream will always be disabled before this is called.
1983 void (*destroy)(struct i915_perf_stream *stream);
1987 * struct i915_perf_stream - state for a single open stream FD
1989 struct i915_perf_stream {
1991 * @dev_priv: i915 drm device
1993 struct drm_i915_private *dev_priv;
1996 * @link: Links the stream into ``&drm_i915_private->streams``
1998 struct list_head link;
2001 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2002 * properties given when opening a stream, representing the contents
2003 * of a single sample as read() by userspace.
2008 * @sample_size: Considering the configured contents of a sample
2009 * combined with the required header size, this is the total size
2010 * of a single sample record.
2015 * @ctx: %NULL if measuring system-wide across all contexts or a
2016 * specific context that is being monitored.
2018 struct i915_gem_context *ctx;
2021 * @enabled: Whether the stream is currently enabled, considering
2022 * whether the stream was opened in a disabled state and based
2023 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2028 * @ops: The callbacks providing the implementation of this specific
2029 * type of configured stream.
2031 const struct i915_perf_stream_ops *ops;
2035 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2037 struct i915_oa_ops {
2039 * @init_oa_buffer: Resets the head and tail pointers of the
2040 * circular buffer for periodic OA reports.
2042 * Called when first opening a stream for OA metrics, but also may be
2043 * called in response to an OA buffer overflow or other error
2046 * Note it may be necessary to clear the full OA buffer here as part of
2047 * maintaining the invariable that new reports must be written to
2048 * zeroed memory for us to be able to reliable detect if an expected
2049 * report has not yet landed in memory. (At least on Haswell the OA
2050 * buffer tail pointer is not synchronized with reports being visible
2053 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2056 * @enable_metric_set: Applies any MUX configuration to set up the
2057 * Boolean and Custom (B/C) counters that are part of the counter
2058 * reports being sampled. May apply system constraints such as
2059 * disabling EU clock gating as required.
2061 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2064 * @disable_metric_set: Remove system constraints associated with using
2067 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2070 * @oa_enable: Enable periodic sampling
2072 void (*oa_enable)(struct drm_i915_private *dev_priv);
2075 * @oa_disable: Disable periodic sampling
2077 void (*oa_disable)(struct drm_i915_private *dev_priv);
2080 * @read: Copy data from the circular OA buffer into a given userspace
2083 int (*read)(struct i915_perf_stream *stream,
2089 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2091 * This is either called via fops or the poll check hrtimer (atomic
2092 * ctx) without any locks taken.
2094 * It's safe to read OA config state here unlocked, assuming that this
2095 * is only called while the stream is enabled, while the global OA
2096 * configuration can't be modified.
2098 * Efficiency is more important than avoiding some false positives
2099 * here, which will be handled gracefully - likely resulting in an
2100 * %EAGAIN error for userspace.
2102 bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2105 struct intel_cdclk_state {
2106 unsigned int cdclk, vco, ref;
2109 struct drm_i915_private {
2110 struct drm_device drm;
2112 struct kmem_cache *objects;
2113 struct kmem_cache *vmas;
2114 struct kmem_cache *requests;
2115 struct kmem_cache *dependencies;
2117 const struct intel_device_info info;
2121 struct intel_uncore uncore;
2123 struct i915_virtual_gpu vgpu;
2125 struct intel_gvt *gvt;
2127 struct intel_huc huc;
2128 struct intel_guc guc;
2130 struct intel_csr csr;
2132 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2134 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2135 * controller on different i2c buses. */
2136 struct mutex gmbus_mutex;
2139 * Base address of the gmbus and gpio block.
2141 uint32_t gpio_mmio_base;
2143 /* MMIO base address for MIPI regs */
2144 uint32_t mipi_mmio_base;
2146 uint32_t psr_mmio_base;
2148 uint32_t pps_mmio_base;
2150 wait_queue_head_t gmbus_wait_queue;
2152 struct pci_dev *bridge_dev;
2153 struct i915_gem_context *kernel_context;
2154 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2155 struct i915_vma *semaphore;
2157 struct drm_dma_handle *status_page_dmah;
2158 struct resource mch_res;
2160 /* protects the irq masks */
2161 spinlock_t irq_lock;
2163 /* protects the mmio flip data */
2164 spinlock_t mmio_flip_lock;
2166 bool display_irqs_enabled;
2168 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2169 struct pm_qos_request pm_qos;
2171 /* Sideband mailbox protection */
2172 struct mutex sb_lock;
2174 /** Cached value of IMR to avoid reads in updating the bitfield */
2177 u32 de_irq_mask[I915_MAX_PIPES];
2184 u32 pipestat_irq_mask[I915_MAX_PIPES];
2186 struct i915_hotplug hotplug;
2187 struct intel_fbc fbc;
2188 struct i915_drrs drrs;
2189 struct intel_opregion opregion;
2190 struct intel_vbt_data vbt;
2192 bool preserve_bios_swizzle;
2195 struct intel_overlay *overlay;
2197 /* backlight registers and fields in struct intel_panel */
2198 struct mutex backlight_lock;
2201 bool no_aux_handshake;
2203 /* protects panel power sequencer state */
2204 struct mutex pps_mutex;
2206 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2207 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2209 unsigned int fsb_freq, mem_freq, is_ddr3;
2210 unsigned int skl_preferred_vco_freq;
2211 unsigned int max_cdclk_freq;
2213 unsigned int max_dotclk_freq;
2214 unsigned int rawclk_freq;
2215 unsigned int hpll_freq;
2216 unsigned int czclk_freq;
2220 * The current logical cdclk state.
2221 * See intel_atomic_state.cdclk.logical
2223 * For reading holding any crtc lock is sufficient,
2224 * for writing must hold all of them.
2226 struct intel_cdclk_state logical;
2228 * The current actual cdclk state.
2229 * See intel_atomic_state.cdclk.actual
2231 struct intel_cdclk_state actual;
2232 /* The current hardware cdclk state */
2233 struct intel_cdclk_state hw;
2237 * wq - Driver workqueue for GEM.
2239 * NOTE: Work items scheduled here are not allowed to grab any modeset
2240 * locks, for otherwise the flushing done in the pageflip code will
2241 * result in deadlocks.
2243 struct workqueue_struct *wq;
2245 /* Display functions */
2246 struct drm_i915_display_funcs display;
2248 /* PCH chipset type */
2249 enum intel_pch pch_type;
2250 unsigned short pch_id;
2252 unsigned long quirks;
2254 enum modeset_restore modeset_restore;
2255 struct mutex modeset_restore_lock;
2256 struct drm_atomic_state *modeset_restore_state;
2257 struct drm_modeset_acquire_ctx reset_ctx;
2259 struct list_head vm_list; /* Global list of all address spaces */
2260 struct i915_ggtt ggtt; /* VM representing the global address space */
2262 struct i915_gem_mm mm;
2263 DECLARE_HASHTABLE(mm_structs, 7);
2264 struct mutex mm_lock;
2266 /* The hw wants to have a stable context identifier for the lifetime
2267 * of the context (for OA, PASID, faults, etc). This is limited
2268 * in execlists to 21 bits.
2270 struct ida context_hw_ida;
2271 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2273 /* Kernel Modesetting */
2275 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2276 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2277 wait_queue_head_t pending_flip_queue;
2279 #ifdef CONFIG_DEBUG_FS
2280 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2283 /* dpll and cdclk state is protected by connection_mutex */
2284 int num_shared_dpll;
2285 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2286 const struct intel_dpll_mgr *dpll_mgr;
2289 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2290 * Must be global rather than per dpll, because on some platforms
2291 * plls share registers.
2293 struct mutex dpll_lock;
2295 unsigned int active_crtcs;
2296 unsigned int min_pixclk[I915_MAX_PIPES];
2298 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2300 struct i915_workarounds workarounds;
2302 struct i915_frontbuffer_tracking fb_tracking;
2304 struct intel_atomic_helper {
2305 struct llist_head free_list;
2306 struct work_struct free_work;
2311 bool mchbar_need_disable;
2313 struct intel_l3_parity l3_parity;
2315 /* Cannot be determined by PCIID. You must always read a register. */
2318 /* gen6+ rps state */
2319 struct intel_gen6_power_mgmt rps;
2321 /* ilk-only ips/rps state. Everything in here is protected by the global
2322 * mchdev_lock in intel_pm.c */
2323 struct intel_ilk_power_mgmt ips;
2325 struct i915_power_domains power_domains;
2327 struct i915_psr psr;
2329 struct i915_gpu_error gpu_error;
2331 struct drm_i915_gem_object *vlv_pctx;
2333 #ifdef CONFIG_DRM_FBDEV_EMULATION
2334 /* list of fbdev register on this device */
2335 struct intel_fbdev *fbdev;
2336 struct work_struct fbdev_suspend_work;
2339 struct drm_property *broadcast_rgb_property;
2340 struct drm_property *force_audio_property;
2342 /* hda/i915 audio component */
2343 struct i915_audio_component *audio_component;
2344 bool audio_component_registered;
2346 * av_mutex - mutex for audio/video sync
2349 struct mutex av_mutex;
2351 uint32_t hw_context_size;
2352 struct list_head context_list;
2356 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2357 u32 chv_phy_control;
2359 * Shadows for CHV DPLL_MD regs to keep the state
2360 * checker somewhat working in the presence hardware
2361 * crappiness (can't read out DPLL_MD for pipes B & C).
2363 u32 chv_dpll_md[I915_MAX_PIPES];
2367 bool suspended_to_idle;
2368 struct i915_suspend_saved_registers regfile;
2369 struct vlv_s0ix_state vlv_s0ix_state;
2372 I915_SAGV_UNKNOWN = 0,
2375 I915_SAGV_NOT_CONTROLLED
2379 /* protects DSPARB registers on pre-g4x/vlv/chv */
2380 spinlock_t dsparb_lock;
2383 * Raw watermark latency values:
2384 * in 0.1us units for WM0,
2385 * in 0.5us units for WM1+.
2388 uint16_t pri_latency[5];
2390 uint16_t spr_latency[5];
2392 uint16_t cur_latency[5];
2394 * Raw watermark memory latency values
2395 * for SKL for all 8 levels
2398 uint16_t skl_latency[8];
2400 /* current hardware state */
2402 struct ilk_wm_values hw;
2403 struct skl_wm_values skl_hw;
2404 struct vlv_wm_values vlv;
2410 * Should be held around atomic WM register writing; also
2411 * protects * intel_crtc->wm.active and
2412 * cstate->wm.need_postvbl_update.
2414 struct mutex wm_mutex;
2417 * Set during HW readout of watermarks/DDB. Some platforms
2418 * need to know when we're still using BIOS-provided values
2419 * (which we don't fully trust).
2421 bool distrust_bios_wm;
2424 struct i915_runtime_pm pm;
2429 struct kobject *metrics_kobj;
2430 struct ctl_table_header *sysctl_header;
2433 struct list_head streams;
2435 spinlock_t hook_lock;
2438 struct i915_perf_stream *exclusive_stream;
2440 u32 specific_ctx_id;
2442 struct hrtimer poll_check_timer;
2443 wait_queue_head_t poll_wq;
2447 int period_exponent;
2448 int timestamp_frequency;
2454 const struct i915_oa_reg *mux_regs;
2456 const struct i915_oa_reg *b_counter_regs;
2457 int b_counter_regs_len;
2460 struct i915_vma *vma;
2466 u32 gen7_latched_oastatus1;
2468 struct i915_oa_ops ops;
2469 const struct i915_oa_format *oa_formats;
2474 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2476 void (*resume)(struct drm_i915_private *);
2477 void (*cleanup_engine)(struct intel_engine_cs *engine);
2479 struct list_head timelines;
2480 struct i915_gem_timeline global_timeline;
2481 u32 active_requests;
2484 * Is the GPU currently considered idle, or busy executing
2485 * userspace requests? Whilst idle, we allow runtime power
2486 * management to power down the hardware and display clocks.
2487 * In order to reduce the effect on performance, there
2488 * is a slight delay before we do so.
2493 * We leave the user IRQ off as much as possible,
2494 * but this means that requests will finish and never
2495 * be retired once the system goes idle. Set a timer to
2496 * fire periodically while the ring is running. When it
2497 * fires, go retire requests.
2499 struct delayed_work retire_work;
2502 * When we detect an idle GPU, we want to turn on
2503 * powersaving features. So once we see that there
2504 * are no more requests outstanding and no more
2505 * arrive within a small period of time, we fire
2506 * off the idle_work.
2508 struct delayed_work idle_work;
2510 ktime_t last_init_time;
2513 /* perform PHY state sanity checks? */
2514 bool chv_phy_assert[2];
2518 /* Used to save the pipe-to-encoder mapping for audio */
2519 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2521 /* necessary resource sharing with HDMI LPE audio driver. */
2523 struct platform_device *platdev;
2528 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2529 * will be rejected. Instead look for a better place.
2533 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2535 return container_of(dev, struct drm_i915_private, drm);
2538 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2540 return to_i915(dev_get_drvdata(kdev));
2543 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2545 return container_of(guc, struct drm_i915_private, guc);
2548 /* Simple iterator over all initialised engines */
2549 #define for_each_engine(engine__, dev_priv__, id__) \
2551 (id__) < I915_NUM_ENGINES; \
2553 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2555 #define __mask_next_bit(mask) ({ \
2556 int __idx = ffs(mask) - 1; \
2557 mask &= ~BIT(__idx); \
2561 /* Iterator over subset of engines selected by mask */
2562 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2563 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2564 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2566 enum hdmi_force_audio {
2567 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2568 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2569 HDMI_AUDIO_AUTO, /* trust EDID */
2570 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2573 #define I915_GTT_OFFSET_NONE ((u32)-1)
2576 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2577 * considered to be the frontbuffer for the given plane interface-wise. This
2578 * doesn't mean that the hw necessarily already scans it out, but that any
2579 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2581 * We have one bit per pipe and per scanout plane type.
2583 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2584 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2585 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2586 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2587 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2588 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2589 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2590 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2591 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2592 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2593 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2594 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2597 * Optimised SGL iterator for GEM objects
2599 static __always_inline struct sgt_iter {
2600 struct scatterlist *sgp;
2607 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2608 struct sgt_iter s = { .sgp = sgl };
2611 s.max = s.curr = s.sgp->offset;
2612 s.max += s.sgp->length;
2614 s.dma = sg_dma_address(s.sgp);
2616 s.pfn = page_to_pfn(sg_page(s.sgp));
2622 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2625 if (unlikely(sg_is_chain(sg)))
2626 sg = sg_chain_ptr(sg);
2631 * __sg_next - return the next scatterlist entry in a list
2632 * @sg: The current sg entry
2635 * If the entry is the last, return NULL; otherwise, step to the next
2636 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2637 * otherwise just return the pointer to the current element.
2639 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2641 #ifdef CONFIG_DEBUG_SG
2642 BUG_ON(sg->sg_magic != SG_MAGIC);
2644 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2648 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2649 * @__dmap: DMA address (output)
2650 * @__iter: 'struct sgt_iter' (iterator state, internal)
2651 * @__sgt: sg_table to iterate over (input)
2653 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2654 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2655 ((__dmap) = (__iter).dma + (__iter).curr); \
2656 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2657 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2660 * for_each_sgt_page - iterate over the pages of the given sg_table
2661 * @__pp: page pointer (output)
2662 * @__iter: 'struct sgt_iter' (iterator state, internal)
2663 * @__sgt: sg_table to iterate over (input)
2665 #define for_each_sgt_page(__pp, __iter, __sgt) \
2666 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2667 ((__pp) = (__iter).pfn == 0 ? NULL : \
2668 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2669 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2670 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2672 static inline const struct intel_device_info *
2673 intel_info(const struct drm_i915_private *dev_priv)
2675 return &dev_priv->info;
2678 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2680 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2681 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2683 #define REVID_FOREVER 0xff
2684 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2686 #define GEN_FOREVER (0)
2688 * Returns true if Gen is in inclusive range [Start, End].
2690 * Use GEN_FOREVER for unbound start and or end.
2692 #define IS_GEN(dev_priv, s, e) ({ \
2693 unsigned int __s = (s), __e = (e); \
2694 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2695 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2696 if ((__s) != GEN_FOREVER) \
2698 if ((__e) == GEN_FOREVER) \
2699 __e = BITS_PER_LONG - 1; \
2702 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2706 * Return true if revision is in range [since,until] inclusive.
2708 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2710 #define IS_REVID(p, since, until) \
2711 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2713 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2714 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2715 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2716 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2717 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2718 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2719 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2720 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2721 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2722 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2723 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2724 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2725 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2726 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2727 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2728 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2729 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2730 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2731 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2732 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2733 INTEL_DEVID(dev_priv) == 0x0152 || \
2734 INTEL_DEVID(dev_priv) == 0x015a)
2735 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2736 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2737 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2738 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2739 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2740 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2741 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2742 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2743 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2744 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2745 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2746 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2747 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2748 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2749 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2750 /* ULX machines are also considered ULT. */
2751 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2752 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2753 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2754 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2755 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2756 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2757 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2758 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2759 /* ULX machines are also considered ULT. */
2760 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2761 INTEL_DEVID(dev_priv) == 0x0A1E)
2762 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2763 INTEL_DEVID(dev_priv) == 0x1913 || \
2764 INTEL_DEVID(dev_priv) == 0x1916 || \
2765 INTEL_DEVID(dev_priv) == 0x1921 || \
2766 INTEL_DEVID(dev_priv) == 0x1926)
2767 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2768 INTEL_DEVID(dev_priv) == 0x1915 || \
2769 INTEL_DEVID(dev_priv) == 0x191E)
2770 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2771 INTEL_DEVID(dev_priv) == 0x5913 || \
2772 INTEL_DEVID(dev_priv) == 0x5916 || \
2773 INTEL_DEVID(dev_priv) == 0x5921 || \
2774 INTEL_DEVID(dev_priv) == 0x5926)
2775 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2776 INTEL_DEVID(dev_priv) == 0x5915 || \
2777 INTEL_DEVID(dev_priv) == 0x591E)
2778 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2779 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2780 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2781 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2783 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2785 #define SKL_REVID_A0 0x0
2786 #define SKL_REVID_B0 0x1
2787 #define SKL_REVID_C0 0x2
2788 #define SKL_REVID_D0 0x3
2789 #define SKL_REVID_E0 0x4
2790 #define SKL_REVID_F0 0x5
2791 #define SKL_REVID_G0 0x6
2792 #define SKL_REVID_H0 0x7
2794 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2796 #define BXT_REVID_A0 0x0
2797 #define BXT_REVID_A1 0x1
2798 #define BXT_REVID_B0 0x3
2799 #define BXT_REVID_B_LAST 0x8
2800 #define BXT_REVID_C0 0x9
2802 #define IS_BXT_REVID(dev_priv, since, until) \
2803 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2805 #define KBL_REVID_A0 0x0
2806 #define KBL_REVID_B0 0x1
2807 #define KBL_REVID_C0 0x2
2808 #define KBL_REVID_D0 0x3
2809 #define KBL_REVID_E0 0x4
2811 #define IS_KBL_REVID(dev_priv, since, until) \
2812 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2814 #define GLK_REVID_A0 0x0
2815 #define GLK_REVID_A1 0x1
2817 #define IS_GLK_REVID(dev_priv, since, until) \
2818 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2821 * The genX designation typically refers to the render engine, so render
2822 * capability related checks should use IS_GEN, while display and other checks
2823 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2826 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2827 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2828 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2829 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2830 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2831 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2832 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2833 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2835 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2836 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2837 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2839 #define ENGINE_MASK(id) BIT(id)
2840 #define RENDER_RING ENGINE_MASK(RCS)
2841 #define BSD_RING ENGINE_MASK(VCS)
2842 #define BLT_RING ENGINE_MASK(BCS)
2843 #define VEBOX_RING ENGINE_MASK(VECS)
2844 #define BSD2_RING ENGINE_MASK(VCS2)
2845 #define ALL_ENGINES (~0)
2847 #define HAS_ENGINE(dev_priv, id) \
2848 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2850 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2851 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2852 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2853 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2855 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2856 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2857 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2858 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2859 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2861 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2863 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2864 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2865 ((dev_priv)->info.has_logical_ring_contexts)
2866 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2867 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2868 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2870 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2871 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2872 ((dev_priv)->info.overlay_needs_physical)
2874 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2875 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2877 /* WaRsDisableCoarsePowerGating:skl,bxt */
2878 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2879 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2882 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2883 * even when in MSI mode. This results in spurious interrupt warnings if the
2884 * legacy irq no. is shared with another device. The kernel then disables that
2885 * interrupt source and so prevents the other device from working properly.
2887 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2888 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2890 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2891 * rows, which changed the alignment requirements and fence programming.
2893 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2894 !(IS_I915G(dev_priv) || \
2895 IS_I915GM(dev_priv)))
2896 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2897 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2899 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2900 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2901 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2903 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2905 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2907 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2908 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2909 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2910 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2911 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2913 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2915 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2916 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2919 * For now, anything with a GuC requires uCode loading, and then supports
2920 * command submission once loaded. But these are logically independent
2921 * properties, so we have separate macros to test them.
2923 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2924 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2925 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2926 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2928 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2930 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2932 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2933 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2934 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2935 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2936 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2937 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2938 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2939 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2940 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2941 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2942 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2943 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2945 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2946 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2947 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2948 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2949 #define HAS_PCH_LPT_LP(dev_priv) \
2950 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2951 #define HAS_PCH_LPT_H(dev_priv) \
2952 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2953 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2954 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2955 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2956 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2958 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2960 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2962 /* DPF == dynamic parity feature */
2963 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2964 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2965 2 : HAS_L3_DPF(dev_priv))
2967 #define GT_FREQUENCY_MULTIPLIER 50
2968 #define GEN9_FREQ_SCALER 3
2970 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2972 #include "i915_trace.h"
2974 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2976 #ifdef CONFIG_INTEL_IOMMU
2977 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2983 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2986 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2990 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2991 const char *fmt, ...);
2993 #define i915_report_error(dev_priv, fmt, ...) \
2994 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2996 #ifdef CONFIG_COMPAT
2997 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
3000 #define i915_compat_ioctl NULL
3002 extern const struct dev_pm_ops i915_pm_ops;
3004 extern int i915_driver_load(struct pci_dev *pdev,
3005 const struct pci_device_id *ent);
3006 extern void i915_driver_unload(struct drm_device *dev);
3007 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3008 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3009 extern void i915_reset(struct drm_i915_private *dev_priv);
3010 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3011 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3012 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3013 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3014 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3015 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3016 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3017 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3019 int intel_engines_init_early(struct drm_i915_private *dev_priv);
3020 int intel_engines_init(struct drm_i915_private *dev_priv);
3022 /* intel_hotplug.c */
3023 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3024 u32 pin_mask, u32 long_mask);
3025 void intel_hpd_init(struct drm_i915_private *dev_priv);
3026 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3027 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3028 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3029 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3030 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3033 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3035 unsigned long delay;
3037 if (unlikely(!i915.enable_hangcheck))
3040 /* Don't continually defer the hangcheck so that it is always run at
3041 * least once after work has been scheduled on any ring. Otherwise,
3042 * we will ignore a hung ring if a second ring is kept busy.
3045 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3046 queue_delayed_work(system_long_wq,
3047 &dev_priv->gpu_error.hangcheck_work, delay);
3051 void i915_handle_error(struct drm_i915_private *dev_priv,
3053 const char *fmt, ...);
3055 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3056 int intel_irq_install(struct drm_i915_private *dev_priv);
3057 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3059 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3060 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3061 bool restore_forcewake);
3062 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3063 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3064 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3065 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3066 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3068 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3069 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3070 enum forcewake_domains domains);
3071 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3072 enum forcewake_domains domains);
3073 /* Like above but the caller must manage the uncore.lock itself.
3074 * Must be used with I915_READ_FW and friends.
3076 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3077 enum forcewake_domains domains);
3078 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3079 enum forcewake_domains domains);
3080 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3082 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3084 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3088 const unsigned long timeout_ms);
3089 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3093 const unsigned long timeout_ms);
3095 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3097 return dev_priv->gvt;
3100 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3102 return dev_priv->vgpu.active;
3106 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3110 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3113 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3114 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3115 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3118 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3119 uint32_t interrupt_mask,
3120 uint32_t enabled_irq_mask);
3122 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3124 ilk_update_display_irq(dev_priv, bits, bits);
3127 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3129 ilk_update_display_irq(dev_priv, bits, 0);
3131 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3133 uint32_t interrupt_mask,
3134 uint32_t enabled_irq_mask);
3135 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3136 enum pipe pipe, uint32_t bits)
3138 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3140 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3141 enum pipe pipe, uint32_t bits)
3143 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3145 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3146 uint32_t interrupt_mask,
3147 uint32_t enabled_irq_mask);
3149 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3151 ibx_display_interrupt_update(dev_priv, bits, bits);
3154 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3156 ibx_display_interrupt_update(dev_priv, bits, 0);
3160 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3161 struct drm_file *file_priv);
3162 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3163 struct drm_file *file_priv);
3164 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3165 struct drm_file *file_priv);
3166 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3167 struct drm_file *file_priv);
3168 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3169 struct drm_file *file_priv);
3170 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3171 struct drm_file *file_priv);
3172 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3173 struct drm_file *file_priv);
3174 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3175 struct drm_file *file_priv);
3176 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3177 struct drm_file *file_priv);
3178 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3179 struct drm_file *file_priv);
3180 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3181 struct drm_file *file);
3182 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3183 struct drm_file *file);
3184 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3185 struct drm_file *file_priv);
3186 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3187 struct drm_file *file_priv);
3188 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3189 struct drm_file *file_priv);
3190 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3191 struct drm_file *file_priv);
3192 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3193 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3194 struct drm_file *file);
3195 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3196 struct drm_file *file_priv);
3197 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3198 struct drm_file *file_priv);
3199 void i915_gem_sanitize(struct drm_i915_private *i915);
3200 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3201 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3202 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3203 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3204 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3206 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3207 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3208 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3209 const struct drm_i915_gem_object_ops *ops);
3210 struct drm_i915_gem_object *
3211 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3212 struct drm_i915_gem_object *
3213 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3214 const void *data, size_t size);
3215 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3216 void i915_gem_free_object(struct drm_gem_object *obj);
3218 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3220 /* A single pass should suffice to release all the freed objects (along
3221 * most call paths) , but be a little more paranoid in that freeing
3222 * the objects does take a little amount of time, during which the rcu
3223 * callbacks could have added new objects into the freed list, and
3224 * armed the work again.
3228 } while (flush_work(&i915->mm.free_work));
3231 struct i915_vma * __must_check
3232 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3233 const struct i915_ggtt_view *view,
3238 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3239 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3241 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3243 static inline int __sg_page_count(const struct scatterlist *sg)
3245 return sg->length >> PAGE_SHIFT;
3248 struct scatterlist *
3249 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3250 unsigned int n, unsigned int *offset);
3253 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3257 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3261 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3264 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3265 struct sg_table *pages);
3266 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3268 static inline int __must_check
3269 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3271 might_lock(&obj->mm.lock);
3273 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3276 return __i915_gem_object_get_pages(obj);
3280 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3282 GEM_BUG_ON(!obj->mm.pages);
3284 atomic_inc(&obj->mm.pages_pin_count);
3288 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3290 return atomic_read(&obj->mm.pages_pin_count);
3294 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3296 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3297 GEM_BUG_ON(!obj->mm.pages);
3299 atomic_dec(&obj->mm.pages_pin_count);
3303 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3305 __i915_gem_object_unpin_pages(obj);
3308 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3313 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3314 enum i915_mm_subclass subclass);
3315 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3317 enum i915_map_type {
3323 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3324 * @obj: the object to map into kernel address space
3325 * @type: the type of mapping, used to select pgprot_t
3327 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3328 * pages and then returns a contiguous mapping of the backing storage into
3329 * the kernel address space. Based on the @type of mapping, the PTE will be
3330 * set to either WriteBack or WriteCombine (via pgprot_t).
3332 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3333 * mapping is no longer required.
3335 * Returns the pointer through which to access the mapped object, or an
3336 * ERR_PTR() on error.
3338 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3339 enum i915_map_type type);
3342 * i915_gem_object_unpin_map - releases an earlier mapping
3343 * @obj: the object to unmap
3345 * After pinning the object and mapping its pages, once you are finished
3346 * with your access, call i915_gem_object_unpin_map() to release the pin
3347 * upon the mapping. Once the pin count reaches zero, that mapping may be
3350 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3352 i915_gem_object_unpin_pages(obj);
3355 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3356 unsigned int *needs_clflush);
3357 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3358 unsigned int *needs_clflush);
3359 #define CLFLUSH_BEFORE 0x1
3360 #define CLFLUSH_AFTER 0x2
3361 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3364 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3366 i915_gem_object_unpin_pages(obj);
3369 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3370 void i915_vma_move_to_active(struct i915_vma *vma,
3371 struct drm_i915_gem_request *req,
3372 unsigned int flags);
3373 int i915_gem_dumb_create(struct drm_file *file_priv,
3374 struct drm_device *dev,
3375 struct drm_mode_create_dumb *args);
3376 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3377 uint32_t handle, uint64_t *offset);
3378 int i915_gem_mmap_gtt_version(void);
3380 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3381 struct drm_i915_gem_object *new,
3382 unsigned frontbuffer_bits);
3384 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3386 struct drm_i915_gem_request *
3387 i915_gem_find_active_request(struct intel_engine_cs *engine);
3389 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3391 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3393 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3396 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3398 return unlikely(test_bit(I915_WEDGED, &error->flags));
3401 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3403 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3406 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3408 return READ_ONCE(error->reset_count);
3411 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3412 void i915_gem_reset(struct drm_i915_private *dev_priv);
3413 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3414 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3416 void i915_gem_init_mmio(struct drm_i915_private *i915);
3417 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3418 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3419 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3420 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3421 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3422 unsigned int flags);
3423 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3424 void i915_gem_resume(struct drm_i915_private *dev_priv);
3425 int i915_gem_fault(struct vm_fault *vmf);
3426 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3429 struct intel_rps_client *rps);
3430 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3433 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3436 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3439 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3440 struct i915_vma * __must_check
3441 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3443 const struct i915_ggtt_view *view);
3444 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3445 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3447 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3448 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3450 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3451 enum i915_cache_level cache_level);
3453 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3454 struct dma_buf *dma_buf);
3456 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3457 struct drm_gem_object *gem_obj, int flags);
3459 static inline struct i915_hw_ppgtt *
3460 i915_vm_to_ppgtt(struct i915_address_space *vm)
3462 return container_of(vm, struct i915_hw_ppgtt, base);
3465 /* i915_gem_fence_reg.c */
3466 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3467 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3469 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3470 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3472 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3473 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3474 struct sg_table *pages);
3475 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3476 struct sg_table *pages);
3478 static inline struct i915_gem_context *
3479 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3481 struct i915_gem_context *ctx;
3483 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3485 ctx = idr_find(&file_priv->context_idr, id);
3487 return ERR_PTR(-ENOENT);
3492 static inline struct i915_gem_context *
3493 i915_gem_context_get(struct i915_gem_context *ctx)
3495 kref_get(&ctx->ref);
3499 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3501 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3502 kref_put(&ctx->ref, i915_gem_context_free);
3505 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3507 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3509 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3513 static inline struct intel_timeline *
3514 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3515 struct intel_engine_cs *engine)
3517 struct i915_address_space *vm;
3519 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3520 return &vm->timeline.engine[engine->id];
3523 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3524 struct drm_file *file);
3526 /* i915_gem_evict.c */
3527 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3528 u64 min_size, u64 alignment,
3529 unsigned cache_level,
3532 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3533 struct drm_mm_node *node,
3534 unsigned int flags);
3535 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3537 /* belongs in i915_gem_gtt.h */
3538 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3541 if (INTEL_GEN(dev_priv) < 6)
3542 intel_gtt_chipset_flush();
3545 /* i915_gem_stolen.c */
3546 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3547 struct drm_mm_node *node, u64 size,
3548 unsigned alignment);
3549 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3550 struct drm_mm_node *node, u64 size,
3551 unsigned alignment, u64 start,
3553 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3554 struct drm_mm_node *node);
3555 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3556 void i915_gem_cleanup_stolen(struct drm_device *dev);
3557 struct drm_i915_gem_object *
3558 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3559 struct drm_i915_gem_object *
3560 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3565 /* i915_gem_internal.c */
3566 struct drm_i915_gem_object *
3567 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3570 /* i915_gem_shrinker.c */
3571 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3572 unsigned long target,
3574 #define I915_SHRINK_PURGEABLE 0x1
3575 #define I915_SHRINK_UNBOUND 0x2
3576 #define I915_SHRINK_BOUND 0x4
3577 #define I915_SHRINK_ACTIVE 0x8
3578 #define I915_SHRINK_VMAPS 0x10
3579 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3580 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3581 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3584 /* i915_gem_tiling.c */
3585 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3587 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3589 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3590 i915_gem_object_is_tiled(obj);
3593 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3594 unsigned int tiling, unsigned int stride);
3595 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3596 unsigned int tiling, unsigned int stride);
3598 /* i915_debugfs.c */
3599 #ifdef CONFIG_DEBUG_FS
3600 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3601 int i915_debugfs_connector_add(struct drm_connector *connector);
3602 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3604 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3605 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3607 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3610 /* i915_gpu_error.c */
3611 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3614 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3615 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3616 const struct i915_gpu_state *gpu);
3617 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3618 struct drm_i915_private *i915,
3619 size_t count, loff_t pos);
3620 static inline void i915_error_state_buf_release(
3621 struct drm_i915_error_state_buf *eb)
3626 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3627 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3629 const char *error_msg);
3631 static inline struct i915_gpu_state *
3632 i915_gpu_state_get(struct i915_gpu_state *gpu)
3634 kref_get(&gpu->ref);
3638 void __i915_gpu_state_free(struct kref *kref);
3639 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3642 kref_put(&gpu->ref, __i915_gpu_state_free);
3645 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3646 void i915_reset_error_state(struct drm_i915_private *i915);
3650 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3652 const char *error_msg)
3656 static inline struct i915_gpu_state *
3657 i915_first_error_state(struct drm_i915_private *i915)
3662 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3668 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3670 /* i915_cmd_parser.c */
3671 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3672 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3673 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3674 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3675 struct drm_i915_gem_object *batch_obj,
3676 struct drm_i915_gem_object *shadow_batch_obj,
3677 u32 batch_start_offset,
3682 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3683 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3684 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3685 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3687 /* i915_suspend.c */
3688 extern int i915_save_state(struct drm_i915_private *dev_priv);
3689 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3692 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3693 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3695 /* intel_lpe_audio.c */
3696 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3697 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3698 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3699 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3700 void *eld, int port, int pipe, int tmds_clk_speed,
3701 bool dp_output, int link_rate);
3704 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3705 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3706 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3709 extern struct i2c_adapter *
3710 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3711 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3712 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3713 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3715 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3717 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3720 int intel_bios_init(struct drm_i915_private *dev_priv);
3721 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3722 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3723 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3724 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3725 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3726 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3727 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3728 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3730 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3734 /* intel_opregion.c */
3736 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3737 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3738 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3739 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3740 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3742 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3744 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3746 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3747 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3748 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3749 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3753 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3758 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3762 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3770 extern void intel_register_dsm_handler(void);
3771 extern void intel_unregister_dsm_handler(void);
3773 static inline void intel_register_dsm_handler(void) { return; }
3774 static inline void intel_unregister_dsm_handler(void) { return; }
3775 #endif /* CONFIG_ACPI */
3777 /* intel_device_info.c */
3778 static inline struct intel_device_info *
3779 mkwrite_device_info(struct drm_i915_private *dev_priv)
3781 return (struct intel_device_info *)&dev_priv->info;
3784 const char *intel_platform_name(enum intel_platform platform);
3785 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3786 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3789 extern void intel_modeset_init_hw(struct drm_device *dev);
3790 extern int intel_modeset_init(struct drm_device *dev);
3791 extern void intel_modeset_gem_init(struct drm_device *dev);
3792 extern void intel_modeset_cleanup(struct drm_device *dev);
3793 extern int intel_connector_register(struct drm_connector *);
3794 extern void intel_connector_unregister(struct drm_connector *);
3795 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3797 extern void intel_display_resume(struct drm_device *dev);
3798 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3799 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3800 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3801 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3802 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3803 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3806 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3807 struct drm_file *file);
3810 extern struct intel_overlay_error_state *
3811 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3812 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3813 struct intel_overlay_error_state *error);
3815 extern struct intel_display_error_state *
3816 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3817 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3818 struct intel_display_error_state *error);
3820 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3821 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3822 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3823 u32 reply_mask, u32 reply, int timeout_base_ms);
3825 /* intel_sideband.c */
3826 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3827 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3828 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3829 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3830 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3831 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3832 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3833 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3834 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3835 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3836 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3837 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3838 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3839 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3840 enum intel_sbi_destination destination);
3841 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3842 enum intel_sbi_destination destination);
3843 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3844 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3846 /* intel_dpio_phy.c */
3847 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3848 enum dpio_phy *phy, enum dpio_channel *ch);
3849 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3850 enum port port, u32 margin, u32 scale,
3851 u32 enable, u32 deemphasis);
3852 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3853 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3854 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3856 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3858 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3859 uint8_t lane_count);
3860 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3861 uint8_t lane_lat_optim_mask);
3862 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3864 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3865 u32 deemph_reg_value, u32 margin_reg_value,
3866 bool uniq_trans_scale);
3867 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3869 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3870 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3871 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3872 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3874 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3875 u32 demph_reg_value, u32 preemph_reg_value,
3876 u32 uniqtranscale_reg_value, u32 tx3_demph);
3877 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3878 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3879 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3881 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3882 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3884 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3885 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3887 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3888 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3889 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3890 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3892 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3893 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3894 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3895 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3897 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3898 * will be implemented using 2 32-bit writes in an arbitrary order with
3899 * an arbitrary delay between them. This can cause the hardware to
3900 * act upon the intermediate value, possibly leading to corruption and
3901 * machine death. For this reason we do not support I915_WRITE64, or
3902 * dev_priv->uncore.funcs.mmio_writeq.
3904 * When reading a 64-bit value as two 32-bit values, the delay may cause
3905 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3906 * occasionally a 64-bit register does not actualy support a full readq
3907 * and must be read using two 32-bit reads.
3909 * You have been warned.
3911 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3913 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3914 u32 upper, lower, old_upper, loop = 0; \
3915 upper = I915_READ(upper_reg); \
3917 old_upper = upper; \
3918 lower = I915_READ(lower_reg); \
3919 upper = I915_READ(upper_reg); \
3920 } while (upper != old_upper && loop++ < 2); \
3921 (u64)upper << 32 | lower; })
3923 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3924 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3926 #define __raw_read(x, s) \
3927 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3930 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3933 #define __raw_write(x, s) \
3934 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3935 i915_reg_t reg, uint##x##_t val) \
3937 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3952 /* These are untraced mmio-accessors that are only valid to be used inside
3953 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3956 * Think twice, and think again, before using these.
3958 * As an example, these accessors can possibly be used between:
3960 * spin_lock_irq(&dev_priv->uncore.lock);
3961 * intel_uncore_forcewake_get__locked();
3965 * intel_uncore_forcewake_put__locked();
3966 * spin_unlock_irq(&dev_priv->uncore.lock);
3969 * Note: some registers may not need forcewake held, so
3970 * intel_uncore_forcewake_{get,put} can be omitted, see
3971 * intel_uncore_forcewake_for_reg().
3973 * Certain architectures will die if the same cacheline is concurrently accessed
3974 * by different clients (e.g. on Ivybridge). Access to registers should
3975 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3976 * a more localised lock guarding all access to that bank of registers.
3978 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3979 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3980 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3981 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3983 /* "Broadcast RGB" property */
3984 #define INTEL_BROADCAST_RGB_AUTO 0
3985 #define INTEL_BROADCAST_RGB_FULL 1
3986 #define INTEL_BROADCAST_RGB_LIMITED 2
3988 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3990 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3991 return VLV_VGACNTRL;
3992 else if (INTEL_GEN(dev_priv) >= 5)
3993 return CPU_VGACNTRL;
3998 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
4000 unsigned long j = msecs_to_jiffies(m);
4002 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4005 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4007 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4010 static inline unsigned long
4011 timespec_to_jiffies_timeout(const struct timespec *value)
4013 unsigned long j = timespec_to_jiffies(value);
4015 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4019 * If you need to wait X milliseconds between events A and B, but event B
4020 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4021 * when event A happened, then just before event B you call this function and
4022 * pass the timestamp as the first argument, and X as the second argument.
4025 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4027 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4030 * Don't re-read the value of "jiffies" every time since it may change
4031 * behind our back and break the math.
4033 tmp_jiffies = jiffies;
4034 target_jiffies = timestamp_jiffies +
4035 msecs_to_jiffies_timeout(to_wait_ms);
4037 if (time_after(target_jiffies, tmp_jiffies)) {
4038 remaining_jiffies = target_jiffies - tmp_jiffies;
4039 while (remaining_jiffies)
4041 schedule_timeout_uninterruptible(remaining_jiffies);
4046 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4048 struct intel_engine_cs *engine = req->engine;
4051 /* Note that the engine may have wrapped around the seqno, and
4052 * so our request->global_seqno will be ahead of the hardware,
4053 * even though it completed the request before wrapping. We catch
4054 * this by kicking all the waiters before resetting the seqno
4055 * in hardware, and also signal the fence.
4057 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4060 /* The request was dequeued before we were awoken. We check after
4061 * inspecting the hw to confirm that this was the same request
4062 * that generated the HWS update. The memory barriers within
4063 * the request execution are sufficient to ensure that a check
4064 * after reading the value from hw matches this request.
4066 seqno = i915_gem_request_global_seqno(req);
4070 /* Before we do the heavier coherent read of the seqno,
4071 * check the value (hopefully) in the CPU cacheline.
4073 if (__i915_gem_request_completed(req, seqno))
4076 /* Ensure our read of the seqno is coherent so that we
4077 * do not "miss an interrupt" (i.e. if this is the last
4078 * request and the seqno write from the GPU is not visible
4079 * by the time the interrupt fires, we will see that the
4080 * request is incomplete and go back to sleep awaiting
4081 * another interrupt that will never come.)
4083 * Strictly, we only need to do this once after an interrupt,
4084 * but it is easier and safer to do it every time the waiter
4087 if (engine->irq_seqno_barrier &&
4088 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4089 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4090 unsigned long flags;
4092 /* The ordering of irq_posted versus applying the barrier
4093 * is crucial. The clearing of the current irq_posted must
4094 * be visible before we perform the barrier operation,
4095 * such that if a subsequent interrupt arrives, irq_posted
4096 * is reasserted and our task rewoken (which causes us to
4097 * do another __i915_request_irq_complete() immediately
4098 * and reapply the barrier). Conversely, if the clear
4099 * occurs after the barrier, then an interrupt that arrived
4100 * whilst we waited on the barrier would not trigger a
4101 * barrier on the next pass, and the read may not see the
4104 engine->irq_seqno_barrier(engine);
4106 /* If we consume the irq, but we are no longer the bottom-half,
4107 * the real bottom-half may not have serialised their own
4108 * seqno check with the irq-barrier (i.e. may have inspected
4109 * the seqno before we believe it coherent since they see
4110 * irq_posted == false but we are still running).
4112 spin_lock_irqsave(&b->irq_lock, flags);
4113 if (b->irq_wait && b->irq_wait->tsk != current)
4114 /* Note that if the bottom-half is changed as we
4115 * are sending the wake-up, the new bottom-half will
4116 * be woken by whomever made the change. We only have
4117 * to worry about when we steal the irq-posted for
4120 wake_up_process(b->irq_wait->tsk);
4121 spin_unlock_irqrestore(&b->irq_lock, flags);
4123 if (__i915_gem_request_completed(req, seqno))
4130 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4131 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4133 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4134 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4135 * perform the operation. To check beforehand, pass in the parameters to
4136 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4137 * you only need to pass in the minor offsets, page-aligned pointers are
4140 * For just checking for SSE4.1, in the foreknowledge that the future use
4141 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4143 #define i915_can_memcpy_from_wc(dst, src, len) \
4144 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4146 #define i915_has_memcpy_from_wc() \
4147 i915_memcpy_from_wc(NULL, NULL, 0)
4150 int remap_io_mapping(struct vm_area_struct *vma,
4151 unsigned long addr, unsigned long pfn, unsigned long size,
4152 struct io_mapping *iomap);
4154 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4156 return (obj->cache_level != I915_CACHE_NONE ||
4157 HAS_LLC(to_i915(obj->base.dev)));