1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
58 #include "i915_fixed.h"
59 #include "i915_params.h"
61 #include "i915_utils.h"
63 #include "intel_bios.h"
64 #include "intel_device_info.h"
65 #include "intel_display.h"
66 #include "intel_dpll_mgr.h"
67 #include "intel_lrc.h"
68 #include "intel_opregion.h"
69 #include "intel_ringbuffer.h"
70 #include "intel_uncore.h"
71 #include "intel_wopcm.h"
72 #include "intel_workarounds.h"
76 #include "i915_gem_context.h"
77 #include "i915_gem_fence_reg.h"
78 #include "i915_gem_object.h"
79 #include "i915_gem_gtt.h"
80 #include "i915_gpu_error.h"
81 #include "i915_request.h"
82 #include "i915_scheduler.h"
83 #include "i915_timeline.h"
86 #include "intel_gvt.h"
88 /* General customization:
91 #define DRIVER_NAME "i915"
92 #define DRIVER_DESC "Intel Graphics"
93 #define DRIVER_DATE "20181221"
94 #define DRIVER_TIMESTAMP 1545422678
96 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
97 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
98 * which may not necessarily be a user visible problem. This will either
99 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
100 * enable distros and users to tailor their preferred amount of i915 abrt
103 #define I915_STATE_WARN(condition, format...) ({ \
104 int __ret_warn_on = !!(condition); \
105 if (unlikely(__ret_warn_on)) \
106 if (!WARN(i915_modparams.verbose_state_checks, format)) \
108 unlikely(__ret_warn_on); \
111 #define I915_STATE_WARN_ON(x) \
112 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
114 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
116 bool __i915_inject_load_failure(const char *func, int line);
117 #define i915_inject_load_failure() \
118 __i915_inject_load_failure(__func__, __LINE__)
120 bool i915_error_injected(void);
124 #define i915_inject_load_failure() false
125 #define i915_error_injected() false
129 #define i915_load_error(i915, fmt, ...) \
130 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
135 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
148 #define for_each_hpd_pin(__pin) \
149 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
151 /* Threshold == 5 for long IRQs, 50 for short */
152 #define HPD_STORM_DEFAULT_THRESHOLD 50
154 struct i915_hotplug {
155 struct work_struct hotplug_work;
158 unsigned long last_jiffies;
163 HPD_MARK_DISABLED = 2
165 } stats[HPD_NUM_PINS];
167 struct delayed_work reenable_work;
171 struct work_struct dig_port_work;
173 struct work_struct poll_init_work;
176 unsigned int hpd_storm_threshold;
177 /* Whether or not to count short HPD IRQs in HPD storms */
178 u8 hpd_short_storm_enabled;
181 * if we get a HPD irq from DP and a HPD irq from non-DP
182 * the non-DP HPD could block the workqueue on a mode config
183 * mutex getting, that userspace may have taken. However
184 * userspace is waiting on the DP workqueue to run which is
185 * blocked behind the non-DP one.
187 struct workqueue_struct *dp_wq;
190 #define I915_GEM_GPU_DOMAINS \
191 (I915_GEM_DOMAIN_RENDER | \
192 I915_GEM_DOMAIN_SAMPLER | \
193 I915_GEM_DOMAIN_COMMAND | \
194 I915_GEM_DOMAIN_INSTRUCTION | \
195 I915_GEM_DOMAIN_VERTEX)
197 struct drm_i915_private;
198 struct i915_mm_struct;
199 struct i915_mmu_object;
201 struct drm_i915_file_private {
202 struct drm_i915_private *dev_priv;
203 struct drm_file *file;
207 struct list_head request_list;
208 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
209 * chosen to prevent the CPU getting more than a frame ahead of the GPU
210 * (when using lax throttling for the frontbuffer). We also use it to
211 * offer free GPU waitboosts for severely congested workloads.
213 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
215 struct idr context_idr;
217 struct intel_rps_client {
221 unsigned int bsd_engine;
224 * Every context ban increments per client ban score. Also
225 * hangs in short succession increments ban score. If ban threshold
226 * is reached, client is considered banned and submitting more work
227 * will fail. This is a stop gap measure to limit the badly behaving
228 * clients access to gpu. Note that unbannable contexts never increment
229 * the client ban score.
231 #define I915_CLIENT_SCORE_HANG_FAST 1
232 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
233 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
234 #define I915_CLIENT_SCORE_BANNED 9
235 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
237 unsigned long hang_timestamp;
240 /* Interface history:
243 * 1.2: Add Power Management
244 * 1.3: Add vblank support
245 * 1.4: Fix cmdbuffer path, add heap destroy
246 * 1.5: Add vblank pipe configuration
247 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
248 * - Support vertical blank on secondary display pipe
250 #define DRIVER_MAJOR 1
251 #define DRIVER_MINOR 6
252 #define DRIVER_PATCHLEVEL 0
254 struct intel_overlay;
255 struct intel_overlay_error_state;
257 struct sdvo_device_mapping {
266 struct intel_connector;
267 struct intel_encoder;
268 struct intel_atomic_state;
269 struct intel_crtc_state;
270 struct intel_initial_plane_config;
274 struct intel_cdclk_state;
276 struct drm_i915_display_funcs {
277 void (*get_cdclk)(struct drm_i915_private *dev_priv,
278 struct intel_cdclk_state *cdclk_state);
279 void (*set_cdclk)(struct drm_i915_private *dev_priv,
280 const struct intel_cdclk_state *cdclk_state);
281 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
282 enum i9xx_plane_id i9xx_plane);
283 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
284 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
285 void (*initial_watermarks)(struct intel_atomic_state *state,
286 struct intel_crtc_state *cstate);
287 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
288 struct intel_crtc_state *cstate);
289 void (*optimize_watermarks)(struct intel_atomic_state *state,
290 struct intel_crtc_state *cstate);
291 int (*compute_global_watermarks)(struct intel_atomic_state *state);
292 void (*update_wm)(struct intel_crtc *crtc);
293 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
294 /* Returns the active state of the crtc, and if the crtc is active,
295 * fills out the pipe-config with the hw state. */
296 bool (*get_pipe_config)(struct intel_crtc *,
297 struct intel_crtc_state *);
298 void (*get_initial_plane_config)(struct intel_crtc *,
299 struct intel_initial_plane_config *);
300 int (*crtc_compute_clock)(struct intel_crtc *crtc,
301 struct intel_crtc_state *crtc_state);
302 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
303 struct drm_atomic_state *old_state);
304 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
305 struct drm_atomic_state *old_state);
306 void (*update_crtcs)(struct drm_atomic_state *state);
307 void (*audio_codec_enable)(struct intel_encoder *encoder,
308 const struct intel_crtc_state *crtc_state,
309 const struct drm_connector_state *conn_state);
310 void (*audio_codec_disable)(struct intel_encoder *encoder,
311 const struct intel_crtc_state *old_crtc_state,
312 const struct drm_connector_state *old_conn_state);
313 void (*fdi_link_train)(struct intel_crtc *crtc,
314 const struct intel_crtc_state *crtc_state);
315 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
316 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
317 /* clock updates for mode set */
319 /* render clock increase/decrease */
320 /* display clock increase/decrease */
321 /* pll clock increase/decrease */
323 void (*load_csc_matrix)(struct intel_crtc_state *crtc_state);
324 void (*load_luts)(struct intel_crtc_state *crtc_state);
327 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
328 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
329 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
332 struct work_struct work;
334 uint32_t required_version;
335 uint32_t max_fw_size; /* bytes */
336 uint32_t *dmc_payload;
337 uint32_t dmc_fw_size; /* dwords */
340 i915_reg_t mmioaddr[8];
341 uint32_t mmiodata[8];
343 uint32_t allowed_dc_mask;
346 enum i915_cache_level {
348 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
349 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
350 caches, eg sampler/render caches, and the
351 large Last-Level-Cache. LLC is coherent with
352 the CPU, but L3 is only visible to the GPU. */
353 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
356 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
367 /* This is always the inner lock when overlapping with struct_mutex and
368 * it's the outer lock when overlapping with stolen_lock. */
371 unsigned int possible_framebuffer_bits;
372 unsigned int busy_bits;
373 unsigned int visible_pipes_mask;
374 struct intel_crtc *crtc;
376 struct drm_mm_node compressed_fb;
377 struct drm_mm_node *compressed_llb;
385 bool underrun_detected;
386 struct work_struct underrun_work;
389 * Due to the atomic rules we can't access some structures without the
390 * appropriate locking, so we cache information here in order to avoid
393 struct intel_fbc_state_cache {
394 struct i915_vma *vma;
398 unsigned int mode_flags;
399 uint32_t hsw_bdw_pixel_rate;
403 unsigned int rotation;
408 * Display surface base address adjustement for
409 * pageflips. Note that on gen4+ this only adjusts up
410 * to a tile, offsets within a tile are handled in
411 * the hw itself (with the TILEOFF register).
418 uint16_t pixel_blend_mode;
422 const struct drm_format_info *format;
428 * This structure contains everything that's relevant to program the
429 * hardware registers. When we want to figure out if we need to disable
430 * and re-enable FBC for a new configuration we just check if there's
431 * something different in the struct. The genx_fbc_activate functions
432 * are supposed to read from it in order to program the registers.
434 struct intel_fbc_reg_params {
435 struct i915_vma *vma;
440 enum i9xx_plane_id i9xx_plane;
441 unsigned int fence_y_offset;
445 const struct drm_format_info *format;
450 unsigned int gen9_wa_cfb_stride;
453 const char *no_fbc_reason;
457 * HIGH_RR is the highest eDP panel refresh rate read from EDID
458 * LOW_RR is the lowest eDP panel refresh rate found from EDID
459 * parsing for same resolution.
461 enum drrs_refresh_rate_type {
464 DRRS_MAX_RR, /* RR count */
467 enum drrs_support_type {
468 DRRS_NOT_SUPPORTED = 0,
469 STATIC_DRRS_SUPPORT = 1,
470 SEAMLESS_DRRS_SUPPORT = 2
476 struct delayed_work work;
478 unsigned busy_frontbuffer_bits;
479 enum drrs_refresh_rate_type refresh_rate_type;
480 enum drrs_support_type type;
486 #define I915_PSR_DEBUG_MODE_MASK 0x0f
487 #define I915_PSR_DEBUG_DEFAULT 0x00
488 #define I915_PSR_DEBUG_DISABLE 0x01
489 #define I915_PSR_DEBUG_ENABLE 0x02
490 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
491 #define I915_PSR_DEBUG_IRQ 0x10
495 bool prepared, enabled;
499 struct work_struct work;
500 unsigned busy_frontbuffer_bits;
501 bool sink_psr2_support;
503 bool colorimetry_support;
505 u8 sink_sync_latency;
506 ktime_t last_entry_attempt;
508 bool sink_not_reliable;
510 u16 su_x_granularity;
514 PCH_NONE = 0, /* No PCH present */
515 PCH_IBX, /* Ibexpeak PCH */
516 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
517 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
518 PCH_SPT, /* Sunrisepoint PCH */
519 PCH_KBP, /* Kaby Lake PCH */
520 PCH_CNP, /* Cannon Lake PCH */
521 PCH_ICP, /* Ice Lake PCH */
522 PCH_NOP, /* PCH without south display */
525 enum intel_sbi_destination {
530 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
531 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
532 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
533 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
534 #define QUIRK_INCREASE_T12_DELAY (1<<6)
535 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
538 struct intel_fbc_work;
541 struct i2c_adapter adapter;
542 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
546 struct i2c_algo_bit_data bit_algo;
547 struct drm_i915_private *dev_priv;
550 struct i915_suspend_saved_registers {
553 u32 saveCACHE_MODE_0;
554 u32 saveMI_ARB_STATE;
558 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
559 u32 savePCH_PORT_HOTPLUG;
563 struct vlv_s0ix_state {
570 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
571 u32 media_max_req_count;
572 u32 gfx_max_req_count;
604 /* Display 1 CZ domain */
609 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
611 /* GT SA CZ domain */
618 /* Display 2 CZ domain */
625 struct intel_rps_ei {
633 * work, interrupts_enabled and pm_iir are protected by
636 struct work_struct work;
637 bool interrupts_enabled;
640 /* PM interrupt bits that should never be masked */
643 /* Frequencies are stored in potentially platform dependent multiples.
644 * In other words, *_freq needs to be multiplied by X to be interesting.
645 * Soft limits are those which are used for the dynamic reclocking done
646 * by the driver (raise frequencies under heavy loads, and lower for
647 * lighter loads). Hard limits are those imposed by the hardware.
649 * A distinction is made for overclocking, which is never enabled by
650 * default, and is considered to be above the hard limit if it's
653 u8 cur_freq; /* Current frequency (cached, may not == HW) */
654 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
655 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
656 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
657 u8 min_freq; /* AKA RPn. Minimum frequency */
658 u8 boost_freq; /* Frequency to request when wait boosting */
659 u8 idle_freq; /* Frequency to request when we are idle */
660 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
661 u8 rp1_freq; /* "less than" RP0 power/freqency */
662 u8 rp0_freq; /* Non-overclocked max frequency. */
663 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
670 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
671 unsigned int interactive;
673 u8 up_threshold; /* Current %busy required to uplock */
674 u8 down_threshold; /* Current %busy required to downclock */
678 atomic_t num_waiters;
681 /* manual wa residency calculations */
682 struct intel_rps_ei ei;
687 u64 prev_hw_residency[4];
688 u64 cur_residency[4];
691 struct intel_llc_pstate {
695 struct intel_gen6_power_mgmt {
696 struct intel_rps rps;
697 struct intel_rc6 rc6;
698 struct intel_llc_pstate llc_pstate;
701 /* defined intel_pm.c */
702 extern spinlock_t mchdev_lock;
704 struct intel_ilk_power_mgmt {
712 unsigned long last_time1;
713 unsigned long chipset_power;
716 unsigned long gfx_power;
723 struct drm_i915_private;
724 struct i915_power_well;
726 struct i915_power_well_ops {
728 * Synchronize the well's hw state to match the current sw state, for
729 * example enable/disable it based on the current refcount. Called
730 * during driver init and resume time, possibly after first calling
731 * the enable/disable handlers.
733 void (*sync_hw)(struct drm_i915_private *dev_priv,
734 struct i915_power_well *power_well);
736 * Enable the well and resources that depend on it (for example
737 * interrupts located on the well). Called after the 0->1 refcount
740 void (*enable)(struct drm_i915_private *dev_priv,
741 struct i915_power_well *power_well);
743 * Disable the well and resources that depend on it. Called after
744 * the 1->0 refcount transition.
746 void (*disable)(struct drm_i915_private *dev_priv,
747 struct i915_power_well *power_well);
748 /* Returns the hw enabled state. */
749 bool (*is_enabled)(struct drm_i915_private *dev_priv,
750 struct i915_power_well *power_well);
753 struct i915_power_well_regs {
760 /* Power well structure for haswell */
761 struct i915_power_well_desc {
765 /* unique identifier for this power well */
766 enum i915_power_well_id id;
768 * Arbitraty data associated with this power well. Platform and power
774 * request/status flag index in the PUNIT power well
775 * control/status registers.
783 const struct i915_power_well_regs *regs;
785 * request/status flag index in the power well
786 * constrol/status registers.
789 /* Mask of pipes whose IRQ logic is backed by the pw */
791 /* The pw is backing the VGA functionality */
795 * The pw is for an ICL+ TypeC PHY port in
801 const struct i915_power_well_ops *ops;
804 struct i915_power_well {
805 const struct i915_power_well_desc *desc;
806 /* power well enable/disable usage count */
808 /* cached hw enabled state */
812 struct i915_power_domains {
814 * Power wells needed for initialization at driver init and suspend
815 * time are on. They are kept on until after the first modeset.
818 bool display_core_suspended;
819 int power_well_count;
822 int domain_use_count[POWER_DOMAIN_NUM];
823 struct i915_power_well *power_wells;
826 #define MAX_L3_SLICES 2
827 struct intel_l3_parity {
828 u32 *remap_info[MAX_L3_SLICES];
829 struct work_struct error_work;
834 /** Memory allocator for GTT stolen memory */
835 struct drm_mm stolen;
836 /** Protects the usage of the GTT stolen memory allocator. This is
837 * always the inner lock when overlapping with struct_mutex. */
838 struct mutex stolen_lock;
840 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
843 /** List of all objects in gtt_space. Used to restore gtt
844 * mappings on resume */
845 struct list_head bound_list;
847 * List of objects which are not bound to the GTT (thus
848 * are idle and not used by the GPU). These objects may or may
849 * not actually have any pages attached.
851 struct list_head unbound_list;
853 /** List of all objects in gtt_space, currently mmaped by userspace.
854 * All objects within this list must also be on bound_list.
856 struct list_head userfault_list;
859 * List of objects which are pending destruction.
861 struct llist_head free_list;
862 struct work_struct free_work;
863 spinlock_t free_lock;
865 * Count of objects pending destructions. Used to skip needlessly
866 * waiting on an RCU barrier if no objects are waiting to be freed.
871 * Small stash of WC pages
873 struct pagestash wc_stash;
876 * tmpfs instance used for shmem backed objects
878 struct vfsmount *gemfs;
880 /** PPGTT used for aliasing the PPGTT with the GTT */
881 struct i915_hw_ppgtt *aliasing_ppgtt;
883 struct notifier_block oom_notifier;
884 struct notifier_block vmap_notifier;
885 struct shrinker shrinker;
887 /** LRU list of objects with fence regs on them. */
888 struct list_head fence_list;
891 * Workqueue to fault in userptr pages, flushed by the execbuf
892 * when required but otherwise left to userspace to try again
895 struct workqueue_struct *userptr_wq;
897 u64 unordered_timeline;
899 /* the indicator for dispatch video commands on two BSD rings */
900 atomic_t bsd_engine_dispatch_index;
902 /** Bit 6 swizzling required for X tiling */
903 uint32_t bit_6_swizzle_x;
904 /** Bit 6 swizzling required for Y tiling */
905 uint32_t bit_6_swizzle_y;
907 /* accounting, useful for userland debugging */
908 spinlock_t object_stat_lock;
913 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
915 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
916 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
918 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
919 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
921 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
923 struct ddi_vbt_port_info {
927 * This is an index in the HDMI/DVI DDI buffer translation table.
928 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
929 * populate this field.
931 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
932 uint8_t hdmi_level_shift;
934 uint8_t supports_dvi:1;
935 uint8_t supports_hdmi:1;
936 uint8_t supports_dp:1;
937 uint8_t supports_edp:1;
938 uint8_t supports_typec_usb:1;
939 uint8_t supports_tbt:1;
941 uint8_t alternate_aux_channel;
942 uint8_t alternate_ddc_pin;
944 uint8_t dp_boost_level;
945 uint8_t hdmi_boost_level;
946 int dp_max_link_rate; /* 0 for not limited by VBT */
949 enum psr_lines_to_wait {
950 PSR_0_LINES_TO_WAIT = 0,
956 struct intel_vbt_data {
957 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
958 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
961 unsigned int int_tv_support:1;
962 unsigned int lvds_dither:1;
963 unsigned int int_crt_support:1;
964 unsigned int lvds_use_ssc:1;
965 unsigned int int_lvds_support:1;
966 unsigned int display_clock_mode:1;
967 unsigned int fdi_rx_polarity_inverted:1;
968 unsigned int panel_type:4;
970 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
971 enum drm_panel_orientation orientation;
973 enum drrs_support_type drrs_type;
983 struct edp_power_seq pps;
989 bool require_aux_wakeup;
991 enum psr_lines_to_wait lines_to_wait;
992 int tp1_wakeup_time_us;
993 int tp2_tp3_wakeup_time_us;
1000 u8 min_brightness; /* min_brightness/255 of max */
1001 u8 controller; /* brightness controller number */
1002 enum intel_backlight_type type;
1008 struct mipi_config *config;
1009 struct mipi_pps_data *pps;
1015 const u8 *sequence[MIPI_SEQ_MAX];
1016 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1017 enum drm_panel_orientation orientation;
1023 struct child_device_config *child_dev;
1025 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1026 struct sdvo_device_mapping sdvo_mappings[2];
1029 enum intel_ddb_partitioning {
1031 INTEL_DDB_PART_5_6, /* IVB+ */
1034 struct intel_wm_level {
1042 struct ilk_wm_values {
1043 uint32_t wm_pipe[3];
1045 uint32_t wm_lp_spr[3];
1046 uint32_t wm_linetime[3];
1048 enum intel_ddb_partitioning partitioning;
1051 struct g4x_pipe_wm {
1052 uint16_t plane[I915_MAX_PLANES];
1062 struct vlv_wm_ddl_values {
1063 uint8_t plane[I915_MAX_PLANES];
1066 struct vlv_wm_values {
1067 struct g4x_pipe_wm pipe[3];
1068 struct g4x_sr_wm sr;
1069 struct vlv_wm_ddl_values ddl[3];
1074 struct g4x_wm_values {
1075 struct g4x_pipe_wm pipe[2];
1076 struct g4x_sr_wm sr;
1077 struct g4x_sr_wm hpll;
1083 struct skl_ddb_entry {
1084 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1087 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1089 return entry->end - entry->start;
1092 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1093 const struct skl_ddb_entry *e2)
1095 if (e1->start == e2->start && e1->end == e2->end)
1101 struct skl_ddb_allocation {
1102 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1105 struct skl_ddb_values {
1106 unsigned dirty_pipes;
1107 struct skl_ddb_allocation ddb;
1110 struct skl_wm_level {
1111 uint16_t plane_res_b;
1112 uint8_t plane_res_l;
1116 /* Stores plane specific WM parameters */
1117 struct skl_wm_params {
1118 bool x_tiled, y_tiled;
1123 uint32_t plane_pixel_rate;
1124 uint32_t y_min_scanlines;
1125 uint32_t plane_bytes_per_line;
1126 uint_fixed_16_16_t plane_blocks_per_line;
1127 uint_fixed_16_16_t y_tile_minimum;
1128 uint32_t linetime_us;
1129 uint32_t dbuf_block_size;
1133 * This struct helps tracking the state needed for runtime PM, which puts the
1134 * device in PCI D3 state. Notice that when this happens, nothing on the
1135 * graphics device works, even register access, so we don't get interrupts nor
1138 * Every piece of our code that needs to actually touch the hardware needs to
1139 * either call intel_runtime_pm_get or call intel_display_power_get with the
1140 * appropriate power domain.
1142 * Our driver uses the autosuspend delay feature, which means we'll only really
1143 * suspend if we stay with zero refcount for a certain amount of time. The
1144 * default value is currently very conservative (see intel_runtime_pm_enable), but
1145 * it can be changed with the standard runtime PM files from sysfs.
1147 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1148 * goes back to false exactly before we reenable the IRQs. We use this variable
1149 * to check if someone is trying to enable/disable IRQs while they're supposed
1150 * to be disabled. This shouldn't happen and we'll print some error messages in
1153 * For more, read the Documentation/power/runtime_pm.txt.
1155 struct i915_runtime_pm {
1156 atomic_t wakeref_count;
1161 enum intel_pipe_crc_source {
1162 INTEL_PIPE_CRC_SOURCE_NONE,
1163 INTEL_PIPE_CRC_SOURCE_PLANE1,
1164 INTEL_PIPE_CRC_SOURCE_PLANE2,
1165 INTEL_PIPE_CRC_SOURCE_PF,
1166 INTEL_PIPE_CRC_SOURCE_PIPE,
1167 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1168 INTEL_PIPE_CRC_SOURCE_TV,
1169 INTEL_PIPE_CRC_SOURCE_DP_B,
1170 INTEL_PIPE_CRC_SOURCE_DP_C,
1171 INTEL_PIPE_CRC_SOURCE_DP_D,
1172 INTEL_PIPE_CRC_SOURCE_AUTO,
1173 INTEL_PIPE_CRC_SOURCE_MAX,
1176 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1177 struct intel_pipe_crc {
1180 enum intel_pipe_crc_source source;
1183 struct i915_frontbuffer_tracking {
1187 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1194 struct i915_virtual_gpu {
1199 /* used in computing the new watermarks state */
1200 struct intel_wm_config {
1201 unsigned int num_pipes_active;
1202 bool sprites_enabled;
1203 bool sprites_scaled;
1206 struct i915_oa_format {
1211 struct i915_oa_reg {
1216 struct i915_oa_config {
1217 char uuid[UUID_STRING_LEN + 1];
1220 const struct i915_oa_reg *mux_regs;
1222 const struct i915_oa_reg *b_counter_regs;
1223 u32 b_counter_regs_len;
1224 const struct i915_oa_reg *flex_regs;
1227 struct attribute_group sysfs_metric;
1228 struct attribute *attrs[2];
1229 struct device_attribute sysfs_metric_id;
1234 struct i915_perf_stream;
1237 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1239 struct i915_perf_stream_ops {
1241 * @enable: Enables the collection of HW samples, either in response to
1242 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1243 * without `I915_PERF_FLAG_DISABLED`.
1245 void (*enable)(struct i915_perf_stream *stream);
1248 * @disable: Disables the collection of HW samples, either in response
1249 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1252 void (*disable)(struct i915_perf_stream *stream);
1255 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1256 * once there is something ready to read() for the stream
1258 void (*poll_wait)(struct i915_perf_stream *stream,
1263 * @wait_unlocked: For handling a blocking read, wait until there is
1264 * something to ready to read() for the stream. E.g. wait on the same
1265 * wait queue that would be passed to poll_wait().
1267 int (*wait_unlocked)(struct i915_perf_stream *stream);
1270 * @read: Copy buffered metrics as records to userspace
1271 * **buf**: the userspace, destination buffer
1272 * **count**: the number of bytes to copy, requested by userspace
1273 * **offset**: zero at the start of the read, updated as the read
1274 * proceeds, it represents how many bytes have been copied so far and
1275 * the buffer offset for copying the next record.
1277 * Copy as many buffered i915 perf samples and records for this stream
1278 * to userspace as will fit in the given buffer.
1280 * Only write complete records; returning -%ENOSPC if there isn't room
1281 * for a complete record.
1283 * Return any error condition that results in a short read such as
1284 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1285 * returning to userspace.
1287 int (*read)(struct i915_perf_stream *stream,
1293 * @destroy: Cleanup any stream specific resources.
1295 * The stream will always be disabled before this is called.
1297 void (*destroy)(struct i915_perf_stream *stream);
1301 * struct i915_perf_stream - state for a single open stream FD
1303 struct i915_perf_stream {
1305 * @dev_priv: i915 drm device
1307 struct drm_i915_private *dev_priv;
1310 * @link: Links the stream into ``&drm_i915_private->streams``
1312 struct list_head link;
1315 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1316 * properties given when opening a stream, representing the contents
1317 * of a single sample as read() by userspace.
1322 * @sample_size: Considering the configured contents of a sample
1323 * combined with the required header size, this is the total size
1324 * of a single sample record.
1329 * @ctx: %NULL if measuring system-wide across all contexts or a
1330 * specific context that is being monitored.
1332 struct i915_gem_context *ctx;
1335 * @enabled: Whether the stream is currently enabled, considering
1336 * whether the stream was opened in a disabled state and based
1337 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1342 * @ops: The callbacks providing the implementation of this specific
1343 * type of configured stream.
1345 const struct i915_perf_stream_ops *ops;
1348 * @oa_config: The OA configuration used by the stream.
1350 struct i915_oa_config *oa_config;
1354 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1356 struct i915_oa_ops {
1358 * @is_valid_b_counter_reg: Validates register's address for
1359 * programming boolean counters for a particular platform.
1361 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1365 * @is_valid_mux_reg: Validates register's address for programming mux
1366 * for a particular platform.
1368 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1371 * @is_valid_flex_reg: Validates register's address for programming
1372 * flex EU filtering for a particular platform.
1374 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1377 * @enable_metric_set: Selects and applies any MUX configuration to set
1378 * up the Boolean and Custom (B/C) counters that are part of the
1379 * counter reports being sampled. May apply system constraints such as
1380 * disabling EU clock gating as required.
1382 int (*enable_metric_set)(struct i915_perf_stream *stream);
1385 * @disable_metric_set: Remove system constraints associated with using
1388 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1391 * @oa_enable: Enable periodic sampling
1393 void (*oa_enable)(struct i915_perf_stream *stream);
1396 * @oa_disable: Disable periodic sampling
1398 void (*oa_disable)(struct i915_perf_stream *stream);
1401 * @read: Copy data from the circular OA buffer into a given userspace
1404 int (*read)(struct i915_perf_stream *stream,
1410 * @oa_hw_tail_read: read the OA tail pointer register
1412 * In particular this enables us to share all the fiddly code for
1413 * handling the OA unit tail pointer race that affects multiple
1416 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1419 struct intel_cdclk_state {
1420 unsigned int cdclk, vco, ref, bypass;
1424 struct drm_i915_private {
1425 struct drm_device drm;
1427 struct kmem_cache *objects;
1428 struct kmem_cache *vmas;
1429 struct kmem_cache *luts;
1430 struct kmem_cache *requests;
1431 struct kmem_cache *dependencies;
1432 struct kmem_cache *priorities;
1434 const struct intel_device_info info;
1435 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1436 struct intel_driver_caps caps;
1439 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1440 * end of stolen which we can optionally use to create GEM objects
1441 * backed by stolen memory. Note that stolen_usable_size tells us
1442 * exactly how much of this we are actually allowed to use, given that
1443 * some portion of it is in fact reserved for use by hardware functions.
1445 struct resource dsm;
1447 * Reseved portion of Data Stolen Memory
1449 struct resource dsm_reserved;
1452 * Stolen memory is segmented in hardware with different portions
1453 * offlimits to certain functions.
1455 * The drm_mm is initialised to the total accessible range, as found
1456 * from the PCI config. On Broadwell+, this is further restricted to
1457 * avoid the first page! The upper end of stolen memory is reserved for
1458 * hardware functions and similarly removed from the accessible range.
1460 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1464 struct intel_uncore uncore;
1466 struct i915_virtual_gpu vgpu;
1468 struct intel_gvt *gvt;
1470 struct intel_wopcm wopcm;
1472 struct intel_huc huc;
1473 struct intel_guc guc;
1475 struct intel_csr csr;
1477 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1479 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1480 * controller on different i2c buses. */
1481 struct mutex gmbus_mutex;
1484 * Base address of where the gmbus and gpio blocks are located (either
1485 * on PCH or on SoC for platforms without PCH).
1487 uint32_t gpio_mmio_base;
1489 /* MMIO base address for MIPI regs */
1490 uint32_t mipi_mmio_base;
1492 uint32_t psr_mmio_base;
1494 uint32_t pps_mmio_base;
1496 wait_queue_head_t gmbus_wait_queue;
1498 struct pci_dev *bridge_dev;
1499 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1500 /* Context used internally to idle the GPU and setup initial state */
1501 struct i915_gem_context *kernel_context;
1502 /* Context only to be used for injecting preemption commands */
1503 struct i915_gem_context *preempt_context;
1504 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1505 [MAX_ENGINE_INSTANCE + 1];
1507 struct resource mch_res;
1509 /* protects the irq masks */
1510 spinlock_t irq_lock;
1512 bool display_irqs_enabled;
1514 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1515 struct pm_qos_request pm_qos;
1517 /* Sideband mailbox protection */
1518 struct mutex sb_lock;
1520 /** Cached value of IMR to avoid reads in updating the bitfield */
1523 u32 de_irq_mask[I915_MAX_PIPES];
1530 u32 pipestat_irq_mask[I915_MAX_PIPES];
1532 struct i915_hotplug hotplug;
1533 struct intel_fbc fbc;
1534 struct i915_drrs drrs;
1535 struct intel_opregion opregion;
1536 struct intel_vbt_data vbt;
1538 bool preserve_bios_swizzle;
1541 struct intel_overlay *overlay;
1543 /* backlight registers and fields in struct intel_panel */
1544 struct mutex backlight_lock;
1547 bool no_aux_handshake;
1549 /* protects panel power sequencer state */
1550 struct mutex pps_mutex;
1552 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1553 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1555 unsigned int fsb_freq, mem_freq, is_ddr3;
1556 unsigned int skl_preferred_vco_freq;
1557 unsigned int max_cdclk_freq;
1559 unsigned int max_dotclk_freq;
1560 unsigned int rawclk_freq;
1561 unsigned int hpll_freq;
1562 unsigned int fdi_pll_freq;
1563 unsigned int czclk_freq;
1567 * The current logical cdclk state.
1568 * See intel_atomic_state.cdclk.logical
1570 * For reading holding any crtc lock is sufficient,
1571 * for writing must hold all of them.
1573 struct intel_cdclk_state logical;
1575 * The current actual cdclk state.
1576 * See intel_atomic_state.cdclk.actual
1578 struct intel_cdclk_state actual;
1579 /* The current hardware cdclk state */
1580 struct intel_cdclk_state hw;
1584 * wq - Driver workqueue for GEM.
1586 * NOTE: Work items scheduled here are not allowed to grab any modeset
1587 * locks, for otherwise the flushing done in the pageflip code will
1588 * result in deadlocks.
1590 struct workqueue_struct *wq;
1592 /* ordered wq for modesets */
1593 struct workqueue_struct *modeset_wq;
1595 /* Display functions */
1596 struct drm_i915_display_funcs display;
1598 /* PCH chipset type */
1599 enum intel_pch pch_type;
1600 unsigned short pch_id;
1602 unsigned long quirks;
1604 struct drm_atomic_state *modeset_restore_state;
1605 struct drm_modeset_acquire_ctx reset_ctx;
1607 struct i915_ggtt ggtt; /* VM representing the global address space */
1609 struct i915_gem_mm mm;
1610 DECLARE_HASHTABLE(mm_structs, 7);
1611 struct mutex mm_lock;
1613 struct intel_ppat ppat;
1615 /* Kernel Modesetting */
1617 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1618 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1620 #ifdef CONFIG_DEBUG_FS
1621 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1624 /* dpll and cdclk state is protected by connection_mutex */
1625 int num_shared_dpll;
1626 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1627 const struct intel_dpll_mgr *dpll_mgr;
1630 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1631 * Must be global rather than per dpll, because on some platforms
1632 * plls share registers.
1634 struct mutex dpll_lock;
1636 unsigned int active_crtcs;
1637 /* minimum acceptable cdclk for each pipe */
1638 int min_cdclk[I915_MAX_PIPES];
1639 /* minimum acceptable voltage level for each pipe */
1640 u8 min_voltage_level[I915_MAX_PIPES];
1642 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1644 struct i915_wa_list gt_wa_list;
1646 struct i915_frontbuffer_tracking fb_tracking;
1648 struct intel_atomic_helper {
1649 struct llist_head free_list;
1650 struct work_struct free_work;
1655 bool mchbar_need_disable;
1657 struct intel_l3_parity l3_parity;
1659 /* Cannot be determined by PCIID. You must always read a register. */
1663 * Protects RPS/RC6 register access and PCU communication.
1664 * Must be taken after struct_mutex if nested. Note that
1665 * this lock may be held for long periods of time when
1666 * talking to hw - so only take it when talking to hw!
1668 struct mutex pcu_lock;
1670 /* gen6+ GT PM state */
1671 struct intel_gen6_power_mgmt gt_pm;
1673 /* ilk-only ips/rps state. Everything in here is protected by the global
1674 * mchdev_lock in intel_pm.c */
1675 struct intel_ilk_power_mgmt ips;
1677 struct i915_power_domains power_domains;
1679 struct i915_psr psr;
1681 struct i915_gpu_error gpu_error;
1683 struct drm_i915_gem_object *vlv_pctx;
1685 /* list of fbdev register on this device */
1686 struct intel_fbdev *fbdev;
1687 struct work_struct fbdev_suspend_work;
1689 struct drm_property *broadcast_rgb_property;
1690 struct drm_property *force_audio_property;
1692 /* hda/i915 audio component */
1693 struct i915_audio_component *audio_component;
1694 bool audio_component_registered;
1696 * av_mutex - mutex for audio/video sync
1699 struct mutex av_mutex;
1703 struct list_head list;
1704 struct llist_head free_list;
1705 struct work_struct free_work;
1707 /* The hw wants to have a stable context identifier for the
1708 * lifetime of the context (for OA, PASID, faults, etc).
1709 * This is limited in execlists to 21 bits.
1712 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1713 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1714 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1715 struct list_head hw_id_list;
1720 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1721 u32 chv_phy_control;
1723 * Shadows for CHV DPLL_MD regs to keep the state
1724 * checker somewhat working in the presence hardware
1725 * crappiness (can't read out DPLL_MD for pipes B & C).
1727 u32 chv_dpll_md[I915_MAX_PIPES];
1731 bool power_domains_suspended;
1732 struct i915_suspend_saved_registers regfile;
1733 struct vlv_s0ix_state vlv_s0ix_state;
1736 I915_SAGV_UNKNOWN = 0,
1739 I915_SAGV_NOT_CONTROLLED
1744 * Raw watermark latency values:
1745 * in 0.1us units for WM0,
1746 * in 0.5us units for WM1+.
1749 uint16_t pri_latency[5];
1751 uint16_t spr_latency[5];
1753 uint16_t cur_latency[5];
1755 * Raw watermark memory latency values
1756 * for SKL for all 8 levels
1759 uint16_t skl_latency[8];
1761 /* current hardware state */
1763 struct ilk_wm_values hw;
1764 struct skl_ddb_values skl_hw;
1765 struct vlv_wm_values vlv;
1766 struct g4x_wm_values g4x;
1772 * Should be held around atomic WM register writing; also
1773 * protects * intel_crtc->wm.active and
1774 * cstate->wm.need_postvbl_update.
1776 struct mutex wm_mutex;
1779 * Set during HW readout of watermarks/DDB. Some platforms
1780 * need to know when we're still using BIOS-provided values
1781 * (which we don't fully trust).
1783 bool distrust_bios_wm;
1791 I915_DRAM_RANK_INVALID = 0,
1792 I915_DRAM_RANK_SINGLE,
1796 bool symmetric_memory;
1799 struct i915_runtime_pm runtime_pm;
1804 struct kobject *metrics_kobj;
1805 struct ctl_table_header *sysctl_header;
1808 * Lock associated with adding/modifying/removing OA configs
1809 * in dev_priv->perf.metrics_idr.
1811 struct mutex metrics_lock;
1814 * List of dynamic configurations, you need to hold
1815 * dev_priv->perf.metrics_lock to access it.
1817 struct idr metrics_idr;
1820 * Lock associated with anything below within this structure
1821 * except exclusive_stream.
1824 struct list_head streams;
1828 * The stream currently using the OA unit. If accessed
1829 * outside a syscall associated to its file
1830 * descriptor, you need to hold
1831 * dev_priv->drm.struct_mutex.
1833 struct i915_perf_stream *exclusive_stream;
1835 struct intel_context *pinned_ctx;
1836 u32 specific_ctx_id;
1837 u32 specific_ctx_id_mask;
1839 struct hrtimer poll_check_timer;
1840 wait_queue_head_t poll_wq;
1844 * For rate limiting any notifications of spurious
1845 * invalid OA reports
1847 struct ratelimit_state spurious_report_rs;
1850 int period_exponent;
1852 struct i915_oa_config test_config;
1855 struct i915_vma *vma;
1862 * Locks reads and writes to all head/tail state
1864 * Consider: the head and tail pointer state
1865 * needs to be read consistently from a hrtimer
1866 * callback (atomic context) and read() fop
1867 * (user context) with tail pointer updates
1868 * happening in atomic context and head updates
1869 * in user context and the (unlikely)
1870 * possibility of read() errors needing to
1871 * reset all head/tail state.
1873 * Note: Contention or performance aren't
1874 * currently a significant concern here
1875 * considering the relatively low frequency of
1876 * hrtimer callbacks (5ms period) and that
1877 * reads typically only happen in response to a
1878 * hrtimer event and likely complete before the
1881 * Note: This lock is not held *while* reading
1882 * and copying data to userspace so the value
1883 * of head observed in htrimer callbacks won't
1884 * represent any partial consumption of data.
1886 spinlock_t ptr_lock;
1889 * One 'aging' tail pointer and one 'aged'
1890 * tail pointer ready to used for reading.
1892 * Initial values of 0xffffffff are invalid
1893 * and imply that an update is required
1894 * (and should be ignored by an attempted
1902 * Index for the aged tail ready to read()
1905 unsigned int aged_tail_idx;
1908 * A monotonic timestamp for when the current
1909 * aging tail pointer was read; used to
1910 * determine when it is old enough to trust.
1912 u64 aging_timestamp;
1915 * Although we can always read back the head
1916 * pointer register, we prefer to avoid
1917 * trusting the HW state, just to avoid any
1918 * risk that some hardware condition could
1919 * somehow bump the head pointer unpredictably
1920 * and cause us to forward the wrong OA buffer
1921 * data to userspace.
1926 u32 gen7_latched_oastatus1;
1927 u32 ctx_oactxctrl_offset;
1928 u32 ctx_flexeu0_offset;
1931 * The RPT_ID/reason field for Gen8+ includes a bit
1932 * to determine if the CTX ID in the report is valid
1933 * but the specific bit differs between Gen 8 and 9
1935 u32 gen8_valid_ctx_bit;
1937 struct i915_oa_ops ops;
1938 const struct i915_oa_format *oa_formats;
1942 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1944 void (*resume)(struct drm_i915_private *);
1945 void (*cleanup_engine)(struct intel_engine_cs *engine);
1947 struct list_head timelines;
1949 struct list_head active_rings;
1950 struct list_head closed_vma;
1951 u32 active_requests;
1954 * Is the GPU currently considered idle, or busy executing
1955 * userspace requests? Whilst idle, we allow runtime power
1956 * management to power down the hardware and display clocks.
1957 * In order to reduce the effect on performance, there
1958 * is a slight delay before we do so.
1963 * The number of times we have woken up.
1966 #define I915_EPOCH_INVALID 0
1969 * We leave the user IRQ off as much as possible,
1970 * but this means that requests will finish and never
1971 * be retired once the system goes idle. Set a timer to
1972 * fire periodically while the ring is running. When it
1973 * fires, go retire requests.
1975 struct delayed_work retire_work;
1978 * When we detect an idle GPU, we want to turn on
1979 * powersaving features. So once we see that there
1980 * are no more requests outstanding and no more
1981 * arrive within a small period of time, we fire
1982 * off the idle_work.
1984 struct delayed_work idle_work;
1986 ktime_t last_init_time;
1988 struct i915_vma *scratch;
1991 /* perform PHY state sanity checks? */
1992 bool chv_phy_assert[2];
1996 /* Used to save the pipe-to-encoder mapping for audio */
1997 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1999 /* necessary resource sharing with HDMI LPE audio driver. */
2001 struct platform_device *platdev;
2005 struct i915_pmu pmu;
2008 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2009 * will be rejected. Instead look for a better place.
2013 struct dram_channel_info {
2016 enum dram_rank rank;
2018 enum dram_rank rank;
2022 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2024 return container_of(dev, struct drm_i915_private, drm);
2027 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2029 return to_i915(dev_get_drvdata(kdev));
2032 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2034 return container_of(wopcm, struct drm_i915_private, wopcm);
2037 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2039 return container_of(guc, struct drm_i915_private, guc);
2042 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2044 return container_of(huc, struct drm_i915_private, huc);
2047 /* Simple iterator over all initialised engines */
2048 #define for_each_engine(engine__, dev_priv__, id__) \
2050 (id__) < I915_NUM_ENGINES; \
2052 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2054 /* Iterator over subset of engines selected by mask */
2055 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2056 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2058 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2061 enum hdmi_force_audio {
2062 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2063 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2064 HDMI_AUDIO_AUTO, /* trust EDID */
2065 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2068 #define I915_GTT_OFFSET_NONE ((u32)-1)
2071 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2072 * considered to be the frontbuffer for the given plane interface-wise. This
2073 * doesn't mean that the hw necessarily already scans it out, but that any
2074 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2076 * We have one bit per pipe and per scanout plane type.
2078 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2079 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2080 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2081 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2082 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2084 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2085 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2086 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2087 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2088 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2091 * Optimised SGL iterator for GEM objects
2093 static __always_inline struct sgt_iter {
2094 struct scatterlist *sgp;
2101 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2102 struct sgt_iter s = { .sgp = sgl };
2105 s.max = s.curr = s.sgp->offset;
2106 s.max += s.sgp->length;
2108 s.dma = sg_dma_address(s.sgp);
2110 s.pfn = page_to_pfn(sg_page(s.sgp));
2116 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2119 if (unlikely(sg_is_chain(sg)))
2120 sg = sg_chain_ptr(sg);
2125 * __sg_next - return the next scatterlist entry in a list
2126 * @sg: The current sg entry
2129 * If the entry is the last, return NULL; otherwise, step to the next
2130 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2131 * otherwise just return the pointer to the current element.
2133 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2135 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2139 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2140 * @__dmap: DMA address (output)
2141 * @__iter: 'struct sgt_iter' (iterator state, internal)
2142 * @__sgt: sg_table to iterate over (input)
2144 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2145 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2146 ((__dmap) = (__iter).dma + (__iter).curr); \
2147 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \
2148 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2151 * for_each_sgt_page - iterate over the pages of the given sg_table
2152 * @__pp: page pointer (output)
2153 * @__iter: 'struct sgt_iter' (iterator state, internal)
2154 * @__sgt: sg_table to iterate over (input)
2156 #define for_each_sgt_page(__pp, __iter, __sgt) \
2157 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2158 ((__pp) = (__iter).pfn == 0 ? NULL : \
2159 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2160 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2161 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2163 bool i915_sg_trim(struct sg_table *orig_st);
2165 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2167 unsigned int page_sizes;
2171 GEM_BUG_ON(sg->offset);
2172 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2173 page_sizes |= sg->length;
2180 static inline unsigned int i915_sg_segment_size(void)
2182 unsigned int size = swiotlb_max_segment();
2185 return SCATTERLIST_MAX_SEGMENT;
2187 size = rounddown(size, PAGE_SIZE);
2188 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2189 if (size < PAGE_SIZE)
2195 static inline const struct intel_device_info *
2196 intel_info(const struct drm_i915_private *dev_priv)
2198 return &dev_priv->info;
2201 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2202 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2203 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2205 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2206 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2208 #define REVID_FOREVER 0xff
2209 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2211 #define INTEL_GEN_MASK(s, e) ( \
2212 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2213 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2214 GENMASK((e) - 1, (s) - 1))
2216 /* Returns true if Gen is in inclusive range [Start, End] */
2217 #define IS_GEN_RANGE(dev_priv, s, e) \
2218 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2220 #define IS_GEN(dev_priv, n) \
2221 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2222 (dev_priv)->info.gen == (n))
2225 * Return true if revision is in range [since,until] inclusive.
2227 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2229 #define IS_REVID(p, since, until) \
2230 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2232 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2234 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2235 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2236 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2237 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2238 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2239 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2240 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2241 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2242 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2243 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2244 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2245 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2246 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2247 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2248 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2249 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2250 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2251 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2252 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2253 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2254 (dev_priv)->info.gt == 1)
2255 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2256 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2257 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2258 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2259 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2260 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2261 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2262 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2263 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2264 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2265 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2266 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2267 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2268 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2269 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2270 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2271 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2272 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2273 /* ULX machines are also considered ULT. */
2274 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2275 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2276 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2277 (dev_priv)->info.gt == 3)
2278 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2279 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2280 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2281 (dev_priv)->info.gt == 3)
2282 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2283 (dev_priv)->info.gt == 1)
2284 /* ULX machines are also considered ULT. */
2285 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2286 INTEL_DEVID(dev_priv) == 0x0A1E)
2287 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2288 INTEL_DEVID(dev_priv) == 0x1913 || \
2289 INTEL_DEVID(dev_priv) == 0x1916 || \
2290 INTEL_DEVID(dev_priv) == 0x1921 || \
2291 INTEL_DEVID(dev_priv) == 0x1926)
2292 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2293 INTEL_DEVID(dev_priv) == 0x1915 || \
2294 INTEL_DEVID(dev_priv) == 0x191E)
2295 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2296 INTEL_DEVID(dev_priv) == 0x5913 || \
2297 INTEL_DEVID(dev_priv) == 0x5916 || \
2298 INTEL_DEVID(dev_priv) == 0x5921 || \
2299 INTEL_DEVID(dev_priv) == 0x5926)
2300 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2301 INTEL_DEVID(dev_priv) == 0x5915 || \
2302 INTEL_DEVID(dev_priv) == 0x591E)
2303 #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
2304 INTEL_DEVID(dev_priv) == 0x87C0)
2305 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2306 (dev_priv)->info.gt == 2)
2307 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2308 (dev_priv)->info.gt == 3)
2309 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2310 (dev_priv)->info.gt == 4)
2311 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2312 (dev_priv)->info.gt == 2)
2313 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2314 (dev_priv)->info.gt == 3)
2315 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2316 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2317 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2318 (dev_priv)->info.gt == 2)
2319 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2320 (dev_priv)->info.gt == 3)
2321 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2322 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2324 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2326 #define SKL_REVID_A0 0x0
2327 #define SKL_REVID_B0 0x1
2328 #define SKL_REVID_C0 0x2
2329 #define SKL_REVID_D0 0x3
2330 #define SKL_REVID_E0 0x4
2331 #define SKL_REVID_F0 0x5
2332 #define SKL_REVID_G0 0x6
2333 #define SKL_REVID_H0 0x7
2335 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2337 #define BXT_REVID_A0 0x0
2338 #define BXT_REVID_A1 0x1
2339 #define BXT_REVID_B0 0x3
2340 #define BXT_REVID_B_LAST 0x8
2341 #define BXT_REVID_C0 0x9
2343 #define IS_BXT_REVID(dev_priv, since, until) \
2344 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2346 #define KBL_REVID_A0 0x0
2347 #define KBL_REVID_B0 0x1
2348 #define KBL_REVID_C0 0x2
2349 #define KBL_REVID_D0 0x3
2350 #define KBL_REVID_E0 0x4
2352 #define IS_KBL_REVID(dev_priv, since, until) \
2353 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2355 #define GLK_REVID_A0 0x0
2356 #define GLK_REVID_A1 0x1
2358 #define IS_GLK_REVID(dev_priv, since, until) \
2359 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2361 #define CNL_REVID_A0 0x0
2362 #define CNL_REVID_B0 0x1
2363 #define CNL_REVID_C0 0x2
2365 #define IS_CNL_REVID(p, since, until) \
2366 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2368 #define ICL_REVID_A0 0x0
2369 #define ICL_REVID_A2 0x1
2370 #define ICL_REVID_B0 0x3
2371 #define ICL_REVID_B2 0x4
2372 #define ICL_REVID_C0 0x5
2374 #define IS_ICL_REVID(p, since, until) \
2375 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2377 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2378 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2379 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2381 #define ENGINE_MASK(id) BIT(id)
2382 #define RENDER_RING ENGINE_MASK(RCS)
2383 #define BSD_RING ENGINE_MASK(VCS)
2384 #define BLT_RING ENGINE_MASK(BCS)
2385 #define VEBOX_RING ENGINE_MASK(VECS)
2386 #define BSD2_RING ENGINE_MASK(VCS2)
2387 #define BSD3_RING ENGINE_MASK(VCS3)
2388 #define BSD4_RING ENGINE_MASK(VCS4)
2389 #define VEBOX2_RING ENGINE_MASK(VECS2)
2390 #define ALL_ENGINES (~0)
2392 #define HAS_ENGINE(dev_priv, id) \
2393 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2395 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2396 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2397 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2398 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2400 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2401 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2402 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2403 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2404 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2406 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2408 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2409 ((dev_priv)->info.has_logical_ring_contexts)
2410 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2411 ((dev_priv)->info.has_logical_ring_elsq)
2412 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2413 ((dev_priv)->info.has_logical_ring_preemption)
2415 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2417 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
2418 #define HAS_PPGTT(dev_priv) \
2419 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2420 #define HAS_FULL_PPGTT(dev_priv) \
2421 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2422 #define HAS_FULL_48BIT_PPGTT(dev_priv) \
2423 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
2425 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2426 GEM_BUG_ON((sizes) == 0); \
2427 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2430 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay)
2431 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2432 ((dev_priv)->info.display.overlay_needs_physical)
2434 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2435 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2437 /* WaRsDisableCoarsePowerGating:skl,cnl */
2438 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2439 (IS_CANNONLAKE(dev_priv) || \
2440 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2442 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2443 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2444 IS_GEMINILAKE(dev_priv) || \
2445 IS_KABYLAKE(dev_priv))
2447 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2448 * rows, which changed the alignment requirements and fence programming.
2450 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2451 !(IS_I915G(dev_priv) || \
2452 IS_I915GM(dev_priv)))
2453 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv)
2454 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug)
2456 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2457 #define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc)
2458 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2460 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2462 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst)
2464 #define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi)
2465 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2466 #define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr)
2468 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2469 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2470 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2472 #define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr)
2474 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2475 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2477 #define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc)
2480 * For now, anything with a GuC requires uCode loading, and then supports
2481 * command submission once loaded. But these are logically independent
2482 * properties, so we have separate macros to test them.
2484 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2485 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2486 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2487 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2489 /* For now, anything with a GuC has also HuC */
2490 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2491 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2493 /* Having a GuC is not the same as using a GuC */
2494 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2495 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2496 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2498 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2500 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2501 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2502 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2503 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2504 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2505 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2506 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2507 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2508 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2509 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2510 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2511 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2512 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2513 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2514 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2515 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2516 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2518 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2519 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2520 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2521 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2522 #define HAS_PCH_CNP_LP(dev_priv) \
2523 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2524 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2525 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2526 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2527 #define HAS_PCH_LPT_LP(dev_priv) \
2528 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2529 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2530 #define HAS_PCH_LPT_H(dev_priv) \
2531 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2532 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2533 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2534 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2535 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2536 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2538 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display)
2540 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2542 /* DPF == dynamic parity feature */
2543 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2544 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2545 2 : HAS_L3_DPF(dev_priv))
2547 #define GT_FREQUENCY_MULTIPLIER 50
2548 #define GEN9_FREQ_SCALER 3
2550 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2552 #include "i915_trace.h"
2554 static inline bool intel_vtd_active(void)
2556 #ifdef CONFIG_INTEL_IOMMU
2557 if (intel_iommu_gfx_mapped)
2563 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2565 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2569 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2571 return IS_BROXTON(dev_priv) && intel_vtd_active();
2576 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2577 const char *fmt, ...);
2579 #define i915_report_error(dev_priv, fmt, ...) \
2580 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2582 #ifdef CONFIG_COMPAT
2583 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2586 #define i915_compat_ioctl NULL
2588 extern const struct dev_pm_ops i915_pm_ops;
2590 extern int i915_driver_load(struct pci_dev *pdev,
2591 const struct pci_device_id *ent);
2592 extern void i915_driver_unload(struct drm_device *dev);
2593 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2594 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2596 extern void i915_reset(struct drm_i915_private *i915,
2597 unsigned int stalled_mask,
2598 const char *reason);
2599 extern int i915_reset_engine(struct intel_engine_cs *engine,
2600 const char *reason);
2602 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2603 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2604 extern int intel_guc_reset_engine(struct intel_guc *guc,
2605 struct intel_engine_cs *engine);
2606 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2607 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2608 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2609 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2610 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2611 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2612 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2614 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2615 int intel_engines_init(struct drm_i915_private *dev_priv);
2617 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2619 /* intel_hotplug.c */
2620 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2621 u32 pin_mask, u32 long_mask);
2622 void intel_hpd_init(struct drm_i915_private *dev_priv);
2623 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2624 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2625 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2627 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2628 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2631 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2633 unsigned long delay;
2635 if (unlikely(!i915_modparams.enable_hangcheck))
2638 /* Don't continually defer the hangcheck so that it is always run at
2639 * least once after work has been scheduled on any ring. Otherwise,
2640 * we will ignore a hung ring if a second ring is kept busy.
2643 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2644 queue_delayed_work(system_long_wq,
2645 &dev_priv->gpu_error.hangcheck_work, delay);
2649 void i915_handle_error(struct drm_i915_private *dev_priv,
2651 unsigned long flags,
2652 const char *fmt, ...);
2653 #define I915_ERROR_CAPTURE BIT(0)
2655 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2656 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2657 int intel_irq_install(struct drm_i915_private *dev_priv);
2658 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2660 void i915_clear_error_registers(struct drm_i915_private *dev_priv);
2662 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2664 return dev_priv->gvt;
2667 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2669 return dev_priv->vgpu.active;
2672 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2675 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2679 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2682 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2683 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2684 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2687 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2688 uint32_t interrupt_mask,
2689 uint32_t enabled_irq_mask);
2691 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2693 ilk_update_display_irq(dev_priv, bits, bits);
2696 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2698 ilk_update_display_irq(dev_priv, bits, 0);
2700 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2702 uint32_t interrupt_mask,
2703 uint32_t enabled_irq_mask);
2704 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2705 enum pipe pipe, uint32_t bits)
2707 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2709 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2710 enum pipe pipe, uint32_t bits)
2712 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2714 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2715 uint32_t interrupt_mask,
2716 uint32_t enabled_irq_mask);
2718 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2720 ibx_display_interrupt_update(dev_priv, bits, bits);
2723 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2725 ibx_display_interrupt_update(dev_priv, bits, 0);
2729 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2730 struct drm_file *file_priv);
2731 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2732 struct drm_file *file_priv);
2733 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2734 struct drm_file *file_priv);
2735 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2736 struct drm_file *file_priv);
2737 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2738 struct drm_file *file_priv);
2739 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2740 struct drm_file *file_priv);
2741 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2742 struct drm_file *file_priv);
2743 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2744 struct drm_file *file_priv);
2745 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2746 struct drm_file *file_priv);
2747 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2748 struct drm_file *file_priv);
2749 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2750 struct drm_file *file);
2751 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2752 struct drm_file *file);
2753 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2754 struct drm_file *file_priv);
2755 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2756 struct drm_file *file_priv);
2757 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2758 struct drm_file *file_priv);
2759 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2760 struct drm_file *file_priv);
2761 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2762 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2763 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2764 struct drm_file *file);
2765 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2766 struct drm_file *file_priv);
2767 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2768 struct drm_file *file_priv);
2769 void i915_gem_sanitize(struct drm_i915_private *i915);
2770 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2771 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2772 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2773 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2774 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2776 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2777 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2778 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2779 const struct drm_i915_gem_object_ops *ops);
2780 struct drm_i915_gem_object *
2781 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2782 struct drm_i915_gem_object *
2783 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2784 const void *data, size_t size);
2785 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2786 void i915_gem_free_object(struct drm_gem_object *obj);
2788 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2790 if (!atomic_read(&i915->mm.free_count))
2793 /* A single pass should suffice to release all the freed objects (along
2794 * most call paths) , but be a little more paranoid in that freeing
2795 * the objects does take a little amount of time, during which the rcu
2796 * callbacks could have added new objects into the freed list, and
2797 * armed the work again.
2801 } while (flush_work(&i915->mm.free_work));
2804 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2807 * Similar to objects above (see i915_gem_drain_freed-objects), in
2808 * general we have workers that are armed by RCU and then rearm
2809 * themselves in their callbacks. To be paranoid, we need to
2810 * drain the workqueue a second time after waiting for the RCU
2811 * grace period so that we catch work queued via RCU from the first
2812 * pass. As neither drain_workqueue() nor flush_workqueue() report
2813 * a result, we make an assumption that we only don't require more
2814 * than 2 passes to catch all recursive RCU delayed work.
2820 drain_workqueue(i915->wq);
2824 struct i915_vma * __must_check
2825 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2826 const struct i915_ggtt_view *view,
2831 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2832 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2834 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2836 static inline int __sg_page_count(const struct scatterlist *sg)
2838 return sg->length >> PAGE_SHIFT;
2841 struct scatterlist *
2842 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2843 unsigned int n, unsigned int *offset);
2846 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2850 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2854 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2857 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2858 struct sg_table *pages,
2859 unsigned int sg_page_sizes);
2860 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2862 static inline int __must_check
2863 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2865 might_lock(&obj->mm.lock);
2867 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2870 return __i915_gem_object_get_pages(obj);
2874 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2876 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2880 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2882 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2884 atomic_inc(&obj->mm.pages_pin_count);
2888 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2890 return atomic_read(&obj->mm.pages_pin_count);
2894 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2896 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2897 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
2899 atomic_dec(&obj->mm.pages_pin_count);
2903 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2905 __i915_gem_object_unpin_pages(obj);
2908 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
2913 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2914 enum i915_mm_subclass subclass);
2915 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
2917 enum i915_map_type {
2920 #define I915_MAP_OVERRIDE BIT(31)
2921 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
2922 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
2925 static inline enum i915_map_type
2926 i915_coherent_map_type(struct drm_i915_private *i915)
2928 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2932 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
2933 * @obj: the object to map into kernel address space
2934 * @type: the type of mapping, used to select pgprot_t
2936 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
2937 * pages and then returns a contiguous mapping of the backing storage into
2938 * the kernel address space. Based on the @type of mapping, the PTE will be
2939 * set to either WriteBack or WriteCombine (via pgprot_t).
2941 * The caller is responsible for calling i915_gem_object_unpin_map() when the
2942 * mapping is no longer required.
2944 * Returns the pointer through which to access the mapped object, or an
2945 * ERR_PTR() on error.
2947 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2948 enum i915_map_type type);
2951 * i915_gem_object_unpin_map - releases an earlier mapping
2952 * @obj: the object to unmap
2954 * After pinning the object and mapping its pages, once you are finished
2955 * with your access, call i915_gem_object_unpin_map() to release the pin
2956 * upon the mapping. Once the pin count reaches zero, that mapping may be
2959 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
2961 i915_gem_object_unpin_pages(obj);
2964 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2965 unsigned int *needs_clflush);
2966 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
2967 unsigned int *needs_clflush);
2968 #define CLFLUSH_BEFORE BIT(0)
2969 #define CLFLUSH_AFTER BIT(1)
2970 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
2973 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
2975 i915_gem_object_unpin_pages(obj);
2978 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2979 int i915_gem_dumb_create(struct drm_file *file_priv,
2980 struct drm_device *dev,
2981 struct drm_mode_create_dumb *args);
2982 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2983 uint32_t handle, uint64_t *offset);
2984 int i915_gem_mmap_gtt_version(void);
2986 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2987 struct drm_i915_gem_object *new,
2988 unsigned frontbuffer_bits);
2990 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
2992 struct i915_request *
2993 i915_gem_find_active_request(struct intel_engine_cs *engine);
2995 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
2997 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3000 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3002 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3005 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3007 return unlikely(test_bit(I915_WEDGED, &error->flags));
3010 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3012 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3015 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3017 return READ_ONCE(error->reset_count);
3020 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3021 struct intel_engine_cs *engine)
3023 return READ_ONCE(error->reset_engine_count[engine->id]);
3026 struct i915_request *
3027 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3028 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3029 void i915_gem_reset(struct drm_i915_private *dev_priv,
3030 unsigned int stalled_mask);
3031 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3032 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3033 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3034 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3035 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3036 struct i915_request *request,
3039 void i915_gem_init_mmio(struct drm_i915_private *i915);
3040 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3041 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3042 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3043 void i915_gem_fini(struct drm_i915_private *dev_priv);
3044 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3045 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3046 unsigned int flags, long timeout);
3047 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3048 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3049 void i915_gem_resume(struct drm_i915_private *dev_priv);
3050 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3051 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3054 struct intel_rps_client *rps);
3055 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3057 const struct i915_sched_attr *attr);
3058 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
3061 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3063 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3065 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3066 struct i915_vma * __must_check
3067 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3069 const struct i915_ggtt_view *view,
3070 unsigned int flags);
3071 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3072 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3074 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3075 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3077 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3078 enum i915_cache_level cache_level);
3080 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3081 struct dma_buf *dma_buf);
3083 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3084 struct drm_gem_object *gem_obj, int flags);
3086 static inline struct i915_hw_ppgtt *
3087 i915_vm_to_ppgtt(struct i915_address_space *vm)
3089 return container_of(vm, struct i915_hw_ppgtt, vm);
3092 /* i915_gem_fence_reg.c */
3093 struct drm_i915_fence_reg *
3094 i915_reserve_fence(struct drm_i915_private *dev_priv);
3095 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3097 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3098 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3100 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3101 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3102 struct sg_table *pages);
3103 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3104 struct sg_table *pages);
3106 static inline struct i915_gem_context *
3107 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3109 return idr_find(&file_priv->context_idr, id);
3112 static inline struct i915_gem_context *
3113 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3115 struct i915_gem_context *ctx;
3118 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3119 if (ctx && !kref_get_unless_zero(&ctx->ref))
3126 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3127 struct drm_file *file);
3128 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3129 struct drm_file *file);
3130 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3131 struct drm_file *file);
3132 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3133 struct i915_gem_context *ctx,
3134 uint32_t *reg_state);
3136 /* i915_gem_evict.c */
3137 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3138 u64 min_size, u64 alignment,
3139 unsigned cache_level,
3142 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3143 struct drm_mm_node *node,
3144 unsigned int flags);
3145 int i915_gem_evict_vm(struct i915_address_space *vm);
3147 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3149 /* belongs in i915_gem_gtt.h */
3150 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3153 if (INTEL_GEN(dev_priv) < 6)
3154 intel_gtt_chipset_flush();
3157 /* i915_gem_stolen.c */
3158 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3159 struct drm_mm_node *node, u64 size,
3160 unsigned alignment);
3161 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3162 struct drm_mm_node *node, u64 size,
3163 unsigned alignment, u64 start,
3165 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3166 struct drm_mm_node *node);
3167 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3168 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
3169 struct drm_i915_gem_object *
3170 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3171 resource_size_t size);
3172 struct drm_i915_gem_object *
3173 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3174 resource_size_t stolen_offset,
3175 resource_size_t gtt_offset,
3176 resource_size_t size);
3178 /* i915_gem_internal.c */
3179 struct drm_i915_gem_object *
3180 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3183 /* i915_gem_shrinker.c */
3184 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3185 unsigned long target,
3186 unsigned long *nr_scanned,
3188 #define I915_SHRINK_PURGEABLE 0x1
3189 #define I915_SHRINK_UNBOUND 0x2
3190 #define I915_SHRINK_BOUND 0x4
3191 #define I915_SHRINK_ACTIVE 0x8
3192 #define I915_SHRINK_VMAPS 0x10
3193 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3194 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3195 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3196 void i915_gem_shrinker_taints_mutex(struct mutex *mutex);
3198 /* i915_gem_tiling.c */
3199 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3201 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3203 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3204 i915_gem_object_is_tiled(obj);
3207 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3208 unsigned int tiling, unsigned int stride);
3209 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3210 unsigned int tiling, unsigned int stride);
3212 /* i915_debugfs.c */
3213 #ifdef CONFIG_DEBUG_FS
3214 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3215 int i915_debugfs_connector_add(struct drm_connector *connector);
3216 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3218 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3219 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3221 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3224 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3226 /* i915_cmd_parser.c */
3227 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3228 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3229 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3230 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3231 struct drm_i915_gem_object *batch_obj,
3232 struct drm_i915_gem_object *shadow_batch_obj,
3233 u32 batch_start_offset,
3238 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3239 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3240 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3241 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3243 /* i915_suspend.c */
3244 extern int i915_save_state(struct drm_i915_private *dev_priv);
3245 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3248 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3249 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3251 /* intel_lpe_audio.c */
3252 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3253 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3254 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3255 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3256 enum pipe pipe, enum port port,
3257 const void *eld, int ls_clock, bool dp_output);
3260 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3261 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3262 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3264 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3266 extern struct i2c_adapter *
3267 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3268 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3269 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3270 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3272 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3274 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3277 void intel_bios_init(struct drm_i915_private *dev_priv);
3278 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3279 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3280 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3281 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3282 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3283 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3284 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3285 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3286 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3288 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3290 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
3294 extern void intel_register_dsm_handler(void);
3295 extern void intel_unregister_dsm_handler(void);
3297 static inline void intel_register_dsm_handler(void) { return; }
3298 static inline void intel_unregister_dsm_handler(void) { return; }
3299 #endif /* CONFIG_ACPI */
3301 /* intel_device_info.c */
3302 static inline struct intel_device_info *
3303 mkwrite_device_info(struct drm_i915_private *dev_priv)
3305 return (struct intel_device_info *)&dev_priv->info;
3309 extern void intel_modeset_init_hw(struct drm_device *dev);
3310 extern int intel_modeset_init(struct drm_device *dev);
3311 extern void intel_modeset_cleanup(struct drm_device *dev);
3312 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3314 extern void intel_display_resume(struct drm_device *dev);
3315 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3316 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3317 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3318 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3319 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3320 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3322 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3324 void intel_dsc_enable(struct intel_encoder *encoder,
3325 const struct intel_crtc_state *crtc_state);
3326 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
3328 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3329 struct drm_file *file);
3332 extern struct intel_overlay_error_state *
3333 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3334 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3335 struct intel_overlay_error_state *error);
3337 extern struct intel_display_error_state *
3338 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3339 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3340 struct intel_display_error_state *error);
3342 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3343 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3344 u32 val, int fast_timeout_us,
3345 int slow_timeout_ms);
3346 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3347 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3349 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3350 u32 reply_mask, u32 reply, int timeout_base_ms);
3352 /* intel_sideband.c */
3353 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3354 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3355 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3356 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3357 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3358 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3359 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3360 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3361 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3362 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3363 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3364 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3365 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3366 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3367 enum intel_sbi_destination destination);
3368 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3369 enum intel_sbi_destination destination);
3370 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3371 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3373 /* intel_dpio_phy.c */
3374 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3375 enum dpio_phy *phy, enum dpio_channel *ch);
3376 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3377 enum port port, u32 margin, u32 scale,
3378 u32 enable, u32 deemphasis);
3379 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3380 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3381 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3383 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3385 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3386 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3387 uint8_t lane_lat_optim_mask);
3388 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3390 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3391 u32 deemph_reg_value, u32 margin_reg_value,
3392 bool uniq_trans_scale);
3393 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3394 const struct intel_crtc_state *crtc_state,
3396 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3397 const struct intel_crtc_state *crtc_state);
3398 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3399 const struct intel_crtc_state *crtc_state);
3400 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3401 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3402 const struct intel_crtc_state *old_crtc_state);
3404 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3405 u32 demph_reg_value, u32 preemph_reg_value,
3406 u32 uniqtranscale_reg_value, u32 tx3_demph);
3407 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3408 const struct intel_crtc_state *crtc_state);
3409 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3410 const struct intel_crtc_state *crtc_state);
3411 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3412 const struct intel_crtc_state *old_crtc_state);
3414 /* intel_combo_phy.c */
3415 void icl_combo_phys_init(struct drm_i915_private *dev_priv);
3416 void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
3417 void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
3418 void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
3420 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3421 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3422 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3423 const i915_reg_t reg);
3425 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3427 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3428 const i915_reg_t reg)
3430 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3433 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3434 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3436 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3437 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3438 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3439 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3441 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3442 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3443 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3444 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3446 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3447 * will be implemented using 2 32-bit writes in an arbitrary order with
3448 * an arbitrary delay between them. This can cause the hardware to
3449 * act upon the intermediate value, possibly leading to corruption and
3450 * machine death. For this reason we do not support I915_WRITE64, or
3451 * dev_priv->uncore.funcs.mmio_writeq.
3453 * When reading a 64-bit value as two 32-bit values, the delay may cause
3454 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3455 * occasionally a 64-bit register does not actualy support a full readq
3456 * and must be read using two 32-bit reads.
3458 * You have been warned.
3460 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3462 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3463 u32 upper, lower, old_upper, loop = 0; \
3464 upper = I915_READ(upper_reg); \
3466 old_upper = upper; \
3467 lower = I915_READ(lower_reg); \
3468 upper = I915_READ(upper_reg); \
3469 } while (upper != old_upper && loop++ < 2); \
3470 (u64)upper << 32 | lower; })
3472 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3473 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3475 #define __raw_read(x, s) \
3476 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3479 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3482 #define __raw_write(x, s) \
3483 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3484 i915_reg_t reg, uint##x##_t val) \
3486 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3501 /* These are untraced mmio-accessors that are only valid to be used inside
3502 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3505 * Think twice, and think again, before using these.
3507 * As an example, these accessors can possibly be used between:
3509 * spin_lock_irq(&dev_priv->uncore.lock);
3510 * intel_uncore_forcewake_get__locked();
3514 * intel_uncore_forcewake_put__locked();
3515 * spin_unlock_irq(&dev_priv->uncore.lock);
3518 * Note: some registers may not need forcewake held, so
3519 * intel_uncore_forcewake_{get,put} can be omitted, see
3520 * intel_uncore_forcewake_for_reg().
3522 * Certain architectures will die if the same cacheline is concurrently accessed
3523 * by different clients (e.g. on Ivybridge). Access to registers should
3524 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3525 * a more localised lock guarding all access to that bank of registers.
3527 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3528 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3529 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3530 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3532 /* "Broadcast RGB" property */
3533 #define INTEL_BROADCAST_RGB_AUTO 0
3534 #define INTEL_BROADCAST_RGB_FULL 1
3535 #define INTEL_BROADCAST_RGB_LIMITED 2
3537 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3539 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3540 return VLV_VGACNTRL;
3541 else if (INTEL_GEN(dev_priv) >= 5)
3542 return CPU_VGACNTRL;
3547 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3549 unsigned long j = msecs_to_jiffies(m);
3551 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3554 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3556 /* nsecs_to_jiffies64() does not guard against overflow */
3557 if (NSEC_PER_SEC % HZ &&
3558 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3559 return MAX_JIFFY_OFFSET;
3561 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3565 * If you need to wait X milliseconds between events A and B, but event B
3566 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3567 * when event A happened, then just before event B you call this function and
3568 * pass the timestamp as the first argument, and X as the second argument.
3571 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3573 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3576 * Don't re-read the value of "jiffies" every time since it may change
3577 * behind our back and break the math.
3579 tmp_jiffies = jiffies;
3580 target_jiffies = timestamp_jiffies +
3581 msecs_to_jiffies_timeout(to_wait_ms);
3583 if (time_after(target_jiffies, tmp_jiffies)) {
3584 remaining_jiffies = target_jiffies - tmp_jiffies;
3585 while (remaining_jiffies)
3587 schedule_timeout_uninterruptible(remaining_jiffies);
3591 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3592 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3594 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3595 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3596 * perform the operation. To check beforehand, pass in the parameters to
3597 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3598 * you only need to pass in the minor offsets, page-aligned pointers are
3601 * For just checking for SSE4.1, in the foreknowledge that the future use
3602 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3604 #define i915_can_memcpy_from_wc(dst, src, len) \
3605 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3607 #define i915_has_memcpy_from_wc() \
3608 i915_memcpy_from_wc(NULL, NULL, 0)
3611 int remap_io_mapping(struct vm_area_struct *vma,
3612 unsigned long addr, unsigned long pfn, unsigned long size,
3613 struct io_mapping *iomap);
3615 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3617 if (INTEL_GEN(i915) >= 10)
3618 return CNL_HWS_CSB_WRITE_INDEX;
3620 return I915_HWS_CSB_WRITE_INDEX;
3623 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
3625 return i915_ggtt_offset(i915->gt.scratch);