1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/perf_event.h>
44 #include <linux/pm_qos.h>
45 #include <linux/reservation.h>
46 #include <linux/shmem_fs.h>
49 #include <drm/intel-gtt.h>
50 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
51 #include <drm/drm_gem.h>
52 #include <drm/drm_auth.h>
53 #include <drm/drm_cache.h>
55 #include "i915_params.h"
57 #include "i915_utils.h"
59 #include "intel_bios.h"
60 #include "intel_device_info.h"
61 #include "intel_display.h"
62 #include "intel_dpll_mgr.h"
63 #include "intel_lrc.h"
64 #include "intel_opregion.h"
65 #include "intel_ringbuffer.h"
66 #include "intel_uncore.h"
67 #include "intel_wopcm.h"
71 #include "i915_gem_context.h"
72 #include "i915_gem_fence_reg.h"
73 #include "i915_gem_object.h"
74 #include "i915_gem_gtt.h"
75 #include "i915_gem_timeline.h"
76 #include "i915_gpu_error.h"
77 #include "i915_request.h"
80 #include "intel_gvt.h"
82 /* General customization:
85 #define DRIVER_NAME "i915"
86 #define DRIVER_DESC "Intel Graphics"
87 #define DRIVER_DATE "20180308"
88 #define DRIVER_TIMESTAMP 1520513379
90 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
91 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
92 * which may not necessarily be a user visible problem. This will either
93 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
94 * enable distros and users to tailor their preferred amount of i915 abrt
97 #define I915_STATE_WARN(condition, format...) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) \
100 if (!WARN(i915_modparams.verbose_state_checks, format)) \
102 unlikely(__ret_warn_on); \
105 #define I915_STATE_WARN_ON(x) \
106 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
108 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
109 bool __i915_inject_load_failure(const char *func, int line);
110 #define i915_inject_load_failure() \
111 __i915_inject_load_failure(__func__, __LINE__)
113 #define i915_inject_load_failure() false
118 } uint_fixed_16_16_t;
120 #define FP_16_16_MAX ({ \
121 uint_fixed_16_16_t fp; \
126 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
133 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
135 uint_fixed_16_16_t fp;
137 WARN_ON(val > U16_MAX);
143 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
145 return DIV_ROUND_UP(fp.val, 1 << 16);
148 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
153 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
154 uint_fixed_16_16_t min2)
156 uint_fixed_16_16_t min;
158 min.val = min(min1.val, min2.val);
162 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
163 uint_fixed_16_16_t max2)
165 uint_fixed_16_16_t max;
167 max.val = max(max1.val, max2.val);
171 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
173 uint_fixed_16_16_t fp;
174 WARN_ON(val > U32_MAX);
175 fp.val = (uint32_t) val;
179 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
180 uint_fixed_16_16_t d)
182 return DIV_ROUND_UP(val.val, d.val);
185 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
186 uint_fixed_16_16_t mul)
188 uint64_t intermediate_val;
190 intermediate_val = (uint64_t) val * mul.val;
191 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
192 WARN_ON(intermediate_val > U32_MAX);
193 return (uint32_t) intermediate_val;
196 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
197 uint_fixed_16_16_t mul)
199 uint64_t intermediate_val;
201 intermediate_val = (uint64_t) val.val * mul.val;
202 intermediate_val = intermediate_val >> 16;
203 return clamp_u64_to_fixed16(intermediate_val);
206 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
210 interm_val = (uint64_t)val << 16;
211 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
212 return clamp_u64_to_fixed16(interm_val);
215 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
216 uint_fixed_16_16_t d)
220 interm_val = (uint64_t)val << 16;
221 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
222 WARN_ON(interm_val > U32_MAX);
223 return (uint32_t) interm_val;
226 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
227 uint_fixed_16_16_t mul)
229 uint64_t intermediate_val;
231 intermediate_val = (uint64_t) val * mul.val;
232 return clamp_u64_to_fixed16(intermediate_val);
235 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
236 uint_fixed_16_16_t add2)
240 interm_sum = (uint64_t) add1.val + add2.val;
241 return clamp_u64_to_fixed16(interm_sum);
244 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
248 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
250 interm_sum = (uint64_t) add1.val + interm_add2.val;
251 return clamp_u64_to_fixed16(interm_sum);
256 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
268 #define for_each_hpd_pin(__pin) \
269 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
271 #define HPD_STORM_DEFAULT_THRESHOLD 5
273 struct i915_hotplug {
274 struct work_struct hotplug_work;
277 unsigned long last_jiffies;
282 HPD_MARK_DISABLED = 2
284 } stats[HPD_NUM_PINS];
286 struct delayed_work reenable_work;
288 struct intel_digital_port *irq_port[I915_MAX_PORTS];
291 struct work_struct dig_port_work;
293 struct work_struct poll_init_work;
296 unsigned int hpd_storm_threshold;
299 * if we get a HPD irq from DP and a HPD irq from non-DP
300 * the non-DP HPD could block the workqueue on a mode config
301 * mutex getting, that userspace may have taken. However
302 * userspace is waiting on the DP workqueue to run which is
303 * blocked behind the non-DP one.
305 struct workqueue_struct *dp_wq;
308 #define I915_GEM_GPU_DOMAINS \
309 (I915_GEM_DOMAIN_RENDER | \
310 I915_GEM_DOMAIN_SAMPLER | \
311 I915_GEM_DOMAIN_COMMAND | \
312 I915_GEM_DOMAIN_INSTRUCTION | \
313 I915_GEM_DOMAIN_VERTEX)
315 struct drm_i915_private;
316 struct i915_mm_struct;
317 struct i915_mmu_object;
319 struct drm_i915_file_private {
320 struct drm_i915_private *dev_priv;
321 struct drm_file *file;
325 struct list_head request_list;
326 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
327 * chosen to prevent the CPU getting more than a frame ahead of the GPU
328 * (when using lax throttling for the frontbuffer). We also use it to
329 * offer free GPU waitboosts for severely congested workloads.
331 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
333 struct idr context_idr;
335 struct intel_rps_client {
339 unsigned int bsd_engine;
341 /* Client can have a maximum of 3 contexts banned before
342 * it is denied of creating new contexts. As one context
343 * ban needs 4 consecutive hangs, and more if there is
344 * progress in between, this is a last resort stop gap measure
345 * to limit the badly behaving clients access to gpu.
347 #define I915_MAX_CLIENT_CONTEXT_BANS 3
348 atomic_t context_bans;
351 /* Interface history:
354 * 1.2: Add Power Management
355 * 1.3: Add vblank support
356 * 1.4: Fix cmdbuffer path, add heap destroy
357 * 1.5: Add vblank pipe configuration
358 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
359 * - Support vertical blank on secondary display pipe
361 #define DRIVER_MAJOR 1
362 #define DRIVER_MINOR 6
363 #define DRIVER_PATCHLEVEL 0
365 struct intel_overlay;
366 struct intel_overlay_error_state;
368 struct sdvo_device_mapping {
377 struct intel_connector;
378 struct intel_encoder;
379 struct intel_atomic_state;
380 struct intel_crtc_state;
381 struct intel_initial_plane_config;
385 struct intel_cdclk_state;
387 struct drm_i915_display_funcs {
388 void (*get_cdclk)(struct drm_i915_private *dev_priv,
389 struct intel_cdclk_state *cdclk_state);
390 void (*set_cdclk)(struct drm_i915_private *dev_priv,
391 const struct intel_cdclk_state *cdclk_state);
392 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
393 enum i9xx_plane_id i9xx_plane);
394 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
395 int (*compute_intermediate_wm)(struct drm_device *dev,
396 struct intel_crtc *intel_crtc,
397 struct intel_crtc_state *newstate);
398 void (*initial_watermarks)(struct intel_atomic_state *state,
399 struct intel_crtc_state *cstate);
400 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
401 struct intel_crtc_state *cstate);
402 void (*optimize_watermarks)(struct intel_atomic_state *state,
403 struct intel_crtc_state *cstate);
404 int (*compute_global_watermarks)(struct drm_atomic_state *state);
405 void (*update_wm)(struct intel_crtc *crtc);
406 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
407 /* Returns the active state of the crtc, and if the crtc is active,
408 * fills out the pipe-config with the hw state. */
409 bool (*get_pipe_config)(struct intel_crtc *,
410 struct intel_crtc_state *);
411 void (*get_initial_plane_config)(struct intel_crtc *,
412 struct intel_initial_plane_config *);
413 int (*crtc_compute_clock)(struct intel_crtc *crtc,
414 struct intel_crtc_state *crtc_state);
415 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
416 struct drm_atomic_state *old_state);
417 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
418 struct drm_atomic_state *old_state);
419 void (*update_crtcs)(struct drm_atomic_state *state);
420 void (*audio_codec_enable)(struct intel_encoder *encoder,
421 const struct intel_crtc_state *crtc_state,
422 const struct drm_connector_state *conn_state);
423 void (*audio_codec_disable)(struct intel_encoder *encoder,
424 const struct intel_crtc_state *old_crtc_state,
425 const struct drm_connector_state *old_conn_state);
426 void (*fdi_link_train)(struct intel_crtc *crtc,
427 const struct intel_crtc_state *crtc_state);
428 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
429 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
430 /* clock updates for mode set */
432 /* render clock increase/decrease */
433 /* display clock increase/decrease */
434 /* pll clock increase/decrease */
436 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
437 void (*load_luts)(struct drm_crtc_state *crtc_state);
440 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
441 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
442 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
445 struct work_struct work;
447 uint32_t *dmc_payload;
448 uint32_t dmc_fw_size;
451 i915_reg_t mmioaddr[8];
452 uint32_t mmiodata[8];
454 uint32_t allowed_dc_mask;
457 enum i915_cache_level {
459 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
460 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
461 caches, eg sampler/render caches, and the
462 large Last-Level-Cache. LLC is coherent with
463 the CPU, but L3 is only visible to the GPU. */
464 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
467 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
478 /* This is always the inner lock when overlapping with struct_mutex and
479 * it's the outer lock when overlapping with stolen_lock. */
482 unsigned int possible_framebuffer_bits;
483 unsigned int busy_bits;
484 unsigned int visible_pipes_mask;
485 struct intel_crtc *crtc;
487 struct drm_mm_node compressed_fb;
488 struct drm_mm_node *compressed_llb;
495 bool underrun_detected;
496 struct work_struct underrun_work;
499 * Due to the atomic rules we can't access some structures without the
500 * appropriate locking, so we cache information here in order to avoid
503 struct intel_fbc_state_cache {
504 struct i915_vma *vma;
508 unsigned int mode_flags;
509 uint32_t hsw_bdw_pixel_rate;
513 unsigned int rotation;
518 * Display surface base address adjustement for
519 * pageflips. Note that on gen4+ this only adjusts up
520 * to a tile, offsets within a tile are handled in
521 * the hw itself (with the TILEOFF register).
530 const struct drm_format_info *format;
536 * This structure contains everything that's relevant to program the
537 * hardware registers. When we want to figure out if we need to disable
538 * and re-enable FBC for a new configuration we just check if there's
539 * something different in the struct. The genx_fbc_activate functions
540 * are supposed to read from it in order to program the registers.
542 struct intel_fbc_reg_params {
543 struct i915_vma *vma;
548 enum i9xx_plane_id i9xx_plane;
549 unsigned int fence_y_offset;
553 const struct drm_format_info *format;
558 unsigned int gen9_wa_cfb_stride;
561 struct intel_fbc_work {
563 u64 scheduled_vblank;
564 struct work_struct work;
567 const char *no_fbc_reason;
571 * HIGH_RR is the highest eDP panel refresh rate read from EDID
572 * LOW_RR is the lowest eDP panel refresh rate found from EDID
573 * parsing for same resolution.
575 enum drrs_refresh_rate_type {
578 DRRS_MAX_RR, /* RR count */
581 enum drrs_support_type {
582 DRRS_NOT_SUPPORTED = 0,
583 STATIC_DRRS_SUPPORT = 1,
584 SEAMLESS_DRRS_SUPPORT = 2
590 struct delayed_work work;
592 unsigned busy_frontbuffer_bits;
593 enum drrs_refresh_rate_type refresh_rate_type;
594 enum drrs_support_type type;
600 struct intel_dp *enabled;
602 struct delayed_work work;
603 unsigned busy_frontbuffer_bits;
608 bool colorimetry_support;
610 bool has_hw_tracking;
612 void (*enable_source)(struct intel_dp *,
613 const struct intel_crtc_state *);
614 void (*disable_source)(struct intel_dp *,
615 const struct intel_crtc_state *);
616 void (*enable_sink)(struct intel_dp *);
617 void (*activate)(struct intel_dp *);
618 void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
622 PCH_NONE = 0, /* No PCH present */
623 PCH_IBX, /* Ibexpeak PCH */
624 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
625 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
626 PCH_SPT, /* Sunrisepoint PCH */
627 PCH_KBP, /* Kaby Lake PCH */
628 PCH_CNP, /* Cannon Lake PCH */
629 PCH_ICP, /* Ice Lake PCH */
633 enum intel_sbi_destination {
638 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
639 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
640 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
641 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
642 #define QUIRK_INCREASE_T12_DELAY (1<<6)
645 struct intel_fbc_work;
648 struct i2c_adapter adapter;
649 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
653 struct i2c_algo_bit_data bit_algo;
654 struct drm_i915_private *dev_priv;
657 struct i915_suspend_saved_registers {
660 u32 saveCACHE_MODE_0;
661 u32 saveMI_ARB_STATE;
665 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
666 u32 savePCH_PORT_HOTPLUG;
670 struct vlv_s0ix_state {
677 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
678 u32 media_max_req_count;
679 u32 gfx_max_req_count;
711 /* Display 1 CZ domain */
716 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
718 /* GT SA CZ domain */
725 /* Display 2 CZ domain */
732 struct intel_rps_ei {
740 * work, interrupts_enabled and pm_iir are protected by
743 struct work_struct work;
744 bool interrupts_enabled;
747 /* PM interrupt bits that should never be masked */
750 /* Frequencies are stored in potentially platform dependent multiples.
751 * In other words, *_freq needs to be multiplied by X to be interesting.
752 * Soft limits are those which are used for the dynamic reclocking done
753 * by the driver (raise frequencies under heavy loads, and lower for
754 * lighter loads). Hard limits are those imposed by the hardware.
756 * A distinction is made for overclocking, which is never enabled by
757 * default, and is considered to be above the hard limit if it's
760 u8 cur_freq; /* Current frequency (cached, may not == HW) */
761 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
762 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
763 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
764 u8 min_freq; /* AKA RPn. Minimum frequency */
765 u8 boost_freq; /* Frequency to request when wait boosting */
766 u8 idle_freq; /* Frequency to request when we are idle */
767 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
768 u8 rp1_freq; /* "less than" RP0 power/freqency */
769 u8 rp0_freq; /* Non-overclocked max frequency. */
770 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
772 u8 up_threshold; /* Current %busy required to uplock */
773 u8 down_threshold; /* Current %busy required to downclock */
776 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
779 atomic_t num_waiters;
782 /* manual wa residency calculations */
783 struct intel_rps_ei ei;
788 u64 prev_hw_residency[4];
789 u64 cur_residency[4];
792 struct intel_llc_pstate {
796 struct intel_gen6_power_mgmt {
797 struct intel_rps rps;
798 struct intel_rc6 rc6;
799 struct intel_llc_pstate llc_pstate;
802 /* defined intel_pm.c */
803 extern spinlock_t mchdev_lock;
805 struct intel_ilk_power_mgmt {
813 unsigned long last_time1;
814 unsigned long chipset_power;
817 unsigned long gfx_power;
824 struct drm_i915_private;
825 struct i915_power_well;
827 struct i915_power_well_ops {
829 * Synchronize the well's hw state to match the current sw state, for
830 * example enable/disable it based on the current refcount. Called
831 * during driver init and resume time, possibly after first calling
832 * the enable/disable handlers.
834 void (*sync_hw)(struct drm_i915_private *dev_priv,
835 struct i915_power_well *power_well);
837 * Enable the well and resources that depend on it (for example
838 * interrupts located on the well). Called after the 0->1 refcount
841 void (*enable)(struct drm_i915_private *dev_priv,
842 struct i915_power_well *power_well);
844 * Disable the well and resources that depend on it. Called after
845 * the 1->0 refcount transition.
847 void (*disable)(struct drm_i915_private *dev_priv,
848 struct i915_power_well *power_well);
849 /* Returns the hw enabled state. */
850 bool (*is_enabled)(struct drm_i915_private *dev_priv,
851 struct i915_power_well *power_well);
854 /* Power well structure for haswell */
855 struct i915_power_well {
858 /* power well enable/disable usage count */
860 /* cached hw enabled state */
863 /* unique identifier for this power well */
864 enum i915_power_well_id id;
866 * Arbitraty data associated with this power well. Platform and power
874 /* Mask of pipes whose IRQ logic is backed by the pw */
876 /* The pw is backing the VGA functionality */
881 const struct i915_power_well_ops *ops;
884 struct i915_power_domains {
886 * Power wells needed for initialization at driver init and suspend
887 * time are on. They are kept on until after the first modeset.
891 int power_well_count;
894 int domain_use_count[POWER_DOMAIN_NUM];
895 struct i915_power_well *power_wells;
898 #define MAX_L3_SLICES 2
899 struct intel_l3_parity {
900 u32 *remap_info[MAX_L3_SLICES];
901 struct work_struct error_work;
906 /** Memory allocator for GTT stolen memory */
907 struct drm_mm stolen;
908 /** Protects the usage of the GTT stolen memory allocator. This is
909 * always the inner lock when overlapping with struct_mutex. */
910 struct mutex stolen_lock;
912 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
915 /** List of all objects in gtt_space. Used to restore gtt
916 * mappings on resume */
917 struct list_head bound_list;
919 * List of objects which are not bound to the GTT (thus
920 * are idle and not used by the GPU). These objects may or may
921 * not actually have any pages attached.
923 struct list_head unbound_list;
925 /** List of all objects in gtt_space, currently mmaped by userspace.
926 * All objects within this list must also be on bound_list.
928 struct list_head userfault_list;
931 * List of objects which are pending destruction.
933 struct llist_head free_list;
934 struct work_struct free_work;
935 spinlock_t free_lock;
937 * Count of objects pending destructions. Used to skip needlessly
938 * waiting on an RCU barrier if no objects are waiting to be freed.
943 * Small stash of WC pages
945 struct pagevec wc_stash;
948 * tmpfs instance used for shmem backed objects
950 struct vfsmount *gemfs;
952 /** PPGTT used for aliasing the PPGTT with the GTT */
953 struct i915_hw_ppgtt *aliasing_ppgtt;
955 struct notifier_block oom_notifier;
956 struct notifier_block vmap_notifier;
957 struct shrinker shrinker;
959 /** LRU list of objects with fence regs on them. */
960 struct list_head fence_list;
963 * Workqueue to fault in userptr pages, flushed by the execbuf
964 * when required but otherwise left to userspace to try again
967 struct workqueue_struct *userptr_wq;
969 u64 unordered_timeline;
971 /* the indicator for dispatch video commands on two BSD rings */
972 atomic_t bsd_engine_dispatch_index;
974 /** Bit 6 swizzling required for X tiling */
975 uint32_t bit_6_swizzle_x;
976 /** Bit 6 swizzling required for Y tiling */
977 uint32_t bit_6_swizzle_y;
979 /* accounting, useful for userland debugging */
980 spinlock_t object_stat_lock;
985 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
987 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
988 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
990 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
991 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
993 enum modeset_restore {
999 #define DP_AUX_A 0x40
1000 #define DP_AUX_B 0x10
1001 #define DP_AUX_C 0x20
1002 #define DP_AUX_D 0x30
1003 #define DP_AUX_F 0x60
1005 #define DDC_PIN_B 0x05
1006 #define DDC_PIN_C 0x04
1007 #define DDC_PIN_D 0x06
1009 struct ddi_vbt_port_info {
1013 * This is an index in the HDMI/DVI DDI buffer translation table.
1014 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1015 * populate this field.
1017 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1018 uint8_t hdmi_level_shift;
1020 uint8_t supports_dvi:1;
1021 uint8_t supports_hdmi:1;
1022 uint8_t supports_dp:1;
1023 uint8_t supports_edp:1;
1025 uint8_t alternate_aux_channel;
1026 uint8_t alternate_ddc_pin;
1028 uint8_t dp_boost_level;
1029 uint8_t hdmi_boost_level;
1030 int dp_max_link_rate; /* 0 for not limited by VBT */
1033 enum psr_lines_to_wait {
1034 PSR_0_LINES_TO_WAIT = 0,
1036 PSR_4_LINES_TO_WAIT,
1040 struct intel_vbt_data {
1041 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1042 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1045 unsigned int int_tv_support:1;
1046 unsigned int lvds_dither:1;
1047 unsigned int lvds_vbt:1;
1048 unsigned int int_crt_support:1;
1049 unsigned int lvds_use_ssc:1;
1050 unsigned int display_clock_mode:1;
1051 unsigned int fdi_rx_polarity_inverted:1;
1052 unsigned int panel_type:4;
1054 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1056 enum drrs_support_type drrs_type;
1067 struct edp_power_seq pps;
1072 bool require_aux_wakeup;
1074 enum psr_lines_to_wait lines_to_wait;
1075 int tp1_wakeup_time;
1076 int tp2_tp3_wakeup_time;
1082 bool active_low_pwm;
1083 u8 min_brightness; /* min_brightness/255 of max */
1084 u8 controller; /* brightness controller number */
1085 enum intel_backlight_type type;
1091 struct mipi_config *config;
1092 struct mipi_pps_data *pps;
1098 const u8 *sequence[MIPI_SEQ_MAX];
1099 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1105 struct child_device_config *child_dev;
1107 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1108 struct sdvo_device_mapping sdvo_mappings[2];
1111 enum intel_ddb_partitioning {
1113 INTEL_DDB_PART_5_6, /* IVB+ */
1116 struct intel_wm_level {
1124 struct ilk_wm_values {
1125 uint32_t wm_pipe[3];
1127 uint32_t wm_lp_spr[3];
1128 uint32_t wm_linetime[3];
1130 enum intel_ddb_partitioning partitioning;
1133 struct g4x_pipe_wm {
1134 uint16_t plane[I915_MAX_PLANES];
1144 struct vlv_wm_ddl_values {
1145 uint8_t plane[I915_MAX_PLANES];
1148 struct vlv_wm_values {
1149 struct g4x_pipe_wm pipe[3];
1150 struct g4x_sr_wm sr;
1151 struct vlv_wm_ddl_values ddl[3];
1156 struct g4x_wm_values {
1157 struct g4x_pipe_wm pipe[2];
1158 struct g4x_sr_wm sr;
1159 struct g4x_sr_wm hpll;
1165 struct skl_ddb_entry {
1166 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1169 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1171 return entry->end - entry->start;
1174 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1175 const struct skl_ddb_entry *e2)
1177 if (e1->start == e2->start && e1->end == e2->end)
1183 struct skl_ddb_allocation {
1184 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1185 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1188 struct skl_wm_values {
1189 unsigned dirty_pipes;
1190 struct skl_ddb_allocation ddb;
1193 struct skl_wm_level {
1195 uint16_t plane_res_b;
1196 uint8_t plane_res_l;
1199 /* Stores plane specific WM parameters */
1200 struct skl_wm_params {
1201 bool x_tiled, y_tiled;
1205 uint32_t plane_pixel_rate;
1206 uint32_t y_min_scanlines;
1207 uint32_t plane_bytes_per_line;
1208 uint_fixed_16_16_t plane_blocks_per_line;
1209 uint_fixed_16_16_t y_tile_minimum;
1210 uint32_t linetime_us;
1211 uint32_t dbuf_block_size;
1215 * This struct helps tracking the state needed for runtime PM, which puts the
1216 * device in PCI D3 state. Notice that when this happens, nothing on the
1217 * graphics device works, even register access, so we don't get interrupts nor
1220 * Every piece of our code that needs to actually touch the hardware needs to
1221 * either call intel_runtime_pm_get or call intel_display_power_get with the
1222 * appropriate power domain.
1224 * Our driver uses the autosuspend delay feature, which means we'll only really
1225 * suspend if we stay with zero refcount for a certain amount of time. The
1226 * default value is currently very conservative (see intel_runtime_pm_enable), but
1227 * it can be changed with the standard runtime PM files from sysfs.
1229 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1230 * goes back to false exactly before we reenable the IRQs. We use this variable
1231 * to check if someone is trying to enable/disable IRQs while they're supposed
1232 * to be disabled. This shouldn't happen and we'll print some error messages in
1235 * For more, read the Documentation/power/runtime_pm.txt.
1237 struct i915_runtime_pm {
1238 atomic_t wakeref_count;
1243 enum intel_pipe_crc_source {
1244 INTEL_PIPE_CRC_SOURCE_NONE,
1245 INTEL_PIPE_CRC_SOURCE_PLANE1,
1246 INTEL_PIPE_CRC_SOURCE_PLANE2,
1247 INTEL_PIPE_CRC_SOURCE_PF,
1248 INTEL_PIPE_CRC_SOURCE_PIPE,
1249 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1250 INTEL_PIPE_CRC_SOURCE_TV,
1251 INTEL_PIPE_CRC_SOURCE_DP_B,
1252 INTEL_PIPE_CRC_SOURCE_DP_C,
1253 INTEL_PIPE_CRC_SOURCE_DP_D,
1254 INTEL_PIPE_CRC_SOURCE_AUTO,
1255 INTEL_PIPE_CRC_SOURCE_MAX,
1258 struct intel_pipe_crc_entry {
1263 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1264 struct intel_pipe_crc {
1266 bool opened; /* exclusive access to the result file */
1267 struct intel_pipe_crc_entry *entries;
1268 enum intel_pipe_crc_source source;
1270 wait_queue_head_t wq;
1274 struct i915_frontbuffer_tracking {
1278 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1285 struct i915_wa_reg {
1288 /* bitmask representing WA bits */
1292 #define I915_MAX_WA_REGS 16
1294 struct i915_workarounds {
1295 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1297 u32 hw_whitelist_count[I915_NUM_ENGINES];
1300 struct i915_virtual_gpu {
1305 /* used in computing the new watermarks state */
1306 struct intel_wm_config {
1307 unsigned int num_pipes_active;
1308 bool sprites_enabled;
1309 bool sprites_scaled;
1312 struct i915_oa_format {
1317 struct i915_oa_reg {
1322 struct i915_oa_config {
1323 char uuid[UUID_STRING_LEN + 1];
1326 const struct i915_oa_reg *mux_regs;
1328 const struct i915_oa_reg *b_counter_regs;
1329 u32 b_counter_regs_len;
1330 const struct i915_oa_reg *flex_regs;
1333 struct attribute_group sysfs_metric;
1334 struct attribute *attrs[2];
1335 struct device_attribute sysfs_metric_id;
1340 struct i915_perf_stream;
1343 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1345 struct i915_perf_stream_ops {
1347 * @enable: Enables the collection of HW samples, either in response to
1348 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1349 * without `I915_PERF_FLAG_DISABLED`.
1351 void (*enable)(struct i915_perf_stream *stream);
1354 * @disable: Disables the collection of HW samples, either in response
1355 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1358 void (*disable)(struct i915_perf_stream *stream);
1361 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1362 * once there is something ready to read() for the stream
1364 void (*poll_wait)(struct i915_perf_stream *stream,
1369 * @wait_unlocked: For handling a blocking read, wait until there is
1370 * something to ready to read() for the stream. E.g. wait on the same
1371 * wait queue that would be passed to poll_wait().
1373 int (*wait_unlocked)(struct i915_perf_stream *stream);
1376 * @read: Copy buffered metrics as records to userspace
1377 * **buf**: the userspace, destination buffer
1378 * **count**: the number of bytes to copy, requested by userspace
1379 * **offset**: zero at the start of the read, updated as the read
1380 * proceeds, it represents how many bytes have been copied so far and
1381 * the buffer offset for copying the next record.
1383 * Copy as many buffered i915 perf samples and records for this stream
1384 * to userspace as will fit in the given buffer.
1386 * Only write complete records; returning -%ENOSPC if there isn't room
1387 * for a complete record.
1389 * Return any error condition that results in a short read such as
1390 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1391 * returning to userspace.
1393 int (*read)(struct i915_perf_stream *stream,
1399 * @destroy: Cleanup any stream specific resources.
1401 * The stream will always be disabled before this is called.
1403 void (*destroy)(struct i915_perf_stream *stream);
1407 * struct i915_perf_stream - state for a single open stream FD
1409 struct i915_perf_stream {
1411 * @dev_priv: i915 drm device
1413 struct drm_i915_private *dev_priv;
1416 * @link: Links the stream into ``&drm_i915_private->streams``
1418 struct list_head link;
1421 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1422 * properties given when opening a stream, representing the contents
1423 * of a single sample as read() by userspace.
1428 * @sample_size: Considering the configured contents of a sample
1429 * combined with the required header size, this is the total size
1430 * of a single sample record.
1435 * @ctx: %NULL if measuring system-wide across all contexts or a
1436 * specific context that is being monitored.
1438 struct i915_gem_context *ctx;
1441 * @enabled: Whether the stream is currently enabled, considering
1442 * whether the stream was opened in a disabled state and based
1443 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1448 * @ops: The callbacks providing the implementation of this specific
1449 * type of configured stream.
1451 const struct i915_perf_stream_ops *ops;
1454 * @oa_config: The OA configuration used by the stream.
1456 struct i915_oa_config *oa_config;
1460 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1462 struct i915_oa_ops {
1464 * @is_valid_b_counter_reg: Validates register's address for
1465 * programming boolean counters for a particular platform.
1467 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1471 * @is_valid_mux_reg: Validates register's address for programming mux
1472 * for a particular platform.
1474 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1477 * @is_valid_flex_reg: Validates register's address for programming
1478 * flex EU filtering for a particular platform.
1480 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1483 * @init_oa_buffer: Resets the head and tail pointers of the
1484 * circular buffer for periodic OA reports.
1486 * Called when first opening a stream for OA metrics, but also may be
1487 * called in response to an OA buffer overflow or other error
1490 * Note it may be necessary to clear the full OA buffer here as part of
1491 * maintaining the invariable that new reports must be written to
1492 * zeroed memory for us to be able to reliable detect if an expected
1493 * report has not yet landed in memory. (At least on Haswell the OA
1494 * buffer tail pointer is not synchronized with reports being visible
1497 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1500 * @enable_metric_set: Selects and applies any MUX configuration to set
1501 * up the Boolean and Custom (B/C) counters that are part of the
1502 * counter reports being sampled. May apply system constraints such as
1503 * disabling EU clock gating as required.
1505 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1506 const struct i915_oa_config *oa_config);
1509 * @disable_metric_set: Remove system constraints associated with using
1512 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1515 * @oa_enable: Enable periodic sampling
1517 void (*oa_enable)(struct drm_i915_private *dev_priv);
1520 * @oa_disable: Disable periodic sampling
1522 void (*oa_disable)(struct drm_i915_private *dev_priv);
1525 * @read: Copy data from the circular OA buffer into a given userspace
1528 int (*read)(struct i915_perf_stream *stream,
1534 * @oa_hw_tail_read: read the OA tail pointer register
1536 * In particular this enables us to share all the fiddly code for
1537 * handling the OA unit tail pointer race that affects multiple
1540 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1543 struct intel_cdclk_state {
1544 unsigned int cdclk, vco, ref, bypass;
1548 struct drm_i915_private {
1549 struct drm_device drm;
1551 struct kmem_cache *objects;
1552 struct kmem_cache *vmas;
1553 struct kmem_cache *luts;
1554 struct kmem_cache *requests;
1555 struct kmem_cache *dependencies;
1556 struct kmem_cache *priorities;
1558 const struct intel_device_info info;
1559 struct intel_driver_caps caps;
1562 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1563 * end of stolen which we can optionally use to create GEM objects
1564 * backed by stolen memory. Note that stolen_usable_size tells us
1565 * exactly how much of this we are actually allowed to use, given that
1566 * some portion of it is in fact reserved for use by hardware functions.
1568 struct resource dsm;
1570 * Reseved portion of Data Stolen Memory
1572 struct resource dsm_reserved;
1575 * Stolen memory is segmented in hardware with different portions
1576 * offlimits to certain functions.
1578 * The drm_mm is initialised to the total accessible range, as found
1579 * from the PCI config. On Broadwell+, this is further restricted to
1580 * avoid the first page! The upper end of stolen memory is reserved for
1581 * hardware functions and similarly removed from the accessible range.
1583 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1587 struct intel_uncore uncore;
1589 struct i915_virtual_gpu vgpu;
1591 struct intel_gvt *gvt;
1593 struct intel_wopcm wopcm;
1595 struct intel_huc huc;
1596 struct intel_guc guc;
1598 struct intel_csr csr;
1600 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1602 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1603 * controller on different i2c buses. */
1604 struct mutex gmbus_mutex;
1607 * Base address of the gmbus and gpio block.
1609 uint32_t gpio_mmio_base;
1611 /* MMIO base address for MIPI regs */
1612 uint32_t mipi_mmio_base;
1614 uint32_t psr_mmio_base;
1616 uint32_t pps_mmio_base;
1618 wait_queue_head_t gmbus_wait_queue;
1620 struct pci_dev *bridge_dev;
1621 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1622 /* Context used internally to idle the GPU and setup initial state */
1623 struct i915_gem_context *kernel_context;
1624 /* Context only to be used for injecting preemption commands */
1625 struct i915_gem_context *preempt_context;
1626 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1627 [MAX_ENGINE_INSTANCE + 1];
1629 struct drm_dma_handle *status_page_dmah;
1630 struct resource mch_res;
1632 /* protects the irq masks */
1633 spinlock_t irq_lock;
1635 bool display_irqs_enabled;
1637 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1638 struct pm_qos_request pm_qos;
1640 /* Sideband mailbox protection */
1641 struct mutex sb_lock;
1643 /** Cached value of IMR to avoid reads in updating the bitfield */
1646 u32 de_irq_mask[I915_MAX_PIPES];
1653 u32 pipestat_irq_mask[I915_MAX_PIPES];
1655 struct i915_hotplug hotplug;
1656 struct intel_fbc fbc;
1657 struct i915_drrs drrs;
1658 struct intel_opregion opregion;
1659 struct intel_vbt_data vbt;
1661 bool preserve_bios_swizzle;
1664 struct intel_overlay *overlay;
1666 /* backlight registers and fields in struct intel_panel */
1667 struct mutex backlight_lock;
1670 bool no_aux_handshake;
1672 /* protects panel power sequencer state */
1673 struct mutex pps_mutex;
1675 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1676 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1678 unsigned int fsb_freq, mem_freq, is_ddr3;
1679 unsigned int skl_preferred_vco_freq;
1680 unsigned int max_cdclk_freq;
1682 unsigned int max_dotclk_freq;
1683 unsigned int rawclk_freq;
1684 unsigned int hpll_freq;
1685 unsigned int fdi_pll_freq;
1686 unsigned int czclk_freq;
1690 * The current logical cdclk state.
1691 * See intel_atomic_state.cdclk.logical
1693 * For reading holding any crtc lock is sufficient,
1694 * for writing must hold all of them.
1696 struct intel_cdclk_state logical;
1698 * The current actual cdclk state.
1699 * See intel_atomic_state.cdclk.actual
1701 struct intel_cdclk_state actual;
1702 /* The current hardware cdclk state */
1703 struct intel_cdclk_state hw;
1707 * wq - Driver workqueue for GEM.
1709 * NOTE: Work items scheduled here are not allowed to grab any modeset
1710 * locks, for otherwise the flushing done in the pageflip code will
1711 * result in deadlocks.
1713 struct workqueue_struct *wq;
1715 /* ordered wq for modesets */
1716 struct workqueue_struct *modeset_wq;
1718 /* Display functions */
1719 struct drm_i915_display_funcs display;
1721 /* PCH chipset type */
1722 enum intel_pch pch_type;
1723 unsigned short pch_id;
1725 unsigned long quirks;
1727 enum modeset_restore modeset_restore;
1728 struct mutex modeset_restore_lock;
1729 struct drm_atomic_state *modeset_restore_state;
1730 struct drm_modeset_acquire_ctx reset_ctx;
1732 struct list_head vm_list; /* Global list of all address spaces */
1733 struct i915_ggtt ggtt; /* VM representing the global address space */
1735 struct i915_gem_mm mm;
1736 DECLARE_HASHTABLE(mm_structs, 7);
1737 struct mutex mm_lock;
1739 struct intel_ppat ppat;
1741 /* Kernel Modesetting */
1743 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1744 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1746 #ifdef CONFIG_DEBUG_FS
1747 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1750 /* dpll and cdclk state is protected by connection_mutex */
1751 int num_shared_dpll;
1752 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1753 const struct intel_dpll_mgr *dpll_mgr;
1756 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1757 * Must be global rather than per dpll, because on some platforms
1758 * plls share registers.
1760 struct mutex dpll_lock;
1762 unsigned int active_crtcs;
1763 /* minimum acceptable cdclk for each pipe */
1764 int min_cdclk[I915_MAX_PIPES];
1765 /* minimum acceptable voltage level for each pipe */
1766 u8 min_voltage_level[I915_MAX_PIPES];
1768 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1770 struct i915_workarounds workarounds;
1772 struct i915_frontbuffer_tracking fb_tracking;
1774 struct intel_atomic_helper {
1775 struct llist_head free_list;
1776 struct work_struct free_work;
1781 bool mchbar_need_disable;
1783 struct intel_l3_parity l3_parity;
1785 /* Cannot be determined by PCIID. You must always read a register. */
1789 * Protects RPS/RC6 register access and PCU communication.
1790 * Must be taken after struct_mutex if nested. Note that
1791 * this lock may be held for long periods of time when
1792 * talking to hw - so only take it when talking to hw!
1794 struct mutex pcu_lock;
1796 /* gen6+ GT PM state */
1797 struct intel_gen6_power_mgmt gt_pm;
1799 /* ilk-only ips/rps state. Everything in here is protected by the global
1800 * mchdev_lock in intel_pm.c */
1801 struct intel_ilk_power_mgmt ips;
1803 struct i915_power_domains power_domains;
1805 struct i915_psr psr;
1807 struct i915_gpu_error gpu_error;
1809 struct drm_i915_gem_object *vlv_pctx;
1811 /* list of fbdev register on this device */
1812 struct intel_fbdev *fbdev;
1813 struct work_struct fbdev_suspend_work;
1815 struct drm_property *broadcast_rgb_property;
1816 struct drm_property *force_audio_property;
1818 /* hda/i915 audio component */
1819 struct i915_audio_component *audio_component;
1820 bool audio_component_registered;
1822 * av_mutex - mutex for audio/video sync
1825 struct mutex av_mutex;
1828 struct list_head list;
1829 struct llist_head free_list;
1830 struct work_struct free_work;
1832 /* The hw wants to have a stable context identifier for the
1833 * lifetime of the context (for OA, PASID, faults, etc).
1834 * This is limited in execlists to 21 bits.
1837 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1838 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1843 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1844 u32 chv_phy_control;
1846 * Shadows for CHV DPLL_MD regs to keep the state
1847 * checker somewhat working in the presence hardware
1848 * crappiness (can't read out DPLL_MD for pipes B & C).
1850 u32 chv_dpll_md[I915_MAX_PIPES];
1854 bool suspended_to_idle;
1855 struct i915_suspend_saved_registers regfile;
1856 struct vlv_s0ix_state vlv_s0ix_state;
1859 I915_SAGV_UNKNOWN = 0,
1862 I915_SAGV_NOT_CONTROLLED
1867 * Raw watermark latency values:
1868 * in 0.1us units for WM0,
1869 * in 0.5us units for WM1+.
1872 uint16_t pri_latency[5];
1874 uint16_t spr_latency[5];
1876 uint16_t cur_latency[5];
1878 * Raw watermark memory latency values
1879 * for SKL for all 8 levels
1882 uint16_t skl_latency[8];
1884 /* current hardware state */
1886 struct ilk_wm_values hw;
1887 struct skl_wm_values skl_hw;
1888 struct vlv_wm_values vlv;
1889 struct g4x_wm_values g4x;
1895 * Should be held around atomic WM register writing; also
1896 * protects * intel_crtc->wm.active and
1897 * cstate->wm.need_postvbl_update.
1899 struct mutex wm_mutex;
1902 * Set during HW readout of watermarks/DDB. Some platforms
1903 * need to know when we're still using BIOS-provided values
1904 * (which we don't fully trust).
1906 bool distrust_bios_wm;
1909 struct i915_runtime_pm runtime_pm;
1914 struct kobject *metrics_kobj;
1915 struct ctl_table_header *sysctl_header;
1918 * Lock associated with adding/modifying/removing OA configs
1919 * in dev_priv->perf.metrics_idr.
1921 struct mutex metrics_lock;
1924 * List of dynamic configurations, you need to hold
1925 * dev_priv->perf.metrics_lock to access it.
1927 struct idr metrics_idr;
1930 * Lock associated with anything below within this structure
1931 * except exclusive_stream.
1934 struct list_head streams;
1938 * The stream currently using the OA unit. If accessed
1939 * outside a syscall associated to its file
1940 * descriptor, you need to hold
1941 * dev_priv->drm.struct_mutex.
1943 struct i915_perf_stream *exclusive_stream;
1945 u32 specific_ctx_id;
1947 struct hrtimer poll_check_timer;
1948 wait_queue_head_t poll_wq;
1952 * For rate limiting any notifications of spurious
1953 * invalid OA reports
1955 struct ratelimit_state spurious_report_rs;
1958 int period_exponent;
1960 struct i915_oa_config test_config;
1963 struct i915_vma *vma;
1970 * Locks reads and writes to all head/tail state
1972 * Consider: the head and tail pointer state
1973 * needs to be read consistently from a hrtimer
1974 * callback (atomic context) and read() fop
1975 * (user context) with tail pointer updates
1976 * happening in atomic context and head updates
1977 * in user context and the (unlikely)
1978 * possibility of read() errors needing to
1979 * reset all head/tail state.
1981 * Note: Contention or performance aren't
1982 * currently a significant concern here
1983 * considering the relatively low frequency of
1984 * hrtimer callbacks (5ms period) and that
1985 * reads typically only happen in response to a
1986 * hrtimer event and likely complete before the
1989 * Note: This lock is not held *while* reading
1990 * and copying data to userspace so the value
1991 * of head observed in htrimer callbacks won't
1992 * represent any partial consumption of data.
1994 spinlock_t ptr_lock;
1997 * One 'aging' tail pointer and one 'aged'
1998 * tail pointer ready to used for reading.
2000 * Initial values of 0xffffffff are invalid
2001 * and imply that an update is required
2002 * (and should be ignored by an attempted
2010 * Index for the aged tail ready to read()
2013 unsigned int aged_tail_idx;
2016 * A monotonic timestamp for when the current
2017 * aging tail pointer was read; used to
2018 * determine when it is old enough to trust.
2020 u64 aging_timestamp;
2023 * Although we can always read back the head
2024 * pointer register, we prefer to avoid
2025 * trusting the HW state, just to avoid any
2026 * risk that some hardware condition could
2027 * somehow bump the head pointer unpredictably
2028 * and cause us to forward the wrong OA buffer
2029 * data to userspace.
2034 u32 gen7_latched_oastatus1;
2035 u32 ctx_oactxctrl_offset;
2036 u32 ctx_flexeu0_offset;
2039 * The RPT_ID/reason field for Gen8+ includes a bit
2040 * to determine if the CTX ID in the report is valid
2041 * but the specific bit differs between Gen 8 and 9
2043 u32 gen8_valid_ctx_bit;
2045 struct i915_oa_ops ops;
2046 const struct i915_oa_format *oa_formats;
2050 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2052 void (*resume)(struct drm_i915_private *);
2053 void (*cleanup_engine)(struct intel_engine_cs *engine);
2055 struct list_head timelines;
2056 struct i915_gem_timeline global_timeline;
2057 u32 active_requests;
2060 * Is the GPU currently considered idle, or busy executing
2061 * userspace requests? Whilst idle, we allow runtime power
2062 * management to power down the hardware and display clocks.
2063 * In order to reduce the effect on performance, there
2064 * is a slight delay before we do so.
2069 * The number of times we have woken up.
2072 #define I915_EPOCH_INVALID 0
2075 * We leave the user IRQ off as much as possible,
2076 * but this means that requests will finish and never
2077 * be retired once the system goes idle. Set a timer to
2078 * fire periodically while the ring is running. When it
2079 * fires, go retire requests.
2081 struct delayed_work retire_work;
2084 * When we detect an idle GPU, we want to turn on
2085 * powersaving features. So once we see that there
2086 * are no more requests outstanding and no more
2087 * arrive within a small period of time, we fire
2088 * off the idle_work.
2090 struct delayed_work idle_work;
2092 ktime_t last_init_time;
2095 /* perform PHY state sanity checks? */
2096 bool chv_phy_assert[2];
2100 /* Used to save the pipe-to-encoder mapping for audio */
2101 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2103 /* necessary resource sharing with HDMI LPE audio driver. */
2105 struct platform_device *platdev;
2109 struct i915_pmu pmu;
2112 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2113 * will be rejected. Instead look for a better place.
2117 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2119 return container_of(dev, struct drm_i915_private, drm);
2122 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2124 return to_i915(dev_get_drvdata(kdev));
2127 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2129 return container_of(wopcm, struct drm_i915_private, wopcm);
2132 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2134 return container_of(guc, struct drm_i915_private, guc);
2137 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2139 return container_of(huc, struct drm_i915_private, huc);
2142 /* Simple iterator over all initialised engines */
2143 #define for_each_engine(engine__, dev_priv__, id__) \
2145 (id__) < I915_NUM_ENGINES; \
2147 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2149 /* Iterator over subset of engines selected by mask */
2150 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2151 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2152 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2154 enum hdmi_force_audio {
2155 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2156 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2157 HDMI_AUDIO_AUTO, /* trust EDID */
2158 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2161 #define I915_GTT_OFFSET_NONE ((u32)-1)
2164 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2165 * considered to be the frontbuffer for the given plane interface-wise. This
2166 * doesn't mean that the hw necessarily already scans it out, but that any
2167 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2169 * We have one bit per pipe and per scanout plane type.
2171 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2172 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2173 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2174 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2175 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2177 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2178 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2179 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2180 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2181 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2184 * Optimised SGL iterator for GEM objects
2186 static __always_inline struct sgt_iter {
2187 struct scatterlist *sgp;
2194 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2195 struct sgt_iter s = { .sgp = sgl };
2198 s.max = s.curr = s.sgp->offset;
2199 s.max += s.sgp->length;
2201 s.dma = sg_dma_address(s.sgp);
2203 s.pfn = page_to_pfn(sg_page(s.sgp));
2209 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2212 if (unlikely(sg_is_chain(sg)))
2213 sg = sg_chain_ptr(sg);
2218 * __sg_next - return the next scatterlist entry in a list
2219 * @sg: The current sg entry
2222 * If the entry is the last, return NULL; otherwise, step to the next
2223 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2224 * otherwise just return the pointer to the current element.
2226 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2228 #ifdef CONFIG_DEBUG_SG
2229 BUG_ON(sg->sg_magic != SG_MAGIC);
2231 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2235 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2236 * @__dmap: DMA address (output)
2237 * @__iter: 'struct sgt_iter' (iterator state, internal)
2238 * @__sgt: sg_table to iterate over (input)
2240 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2241 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2242 ((__dmap) = (__iter).dma + (__iter).curr); \
2243 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2244 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2247 * for_each_sgt_page - iterate over the pages of the given sg_table
2248 * @__pp: page pointer (output)
2249 * @__iter: 'struct sgt_iter' (iterator state, internal)
2250 * @__sgt: sg_table to iterate over (input)
2252 #define for_each_sgt_page(__pp, __iter, __sgt) \
2253 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2254 ((__pp) = (__iter).pfn == 0 ? NULL : \
2255 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2256 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2257 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2259 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2261 unsigned int page_sizes;
2265 GEM_BUG_ON(sg->offset);
2266 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2267 page_sizes |= sg->length;
2274 static inline unsigned int i915_sg_segment_size(void)
2276 unsigned int size = swiotlb_max_segment();
2279 return SCATTERLIST_MAX_SEGMENT;
2281 size = rounddown(size, PAGE_SIZE);
2282 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2283 if (size < PAGE_SIZE)
2289 static inline const struct intel_device_info *
2290 intel_info(const struct drm_i915_private *dev_priv)
2292 return &dev_priv->info;
2295 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2297 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2298 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2300 #define REVID_FOREVER 0xff
2301 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2303 #define GEN_FOREVER (0)
2305 #define INTEL_GEN_MASK(s, e) ( \
2306 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2307 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2308 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2309 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2313 * Returns true if Gen is in inclusive range [Start, End].
2315 * Use GEN_FOREVER for unbound start and or end.
2317 #define IS_GEN(dev_priv, s, e) \
2318 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2321 * Return true if revision is in range [since,until] inclusive.
2323 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2325 #define IS_REVID(p, since, until) \
2326 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2328 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2330 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2331 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2332 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2333 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2334 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2335 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2336 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2337 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2338 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2339 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2340 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2341 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2342 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2343 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2344 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2345 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2346 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2347 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2348 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2349 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2350 (dev_priv)->info.gt == 1)
2351 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2352 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2353 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2354 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2355 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2356 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2357 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2358 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2359 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2360 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2361 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2362 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2363 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2364 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2365 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2366 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2367 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2368 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2369 /* ULX machines are also considered ULT. */
2370 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2371 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2372 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2373 (dev_priv)->info.gt == 3)
2374 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2375 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2376 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2377 (dev_priv)->info.gt == 3)
2378 /* ULX machines are also considered ULT. */
2379 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2380 INTEL_DEVID(dev_priv) == 0x0A1E)
2381 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2382 INTEL_DEVID(dev_priv) == 0x1913 || \
2383 INTEL_DEVID(dev_priv) == 0x1916 || \
2384 INTEL_DEVID(dev_priv) == 0x1921 || \
2385 INTEL_DEVID(dev_priv) == 0x1926)
2386 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2387 INTEL_DEVID(dev_priv) == 0x1915 || \
2388 INTEL_DEVID(dev_priv) == 0x191E)
2389 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2390 INTEL_DEVID(dev_priv) == 0x5913 || \
2391 INTEL_DEVID(dev_priv) == 0x5916 || \
2392 INTEL_DEVID(dev_priv) == 0x5921 || \
2393 INTEL_DEVID(dev_priv) == 0x5926)
2394 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2395 INTEL_DEVID(dev_priv) == 0x5915 || \
2396 INTEL_DEVID(dev_priv) == 0x591E)
2397 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2398 (dev_priv)->info.gt == 2)
2399 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2400 (dev_priv)->info.gt == 3)
2401 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2402 (dev_priv)->info.gt == 4)
2403 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2404 (dev_priv)->info.gt == 2)
2405 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2406 (dev_priv)->info.gt == 3)
2407 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2408 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2409 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2410 (dev_priv)->info.gt == 2)
2411 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2412 (dev_priv)->info.gt == 3)
2413 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2414 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2416 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2418 #define SKL_REVID_A0 0x0
2419 #define SKL_REVID_B0 0x1
2420 #define SKL_REVID_C0 0x2
2421 #define SKL_REVID_D0 0x3
2422 #define SKL_REVID_E0 0x4
2423 #define SKL_REVID_F0 0x5
2424 #define SKL_REVID_G0 0x6
2425 #define SKL_REVID_H0 0x7
2427 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2429 #define BXT_REVID_A0 0x0
2430 #define BXT_REVID_A1 0x1
2431 #define BXT_REVID_B0 0x3
2432 #define BXT_REVID_B_LAST 0x8
2433 #define BXT_REVID_C0 0x9
2435 #define IS_BXT_REVID(dev_priv, since, until) \
2436 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2438 #define KBL_REVID_A0 0x0
2439 #define KBL_REVID_B0 0x1
2440 #define KBL_REVID_C0 0x2
2441 #define KBL_REVID_D0 0x3
2442 #define KBL_REVID_E0 0x4
2444 #define IS_KBL_REVID(dev_priv, since, until) \
2445 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2447 #define GLK_REVID_A0 0x0
2448 #define GLK_REVID_A1 0x1
2450 #define IS_GLK_REVID(dev_priv, since, until) \
2451 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2453 #define CNL_REVID_A0 0x0
2454 #define CNL_REVID_B0 0x1
2455 #define CNL_REVID_C0 0x2
2457 #define IS_CNL_REVID(p, since, until) \
2458 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2461 * The genX designation typically refers to the render engine, so render
2462 * capability related checks should use IS_GEN, while display and other checks
2463 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2466 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2467 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2468 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2469 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2470 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2471 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2472 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2473 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2474 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2475 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2477 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2478 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2479 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2481 #define ENGINE_MASK(id) BIT(id)
2482 #define RENDER_RING ENGINE_MASK(RCS)
2483 #define BSD_RING ENGINE_MASK(VCS)
2484 #define BLT_RING ENGINE_MASK(BCS)
2485 #define VEBOX_RING ENGINE_MASK(VECS)
2486 #define BSD2_RING ENGINE_MASK(VCS2)
2487 #define BSD3_RING ENGINE_MASK(VCS3)
2488 #define BSD4_RING ENGINE_MASK(VCS4)
2489 #define VEBOX2_RING ENGINE_MASK(VECS2)
2490 #define ALL_ENGINES (~0)
2492 #define HAS_ENGINE(dev_priv, id) \
2493 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2495 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2496 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2497 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2498 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2500 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2502 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2503 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2504 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2505 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2506 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2508 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2510 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2511 ((dev_priv)->info.has_logical_ring_contexts)
2512 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2513 ((dev_priv)->info.has_logical_ring_elsq)
2514 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2515 ((dev_priv)->info.has_logical_ring_preemption)
2517 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2519 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2520 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2521 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2522 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2523 GEM_BUG_ON((sizes) == 0); \
2524 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2527 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2528 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2529 ((dev_priv)->info.overlay_needs_physical)
2531 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2532 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2534 /* WaRsDisableCoarsePowerGating:skl,cnl */
2535 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2536 (IS_CANNONLAKE(dev_priv) || \
2537 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2540 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2541 * even when in MSI mode. This results in spurious interrupt warnings if the
2542 * legacy irq no. is shared with another device. The kernel then disables that
2543 * interrupt source and so prevents the other device from working properly.
2545 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
2548 #define HAS_AUX_IRQ(dev_priv) true
2549 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2551 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2552 * rows, which changed the alignment requirements and fence programming.
2554 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2555 !(IS_I915G(dev_priv) || \
2556 IS_I915GM(dev_priv)))
2557 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2558 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2560 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2561 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2562 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2564 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2566 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2568 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2569 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2570 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2572 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2573 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2574 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2576 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2578 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2579 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2581 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2584 * For now, anything with a GuC requires uCode loading, and then supports
2585 * command submission once loaded. But these are logically independent
2586 * properties, so we have separate macros to test them.
2588 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2589 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2590 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2591 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2593 /* For now, anything with a GuC has also HuC */
2594 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2595 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2597 /* Having a GuC is not the same as using a GuC */
2598 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2599 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2600 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2602 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2604 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2606 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2607 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2608 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2609 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2610 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2611 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2612 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2613 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2614 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2615 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2616 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2617 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2618 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2619 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2620 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2621 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2622 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2624 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2625 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2626 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2627 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2628 #define HAS_PCH_CNP_LP(dev_priv) \
2629 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2630 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2631 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2632 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2633 #define HAS_PCH_LPT_LP(dev_priv) \
2634 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2635 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2636 #define HAS_PCH_LPT_H(dev_priv) \
2637 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2638 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2639 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2640 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2641 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2642 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2644 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2646 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2648 /* DPF == dynamic parity feature */
2649 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2650 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2651 2 : HAS_L3_DPF(dev_priv))
2653 #define GT_FREQUENCY_MULTIPLIER 50
2654 #define GEN9_FREQ_SCALER 3
2656 #include "i915_trace.h"
2658 static inline bool intel_vtd_active(void)
2660 #ifdef CONFIG_INTEL_IOMMU
2661 if (intel_iommu_gfx_mapped)
2667 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2669 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2673 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2675 return IS_BROXTON(dev_priv) && intel_vtd_active();
2678 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2683 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2684 const char *fmt, ...);
2686 #define i915_report_error(dev_priv, fmt, ...) \
2687 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2689 #ifdef CONFIG_COMPAT
2690 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2693 #define i915_compat_ioctl NULL
2695 extern const struct dev_pm_ops i915_pm_ops;
2697 extern int i915_driver_load(struct pci_dev *pdev,
2698 const struct pci_device_id *ent);
2699 extern void i915_driver_unload(struct drm_device *dev);
2700 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2701 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2703 extern void i915_reset(struct drm_i915_private *i915);
2704 extern int i915_reset_engine(struct intel_engine_cs *engine, const char *msg);
2706 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2707 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2708 extern int intel_guc_reset_engine(struct intel_guc *guc,
2709 struct intel_engine_cs *engine);
2710 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2711 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2712 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2713 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2714 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2715 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2716 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2718 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2719 int intel_engines_init(struct drm_i915_private *dev_priv);
2721 /* intel_hotplug.c */
2722 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2723 u32 pin_mask, u32 long_mask);
2724 void intel_hpd_init(struct drm_i915_private *dev_priv);
2725 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2726 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2727 enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
2729 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2731 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2732 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2735 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2737 unsigned long delay;
2739 if (unlikely(!i915_modparams.enable_hangcheck))
2742 /* Don't continually defer the hangcheck so that it is always run at
2743 * least once after work has been scheduled on any ring. Otherwise,
2744 * we will ignore a hung ring if a second ring is kept busy.
2747 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2748 queue_delayed_work(system_long_wq,
2749 &dev_priv->gpu_error.hangcheck_work, delay);
2753 void i915_handle_error(struct drm_i915_private *dev_priv,
2755 unsigned long flags,
2756 const char *fmt, ...);
2757 #define I915_ERROR_CAPTURE BIT(0)
2759 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2760 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2761 int intel_irq_install(struct drm_i915_private *dev_priv);
2762 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2764 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2766 return dev_priv->gvt;
2769 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2771 return dev_priv->vgpu.active;
2774 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2777 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2781 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2784 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2785 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2786 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2789 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2790 uint32_t interrupt_mask,
2791 uint32_t enabled_irq_mask);
2793 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2795 ilk_update_display_irq(dev_priv, bits, bits);
2798 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2800 ilk_update_display_irq(dev_priv, bits, 0);
2802 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2804 uint32_t interrupt_mask,
2805 uint32_t enabled_irq_mask);
2806 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2807 enum pipe pipe, uint32_t bits)
2809 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2811 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2812 enum pipe pipe, uint32_t bits)
2814 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2816 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2817 uint32_t interrupt_mask,
2818 uint32_t enabled_irq_mask);
2820 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2822 ibx_display_interrupt_update(dev_priv, bits, bits);
2825 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2827 ibx_display_interrupt_update(dev_priv, bits, 0);
2831 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2832 struct drm_file *file_priv);
2833 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2834 struct drm_file *file_priv);
2835 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2836 struct drm_file *file_priv);
2837 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2838 struct drm_file *file_priv);
2839 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2840 struct drm_file *file_priv);
2841 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2842 struct drm_file *file_priv);
2843 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2844 struct drm_file *file_priv);
2845 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2846 struct drm_file *file_priv);
2847 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2848 struct drm_file *file_priv);
2849 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2850 struct drm_file *file_priv);
2851 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2852 struct drm_file *file);
2853 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2854 struct drm_file *file);
2855 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2856 struct drm_file *file_priv);
2857 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2858 struct drm_file *file_priv);
2859 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2860 struct drm_file *file_priv);
2861 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2864 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2865 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2866 struct drm_file *file);
2867 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2868 struct drm_file *file_priv);
2869 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2870 struct drm_file *file_priv);
2871 void i915_gem_sanitize(struct drm_i915_private *i915);
2872 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2873 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2874 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2875 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2876 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2878 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2879 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2880 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2881 const struct drm_i915_gem_object_ops *ops);
2882 struct drm_i915_gem_object *
2883 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2884 struct drm_i915_gem_object *
2885 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2886 const void *data, size_t size);
2887 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2888 void i915_gem_free_object(struct drm_gem_object *obj);
2890 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2892 if (!atomic_read(&i915->mm.free_count))
2895 /* A single pass should suffice to release all the freed objects (along
2896 * most call paths) , but be a little more paranoid in that freeing
2897 * the objects does take a little amount of time, during which the rcu
2898 * callbacks could have added new objects into the freed list, and
2899 * armed the work again.
2903 } while (flush_work(&i915->mm.free_work));
2906 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2909 * Similar to objects above (see i915_gem_drain_freed-objects), in
2910 * general we have workers that are armed by RCU and then rearm
2911 * themselves in their callbacks. To be paranoid, we need to
2912 * drain the workqueue a second time after waiting for the RCU
2913 * grace period so that we catch work queued via RCU from the first
2914 * pass. As neither drain_workqueue() nor flush_workqueue() report
2915 * a result, we make an assumption that we only don't require more
2916 * than 2 passes to catch all recursive RCU delayed work.
2922 drain_workqueue(i915->wq);
2926 struct i915_vma * __must_check
2927 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2928 const struct i915_ggtt_view *view,
2933 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2934 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2936 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2938 static inline int __sg_page_count(const struct scatterlist *sg)
2940 return sg->length >> PAGE_SHIFT;
2943 struct scatterlist *
2944 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2945 unsigned int n, unsigned int *offset);
2948 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2952 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2956 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2959 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2960 struct sg_table *pages,
2961 unsigned int sg_page_sizes);
2962 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2964 static inline int __must_check
2965 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2967 might_lock(&obj->mm.lock);
2969 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2972 return __i915_gem_object_get_pages(obj);
2976 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2978 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2982 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2984 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2986 atomic_inc(&obj->mm.pages_pin_count);
2990 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2992 return atomic_read(&obj->mm.pages_pin_count);
2996 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2998 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2999 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3001 atomic_dec(&obj->mm.pages_pin_count);
3005 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3007 __i915_gem_object_unpin_pages(obj);
3010 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3015 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3016 enum i915_mm_subclass subclass);
3017 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3019 enum i915_map_type {
3022 #define I915_MAP_OVERRIDE BIT(31)
3023 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3024 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3028 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3029 * @obj: the object to map into kernel address space
3030 * @type: the type of mapping, used to select pgprot_t
3032 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3033 * pages and then returns a contiguous mapping of the backing storage into
3034 * the kernel address space. Based on the @type of mapping, the PTE will be
3035 * set to either WriteBack or WriteCombine (via pgprot_t).
3037 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3038 * mapping is no longer required.
3040 * Returns the pointer through which to access the mapped object, or an
3041 * ERR_PTR() on error.
3043 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3044 enum i915_map_type type);
3047 * i915_gem_object_unpin_map - releases an earlier mapping
3048 * @obj: the object to unmap
3050 * After pinning the object and mapping its pages, once you are finished
3051 * with your access, call i915_gem_object_unpin_map() to release the pin
3052 * upon the mapping. Once the pin count reaches zero, that mapping may be
3055 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3057 i915_gem_object_unpin_pages(obj);
3060 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3061 unsigned int *needs_clflush);
3062 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3063 unsigned int *needs_clflush);
3064 #define CLFLUSH_BEFORE BIT(0)
3065 #define CLFLUSH_AFTER BIT(1)
3066 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3069 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3071 i915_gem_object_unpin_pages(obj);
3074 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3075 void i915_vma_move_to_active(struct i915_vma *vma,
3076 struct i915_request *rq,
3077 unsigned int flags);
3078 int i915_gem_dumb_create(struct drm_file *file_priv,
3079 struct drm_device *dev,
3080 struct drm_mode_create_dumb *args);
3081 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3082 uint32_t handle, uint64_t *offset);
3083 int i915_gem_mmap_gtt_version(void);
3085 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3086 struct drm_i915_gem_object *new,
3087 unsigned frontbuffer_bits);
3089 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3091 struct i915_request *
3092 i915_gem_find_active_request(struct intel_engine_cs *engine);
3094 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3096 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3099 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3101 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3104 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3106 return unlikely(test_bit(I915_WEDGED, &error->flags));
3109 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3111 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3114 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3116 return READ_ONCE(error->reset_count);
3119 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3120 struct intel_engine_cs *engine)
3122 return READ_ONCE(error->reset_engine_count[engine->id]);
3125 struct i915_request *
3126 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3127 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3128 void i915_gem_reset(struct drm_i915_private *dev_priv);
3129 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3130 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3131 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3132 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3133 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3134 struct i915_request *request);
3136 void i915_gem_init_mmio(struct drm_i915_private *i915);
3137 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3138 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3139 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3140 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3141 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3142 unsigned int flags);
3143 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3144 void i915_gem_resume(struct drm_i915_private *dev_priv);
3145 int i915_gem_fault(struct vm_fault *vmf);
3146 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3149 struct intel_rps_client *rps);
3150 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3153 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3156 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3158 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3160 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3161 struct i915_vma * __must_check
3162 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3164 const struct i915_ggtt_view *view,
3165 unsigned int flags);
3166 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3167 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3169 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3170 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3172 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3173 enum i915_cache_level cache_level);
3175 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3176 struct dma_buf *dma_buf);
3178 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3179 struct drm_gem_object *gem_obj, int flags);
3181 static inline struct i915_hw_ppgtt *
3182 i915_vm_to_ppgtt(struct i915_address_space *vm)
3184 return container_of(vm, struct i915_hw_ppgtt, base);
3187 /* i915_gem_fence_reg.c */
3188 struct drm_i915_fence_reg *
3189 i915_reserve_fence(struct drm_i915_private *dev_priv);
3190 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3192 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3193 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3195 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3196 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3197 struct sg_table *pages);
3198 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3199 struct sg_table *pages);
3201 static inline struct i915_gem_context *
3202 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3204 return idr_find(&file_priv->context_idr, id);
3207 static inline struct i915_gem_context *
3208 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3210 struct i915_gem_context *ctx;
3213 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3214 if (ctx && !kref_get_unless_zero(&ctx->ref))
3221 static inline struct intel_timeline *
3222 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3223 struct intel_engine_cs *engine)
3225 struct i915_address_space *vm;
3227 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3228 return &vm->timeline.engine[engine->id];
3231 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3232 struct drm_file *file);
3233 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3234 struct drm_file *file);
3235 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3236 struct drm_file *file);
3237 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3238 struct i915_gem_context *ctx,
3239 uint32_t *reg_state);
3241 /* i915_gem_evict.c */
3242 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3243 u64 min_size, u64 alignment,
3244 unsigned cache_level,
3247 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3248 struct drm_mm_node *node,
3249 unsigned int flags);
3250 int i915_gem_evict_vm(struct i915_address_space *vm);
3252 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3254 /* belongs in i915_gem_gtt.h */
3255 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3258 if (INTEL_GEN(dev_priv) < 6)
3259 intel_gtt_chipset_flush();
3262 /* i915_gem_stolen.c */
3263 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3264 struct drm_mm_node *node, u64 size,
3265 unsigned alignment);
3266 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3267 struct drm_mm_node *node, u64 size,
3268 unsigned alignment, u64 start,
3270 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3271 struct drm_mm_node *node);
3272 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3273 void i915_gem_cleanup_stolen(struct drm_device *dev);
3274 struct drm_i915_gem_object *
3275 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3276 resource_size_t size);
3277 struct drm_i915_gem_object *
3278 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3279 resource_size_t stolen_offset,
3280 resource_size_t gtt_offset,
3281 resource_size_t size);
3283 /* i915_gem_internal.c */
3284 struct drm_i915_gem_object *
3285 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3288 /* i915_gem_shrinker.c */
3289 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3290 unsigned long target,
3291 unsigned long *nr_scanned,
3293 #define I915_SHRINK_PURGEABLE 0x1
3294 #define I915_SHRINK_UNBOUND 0x2
3295 #define I915_SHRINK_BOUND 0x4
3296 #define I915_SHRINK_ACTIVE 0x8
3297 #define I915_SHRINK_VMAPS 0x10
3298 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3299 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3300 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3303 /* i915_gem_tiling.c */
3304 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3306 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3308 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3309 i915_gem_object_is_tiled(obj);
3312 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3313 unsigned int tiling, unsigned int stride);
3314 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3315 unsigned int tiling, unsigned int stride);
3317 /* i915_debugfs.c */
3318 #ifdef CONFIG_DEBUG_FS
3319 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3320 int i915_debugfs_connector_add(struct drm_connector *connector);
3321 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3323 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3324 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3326 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3329 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3331 /* i915_cmd_parser.c */
3332 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3333 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3334 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3335 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3336 struct drm_i915_gem_object *batch_obj,
3337 struct drm_i915_gem_object *shadow_batch_obj,
3338 u32 batch_start_offset,
3343 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3344 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3345 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3346 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3348 /* i915_suspend.c */
3349 extern int i915_save_state(struct drm_i915_private *dev_priv);
3350 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3353 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3354 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3356 /* intel_lpe_audio.c */
3357 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3358 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3359 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3360 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3361 enum pipe pipe, enum port port,
3362 const void *eld, int ls_clock, bool dp_output);
3365 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3366 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3367 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3369 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3371 extern struct i2c_adapter *
3372 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3373 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3374 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3375 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3377 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3379 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3382 void intel_bios_init(struct drm_i915_private *dev_priv);
3383 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3384 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3385 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3386 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3387 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3388 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3389 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3390 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3391 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3393 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3398 extern void intel_register_dsm_handler(void);
3399 extern void intel_unregister_dsm_handler(void);
3401 static inline void intel_register_dsm_handler(void) { return; }
3402 static inline void intel_unregister_dsm_handler(void) { return; }
3403 #endif /* CONFIG_ACPI */
3405 /* intel_device_info.c */
3406 static inline struct intel_device_info *
3407 mkwrite_device_info(struct drm_i915_private *dev_priv)
3409 return (struct intel_device_info *)&dev_priv->info;
3413 extern void intel_modeset_init_hw(struct drm_device *dev);
3414 extern int intel_modeset_init(struct drm_device *dev);
3415 extern void intel_modeset_cleanup(struct drm_device *dev);
3416 extern int intel_connector_register(struct drm_connector *);
3417 extern void intel_connector_unregister(struct drm_connector *);
3418 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3420 extern void intel_display_resume(struct drm_device *dev);
3421 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3422 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3423 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3424 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3425 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3426 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3429 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3430 struct drm_file *file);
3433 extern struct intel_overlay_error_state *
3434 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3435 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3436 struct intel_overlay_error_state *error);
3438 extern struct intel_display_error_state *
3439 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3440 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3441 struct intel_display_error_state *error);
3443 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3444 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3445 u32 val, int fast_timeout_us,
3446 int slow_timeout_ms);
3447 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3448 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3450 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3451 u32 reply_mask, u32 reply, int timeout_base_ms);
3453 /* intel_sideband.c */
3454 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3455 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3456 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3457 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3458 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3459 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3460 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3461 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3462 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3463 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3464 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3465 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3466 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3467 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3468 enum intel_sbi_destination destination);
3469 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3470 enum intel_sbi_destination destination);
3471 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3472 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3474 /* intel_dpio_phy.c */
3475 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3476 enum dpio_phy *phy, enum dpio_channel *ch);
3477 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3478 enum port port, u32 margin, u32 scale,
3479 u32 enable, u32 deemphasis);
3480 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3481 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3482 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3484 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3486 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3487 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3488 uint8_t lane_lat_optim_mask);
3489 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3491 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3492 u32 deemph_reg_value, u32 margin_reg_value,
3493 bool uniq_trans_scale);
3494 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3495 const struct intel_crtc_state *crtc_state,
3497 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3498 const struct intel_crtc_state *crtc_state);
3499 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3500 const struct intel_crtc_state *crtc_state);
3501 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3502 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3503 const struct intel_crtc_state *old_crtc_state);
3505 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3506 u32 demph_reg_value, u32 preemph_reg_value,
3507 u32 uniqtranscale_reg_value, u32 tx3_demph);
3508 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3509 const struct intel_crtc_state *crtc_state);
3510 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3511 const struct intel_crtc_state *crtc_state);
3512 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3513 const struct intel_crtc_state *old_crtc_state);
3515 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3516 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3517 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3518 const i915_reg_t reg);
3520 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3522 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3523 const i915_reg_t reg)
3525 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3528 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3529 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3531 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3532 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3533 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3534 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3536 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3537 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3538 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3539 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3541 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3542 * will be implemented using 2 32-bit writes in an arbitrary order with
3543 * an arbitrary delay between them. This can cause the hardware to
3544 * act upon the intermediate value, possibly leading to corruption and
3545 * machine death. For this reason we do not support I915_WRITE64, or
3546 * dev_priv->uncore.funcs.mmio_writeq.
3548 * When reading a 64-bit value as two 32-bit values, the delay may cause
3549 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3550 * occasionally a 64-bit register does not actualy support a full readq
3551 * and must be read using two 32-bit reads.
3553 * You have been warned.
3555 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3557 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3558 u32 upper, lower, old_upper, loop = 0; \
3559 upper = I915_READ(upper_reg); \
3561 old_upper = upper; \
3562 lower = I915_READ(lower_reg); \
3563 upper = I915_READ(upper_reg); \
3564 } while (upper != old_upper && loop++ < 2); \
3565 (u64)upper << 32 | lower; })
3567 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3568 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3570 #define __raw_read(x, s) \
3571 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3574 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3577 #define __raw_write(x, s) \
3578 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3579 i915_reg_t reg, uint##x##_t val) \
3581 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3596 /* These are untraced mmio-accessors that are only valid to be used inside
3597 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3600 * Think twice, and think again, before using these.
3602 * As an example, these accessors can possibly be used between:
3604 * spin_lock_irq(&dev_priv->uncore.lock);
3605 * intel_uncore_forcewake_get__locked();
3609 * intel_uncore_forcewake_put__locked();
3610 * spin_unlock_irq(&dev_priv->uncore.lock);
3613 * Note: some registers may not need forcewake held, so
3614 * intel_uncore_forcewake_{get,put} can be omitted, see
3615 * intel_uncore_forcewake_for_reg().
3617 * Certain architectures will die if the same cacheline is concurrently accessed
3618 * by different clients (e.g. on Ivybridge). Access to registers should
3619 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3620 * a more localised lock guarding all access to that bank of registers.
3622 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3623 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3624 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3625 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3627 /* "Broadcast RGB" property */
3628 #define INTEL_BROADCAST_RGB_AUTO 0
3629 #define INTEL_BROADCAST_RGB_FULL 1
3630 #define INTEL_BROADCAST_RGB_LIMITED 2
3632 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3634 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3635 return VLV_VGACNTRL;
3636 else if (INTEL_GEN(dev_priv) >= 5)
3637 return CPU_VGACNTRL;
3642 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3644 unsigned long j = msecs_to_jiffies(m);
3646 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3649 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3651 /* nsecs_to_jiffies64() does not guard against overflow */
3652 if (NSEC_PER_SEC % HZ &&
3653 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3654 return MAX_JIFFY_OFFSET;
3656 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3659 static inline unsigned long
3660 timespec_to_jiffies_timeout(const struct timespec *value)
3662 unsigned long j = timespec_to_jiffies(value);
3664 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3668 * If you need to wait X milliseconds between events A and B, but event B
3669 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3670 * when event A happened, then just before event B you call this function and
3671 * pass the timestamp as the first argument, and X as the second argument.
3674 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3676 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3679 * Don't re-read the value of "jiffies" every time since it may change
3680 * behind our back and break the math.
3682 tmp_jiffies = jiffies;
3683 target_jiffies = timestamp_jiffies +
3684 msecs_to_jiffies_timeout(to_wait_ms);
3686 if (time_after(target_jiffies, tmp_jiffies)) {
3687 remaining_jiffies = target_jiffies - tmp_jiffies;
3688 while (remaining_jiffies)
3690 schedule_timeout_uninterruptible(remaining_jiffies);
3695 __i915_request_irq_complete(const struct i915_request *rq)
3697 struct intel_engine_cs *engine = rq->engine;
3700 /* Note that the engine may have wrapped around the seqno, and
3701 * so our request->global_seqno will be ahead of the hardware,
3702 * even though it completed the request before wrapping. We catch
3703 * this by kicking all the waiters before resetting the seqno
3704 * in hardware, and also signal the fence.
3706 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3709 /* The request was dequeued before we were awoken. We check after
3710 * inspecting the hw to confirm that this was the same request
3711 * that generated the HWS update. The memory barriers within
3712 * the request execution are sufficient to ensure that a check
3713 * after reading the value from hw matches this request.
3715 seqno = i915_request_global_seqno(rq);
3719 /* Before we do the heavier coherent read of the seqno,
3720 * check the value (hopefully) in the CPU cacheline.
3722 if (__i915_request_completed(rq, seqno))
3725 /* Ensure our read of the seqno is coherent so that we
3726 * do not "miss an interrupt" (i.e. if this is the last
3727 * request and the seqno write from the GPU is not visible
3728 * by the time the interrupt fires, we will see that the
3729 * request is incomplete and go back to sleep awaiting
3730 * another interrupt that will never come.)
3732 * Strictly, we only need to do this once after an interrupt,
3733 * but it is easier and safer to do it every time the waiter
3736 if (engine->irq_seqno_barrier &&
3737 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3738 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3740 /* The ordering of irq_posted versus applying the barrier
3741 * is crucial. The clearing of the current irq_posted must
3742 * be visible before we perform the barrier operation,
3743 * such that if a subsequent interrupt arrives, irq_posted
3744 * is reasserted and our task rewoken (which causes us to
3745 * do another __i915_request_irq_complete() immediately
3746 * and reapply the barrier). Conversely, if the clear
3747 * occurs after the barrier, then an interrupt that arrived
3748 * whilst we waited on the barrier would not trigger a
3749 * barrier on the next pass, and the read may not see the
3752 engine->irq_seqno_barrier(engine);
3754 /* If we consume the irq, but we are no longer the bottom-half,
3755 * the real bottom-half may not have serialised their own
3756 * seqno check with the irq-barrier (i.e. may have inspected
3757 * the seqno before we believe it coherent since they see
3758 * irq_posted == false but we are still running).
3760 spin_lock_irq(&b->irq_lock);
3761 if (b->irq_wait && b->irq_wait->tsk != current)
3762 /* Note that if the bottom-half is changed as we
3763 * are sending the wake-up, the new bottom-half will
3764 * be woken by whomever made the change. We only have
3765 * to worry about when we steal the irq-posted for
3768 wake_up_process(b->irq_wait->tsk);
3769 spin_unlock_irq(&b->irq_lock);
3771 if (__i915_request_completed(rq, seqno))
3778 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3779 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3781 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3782 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3783 * perform the operation. To check beforehand, pass in the parameters to
3784 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3785 * you only need to pass in the minor offsets, page-aligned pointers are
3788 * For just checking for SSE4.1, in the foreknowledge that the future use
3789 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3791 #define i915_can_memcpy_from_wc(dst, src, len) \
3792 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3794 #define i915_has_memcpy_from_wc() \
3795 i915_memcpy_from_wc(NULL, NULL, 0)
3798 int remap_io_mapping(struct vm_area_struct *vma,
3799 unsigned long addr, unsigned long pfn, unsigned long size,
3800 struct io_mapping *iomap);
3802 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3804 if (INTEL_GEN(i915) >= 10)
3805 return CNL_HWS_CSB_WRITE_INDEX;
3807 return I915_HWS_CSB_WRITE_INDEX;