1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 #include <linux/backlight.h>
41 /* General customization:
44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46 #define DRIVER_NAME "i915"
47 #define DRIVER_DESC "Intel Graphics"
48 #define DRIVER_DATE "20080730"
56 #define pipe_name(p) ((p) + 'A')
63 #define plane_name(p) ((p) + 'A')
65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
79 #define DRIVER_MAJOR 1
80 #define DRIVER_MINOR 6
81 #define DRIVER_PATCHLEVEL 0
83 #define WATCH_COHERENCY 0
86 #define I915_GEM_PHYS_CURSOR_0 1
87 #define I915_GEM_PHYS_CURSOR_1 2
88 #define I915_GEM_PHYS_OVERLAY_REGS 3
89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91 struct drm_i915_gem_phys_object {
93 struct page **page_list;
94 drm_dma_handle_t *handle;
95 struct drm_i915_gem_object *cur_obj;
99 struct mem_block *next;
100 struct mem_block *prev;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
110 struct drm_i915_private;
112 struct intel_opregion {
113 struct opregion_header *header;
114 struct opregion_acpi *acpi;
115 struct opregion_swsci *swsci;
116 struct opregion_asle *asle;
118 u32 __iomem *lid_state;
120 #define OPREGION_SIZE (8*1024)
122 struct intel_overlay;
123 struct intel_overlay_error_state;
125 struct drm_i915_master_private {
126 drm_local_map_t *sarea;
127 struct _drm_i915_sarea *sarea_priv;
129 #define I915_FENCE_REG_NONE -1
130 #define I915_MAX_NUM_FENCES 16
131 /* 16 fences + sign bit for FENCE_REG_NONE */
132 #define I915_MAX_NUM_FENCE_BITS 5
134 struct drm_i915_fence_reg {
135 struct list_head lru_list;
136 struct drm_i915_gem_object *obj;
137 uint32_t setup_seqno;
141 struct sdvo_device_mapping {
150 struct intel_display_error_state;
152 struct drm_i915_error_state {
155 u32 pipestat[I915_MAX_PIPES];
156 u32 tail[I915_NUM_RINGS];
157 u32 head[I915_NUM_RINGS];
158 u32 ipeir[I915_NUM_RINGS];
159 u32 ipehr[I915_NUM_RINGS];
160 u32 instdone[I915_NUM_RINGS];
161 u32 acthd[I915_NUM_RINGS];
162 u32 error; /* gen6+ */
163 u32 instpm[I915_NUM_RINGS];
164 u32 instps[I915_NUM_RINGS];
166 u32 seqno[I915_NUM_RINGS];
168 u32 faddr[I915_NUM_RINGS];
169 u64 fence[I915_MAX_NUM_FENCES];
171 struct drm_i915_error_object {
175 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
176 struct drm_i915_error_buffer {
183 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
190 } *active_bo, *pinned_bo;
191 u32 active_bo_count, pinned_bo_count;
192 struct intel_overlay_error_state *overlay;
193 struct intel_display_error_state *display;
196 struct drm_i915_display_funcs {
197 void (*dpms)(struct drm_crtc *crtc, int mode);
198 bool (*fbc_enabled)(struct drm_device *dev);
199 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
200 void (*disable_fbc)(struct drm_device *dev);
201 int (*get_display_clock_speed)(struct drm_device *dev);
202 int (*get_fifo_size)(struct drm_device *dev, int plane);
203 void (*update_wm)(struct drm_device *dev);
204 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
205 uint32_t sprite_width, int pixel_size);
206 int (*crtc_mode_set)(struct drm_crtc *crtc,
207 struct drm_display_mode *mode,
208 struct drm_display_mode *adjusted_mode,
210 struct drm_framebuffer *old_fb);
211 void (*write_eld)(struct drm_connector *connector,
212 struct drm_crtc *crtc);
213 void (*fdi_link_train)(struct drm_crtc *crtc);
214 void (*init_clock_gating)(struct drm_device *dev);
215 void (*init_pch_clock_gating)(struct drm_device *dev);
216 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
217 struct drm_framebuffer *fb,
218 struct drm_i915_gem_object *obj);
219 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
221 void (*force_wake_get)(struct drm_i915_private *dev_priv);
222 void (*force_wake_put)(struct drm_i915_private *dev_priv);
223 /* clock updates for mode set */
225 /* render clock increase/decrease */
226 /* display clock increase/decrease */
227 /* pll clock increase/decrease */
230 struct intel_device_info {
246 u8 cursor_needs_physical:1;
248 u8 overlay_needs_physical:1;
256 FBC_NO_OUTPUT, /* no outputs enabled to compress */
257 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
258 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
259 FBC_MODE_TOO_LARGE, /* mode too large for compression */
260 FBC_BAD_PLANE, /* fbc not supported on plane */
261 FBC_NOT_TILED, /* buffer not tiled */
262 FBC_MULTIPLE_PIPES, /* more than one pipe active */
267 PCH_IBX, /* Ibexpeak PCH */
268 PCH_CPT, /* Cougarpoint PCH */
271 #define QUIRK_PIPEA_FORCE (1<<0)
272 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
275 struct intel_fbc_work;
277 typedef struct drm_i915_private {
278 struct drm_device *dev;
280 const struct intel_device_info *info;
283 int relative_constants_mode;
289 struct i2c_adapter adapter;
290 struct i2c_adapter *force_bit;
294 struct pci_dev *bridge_dev;
295 struct intel_ring_buffer ring[I915_NUM_RINGS];
298 drm_dma_handle_t *status_page_dmah;
300 drm_local_map_t hws_map;
301 struct drm_i915_gem_object *pwrctx;
302 struct drm_i915_gem_object *renderctx;
304 struct resource mch_res;
312 atomic_t irq_received;
314 /* protects the irq masks */
316 /** Cached value of IMR to avoid reads in updating the bitfield */
322 u32 hotplug_supported_mask;
323 struct work_struct hotplug_work;
325 int tex_lru_log_granularity;
326 int allow_batchbuffer;
327 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
331 /* For hangcheck timer */
332 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
333 struct timer_list hangcheck_timer;
336 uint32_t last_acthd_bsd;
337 uint32_t last_acthd_blt;
338 uint32_t last_instdone;
339 uint32_t last_instdone1;
341 unsigned long cfb_size;
343 enum plane cfb_plane;
345 struct intel_fbc_work *fbc_work;
347 struct intel_opregion opregion;
350 struct intel_overlay *overlay;
351 bool sprite_scaling_enabled;
354 int backlight_level; /* restore backlight to this value */
355 bool backlight_enabled;
356 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
357 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
359 /* Feature bits from the VBIOS */
360 unsigned int int_tv_support:1;
361 unsigned int lvds_dither:1;
362 unsigned int lvds_vbt:1;
363 unsigned int int_crt_support:1;
364 unsigned int lvds_use_ssc:1;
365 unsigned int display_clock_mode:1;
376 struct edp_power_seq pps;
378 bool no_aux_handshake;
380 struct notifier_block lid_notifier;
383 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
384 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
385 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
387 unsigned int fsb_freq, mem_freq, is_ddr3;
389 spinlock_t error_lock;
390 struct drm_i915_error_state *first_error;
391 struct work_struct error_work;
392 struct completion error_completion;
393 struct workqueue_struct *wq;
395 /* Display functions */
396 struct drm_i915_display_funcs display;
398 /* PCH chipset type */
399 enum intel_pch pch_type;
401 unsigned long quirks;
426 u32 saveTRANS_HTOTAL_A;
427 u32 saveTRANS_HBLANK_A;
428 u32 saveTRANS_HSYNC_A;
429 u32 saveTRANS_VTOTAL_A;
430 u32 saveTRANS_VBLANK_A;
431 u32 saveTRANS_VSYNC_A;
439 u32 savePFIT_PGM_RATIOS;
440 u32 saveBLC_HIST_CTL;
442 u32 saveBLC_PWM_CTL2;
443 u32 saveBLC_CPU_PWM_CTL;
444 u32 saveBLC_CPU_PWM_CTL2;
457 u32 saveTRANS_HTOTAL_B;
458 u32 saveTRANS_HBLANK_B;
459 u32 saveTRANS_HSYNC_B;
460 u32 saveTRANS_VTOTAL_B;
461 u32 saveTRANS_VBLANK_B;
462 u32 saveTRANS_VSYNC_B;
476 u32 savePP_ON_DELAYS;
477 u32 savePP_OFF_DELAYS;
485 u32 savePFIT_CONTROL;
486 u32 save_palette_a[256];
487 u32 save_palette_b[256];
488 u32 saveDPFC_CB_BASE;
489 u32 saveFBC_CFB_BASE;
492 u32 saveFBC_CONTROL2;
502 u32 saveCACHE_MODE_0;
503 u32 saveMI_ARB_STATE;
514 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
525 u32 savePIPEA_GMCH_DATA_M;
526 u32 savePIPEB_GMCH_DATA_M;
527 u32 savePIPEA_GMCH_DATA_N;
528 u32 savePIPEB_GMCH_DATA_N;
529 u32 savePIPEA_DP_LINK_M;
530 u32 savePIPEB_DP_LINK_M;
531 u32 savePIPEA_DP_LINK_N;
532 u32 savePIPEB_DP_LINK_N;
543 u32 savePCH_DREF_CONTROL;
544 u32 saveDISP_ARB_CTL;
545 u32 savePIPEA_DATA_M1;
546 u32 savePIPEA_DATA_N1;
547 u32 savePIPEA_LINK_M1;
548 u32 savePIPEA_LINK_N1;
549 u32 savePIPEB_DATA_M1;
550 u32 savePIPEB_DATA_N1;
551 u32 savePIPEB_LINK_M1;
552 u32 savePIPEB_LINK_N1;
553 u32 saveMCHBAR_RENDER_STANDBY;
554 u32 savePCH_PORT_HOTPLUG;
557 /** Bridge to intel-gtt-ko */
558 const struct intel_gtt *gtt;
559 /** Memory allocator for GTT stolen memory */
560 struct drm_mm stolen;
561 /** Memory allocator for GTT */
562 struct drm_mm gtt_space;
563 /** List of all objects in gtt_space. Used to restore gtt
564 * mappings on resume */
565 struct list_head gtt_list;
567 /** Usable portion of the GTT for GEM */
568 unsigned long gtt_start;
569 unsigned long gtt_mappable_end;
570 unsigned long gtt_end;
572 struct io_mapping *gtt_mapping;
575 struct shrinker inactive_shrinker;
578 * List of objects currently involved in rendering.
580 * Includes buffers having the contents of their GPU caches
581 * flushed, not necessarily primitives. last_rendering_seqno
582 * represents when the rendering involved will be completed.
584 * A reference is held on the buffer while on this list.
586 struct list_head active_list;
589 * List of objects which are not in the ringbuffer but which
590 * still have a write_domain which needs to be flushed before
593 * last_rendering_seqno is 0 while an object is in this list.
595 * A reference is held on the buffer while on this list.
597 struct list_head flushing_list;
600 * LRU list of objects which are not in the ringbuffer and
601 * are ready to unbind, but are still in the GTT.
603 * last_rendering_seqno is 0 while an object is in this list.
605 * A reference is not held on the buffer while on this list,
606 * as merely being GTT-bound shouldn't prevent its being
607 * freed, and we'll pull it off the list in the free path.
609 struct list_head inactive_list;
612 * LRU list of objects which are not in the ringbuffer but
613 * are still pinned in the GTT.
615 struct list_head pinned_list;
617 /** LRU list of objects with fence regs on them. */
618 struct list_head fence_list;
621 * List of objects currently pending being freed.
623 * These objects are no longer in use, but due to a signal
624 * we were prevented from freeing them at the appointed time.
626 struct list_head deferred_free_list;
629 * We leave the user IRQ off as much as possible,
630 * but this means that requests will finish and never
631 * be retired once the system goes idle. Set a timer to
632 * fire periodically while the ring is running. When it
633 * fires, go retire requests.
635 struct delayed_work retire_work;
638 * Are we in a non-interruptible section of code like
644 * Flag if the X Server, and thus DRM, is not currently in
645 * control of the device.
647 * This is set between LeaveVT and EnterVT. It needs to be
648 * replaced with a semaphore. It also needs to be
649 * transitioned away from for kernel modesetting.
654 * Flag if the hardware appears to be wedged.
656 * This is set when attempts to idle the device timeout.
657 * It prevents command submission from occurring and makes
658 * every pending request fail
662 /** Bit 6 swizzling required for X tiling */
663 uint32_t bit_6_swizzle_x;
664 /** Bit 6 swizzling required for Y tiling */
665 uint32_t bit_6_swizzle_y;
667 /* storage for physical objects */
668 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
670 /* accounting, useful for userland debugging */
672 size_t mappable_gtt_total;
673 size_t object_memory;
676 struct sdvo_device_mapping sdvo_mappings[2];
677 /* indicate whether the LVDS_BORDER should be enabled or not */
678 unsigned int lvds_border_bits;
679 /* Panel fitter placement and size for Ironlake+ */
680 u32 pch_pf_pos, pch_pf_size;
682 struct drm_crtc *plane_to_crtc_mapping[3];
683 struct drm_crtc *pipe_to_crtc_mapping[3];
684 wait_queue_head_t pending_flip_queue;
685 bool flip_pending_is_done;
687 /* Reclocking support */
688 bool render_reclock_avail;
689 bool lvds_downclock_avail;
690 /* indicates the reduced downclock for LVDS*/
692 struct work_struct idle_work;
693 struct timer_list idle_timer;
697 struct child_device_config *child_dev;
698 struct drm_connector *int_lvds_connector;
699 struct drm_connector *int_edp_connector;
701 bool mchbar_need_disable;
703 struct work_struct rps_work;
714 unsigned long last_time1;
715 unsigned long chipset_power;
717 struct timespec last_time2;
718 unsigned long gfx_power;
722 spinlock_t *mchdev_lock;
724 enum no_fbc_reason no_fbc_reason;
726 struct drm_mm_node *compressed_fb;
727 struct drm_mm_node *compressed_llb;
729 unsigned long last_gpu_reset;
731 /* list of fbdev register on this device */
732 struct intel_fbdev *fbdev;
734 struct backlight_device *backlight;
736 struct drm_property *broadcast_rgb_property;
737 struct drm_property *force_audio_property;
739 atomic_t forcewake_count;
740 } drm_i915_private_t;
742 enum i915_cache_level {
745 I915_CACHE_LLC_MLC, /* gen6+ */
748 struct drm_i915_gem_object {
749 struct drm_gem_object base;
751 /** Current space allocated to this object in the GTT, if any. */
752 struct drm_mm_node *gtt_space;
753 struct list_head gtt_list;
755 /** This object's place on the active/flushing/inactive lists */
756 struct list_head ring_list;
757 struct list_head mm_list;
758 /** This object's place on GPU write list */
759 struct list_head gpu_write_list;
760 /** This object's place in the batchbuffer or on the eviction list */
761 struct list_head exec_list;
764 * This is set if the object is on the active or flushing lists
765 * (has pending rendering), and is not set if it's on inactive (ready
768 unsigned int active:1;
771 * This is set if the object has been written to since last bound
774 unsigned int dirty:1;
777 * This is set if the object has been written to since the last
780 unsigned int pending_gpu_write:1;
783 * Fence register bits (if any) for this object. Will be set
784 * as needed when mapped into the GTT.
785 * Protected by dev->struct_mutex.
787 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
790 * Advice: are the backing pages purgeable?
795 * Current tiling mode for the object.
797 unsigned int tiling_mode:2;
798 unsigned int tiling_changed:1;
800 /** How many users have pinned this object in GTT space. The following
801 * users can each hold at most one reference: pwrite/pread, pin_ioctl
802 * (via user_pin_count), execbuffer (objects are not allowed multiple
803 * times for the same batchbuffer), and the framebuffer code. When
804 * switching/pageflipping, the framebuffer code has at most two buffers
807 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
808 * bits with absolutely no headroom. So use 4 bits. */
809 unsigned int pin_count:4;
810 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
813 * Is the object at the current location in the gtt mappable and
814 * fenceable? Used to avoid costly recalculations.
816 unsigned int map_and_fenceable:1;
819 * Whether the current gtt mapping needs to be mappable (and isn't just
820 * mappable by accident). Track pin and fault separate for a more
821 * accurate mappable working set.
823 unsigned int fault_mappable:1;
824 unsigned int pin_mappable:1;
827 * Is the GPU currently using a fence to access this buffer,
829 unsigned int pending_fenced_gpu_access:1;
830 unsigned int fenced_gpu_access:1;
832 unsigned int cache_level:2;
839 struct scatterlist *sg_list;
843 * Used for performing relocations during execbuffer insertion.
845 struct hlist_node exec_node;
846 unsigned long exec_handle;
847 struct drm_i915_gem_exec_object2 *exec_entry;
850 * Current offset of the object in GTT space.
852 * This is the same as gtt_space->start
856 /** Breadcrumb of last rendering to the buffer. */
857 uint32_t last_rendering_seqno;
858 struct intel_ring_buffer *ring;
860 /** Breadcrumb of last fenced GPU access to the buffer. */
861 uint32_t last_fenced_seqno;
862 struct intel_ring_buffer *last_fenced_ring;
864 /** Current tiling stride for the object, if it's tiled. */
867 /** Record of address bit 17 of each page at last unbind. */
868 unsigned long *bit_17;
872 * If present, while GEM_DOMAIN_CPU is in the read domain this array
873 * flags which individual pages are valid.
875 uint8_t *page_cpu_valid;
877 /** User space pin count and filp owning the pin */
878 uint32_t user_pin_count;
879 struct drm_file *pin_filp;
881 /** for phy allocated objects */
882 struct drm_i915_gem_phys_object *phys_obj;
885 * Number of crtcs where this object is currently the fb, but
886 * will be page flipped away on the next vblank. When it
887 * reaches 0, dev_priv->pending_flip_queue will be woken up.
889 atomic_t pending_flip;
892 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
895 * Request queue structure.
897 * The request queue allows us to note sequence numbers that have been emitted
898 * and may be associated with active buffers to be retired.
900 * By keeping this list, we can avoid having to do questionable
901 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
902 * an emission time with seqnos for tracking how far ahead of the GPU we are.
904 struct drm_i915_gem_request {
905 /** On Which ring this request was generated */
906 struct intel_ring_buffer *ring;
908 /** GEM sequence number associated with this request. */
911 /** Time at which this request was emitted, in jiffies. */
912 unsigned long emitted_jiffies;
914 /** global list entry for this request */
915 struct list_head list;
917 struct drm_i915_file_private *file_priv;
918 /** file_priv list entry for this request */
919 struct list_head client_list;
922 struct drm_i915_file_private {
924 struct spinlock lock;
925 struct list_head request_list;
929 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
931 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
932 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
933 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
934 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
935 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
936 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
937 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
938 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
939 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
940 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
941 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
942 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
943 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
944 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
945 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
946 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
947 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
948 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
949 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
950 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
953 * The genX designation typically refers to the render engine, so render
954 * capability related checks should use IS_GEN, while display and other checks
955 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
958 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
959 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
960 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
961 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
962 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
963 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
965 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
966 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
967 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
968 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
970 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
971 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
973 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
974 * rows, which changed the alignment requirements and fence programming.
976 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
978 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
979 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
980 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
981 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
982 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
983 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
984 /* dsparb controlled by hw only */
985 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
987 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
988 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
989 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
991 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
992 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
994 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
995 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
996 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
998 #include "i915_trace.h"
1000 extern struct drm_ioctl_desc i915_ioctls[];
1001 extern int i915_max_ioctl;
1002 extern unsigned int i915_fbpercrtc __always_unused;
1003 extern int i915_panel_ignore_lid __read_mostly;
1004 extern unsigned int i915_powersave __read_mostly;
1005 extern int i915_semaphores __read_mostly;
1006 extern unsigned int i915_lvds_downclock __read_mostly;
1007 extern int i915_panel_use_ssc __read_mostly;
1008 extern int i915_vbt_sdvo_panel_type __read_mostly;
1009 extern int i915_enable_rc6 __read_mostly;
1010 extern int i915_enable_fbc __read_mostly;
1011 extern bool i915_enable_hangcheck __read_mostly;
1013 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1014 extern int i915_resume(struct drm_device *dev);
1015 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1016 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1019 extern void i915_kernel_lost_context(struct drm_device * dev);
1020 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1021 extern int i915_driver_unload(struct drm_device *);
1022 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1023 extern void i915_driver_lastclose(struct drm_device * dev);
1024 extern void i915_driver_preclose(struct drm_device *dev,
1025 struct drm_file *file_priv);
1026 extern void i915_driver_postclose(struct drm_device *dev,
1027 struct drm_file *file_priv);
1028 extern int i915_driver_device_is_agp(struct drm_device * dev);
1029 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1031 extern int i915_emit_box(struct drm_device *dev,
1032 struct drm_clip_rect *box,
1034 extern int i915_reset(struct drm_device *dev, u8 flags);
1035 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1036 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1037 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1038 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1042 void i915_hangcheck_elapsed(unsigned long data);
1043 void i915_handle_error(struct drm_device *dev, bool wedged);
1044 extern int i915_irq_emit(struct drm_device *dev, void *data,
1045 struct drm_file *file_priv);
1046 extern int i915_irq_wait(struct drm_device *dev, void *data,
1047 struct drm_file *file_priv);
1049 extern void intel_irq_init(struct drm_device *dev);
1051 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1052 struct drm_file *file_priv);
1053 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1054 struct drm_file *file_priv);
1055 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1056 struct drm_file *file_priv);
1059 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1062 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1064 void intel_enable_asle(struct drm_device *dev);
1066 #ifdef CONFIG_DEBUG_FS
1067 extern void i915_destroy_error_state(struct drm_device *dev);
1069 #define i915_destroy_error_state(x)
1074 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv);
1076 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv);
1078 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv);
1080 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv);
1082 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1083 struct drm_file *file_priv);
1084 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1085 struct drm_file *file_priv);
1086 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1087 struct drm_file *file_priv);
1088 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv);
1094 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv);
1096 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1097 struct drm_file *file_priv);
1098 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv);
1100 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv);
1102 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv);
1104 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1105 struct drm_file *file_priv);
1106 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1107 struct drm_file *file_priv);
1108 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1109 struct drm_file *file_priv);
1110 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1111 struct drm_file *file_priv);
1112 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv);
1114 void i915_gem_load(struct drm_device *dev);
1115 int i915_gem_init_object(struct drm_gem_object *obj);
1116 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1117 uint32_t invalidate_domains,
1118 uint32_t flush_domains);
1119 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1121 void i915_gem_free_object(struct drm_gem_object *obj);
1122 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1124 bool map_and_fenceable);
1125 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1126 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1127 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1128 void i915_gem_lastclose(struct drm_device *dev);
1130 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1131 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1132 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1133 struct intel_ring_buffer *ring,
1136 int i915_gem_dumb_create(struct drm_file *file_priv,
1137 struct drm_device *dev,
1138 struct drm_mode_create_dumb *args);
1139 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1140 uint32_t handle, uint64_t *offset);
1141 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1144 * Returns true if seq1 is later than seq2.
1147 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1149 return (int32_t)(seq1 - seq2) >= 0;
1153 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1155 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1156 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1159 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1160 struct intel_ring_buffer *pipelined);
1161 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1164 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1166 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1167 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1168 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1173 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1175 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1176 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1177 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1181 void i915_gem_retire_requests(struct drm_device *dev);
1182 void i915_gem_reset(struct drm_device *dev);
1183 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1184 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1185 uint32_t read_domains,
1186 uint32_t write_domain);
1187 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1188 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1189 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1190 void i915_gem_do_init(struct drm_device *dev,
1191 unsigned long start,
1192 unsigned long mappable_end,
1194 int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire);
1195 int __must_check i915_gem_idle(struct drm_device *dev);
1196 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1197 struct drm_file *file,
1198 struct drm_i915_gem_request *request);
1199 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1202 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1204 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1207 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1209 struct intel_ring_buffer *pipelined);
1210 int i915_gem_attach_phys_object(struct drm_device *dev,
1211 struct drm_i915_gem_object *obj,
1214 void i915_gem_detach_phys_object(struct drm_device *dev,
1215 struct drm_i915_gem_object *obj);
1216 void i915_gem_free_all_phys_object(struct drm_device *dev);
1217 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1220 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1224 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1225 enum i915_cache_level cache_level);
1227 /* i915_gem_gtt.c */
1228 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1229 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1230 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1231 enum i915_cache_level cache_level);
1232 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1234 /* i915_gem_evict.c */
1235 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1236 unsigned alignment, bool mappable);
1237 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1238 bool purgeable_only);
1239 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1240 bool purgeable_only);
1242 /* i915_gem_tiling.c */
1243 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1244 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1245 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1247 /* i915_gem_debug.c */
1248 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1249 const char *where, uint32_t mark);
1251 int i915_verify_lists(struct drm_device *dev);
1253 #define i915_verify_lists(dev) 0
1255 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1257 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1258 const char *where, uint32_t mark);
1260 /* i915_debugfs.c */
1261 int i915_debugfs_init(struct drm_minor *minor);
1262 void i915_debugfs_cleanup(struct drm_minor *minor);
1264 /* i915_suspend.c */
1265 extern int i915_save_state(struct drm_device *dev);
1266 extern int i915_restore_state(struct drm_device *dev);
1268 /* i915_suspend.c */
1269 extern int i915_save_state(struct drm_device *dev);
1270 extern int i915_restore_state(struct drm_device *dev);
1273 extern int intel_setup_gmbus(struct drm_device *dev);
1274 extern void intel_teardown_gmbus(struct drm_device *dev);
1275 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1276 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1277 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1279 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1281 extern void intel_i2c_reset(struct drm_device *dev);
1283 /* intel_opregion.c */
1284 extern int intel_opregion_setup(struct drm_device *dev);
1286 extern void intel_opregion_init(struct drm_device *dev);
1287 extern void intel_opregion_fini(struct drm_device *dev);
1288 extern void intel_opregion_asle_intr(struct drm_device *dev);
1289 extern void intel_opregion_gse_intr(struct drm_device *dev);
1290 extern void intel_opregion_enable_asle(struct drm_device *dev);
1292 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1293 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1294 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1295 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1296 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1301 extern void intel_register_dsm_handler(void);
1302 extern void intel_unregister_dsm_handler(void);
1304 static inline void intel_register_dsm_handler(void) { return; }
1305 static inline void intel_unregister_dsm_handler(void) { return; }
1306 #endif /* CONFIG_ACPI */
1309 extern void intel_modeset_init(struct drm_device *dev);
1310 extern void intel_modeset_gem_init(struct drm_device *dev);
1311 extern void intel_modeset_cleanup(struct drm_device *dev);
1312 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1313 extern bool intel_fbc_enabled(struct drm_device *dev);
1314 extern void intel_disable_fbc(struct drm_device *dev);
1315 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1316 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1317 extern void ironlake_enable_rc6(struct drm_device *dev);
1318 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1319 extern void intel_detect_pch(struct drm_device *dev);
1320 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1322 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1323 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1324 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1325 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1328 #ifdef CONFIG_DEBUG_FS
1329 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1330 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1332 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1333 extern void intel_display_print_error_state(struct seq_file *m,
1334 struct drm_device *dev,
1335 struct intel_display_error_state *error);
1338 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1340 #define BEGIN_LP_RING(n) \
1341 intel_ring_begin(LP_RING(dev_priv), (n))
1343 #define OUT_RING(x) \
1344 intel_ring_emit(LP_RING(dev_priv), x)
1346 #define ADVANCE_LP_RING() \
1347 intel_ring_advance(LP_RING(dev_priv))
1350 * Lock test for when it's just for synchronization of ring access.
1352 * In that case, we don't need to do it when GEM is initialized as nobody else
1353 * has access to the ring.
1355 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1356 if (LP_RING(dev->dev_private)->obj == NULL) \
1357 LOCK_TEST_WITH_RETURN(dev, file); \
1360 /* On SNB platform, before reading ring registers forcewake bit
1361 * must be set to prevent GT core from power down and stale values being
1364 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1365 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1366 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1368 /* We give fast paths for the really cool registers */
1369 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1370 (((dev_priv)->info->gen >= 6) && \
1371 ((reg) < 0x40000) && \
1372 ((reg) != FORCEWAKE))
1374 #define __i915_read(x, y) \
1375 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1383 #define __i915_write(x, y) \
1384 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1392 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1393 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1395 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1396 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1397 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1398 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1400 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1401 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1402 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1403 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1405 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1406 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1408 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1409 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)