1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
56 #include "i915_params.h"
58 #include "i915_utils.h"
60 #include "intel_bios.h"
61 #include "intel_device_info.h"
62 #include "intel_display.h"
63 #include "intel_dpll_mgr.h"
64 #include "intel_lrc.h"
65 #include "intel_opregion.h"
66 #include "intel_ringbuffer.h"
67 #include "intel_uncore.h"
68 #include "intel_wopcm.h"
72 #include "i915_gem_context.h"
73 #include "i915_gem_fence_reg.h"
74 #include "i915_gem_object.h"
75 #include "i915_gem_gtt.h"
76 #include "i915_gpu_error.h"
77 #include "i915_request.h"
78 #include "i915_scheduler.h"
79 #include "i915_timeline.h"
82 #include "intel_gvt.h"
84 /* General customization:
87 #define DRIVER_NAME "i915"
88 #define DRIVER_DESC "Intel Graphics"
89 #define DRIVER_DATE "20180620"
90 #define DRIVER_TIMESTAMP 1529529048
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915_modparams.verbose_state_checks, format)) \
104 unlikely(__ret_warn_on); \
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
112 bool __i915_inject_load_failure(const char *func, int line);
113 #define i915_inject_load_failure() \
114 __i915_inject_load_failure(__func__, __LINE__)
116 bool i915_error_injected(void);
120 #define i915_inject_load_failure() false
121 #define i915_error_injected() false
125 #define i915_load_error(i915, fmt, ...) \
126 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
131 } uint_fixed_16_16_t;
133 #define FP_16_16_MAX ({ \
134 uint_fixed_16_16_t fp; \
139 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
146 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
148 uint_fixed_16_16_t fp;
150 WARN_ON(val > U16_MAX);
156 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
158 return DIV_ROUND_UP(fp.val, 1 << 16);
161 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
166 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
167 uint_fixed_16_16_t min2)
169 uint_fixed_16_16_t min;
171 min.val = min(min1.val, min2.val);
175 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
176 uint_fixed_16_16_t max2)
178 uint_fixed_16_16_t max;
180 max.val = max(max1.val, max2.val);
184 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
186 uint_fixed_16_16_t fp;
187 WARN_ON(val > U32_MAX);
188 fp.val = (uint32_t) val;
192 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
193 uint_fixed_16_16_t d)
195 return DIV_ROUND_UP(val.val, d.val);
198 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
199 uint_fixed_16_16_t mul)
201 uint64_t intermediate_val;
203 intermediate_val = (uint64_t) val * mul.val;
204 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
205 WARN_ON(intermediate_val > U32_MAX);
206 return (uint32_t) intermediate_val;
209 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
210 uint_fixed_16_16_t mul)
212 uint64_t intermediate_val;
214 intermediate_val = (uint64_t) val.val * mul.val;
215 intermediate_val = intermediate_val >> 16;
216 return clamp_u64_to_fixed16(intermediate_val);
219 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
223 interm_val = (uint64_t)val << 16;
224 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
225 return clamp_u64_to_fixed16(interm_val);
228 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
229 uint_fixed_16_16_t d)
233 interm_val = (uint64_t)val << 16;
234 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
235 WARN_ON(interm_val > U32_MAX);
236 return (uint32_t) interm_val;
239 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
240 uint_fixed_16_16_t mul)
242 uint64_t intermediate_val;
244 intermediate_val = (uint64_t) val * mul.val;
245 return clamp_u64_to_fixed16(intermediate_val);
248 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
249 uint_fixed_16_16_t add2)
253 interm_sum = (uint64_t) add1.val + add2.val;
254 return clamp_u64_to_fixed16(interm_sum);
257 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
261 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
263 interm_sum = (uint64_t) add1.val + interm_add2.val;
264 return clamp_u64_to_fixed16(interm_sum);
269 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
282 #define for_each_hpd_pin(__pin) \
283 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
285 #define HPD_STORM_DEFAULT_THRESHOLD 5
287 struct i915_hotplug {
288 struct work_struct hotplug_work;
291 unsigned long last_jiffies;
296 HPD_MARK_DISABLED = 2
298 } stats[HPD_NUM_PINS];
300 struct delayed_work reenable_work;
302 struct intel_digital_port *irq_port[I915_MAX_PORTS];
305 struct work_struct dig_port_work;
307 struct work_struct poll_init_work;
310 unsigned int hpd_storm_threshold;
313 * if we get a HPD irq from DP and a HPD irq from non-DP
314 * the non-DP HPD could block the workqueue on a mode config
315 * mutex getting, that userspace may have taken. However
316 * userspace is waiting on the DP workqueue to run which is
317 * blocked behind the non-DP one.
319 struct workqueue_struct *dp_wq;
322 #define I915_GEM_GPU_DOMAINS \
323 (I915_GEM_DOMAIN_RENDER | \
324 I915_GEM_DOMAIN_SAMPLER | \
325 I915_GEM_DOMAIN_COMMAND | \
326 I915_GEM_DOMAIN_INSTRUCTION | \
327 I915_GEM_DOMAIN_VERTEX)
329 struct drm_i915_private;
330 struct i915_mm_struct;
331 struct i915_mmu_object;
333 struct drm_i915_file_private {
334 struct drm_i915_private *dev_priv;
335 struct drm_file *file;
339 struct list_head request_list;
340 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
341 * chosen to prevent the CPU getting more than a frame ahead of the GPU
342 * (when using lax throttling for the frontbuffer). We also use it to
343 * offer free GPU waitboosts for severely congested workloads.
345 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
347 struct idr context_idr;
349 struct intel_rps_client {
353 unsigned int bsd_engine;
356 * Every context ban increments per client ban score. Also
357 * hangs in short succession increments ban score. If ban threshold
358 * is reached, client is considered banned and submitting more work
359 * will fail. This is a stop gap measure to limit the badly behaving
360 * clients access to gpu. Note that unbannable contexts never increment
361 * the client ban score.
363 #define I915_CLIENT_SCORE_HANG_FAST 1
364 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
365 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
366 #define I915_CLIENT_SCORE_BANNED 9
367 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
369 unsigned long hang_timestamp;
372 /* Interface history:
375 * 1.2: Add Power Management
376 * 1.3: Add vblank support
377 * 1.4: Fix cmdbuffer path, add heap destroy
378 * 1.5: Add vblank pipe configuration
379 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
380 * - Support vertical blank on secondary display pipe
382 #define DRIVER_MAJOR 1
383 #define DRIVER_MINOR 6
384 #define DRIVER_PATCHLEVEL 0
386 struct intel_overlay;
387 struct intel_overlay_error_state;
389 struct sdvo_device_mapping {
398 struct intel_connector;
399 struct intel_encoder;
400 struct intel_atomic_state;
401 struct intel_crtc_state;
402 struct intel_initial_plane_config;
406 struct intel_cdclk_state;
408 struct drm_i915_display_funcs {
409 void (*get_cdclk)(struct drm_i915_private *dev_priv,
410 struct intel_cdclk_state *cdclk_state);
411 void (*set_cdclk)(struct drm_i915_private *dev_priv,
412 const struct intel_cdclk_state *cdclk_state);
413 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
414 enum i9xx_plane_id i9xx_plane);
415 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
416 int (*compute_intermediate_wm)(struct drm_device *dev,
417 struct intel_crtc *intel_crtc,
418 struct intel_crtc_state *newstate);
419 void (*initial_watermarks)(struct intel_atomic_state *state,
420 struct intel_crtc_state *cstate);
421 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
422 struct intel_crtc_state *cstate);
423 void (*optimize_watermarks)(struct intel_atomic_state *state,
424 struct intel_crtc_state *cstate);
425 int (*compute_global_watermarks)(struct drm_atomic_state *state);
426 void (*update_wm)(struct intel_crtc *crtc);
427 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
428 /* Returns the active state of the crtc, and if the crtc is active,
429 * fills out the pipe-config with the hw state. */
430 bool (*get_pipe_config)(struct intel_crtc *,
431 struct intel_crtc_state *);
432 void (*get_initial_plane_config)(struct intel_crtc *,
433 struct intel_initial_plane_config *);
434 int (*crtc_compute_clock)(struct intel_crtc *crtc,
435 struct intel_crtc_state *crtc_state);
436 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
437 struct drm_atomic_state *old_state);
438 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
439 struct drm_atomic_state *old_state);
440 void (*update_crtcs)(struct drm_atomic_state *state);
441 void (*audio_codec_enable)(struct intel_encoder *encoder,
442 const struct intel_crtc_state *crtc_state,
443 const struct drm_connector_state *conn_state);
444 void (*audio_codec_disable)(struct intel_encoder *encoder,
445 const struct intel_crtc_state *old_crtc_state,
446 const struct drm_connector_state *old_conn_state);
447 void (*fdi_link_train)(struct intel_crtc *crtc,
448 const struct intel_crtc_state *crtc_state);
449 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
450 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
451 /* clock updates for mode set */
453 /* render clock increase/decrease */
454 /* display clock increase/decrease */
455 /* pll clock increase/decrease */
457 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
458 void (*load_luts)(struct drm_crtc_state *crtc_state);
461 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
462 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
463 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
466 struct work_struct work;
468 uint32_t *dmc_payload;
469 uint32_t dmc_fw_size;
472 i915_reg_t mmioaddr[8];
473 uint32_t mmiodata[8];
475 uint32_t allowed_dc_mask;
478 enum i915_cache_level {
480 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
481 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
482 caches, eg sampler/render caches, and the
483 large Last-Level-Cache. LLC is coherent with
484 the CPU, but L3 is only visible to the GPU. */
485 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
488 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
499 /* This is always the inner lock when overlapping with struct_mutex and
500 * it's the outer lock when overlapping with stolen_lock. */
503 unsigned int possible_framebuffer_bits;
504 unsigned int busy_bits;
505 unsigned int visible_pipes_mask;
506 struct intel_crtc *crtc;
508 struct drm_mm_node compressed_fb;
509 struct drm_mm_node *compressed_llb;
517 bool underrun_detected;
518 struct work_struct underrun_work;
521 * Due to the atomic rules we can't access some structures without the
522 * appropriate locking, so we cache information here in order to avoid
525 struct intel_fbc_state_cache {
526 struct i915_vma *vma;
530 unsigned int mode_flags;
531 uint32_t hsw_bdw_pixel_rate;
535 unsigned int rotation;
540 * Display surface base address adjustement for
541 * pageflips. Note that on gen4+ this only adjusts up
542 * to a tile, offsets within a tile are handled in
543 * the hw itself (with the TILEOFF register).
552 const struct drm_format_info *format;
558 * This structure contains everything that's relevant to program the
559 * hardware registers. When we want to figure out if we need to disable
560 * and re-enable FBC for a new configuration we just check if there's
561 * something different in the struct. The genx_fbc_activate functions
562 * are supposed to read from it in order to program the registers.
564 struct intel_fbc_reg_params {
565 struct i915_vma *vma;
570 enum i9xx_plane_id i9xx_plane;
571 unsigned int fence_y_offset;
575 const struct drm_format_info *format;
580 unsigned int gen9_wa_cfb_stride;
583 const char *no_fbc_reason;
587 * HIGH_RR is the highest eDP panel refresh rate read from EDID
588 * LOW_RR is the lowest eDP panel refresh rate found from EDID
589 * parsing for same resolution.
591 enum drrs_refresh_rate_type {
594 DRRS_MAX_RR, /* RR count */
597 enum drrs_support_type {
598 DRRS_NOT_SUPPORTED = 0,
599 STATIC_DRRS_SUPPORT = 1,
600 SEAMLESS_DRRS_SUPPORT = 2
606 struct delayed_work work;
608 unsigned busy_frontbuffer_bits;
609 enum drrs_refresh_rate_type refresh_rate_type;
610 enum drrs_support_type type;
616 struct intel_dp *enabled;
618 struct work_struct work;
619 unsigned busy_frontbuffer_bits;
620 bool sink_psr2_support;
622 bool colorimetry_support;
625 u8 sink_sync_latency;
627 ktime_t last_entry_attempt;
632 PCH_NONE = 0, /* No PCH present */
633 PCH_IBX, /* Ibexpeak PCH */
634 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
635 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
636 PCH_SPT, /* Sunrisepoint PCH */
637 PCH_KBP, /* Kaby Lake PCH */
638 PCH_CNP, /* Cannon Lake PCH */
639 PCH_ICP, /* Ice Lake PCH */
640 PCH_NOP, /* PCH without south display */
643 enum intel_sbi_destination {
648 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
649 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
650 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
651 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
652 #define QUIRK_INCREASE_T12_DELAY (1<<6)
655 struct intel_fbc_work;
658 struct i2c_adapter adapter;
659 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
663 struct i2c_algo_bit_data bit_algo;
664 struct drm_i915_private *dev_priv;
667 struct i915_suspend_saved_registers {
670 u32 saveCACHE_MODE_0;
671 u32 saveMI_ARB_STATE;
675 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
676 u32 savePCH_PORT_HOTPLUG;
680 struct vlv_s0ix_state {
687 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
688 u32 media_max_req_count;
689 u32 gfx_max_req_count;
721 /* Display 1 CZ domain */
726 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
728 /* GT SA CZ domain */
735 /* Display 2 CZ domain */
742 struct intel_rps_ei {
750 * work, interrupts_enabled and pm_iir are protected by
753 struct work_struct work;
754 bool interrupts_enabled;
757 /* PM interrupt bits that should never be masked */
760 /* Frequencies are stored in potentially platform dependent multiples.
761 * In other words, *_freq needs to be multiplied by X to be interesting.
762 * Soft limits are those which are used for the dynamic reclocking done
763 * by the driver (raise frequencies under heavy loads, and lower for
764 * lighter loads). Hard limits are those imposed by the hardware.
766 * A distinction is made for overclocking, which is never enabled by
767 * default, and is considered to be above the hard limit if it's
770 u8 cur_freq; /* Current frequency (cached, may not == HW) */
771 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
772 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
773 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
774 u8 min_freq; /* AKA RPn. Minimum frequency */
775 u8 boost_freq; /* Frequency to request when wait boosting */
776 u8 idle_freq; /* Frequency to request when we are idle */
777 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
778 u8 rp1_freq; /* "less than" RP0 power/freqency */
779 u8 rp0_freq; /* Non-overclocked max frequency. */
780 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
782 u8 up_threshold; /* Current %busy required to uplock */
783 u8 down_threshold; /* Current %busy required to downclock */
786 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
789 atomic_t num_waiters;
792 /* manual wa residency calculations */
793 struct intel_rps_ei ei;
798 u64 prev_hw_residency[4];
799 u64 cur_residency[4];
802 struct intel_llc_pstate {
806 struct intel_gen6_power_mgmt {
807 struct intel_rps rps;
808 struct intel_rc6 rc6;
809 struct intel_llc_pstate llc_pstate;
812 /* defined intel_pm.c */
813 extern spinlock_t mchdev_lock;
815 struct intel_ilk_power_mgmt {
823 unsigned long last_time1;
824 unsigned long chipset_power;
827 unsigned long gfx_power;
834 struct drm_i915_private;
835 struct i915_power_well;
837 struct i915_power_well_ops {
839 * Synchronize the well's hw state to match the current sw state, for
840 * example enable/disable it based on the current refcount. Called
841 * during driver init and resume time, possibly after first calling
842 * the enable/disable handlers.
844 void (*sync_hw)(struct drm_i915_private *dev_priv,
845 struct i915_power_well *power_well);
847 * Enable the well and resources that depend on it (for example
848 * interrupts located on the well). Called after the 0->1 refcount
851 void (*enable)(struct drm_i915_private *dev_priv,
852 struct i915_power_well *power_well);
854 * Disable the well and resources that depend on it. Called after
855 * the 1->0 refcount transition.
857 void (*disable)(struct drm_i915_private *dev_priv,
858 struct i915_power_well *power_well);
859 /* Returns the hw enabled state. */
860 bool (*is_enabled)(struct drm_i915_private *dev_priv,
861 struct i915_power_well *power_well);
864 /* Power well structure for haswell */
865 struct i915_power_well {
868 /* power well enable/disable usage count */
870 /* cached hw enabled state */
873 /* unique identifier for this power well */
874 enum i915_power_well_id id;
876 * Arbitraty data associated with this power well. Platform and power
884 /* Mask of pipes whose IRQ logic is backed by the pw */
886 /* The pw is backing the VGA functionality */
891 const struct i915_power_well_ops *ops;
894 struct i915_power_domains {
896 * Power wells needed for initialization at driver init and suspend
897 * time are on. They are kept on until after the first modeset.
901 int power_well_count;
904 int domain_use_count[POWER_DOMAIN_NUM];
905 struct i915_power_well *power_wells;
908 #define MAX_L3_SLICES 2
909 struct intel_l3_parity {
910 u32 *remap_info[MAX_L3_SLICES];
911 struct work_struct error_work;
916 /** Memory allocator for GTT stolen memory */
917 struct drm_mm stolen;
918 /** Protects the usage of the GTT stolen memory allocator. This is
919 * always the inner lock when overlapping with struct_mutex. */
920 struct mutex stolen_lock;
922 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
925 /** List of all objects in gtt_space. Used to restore gtt
926 * mappings on resume */
927 struct list_head bound_list;
929 * List of objects which are not bound to the GTT (thus
930 * are idle and not used by the GPU). These objects may or may
931 * not actually have any pages attached.
933 struct list_head unbound_list;
935 /** List of all objects in gtt_space, currently mmaped by userspace.
936 * All objects within this list must also be on bound_list.
938 struct list_head userfault_list;
941 * List of objects which are pending destruction.
943 struct llist_head free_list;
944 struct work_struct free_work;
945 spinlock_t free_lock;
947 * Count of objects pending destructions. Used to skip needlessly
948 * waiting on an RCU barrier if no objects are waiting to be freed.
953 * Small stash of WC pages
955 struct pagestash wc_stash;
958 * tmpfs instance used for shmem backed objects
960 struct vfsmount *gemfs;
962 /** PPGTT used for aliasing the PPGTT with the GTT */
963 struct i915_hw_ppgtt *aliasing_ppgtt;
965 struct notifier_block oom_notifier;
966 struct notifier_block vmap_notifier;
967 struct shrinker shrinker;
969 /** LRU list of objects with fence regs on them. */
970 struct list_head fence_list;
973 * Workqueue to fault in userptr pages, flushed by the execbuf
974 * when required but otherwise left to userspace to try again
977 struct workqueue_struct *userptr_wq;
979 u64 unordered_timeline;
981 /* the indicator for dispatch video commands on two BSD rings */
982 atomic_t bsd_engine_dispatch_index;
984 /** Bit 6 swizzling required for X tiling */
985 uint32_t bit_6_swizzle_x;
986 /** Bit 6 swizzling required for Y tiling */
987 uint32_t bit_6_swizzle_y;
989 /* accounting, useful for userland debugging */
990 spinlock_t object_stat_lock;
995 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
997 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
998 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1000 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1001 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1003 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
1005 enum modeset_restore {
1006 MODESET_ON_LID_OPEN,
1011 #define DP_AUX_A 0x40
1012 #define DP_AUX_B 0x10
1013 #define DP_AUX_C 0x20
1014 #define DP_AUX_D 0x30
1015 #define DP_AUX_E 0x50
1016 #define DP_AUX_F 0x60
1018 #define DDC_PIN_B 0x05
1019 #define DDC_PIN_C 0x04
1020 #define DDC_PIN_D 0x06
1022 struct ddi_vbt_port_info {
1026 * This is an index in the HDMI/DVI DDI buffer translation table.
1027 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1028 * populate this field.
1030 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1031 uint8_t hdmi_level_shift;
1033 uint8_t supports_dvi:1;
1034 uint8_t supports_hdmi:1;
1035 uint8_t supports_dp:1;
1036 uint8_t supports_edp:1;
1038 uint8_t alternate_aux_channel;
1039 uint8_t alternate_ddc_pin;
1041 uint8_t dp_boost_level;
1042 uint8_t hdmi_boost_level;
1043 int dp_max_link_rate; /* 0 for not limited by VBT */
1046 enum psr_lines_to_wait {
1047 PSR_0_LINES_TO_WAIT = 0,
1049 PSR_4_LINES_TO_WAIT,
1053 struct intel_vbt_data {
1054 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1055 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1058 unsigned int int_tv_support:1;
1059 unsigned int lvds_dither:1;
1060 unsigned int int_crt_support:1;
1061 unsigned int lvds_use_ssc:1;
1062 unsigned int int_lvds_support:1;
1063 unsigned int display_clock_mode:1;
1064 unsigned int fdi_rx_polarity_inverted:1;
1065 unsigned int panel_type:4;
1067 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1069 enum drrs_support_type drrs_type;
1079 struct edp_power_seq pps;
1085 bool require_aux_wakeup;
1087 enum psr_lines_to_wait lines_to_wait;
1088 int tp1_wakeup_time_us;
1089 int tp2_tp3_wakeup_time_us;
1095 bool active_low_pwm;
1096 u8 min_brightness; /* min_brightness/255 of max */
1097 u8 controller; /* brightness controller number */
1098 enum intel_backlight_type type;
1104 struct mipi_config *config;
1105 struct mipi_pps_data *pps;
1111 const u8 *sequence[MIPI_SEQ_MAX];
1112 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1118 struct child_device_config *child_dev;
1120 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1121 struct sdvo_device_mapping sdvo_mappings[2];
1124 enum intel_ddb_partitioning {
1126 INTEL_DDB_PART_5_6, /* IVB+ */
1129 struct intel_wm_level {
1137 struct ilk_wm_values {
1138 uint32_t wm_pipe[3];
1140 uint32_t wm_lp_spr[3];
1141 uint32_t wm_linetime[3];
1143 enum intel_ddb_partitioning partitioning;
1146 struct g4x_pipe_wm {
1147 uint16_t plane[I915_MAX_PLANES];
1157 struct vlv_wm_ddl_values {
1158 uint8_t plane[I915_MAX_PLANES];
1161 struct vlv_wm_values {
1162 struct g4x_pipe_wm pipe[3];
1163 struct g4x_sr_wm sr;
1164 struct vlv_wm_ddl_values ddl[3];
1169 struct g4x_wm_values {
1170 struct g4x_pipe_wm pipe[2];
1171 struct g4x_sr_wm sr;
1172 struct g4x_sr_wm hpll;
1178 struct skl_ddb_entry {
1179 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1182 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1184 return entry->end - entry->start;
1187 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1188 const struct skl_ddb_entry *e2)
1190 if (e1->start == e2->start && e1->end == e2->end)
1196 struct skl_ddb_allocation {
1198 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1199 struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1200 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1203 struct skl_ddb_values {
1204 unsigned dirty_pipes;
1205 struct skl_ddb_allocation ddb;
1208 struct skl_wm_level {
1210 uint16_t plane_res_b;
1211 uint8_t plane_res_l;
1214 /* Stores plane specific WM parameters */
1215 struct skl_wm_params {
1216 bool x_tiled, y_tiled;
1221 uint32_t plane_pixel_rate;
1222 uint32_t y_min_scanlines;
1223 uint32_t plane_bytes_per_line;
1224 uint_fixed_16_16_t plane_blocks_per_line;
1225 uint_fixed_16_16_t y_tile_minimum;
1226 uint32_t linetime_us;
1227 uint32_t dbuf_block_size;
1231 * This struct helps tracking the state needed for runtime PM, which puts the
1232 * device in PCI D3 state. Notice that when this happens, nothing on the
1233 * graphics device works, even register access, so we don't get interrupts nor
1236 * Every piece of our code that needs to actually touch the hardware needs to
1237 * either call intel_runtime_pm_get or call intel_display_power_get with the
1238 * appropriate power domain.
1240 * Our driver uses the autosuspend delay feature, which means we'll only really
1241 * suspend if we stay with zero refcount for a certain amount of time. The
1242 * default value is currently very conservative (see intel_runtime_pm_enable), but
1243 * it can be changed with the standard runtime PM files from sysfs.
1245 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1246 * goes back to false exactly before we reenable the IRQs. We use this variable
1247 * to check if someone is trying to enable/disable IRQs while they're supposed
1248 * to be disabled. This shouldn't happen and we'll print some error messages in
1251 * For more, read the Documentation/power/runtime_pm.txt.
1253 struct i915_runtime_pm {
1254 atomic_t wakeref_count;
1259 enum intel_pipe_crc_source {
1260 INTEL_PIPE_CRC_SOURCE_NONE,
1261 INTEL_PIPE_CRC_SOURCE_PLANE1,
1262 INTEL_PIPE_CRC_SOURCE_PLANE2,
1263 INTEL_PIPE_CRC_SOURCE_PF,
1264 INTEL_PIPE_CRC_SOURCE_PIPE,
1265 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1266 INTEL_PIPE_CRC_SOURCE_TV,
1267 INTEL_PIPE_CRC_SOURCE_DP_B,
1268 INTEL_PIPE_CRC_SOURCE_DP_C,
1269 INTEL_PIPE_CRC_SOURCE_DP_D,
1270 INTEL_PIPE_CRC_SOURCE_AUTO,
1271 INTEL_PIPE_CRC_SOURCE_MAX,
1274 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1275 struct intel_pipe_crc {
1278 enum intel_pipe_crc_source source;
1281 struct i915_frontbuffer_tracking {
1285 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1292 struct i915_wa_reg {
1295 /* bitmask representing WA bits */
1299 #define I915_MAX_WA_REGS 16
1301 struct i915_workarounds {
1302 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1306 struct i915_virtual_gpu {
1311 /* used in computing the new watermarks state */
1312 struct intel_wm_config {
1313 unsigned int num_pipes_active;
1314 bool sprites_enabled;
1315 bool sprites_scaled;
1318 struct i915_oa_format {
1323 struct i915_oa_reg {
1328 struct i915_oa_config {
1329 char uuid[UUID_STRING_LEN + 1];
1332 const struct i915_oa_reg *mux_regs;
1334 const struct i915_oa_reg *b_counter_regs;
1335 u32 b_counter_regs_len;
1336 const struct i915_oa_reg *flex_regs;
1339 struct attribute_group sysfs_metric;
1340 struct attribute *attrs[2];
1341 struct device_attribute sysfs_metric_id;
1346 struct i915_perf_stream;
1349 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1351 struct i915_perf_stream_ops {
1353 * @enable: Enables the collection of HW samples, either in response to
1354 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1355 * without `I915_PERF_FLAG_DISABLED`.
1357 void (*enable)(struct i915_perf_stream *stream);
1360 * @disable: Disables the collection of HW samples, either in response
1361 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1364 void (*disable)(struct i915_perf_stream *stream);
1367 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1368 * once there is something ready to read() for the stream
1370 void (*poll_wait)(struct i915_perf_stream *stream,
1375 * @wait_unlocked: For handling a blocking read, wait until there is
1376 * something to ready to read() for the stream. E.g. wait on the same
1377 * wait queue that would be passed to poll_wait().
1379 int (*wait_unlocked)(struct i915_perf_stream *stream);
1382 * @read: Copy buffered metrics as records to userspace
1383 * **buf**: the userspace, destination buffer
1384 * **count**: the number of bytes to copy, requested by userspace
1385 * **offset**: zero at the start of the read, updated as the read
1386 * proceeds, it represents how many bytes have been copied so far and
1387 * the buffer offset for copying the next record.
1389 * Copy as many buffered i915 perf samples and records for this stream
1390 * to userspace as will fit in the given buffer.
1392 * Only write complete records; returning -%ENOSPC if there isn't room
1393 * for a complete record.
1395 * Return any error condition that results in a short read such as
1396 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1397 * returning to userspace.
1399 int (*read)(struct i915_perf_stream *stream,
1405 * @destroy: Cleanup any stream specific resources.
1407 * The stream will always be disabled before this is called.
1409 void (*destroy)(struct i915_perf_stream *stream);
1413 * struct i915_perf_stream - state for a single open stream FD
1415 struct i915_perf_stream {
1417 * @dev_priv: i915 drm device
1419 struct drm_i915_private *dev_priv;
1422 * @link: Links the stream into ``&drm_i915_private->streams``
1424 struct list_head link;
1427 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1428 * properties given when opening a stream, representing the contents
1429 * of a single sample as read() by userspace.
1434 * @sample_size: Considering the configured contents of a sample
1435 * combined with the required header size, this is the total size
1436 * of a single sample record.
1441 * @ctx: %NULL if measuring system-wide across all contexts or a
1442 * specific context that is being monitored.
1444 struct i915_gem_context *ctx;
1447 * @enabled: Whether the stream is currently enabled, considering
1448 * whether the stream was opened in a disabled state and based
1449 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1454 * @ops: The callbacks providing the implementation of this specific
1455 * type of configured stream.
1457 const struct i915_perf_stream_ops *ops;
1460 * @oa_config: The OA configuration used by the stream.
1462 struct i915_oa_config *oa_config;
1466 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1468 struct i915_oa_ops {
1470 * @is_valid_b_counter_reg: Validates register's address for
1471 * programming boolean counters for a particular platform.
1473 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1477 * @is_valid_mux_reg: Validates register's address for programming mux
1478 * for a particular platform.
1480 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1483 * @is_valid_flex_reg: Validates register's address for programming
1484 * flex EU filtering for a particular platform.
1486 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1489 * @init_oa_buffer: Resets the head and tail pointers of the
1490 * circular buffer for periodic OA reports.
1492 * Called when first opening a stream for OA metrics, but also may be
1493 * called in response to an OA buffer overflow or other error
1496 * Note it may be necessary to clear the full OA buffer here as part of
1497 * maintaining the invariable that new reports must be written to
1498 * zeroed memory for us to be able to reliable detect if an expected
1499 * report has not yet landed in memory. (At least on Haswell the OA
1500 * buffer tail pointer is not synchronized with reports being visible
1503 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1506 * @enable_metric_set: Selects and applies any MUX configuration to set
1507 * up the Boolean and Custom (B/C) counters that are part of the
1508 * counter reports being sampled. May apply system constraints such as
1509 * disabling EU clock gating as required.
1511 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1512 const struct i915_oa_config *oa_config);
1515 * @disable_metric_set: Remove system constraints associated with using
1518 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1521 * @oa_enable: Enable periodic sampling
1523 void (*oa_enable)(struct drm_i915_private *dev_priv);
1526 * @oa_disable: Disable periodic sampling
1528 void (*oa_disable)(struct drm_i915_private *dev_priv);
1531 * @read: Copy data from the circular OA buffer into a given userspace
1534 int (*read)(struct i915_perf_stream *stream,
1540 * @oa_hw_tail_read: read the OA tail pointer register
1542 * In particular this enables us to share all the fiddly code for
1543 * handling the OA unit tail pointer race that affects multiple
1546 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1549 struct intel_cdclk_state {
1550 unsigned int cdclk, vco, ref, bypass;
1554 struct drm_i915_private {
1555 struct drm_device drm;
1557 struct kmem_cache *objects;
1558 struct kmem_cache *vmas;
1559 struct kmem_cache *luts;
1560 struct kmem_cache *requests;
1561 struct kmem_cache *dependencies;
1562 struct kmem_cache *priorities;
1564 const struct intel_device_info info;
1565 struct intel_driver_caps caps;
1568 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1569 * end of stolen which we can optionally use to create GEM objects
1570 * backed by stolen memory. Note that stolen_usable_size tells us
1571 * exactly how much of this we are actually allowed to use, given that
1572 * some portion of it is in fact reserved for use by hardware functions.
1574 struct resource dsm;
1576 * Reseved portion of Data Stolen Memory
1578 struct resource dsm_reserved;
1581 * Stolen memory is segmented in hardware with different portions
1582 * offlimits to certain functions.
1584 * The drm_mm is initialised to the total accessible range, as found
1585 * from the PCI config. On Broadwell+, this is further restricted to
1586 * avoid the first page! The upper end of stolen memory is reserved for
1587 * hardware functions and similarly removed from the accessible range.
1589 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1593 struct intel_uncore uncore;
1595 struct i915_virtual_gpu vgpu;
1597 struct intel_gvt *gvt;
1599 struct intel_wopcm wopcm;
1601 struct intel_huc huc;
1602 struct intel_guc guc;
1604 struct intel_csr csr;
1606 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1608 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1609 * controller on different i2c buses. */
1610 struct mutex gmbus_mutex;
1613 * Base address of the gmbus and gpio block.
1615 uint32_t gpio_mmio_base;
1617 /* MMIO base address for MIPI regs */
1618 uint32_t mipi_mmio_base;
1620 uint32_t psr_mmio_base;
1622 uint32_t pps_mmio_base;
1624 wait_queue_head_t gmbus_wait_queue;
1626 struct pci_dev *bridge_dev;
1627 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1628 /* Context used internally to idle the GPU and setup initial state */
1629 struct i915_gem_context *kernel_context;
1630 /* Context only to be used for injecting preemption commands */
1631 struct i915_gem_context *preempt_context;
1632 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1633 [MAX_ENGINE_INSTANCE + 1];
1635 struct drm_dma_handle *status_page_dmah;
1636 struct resource mch_res;
1638 /* protects the irq masks */
1639 spinlock_t irq_lock;
1641 bool display_irqs_enabled;
1643 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1644 struct pm_qos_request pm_qos;
1646 /* Sideband mailbox protection */
1647 struct mutex sb_lock;
1649 /** Cached value of IMR to avoid reads in updating the bitfield */
1652 u32 de_irq_mask[I915_MAX_PIPES];
1659 u32 pipestat_irq_mask[I915_MAX_PIPES];
1661 struct i915_hotplug hotplug;
1662 struct intel_fbc fbc;
1663 struct i915_drrs drrs;
1664 struct intel_opregion opregion;
1665 struct intel_vbt_data vbt;
1667 bool preserve_bios_swizzle;
1670 struct intel_overlay *overlay;
1672 /* backlight registers and fields in struct intel_panel */
1673 struct mutex backlight_lock;
1676 bool no_aux_handshake;
1678 /* protects panel power sequencer state */
1679 struct mutex pps_mutex;
1681 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1682 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1684 unsigned int fsb_freq, mem_freq, is_ddr3;
1685 unsigned int skl_preferred_vco_freq;
1686 unsigned int max_cdclk_freq;
1688 unsigned int max_dotclk_freq;
1689 unsigned int rawclk_freq;
1690 unsigned int hpll_freq;
1691 unsigned int fdi_pll_freq;
1692 unsigned int czclk_freq;
1696 * The current logical cdclk state.
1697 * See intel_atomic_state.cdclk.logical
1699 * For reading holding any crtc lock is sufficient,
1700 * for writing must hold all of them.
1702 struct intel_cdclk_state logical;
1704 * The current actual cdclk state.
1705 * See intel_atomic_state.cdclk.actual
1707 struct intel_cdclk_state actual;
1708 /* The current hardware cdclk state */
1709 struct intel_cdclk_state hw;
1713 * wq - Driver workqueue for GEM.
1715 * NOTE: Work items scheduled here are not allowed to grab any modeset
1716 * locks, for otherwise the flushing done in the pageflip code will
1717 * result in deadlocks.
1719 struct workqueue_struct *wq;
1721 /* ordered wq for modesets */
1722 struct workqueue_struct *modeset_wq;
1724 /* Display functions */
1725 struct drm_i915_display_funcs display;
1727 /* PCH chipset type */
1728 enum intel_pch pch_type;
1729 unsigned short pch_id;
1731 unsigned long quirks;
1733 enum modeset_restore modeset_restore;
1734 struct mutex modeset_restore_lock;
1735 struct drm_atomic_state *modeset_restore_state;
1736 struct drm_modeset_acquire_ctx reset_ctx;
1738 struct i915_ggtt ggtt; /* VM representing the global address space */
1740 struct i915_gem_mm mm;
1741 DECLARE_HASHTABLE(mm_structs, 7);
1742 struct mutex mm_lock;
1744 struct intel_ppat ppat;
1746 /* Kernel Modesetting */
1748 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1749 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1751 #ifdef CONFIG_DEBUG_FS
1752 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1755 /* dpll and cdclk state is protected by connection_mutex */
1756 int num_shared_dpll;
1757 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1758 const struct intel_dpll_mgr *dpll_mgr;
1761 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1762 * Must be global rather than per dpll, because on some platforms
1763 * plls share registers.
1765 struct mutex dpll_lock;
1767 unsigned int active_crtcs;
1768 /* minimum acceptable cdclk for each pipe */
1769 int min_cdclk[I915_MAX_PIPES];
1770 /* minimum acceptable voltage level for each pipe */
1771 u8 min_voltage_level[I915_MAX_PIPES];
1773 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1775 struct i915_workarounds workarounds;
1777 struct i915_frontbuffer_tracking fb_tracking;
1779 struct intel_atomic_helper {
1780 struct llist_head free_list;
1781 struct work_struct free_work;
1786 bool mchbar_need_disable;
1788 struct intel_l3_parity l3_parity;
1790 /* Cannot be determined by PCIID. You must always read a register. */
1794 * Protects RPS/RC6 register access and PCU communication.
1795 * Must be taken after struct_mutex if nested. Note that
1796 * this lock may be held for long periods of time when
1797 * talking to hw - so only take it when talking to hw!
1799 struct mutex pcu_lock;
1801 /* gen6+ GT PM state */
1802 struct intel_gen6_power_mgmt gt_pm;
1804 /* ilk-only ips/rps state. Everything in here is protected by the global
1805 * mchdev_lock in intel_pm.c */
1806 struct intel_ilk_power_mgmt ips;
1808 struct i915_power_domains power_domains;
1810 struct i915_psr psr;
1812 struct i915_gpu_error gpu_error;
1814 struct drm_i915_gem_object *vlv_pctx;
1816 /* list of fbdev register on this device */
1817 struct intel_fbdev *fbdev;
1818 struct work_struct fbdev_suspend_work;
1820 struct drm_property *broadcast_rgb_property;
1821 struct drm_property *force_audio_property;
1823 /* hda/i915 audio component */
1824 struct i915_audio_component *audio_component;
1825 bool audio_component_registered;
1827 * av_mutex - mutex for audio/video sync
1830 struct mutex av_mutex;
1833 struct list_head list;
1834 struct llist_head free_list;
1835 struct work_struct free_work;
1837 /* The hw wants to have a stable context identifier for the
1838 * lifetime of the context (for OA, PASID, faults, etc).
1839 * This is limited in execlists to 21 bits.
1842 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1843 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1844 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1849 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1850 u32 chv_phy_control;
1852 * Shadows for CHV DPLL_MD regs to keep the state
1853 * checker somewhat working in the presence hardware
1854 * crappiness (can't read out DPLL_MD for pipes B & C).
1856 u32 chv_dpll_md[I915_MAX_PIPES];
1860 bool power_domains_suspended;
1861 struct i915_suspend_saved_registers regfile;
1862 struct vlv_s0ix_state vlv_s0ix_state;
1865 I915_SAGV_UNKNOWN = 0,
1868 I915_SAGV_NOT_CONTROLLED
1873 * Raw watermark latency values:
1874 * in 0.1us units for WM0,
1875 * in 0.5us units for WM1+.
1878 uint16_t pri_latency[5];
1880 uint16_t spr_latency[5];
1882 uint16_t cur_latency[5];
1884 * Raw watermark memory latency values
1885 * for SKL for all 8 levels
1888 uint16_t skl_latency[8];
1890 /* current hardware state */
1892 struct ilk_wm_values hw;
1893 struct skl_ddb_values skl_hw;
1894 struct vlv_wm_values vlv;
1895 struct g4x_wm_values g4x;
1901 * Should be held around atomic WM register writing; also
1902 * protects * intel_crtc->wm.active and
1903 * cstate->wm.need_postvbl_update.
1905 struct mutex wm_mutex;
1908 * Set during HW readout of watermarks/DDB. Some platforms
1909 * need to know when we're still using BIOS-provided values
1910 * (which we don't fully trust).
1912 bool distrust_bios_wm;
1915 struct i915_runtime_pm runtime_pm;
1920 struct kobject *metrics_kobj;
1921 struct ctl_table_header *sysctl_header;
1924 * Lock associated with adding/modifying/removing OA configs
1925 * in dev_priv->perf.metrics_idr.
1927 struct mutex metrics_lock;
1930 * List of dynamic configurations, you need to hold
1931 * dev_priv->perf.metrics_lock to access it.
1933 struct idr metrics_idr;
1936 * Lock associated with anything below within this structure
1937 * except exclusive_stream.
1940 struct list_head streams;
1944 * The stream currently using the OA unit. If accessed
1945 * outside a syscall associated to its file
1946 * descriptor, you need to hold
1947 * dev_priv->drm.struct_mutex.
1949 struct i915_perf_stream *exclusive_stream;
1951 struct intel_context *pinned_ctx;
1952 u32 specific_ctx_id;
1953 u32 specific_ctx_id_mask;
1955 struct hrtimer poll_check_timer;
1956 wait_queue_head_t poll_wq;
1960 * For rate limiting any notifications of spurious
1961 * invalid OA reports
1963 struct ratelimit_state spurious_report_rs;
1966 int period_exponent;
1968 struct i915_oa_config test_config;
1971 struct i915_vma *vma;
1978 * Locks reads and writes to all head/tail state
1980 * Consider: the head and tail pointer state
1981 * needs to be read consistently from a hrtimer
1982 * callback (atomic context) and read() fop
1983 * (user context) with tail pointer updates
1984 * happening in atomic context and head updates
1985 * in user context and the (unlikely)
1986 * possibility of read() errors needing to
1987 * reset all head/tail state.
1989 * Note: Contention or performance aren't
1990 * currently a significant concern here
1991 * considering the relatively low frequency of
1992 * hrtimer callbacks (5ms period) and that
1993 * reads typically only happen in response to a
1994 * hrtimer event and likely complete before the
1997 * Note: This lock is not held *while* reading
1998 * and copying data to userspace so the value
1999 * of head observed in htrimer callbacks won't
2000 * represent any partial consumption of data.
2002 spinlock_t ptr_lock;
2005 * One 'aging' tail pointer and one 'aged'
2006 * tail pointer ready to used for reading.
2008 * Initial values of 0xffffffff are invalid
2009 * and imply that an update is required
2010 * (and should be ignored by an attempted
2018 * Index for the aged tail ready to read()
2021 unsigned int aged_tail_idx;
2024 * A monotonic timestamp for when the current
2025 * aging tail pointer was read; used to
2026 * determine when it is old enough to trust.
2028 u64 aging_timestamp;
2031 * Although we can always read back the head
2032 * pointer register, we prefer to avoid
2033 * trusting the HW state, just to avoid any
2034 * risk that some hardware condition could
2035 * somehow bump the head pointer unpredictably
2036 * and cause us to forward the wrong OA buffer
2037 * data to userspace.
2042 u32 gen7_latched_oastatus1;
2043 u32 ctx_oactxctrl_offset;
2044 u32 ctx_flexeu0_offset;
2047 * The RPT_ID/reason field for Gen8+ includes a bit
2048 * to determine if the CTX ID in the report is valid
2049 * but the specific bit differs between Gen 8 and 9
2051 u32 gen8_valid_ctx_bit;
2053 struct i915_oa_ops ops;
2054 const struct i915_oa_format *oa_formats;
2058 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2060 void (*resume)(struct drm_i915_private *);
2061 void (*cleanup_engine)(struct intel_engine_cs *engine);
2063 struct list_head timelines;
2065 struct list_head active_rings;
2066 struct list_head closed_vma;
2067 u32 active_requests;
2071 * Is the GPU currently considered idle, or busy executing
2072 * userspace requests? Whilst idle, we allow runtime power
2073 * management to power down the hardware and display clocks.
2074 * In order to reduce the effect on performance, there
2075 * is a slight delay before we do so.
2080 * The number of times we have woken up.
2083 #define I915_EPOCH_INVALID 0
2086 * We leave the user IRQ off as much as possible,
2087 * but this means that requests will finish and never
2088 * be retired once the system goes idle. Set a timer to
2089 * fire periodically while the ring is running. When it
2090 * fires, go retire requests.
2092 struct delayed_work retire_work;
2095 * When we detect an idle GPU, we want to turn on
2096 * powersaving features. So once we see that there
2097 * are no more requests outstanding and no more
2098 * arrive within a small period of time, we fire
2099 * off the idle_work.
2101 struct delayed_work idle_work;
2103 ktime_t last_init_time;
2106 /* perform PHY state sanity checks? */
2107 bool chv_phy_assert[2];
2111 /* Used to save the pipe-to-encoder mapping for audio */
2112 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2114 /* necessary resource sharing with HDMI LPE audio driver. */
2116 struct platform_device *platdev;
2120 struct i915_pmu pmu;
2123 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2124 * will be rejected. Instead look for a better place.
2128 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2130 return container_of(dev, struct drm_i915_private, drm);
2133 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2135 return to_i915(dev_get_drvdata(kdev));
2138 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2140 return container_of(wopcm, struct drm_i915_private, wopcm);
2143 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2145 return container_of(guc, struct drm_i915_private, guc);
2148 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2150 return container_of(huc, struct drm_i915_private, huc);
2153 /* Simple iterator over all initialised engines */
2154 #define for_each_engine(engine__, dev_priv__, id__) \
2156 (id__) < I915_NUM_ENGINES; \
2158 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2160 /* Iterator over subset of engines selected by mask */
2161 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2162 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2164 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2167 enum hdmi_force_audio {
2168 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2169 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2170 HDMI_AUDIO_AUTO, /* trust EDID */
2171 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2174 #define I915_GTT_OFFSET_NONE ((u32)-1)
2177 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2178 * considered to be the frontbuffer for the given plane interface-wise. This
2179 * doesn't mean that the hw necessarily already scans it out, but that any
2180 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2182 * We have one bit per pipe and per scanout plane type.
2184 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2185 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2186 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2187 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2188 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2190 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2191 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2192 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2193 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2194 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2197 * Optimised SGL iterator for GEM objects
2199 static __always_inline struct sgt_iter {
2200 struct scatterlist *sgp;
2207 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2208 struct sgt_iter s = { .sgp = sgl };
2211 s.max = s.curr = s.sgp->offset;
2212 s.max += s.sgp->length;
2214 s.dma = sg_dma_address(s.sgp);
2216 s.pfn = page_to_pfn(sg_page(s.sgp));
2222 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2225 if (unlikely(sg_is_chain(sg)))
2226 sg = sg_chain_ptr(sg);
2231 * __sg_next - return the next scatterlist entry in a list
2232 * @sg: The current sg entry
2235 * If the entry is the last, return NULL; otherwise, step to the next
2236 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2237 * otherwise just return the pointer to the current element.
2239 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2241 #ifdef CONFIG_DEBUG_SG
2242 BUG_ON(sg->sg_magic != SG_MAGIC);
2244 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2248 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2249 * @__dmap: DMA address (output)
2250 * @__iter: 'struct sgt_iter' (iterator state, internal)
2251 * @__sgt: sg_table to iterate over (input)
2253 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2254 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2255 ((__dmap) = (__iter).dma + (__iter).curr); \
2256 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2257 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2260 * for_each_sgt_page - iterate over the pages of the given sg_table
2261 * @__pp: page pointer (output)
2262 * @__iter: 'struct sgt_iter' (iterator state, internal)
2263 * @__sgt: sg_table to iterate over (input)
2265 #define for_each_sgt_page(__pp, __iter, __sgt) \
2266 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2267 ((__pp) = (__iter).pfn == 0 ? NULL : \
2268 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2269 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2270 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2272 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2274 unsigned int page_sizes;
2278 GEM_BUG_ON(sg->offset);
2279 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2280 page_sizes |= sg->length;
2287 static inline unsigned int i915_sg_segment_size(void)
2289 unsigned int size = swiotlb_max_segment();
2292 return SCATTERLIST_MAX_SEGMENT;
2294 size = rounddown(size, PAGE_SIZE);
2295 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2296 if (size < PAGE_SIZE)
2302 static inline const struct intel_device_info *
2303 intel_info(const struct drm_i915_private *dev_priv)
2305 return &dev_priv->info;
2308 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2309 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2311 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2312 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2314 #define REVID_FOREVER 0xff
2315 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2317 #define GEN_FOREVER (0)
2319 #define INTEL_GEN_MASK(s, e) ( \
2320 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2321 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2322 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2323 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2327 * Returns true if Gen is in inclusive range [Start, End].
2329 * Use GEN_FOREVER for unbound start and or end.
2331 #define IS_GEN(dev_priv, s, e) \
2332 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2335 * Return true if revision is in range [since,until] inclusive.
2337 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2339 #define IS_REVID(p, since, until) \
2340 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2342 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2344 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2345 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2346 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2347 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2348 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2349 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2350 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2351 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2352 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2353 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2354 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2355 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2356 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2357 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2358 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2359 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2360 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2361 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2362 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2363 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2364 (dev_priv)->info.gt == 1)
2365 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2366 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2367 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2368 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2369 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2370 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2371 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2372 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2373 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2374 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2375 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2376 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2377 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2378 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2379 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2380 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2381 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2382 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2383 /* ULX machines are also considered ULT. */
2384 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2385 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2386 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2387 (dev_priv)->info.gt == 3)
2388 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2389 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2390 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2391 (dev_priv)->info.gt == 3)
2392 /* ULX machines are also considered ULT. */
2393 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2394 INTEL_DEVID(dev_priv) == 0x0A1E)
2395 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2396 INTEL_DEVID(dev_priv) == 0x1913 || \
2397 INTEL_DEVID(dev_priv) == 0x1916 || \
2398 INTEL_DEVID(dev_priv) == 0x1921 || \
2399 INTEL_DEVID(dev_priv) == 0x1926)
2400 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2401 INTEL_DEVID(dev_priv) == 0x1915 || \
2402 INTEL_DEVID(dev_priv) == 0x191E)
2403 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2404 INTEL_DEVID(dev_priv) == 0x5913 || \
2405 INTEL_DEVID(dev_priv) == 0x5916 || \
2406 INTEL_DEVID(dev_priv) == 0x5921 || \
2407 INTEL_DEVID(dev_priv) == 0x5926)
2408 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2409 INTEL_DEVID(dev_priv) == 0x5915 || \
2410 INTEL_DEVID(dev_priv) == 0x591E)
2411 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2412 (dev_priv)->info.gt == 2)
2413 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2414 (dev_priv)->info.gt == 3)
2415 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2416 (dev_priv)->info.gt == 4)
2417 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2418 (dev_priv)->info.gt == 2)
2419 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2420 (dev_priv)->info.gt == 3)
2421 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2422 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2423 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2424 (dev_priv)->info.gt == 2)
2425 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2426 (dev_priv)->info.gt == 3)
2427 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2428 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2430 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2432 #define SKL_REVID_A0 0x0
2433 #define SKL_REVID_B0 0x1
2434 #define SKL_REVID_C0 0x2
2435 #define SKL_REVID_D0 0x3
2436 #define SKL_REVID_E0 0x4
2437 #define SKL_REVID_F0 0x5
2438 #define SKL_REVID_G0 0x6
2439 #define SKL_REVID_H0 0x7
2441 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2443 #define BXT_REVID_A0 0x0
2444 #define BXT_REVID_A1 0x1
2445 #define BXT_REVID_B0 0x3
2446 #define BXT_REVID_B_LAST 0x8
2447 #define BXT_REVID_C0 0x9
2449 #define IS_BXT_REVID(dev_priv, since, until) \
2450 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2452 #define KBL_REVID_A0 0x0
2453 #define KBL_REVID_B0 0x1
2454 #define KBL_REVID_C0 0x2
2455 #define KBL_REVID_D0 0x3
2456 #define KBL_REVID_E0 0x4
2458 #define IS_KBL_REVID(dev_priv, since, until) \
2459 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2461 #define GLK_REVID_A0 0x0
2462 #define GLK_REVID_A1 0x1
2464 #define IS_GLK_REVID(dev_priv, since, until) \
2465 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2467 #define CNL_REVID_A0 0x0
2468 #define CNL_REVID_B0 0x1
2469 #define CNL_REVID_C0 0x2
2471 #define IS_CNL_REVID(p, since, until) \
2472 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2474 #define ICL_REVID_A0 0x0
2475 #define ICL_REVID_A2 0x1
2476 #define ICL_REVID_B0 0x3
2477 #define ICL_REVID_B2 0x4
2478 #define ICL_REVID_C0 0x5
2480 #define IS_ICL_REVID(p, since, until) \
2481 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2484 * The genX designation typically refers to the render engine, so render
2485 * capability related checks should use IS_GEN, while display and other checks
2486 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2489 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2490 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2491 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2492 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2493 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2494 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2495 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2496 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2497 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2498 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2500 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2501 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2502 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2504 #define ENGINE_MASK(id) BIT(id)
2505 #define RENDER_RING ENGINE_MASK(RCS)
2506 #define BSD_RING ENGINE_MASK(VCS)
2507 #define BLT_RING ENGINE_MASK(BCS)
2508 #define VEBOX_RING ENGINE_MASK(VECS)
2509 #define BSD2_RING ENGINE_MASK(VCS2)
2510 #define BSD3_RING ENGINE_MASK(VCS3)
2511 #define BSD4_RING ENGINE_MASK(VCS4)
2512 #define VEBOX2_RING ENGINE_MASK(VECS2)
2513 #define ALL_ENGINES (~0)
2515 #define HAS_ENGINE(dev_priv, id) \
2516 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2518 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2519 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2520 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2521 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2523 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2525 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2526 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2527 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2528 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2529 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2531 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2533 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2534 ((dev_priv)->info.has_logical_ring_contexts)
2535 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2536 ((dev_priv)->info.has_logical_ring_elsq)
2537 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2538 ((dev_priv)->info.has_logical_ring_preemption)
2540 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2542 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2543 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2544 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2545 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2546 GEM_BUG_ON((sizes) == 0); \
2547 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2550 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2551 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2552 ((dev_priv)->info.overlay_needs_physical)
2554 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2555 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2557 /* WaRsDisableCoarsePowerGating:skl,cnl */
2558 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2559 (IS_CANNONLAKE(dev_priv) || \
2560 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2562 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2564 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2565 * rows, which changed the alignment requirements and fence programming.
2567 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2568 !(IS_I915G(dev_priv) || \
2569 IS_I915GM(dev_priv)))
2570 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2571 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2573 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2574 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2575 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2577 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2579 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2581 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2582 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2583 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2585 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2586 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2587 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2589 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2591 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2592 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2594 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2597 * For now, anything with a GuC requires uCode loading, and then supports
2598 * command submission once loaded. But these are logically independent
2599 * properties, so we have separate macros to test them.
2601 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2602 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2603 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2604 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2606 /* For now, anything with a GuC has also HuC */
2607 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2608 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2610 /* Having a GuC is not the same as using a GuC */
2611 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2612 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2613 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2615 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2617 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2619 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2620 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2621 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2622 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2623 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2624 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2625 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2626 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2627 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2628 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2629 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2630 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2631 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2632 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2633 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2634 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2635 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2637 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2638 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2639 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2640 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2641 #define HAS_PCH_CNP_LP(dev_priv) \
2642 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2643 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2644 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2645 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2646 #define HAS_PCH_LPT_LP(dev_priv) \
2647 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2648 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2649 #define HAS_PCH_LPT_H(dev_priv) \
2650 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2651 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2652 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2653 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2654 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2655 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2657 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2659 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2661 /* DPF == dynamic parity feature */
2662 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2663 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2664 2 : HAS_L3_DPF(dev_priv))
2666 #define GT_FREQUENCY_MULTIPLIER 50
2667 #define GEN9_FREQ_SCALER 3
2669 #include "i915_trace.h"
2671 static inline bool intel_vtd_active(void)
2673 #ifdef CONFIG_INTEL_IOMMU
2674 if (intel_iommu_gfx_mapped)
2680 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2682 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2686 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2688 return IS_BROXTON(dev_priv) && intel_vtd_active();
2691 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2696 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2697 const char *fmt, ...);
2699 #define i915_report_error(dev_priv, fmt, ...) \
2700 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2702 #ifdef CONFIG_COMPAT
2703 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2706 #define i915_compat_ioctl NULL
2708 extern const struct dev_pm_ops i915_pm_ops;
2710 extern int i915_driver_load(struct pci_dev *pdev,
2711 const struct pci_device_id *ent);
2712 extern void i915_driver_unload(struct drm_device *dev);
2713 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2714 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2716 extern void i915_reset(struct drm_i915_private *i915,
2717 unsigned int stalled_mask,
2718 const char *reason);
2719 extern int i915_reset_engine(struct intel_engine_cs *engine,
2720 const char *reason);
2722 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2723 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2724 extern int intel_guc_reset_engine(struct intel_guc *guc,
2725 struct intel_engine_cs *engine);
2726 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2727 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2728 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2729 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2730 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2731 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2732 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2734 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2735 int intel_engines_init(struct drm_i915_private *dev_priv);
2737 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2739 /* intel_hotplug.c */
2740 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2741 u32 pin_mask, u32 long_mask);
2742 void intel_hpd_init(struct drm_i915_private *dev_priv);
2743 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2744 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2745 enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
2747 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2749 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2750 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2753 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2755 unsigned long delay;
2757 if (unlikely(!i915_modparams.enable_hangcheck))
2760 /* Don't continually defer the hangcheck so that it is always run at
2761 * least once after work has been scheduled on any ring. Otherwise,
2762 * we will ignore a hung ring if a second ring is kept busy.
2765 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2766 queue_delayed_work(system_long_wq,
2767 &dev_priv->gpu_error.hangcheck_work, delay);
2771 void i915_handle_error(struct drm_i915_private *dev_priv,
2773 unsigned long flags,
2774 const char *fmt, ...);
2775 #define I915_ERROR_CAPTURE BIT(0)
2777 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2778 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2779 int intel_irq_install(struct drm_i915_private *dev_priv);
2780 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2782 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2784 return dev_priv->gvt;
2787 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2789 return dev_priv->vgpu.active;
2792 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2795 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2799 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2802 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2803 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2804 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2807 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2808 uint32_t interrupt_mask,
2809 uint32_t enabled_irq_mask);
2811 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2813 ilk_update_display_irq(dev_priv, bits, bits);
2816 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2818 ilk_update_display_irq(dev_priv, bits, 0);
2820 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2822 uint32_t interrupt_mask,
2823 uint32_t enabled_irq_mask);
2824 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2825 enum pipe pipe, uint32_t bits)
2827 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2829 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2830 enum pipe pipe, uint32_t bits)
2832 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2834 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2835 uint32_t interrupt_mask,
2836 uint32_t enabled_irq_mask);
2838 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2840 ibx_display_interrupt_update(dev_priv, bits, bits);
2843 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2845 ibx_display_interrupt_update(dev_priv, bits, 0);
2849 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2850 struct drm_file *file_priv);
2851 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2852 struct drm_file *file_priv);
2853 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2854 struct drm_file *file_priv);
2855 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2856 struct drm_file *file_priv);
2857 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2858 struct drm_file *file_priv);
2859 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2860 struct drm_file *file_priv);
2861 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2864 struct drm_file *file_priv);
2865 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2866 struct drm_file *file_priv);
2867 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2868 struct drm_file *file_priv);
2869 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2870 struct drm_file *file);
2871 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2872 struct drm_file *file);
2873 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2874 struct drm_file *file_priv);
2875 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2876 struct drm_file *file_priv);
2877 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2878 struct drm_file *file_priv);
2879 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2880 struct drm_file *file_priv);
2881 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2882 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2883 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2884 struct drm_file *file);
2885 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2886 struct drm_file *file_priv);
2887 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2888 struct drm_file *file_priv);
2889 void i915_gem_sanitize(struct drm_i915_private *i915);
2890 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2891 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2892 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2893 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2894 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2896 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2897 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2898 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2899 const struct drm_i915_gem_object_ops *ops);
2900 struct drm_i915_gem_object *
2901 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2902 struct drm_i915_gem_object *
2903 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2904 const void *data, size_t size);
2905 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2906 void i915_gem_free_object(struct drm_gem_object *obj);
2908 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2910 if (!atomic_read(&i915->mm.free_count))
2913 /* A single pass should suffice to release all the freed objects (along
2914 * most call paths) , but be a little more paranoid in that freeing
2915 * the objects does take a little amount of time, during which the rcu
2916 * callbacks could have added new objects into the freed list, and
2917 * armed the work again.
2921 } while (flush_work(&i915->mm.free_work));
2924 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2927 * Similar to objects above (see i915_gem_drain_freed-objects), in
2928 * general we have workers that are armed by RCU and then rearm
2929 * themselves in their callbacks. To be paranoid, we need to
2930 * drain the workqueue a second time after waiting for the RCU
2931 * grace period so that we catch work queued via RCU from the first
2932 * pass. As neither drain_workqueue() nor flush_workqueue() report
2933 * a result, we make an assumption that we only don't require more
2934 * than 2 passes to catch all recursive RCU delayed work.
2940 drain_workqueue(i915->wq);
2944 struct i915_vma * __must_check
2945 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2946 const struct i915_ggtt_view *view,
2951 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2952 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2954 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2956 static inline int __sg_page_count(const struct scatterlist *sg)
2958 return sg->length >> PAGE_SHIFT;
2961 struct scatterlist *
2962 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2963 unsigned int n, unsigned int *offset);
2966 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2970 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2974 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2977 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2978 struct sg_table *pages,
2979 unsigned int sg_page_sizes);
2980 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2982 static inline int __must_check
2983 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2985 might_lock(&obj->mm.lock);
2987 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2990 return __i915_gem_object_get_pages(obj);
2994 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2996 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
3000 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3002 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3004 atomic_inc(&obj->mm.pages_pin_count);
3008 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3010 return atomic_read(&obj->mm.pages_pin_count);
3014 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3016 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3017 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3019 atomic_dec(&obj->mm.pages_pin_count);
3023 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3025 __i915_gem_object_unpin_pages(obj);
3028 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3033 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3034 enum i915_mm_subclass subclass);
3035 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3037 enum i915_map_type {
3040 #define I915_MAP_OVERRIDE BIT(31)
3041 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3042 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3046 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3047 * @obj: the object to map into kernel address space
3048 * @type: the type of mapping, used to select pgprot_t
3050 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3051 * pages and then returns a contiguous mapping of the backing storage into
3052 * the kernel address space. Based on the @type of mapping, the PTE will be
3053 * set to either WriteBack or WriteCombine (via pgprot_t).
3055 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3056 * mapping is no longer required.
3058 * Returns the pointer through which to access the mapped object, or an
3059 * ERR_PTR() on error.
3061 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3062 enum i915_map_type type);
3065 * i915_gem_object_unpin_map - releases an earlier mapping
3066 * @obj: the object to unmap
3068 * After pinning the object and mapping its pages, once you are finished
3069 * with your access, call i915_gem_object_unpin_map() to release the pin
3070 * upon the mapping. Once the pin count reaches zero, that mapping may be
3073 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3075 i915_gem_object_unpin_pages(obj);
3078 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3079 unsigned int *needs_clflush);
3080 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3081 unsigned int *needs_clflush);
3082 #define CLFLUSH_BEFORE BIT(0)
3083 #define CLFLUSH_AFTER BIT(1)
3084 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3087 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3089 i915_gem_object_unpin_pages(obj);
3092 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3093 int __must_check i915_vma_move_to_active(struct i915_vma *vma,
3094 struct i915_request *rq,
3095 unsigned int flags);
3096 int i915_gem_dumb_create(struct drm_file *file_priv,
3097 struct drm_device *dev,
3098 struct drm_mode_create_dumb *args);
3099 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3100 uint32_t handle, uint64_t *offset);
3101 int i915_gem_mmap_gtt_version(void);
3103 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3104 struct drm_i915_gem_object *new,
3105 unsigned frontbuffer_bits);
3107 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3109 struct i915_request *
3110 i915_gem_find_active_request(struct intel_engine_cs *engine);
3112 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3114 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3117 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3119 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3122 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3124 return unlikely(test_bit(I915_WEDGED, &error->flags));
3127 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3129 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3132 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3134 return READ_ONCE(error->reset_count);
3137 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3138 struct intel_engine_cs *engine)
3140 return READ_ONCE(error->reset_engine_count[engine->id]);
3143 struct i915_request *
3144 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3145 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3146 void i915_gem_reset(struct drm_i915_private *dev_priv,
3147 unsigned int stalled_mask);
3148 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3149 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3150 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3151 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3152 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3153 struct i915_request *request,
3156 void i915_gem_init_mmio(struct drm_i915_private *i915);
3157 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3158 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3159 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3160 void i915_gem_fini(struct drm_i915_private *dev_priv);
3161 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3162 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3163 unsigned int flags);
3164 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3165 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3166 void i915_gem_resume(struct drm_i915_private *dev_priv);
3167 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3168 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3171 struct intel_rps_client *rps);
3172 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3174 const struct i915_sched_attr *attr);
3175 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3178 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3180 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3182 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3183 struct i915_vma * __must_check
3184 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3186 const struct i915_ggtt_view *view,
3187 unsigned int flags);
3188 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3189 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3191 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3192 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3194 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3195 enum i915_cache_level cache_level);
3197 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3198 struct dma_buf *dma_buf);
3200 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3201 struct drm_gem_object *gem_obj, int flags);
3203 static inline struct i915_hw_ppgtt *
3204 i915_vm_to_ppgtt(struct i915_address_space *vm)
3206 return container_of(vm, struct i915_hw_ppgtt, vm);
3209 /* i915_gem_fence_reg.c */
3210 struct drm_i915_fence_reg *
3211 i915_reserve_fence(struct drm_i915_private *dev_priv);
3212 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3214 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3215 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3217 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3218 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3219 struct sg_table *pages);
3220 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3221 struct sg_table *pages);
3223 static inline struct i915_gem_context *
3224 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3226 return idr_find(&file_priv->context_idr, id);
3229 static inline struct i915_gem_context *
3230 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3232 struct i915_gem_context *ctx;
3235 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3236 if (ctx && !kref_get_unless_zero(&ctx->ref))
3243 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3244 struct drm_file *file);
3245 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3246 struct drm_file *file);
3247 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3248 struct drm_file *file);
3249 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3250 struct i915_gem_context *ctx,
3251 uint32_t *reg_state);
3253 /* i915_gem_evict.c */
3254 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3255 u64 min_size, u64 alignment,
3256 unsigned cache_level,
3259 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3260 struct drm_mm_node *node,
3261 unsigned int flags);
3262 int i915_gem_evict_vm(struct i915_address_space *vm);
3264 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3266 /* belongs in i915_gem_gtt.h */
3267 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3270 if (INTEL_GEN(dev_priv) < 6)
3271 intel_gtt_chipset_flush();
3274 /* i915_gem_stolen.c */
3275 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3276 struct drm_mm_node *node, u64 size,
3277 unsigned alignment);
3278 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3279 struct drm_mm_node *node, u64 size,
3280 unsigned alignment, u64 start,
3282 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3283 struct drm_mm_node *node);
3284 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3285 void i915_gem_cleanup_stolen(struct drm_device *dev);
3286 struct drm_i915_gem_object *
3287 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3288 resource_size_t size);
3289 struct drm_i915_gem_object *
3290 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3291 resource_size_t stolen_offset,
3292 resource_size_t gtt_offset,
3293 resource_size_t size);
3295 /* i915_gem_internal.c */
3296 struct drm_i915_gem_object *
3297 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3300 /* i915_gem_shrinker.c */
3301 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3302 unsigned long target,
3303 unsigned long *nr_scanned,
3305 #define I915_SHRINK_PURGEABLE 0x1
3306 #define I915_SHRINK_UNBOUND 0x2
3307 #define I915_SHRINK_BOUND 0x4
3308 #define I915_SHRINK_ACTIVE 0x8
3309 #define I915_SHRINK_VMAPS 0x10
3310 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3311 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3312 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3315 /* i915_gem_tiling.c */
3316 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3318 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3320 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3321 i915_gem_object_is_tiled(obj);
3324 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3325 unsigned int tiling, unsigned int stride);
3326 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3327 unsigned int tiling, unsigned int stride);
3329 /* i915_debugfs.c */
3330 #ifdef CONFIG_DEBUG_FS
3331 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3332 int i915_debugfs_connector_add(struct drm_connector *connector);
3333 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3335 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3336 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3338 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3341 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3343 /* i915_cmd_parser.c */
3344 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3345 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3346 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3347 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3348 struct drm_i915_gem_object *batch_obj,
3349 struct drm_i915_gem_object *shadow_batch_obj,
3350 u32 batch_start_offset,
3355 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3356 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3357 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3358 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3360 /* i915_suspend.c */
3361 extern int i915_save_state(struct drm_i915_private *dev_priv);
3362 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3365 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3366 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3368 /* intel_lpe_audio.c */
3369 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3370 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3371 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3372 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3373 enum pipe pipe, enum port port,
3374 const void *eld, int ls_clock, bool dp_output);
3377 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3378 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3379 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3381 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3383 extern struct i2c_adapter *
3384 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3385 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3386 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3387 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3389 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3391 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3394 void intel_bios_init(struct drm_i915_private *dev_priv);
3395 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3396 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3397 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3398 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3399 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3400 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3401 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3402 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3403 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3405 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3410 extern void intel_register_dsm_handler(void);
3411 extern void intel_unregister_dsm_handler(void);
3413 static inline void intel_register_dsm_handler(void) { return; }
3414 static inline void intel_unregister_dsm_handler(void) { return; }
3415 #endif /* CONFIG_ACPI */
3417 /* intel_device_info.c */
3418 static inline struct intel_device_info *
3419 mkwrite_device_info(struct drm_i915_private *dev_priv)
3421 return (struct intel_device_info *)&dev_priv->info;
3425 extern void intel_modeset_init_hw(struct drm_device *dev);
3426 extern int intel_modeset_init(struct drm_device *dev);
3427 extern void intel_modeset_cleanup(struct drm_device *dev);
3428 extern int intel_connector_register(struct drm_connector *);
3429 extern void intel_connector_unregister(struct drm_connector *);
3430 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3432 extern void intel_display_resume(struct drm_device *dev);
3433 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3434 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3435 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3436 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3437 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3438 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3441 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3442 struct drm_file *file);
3445 extern struct intel_overlay_error_state *
3446 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3447 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3448 struct intel_overlay_error_state *error);
3450 extern struct intel_display_error_state *
3451 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3452 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3453 struct intel_display_error_state *error);
3455 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3456 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3457 u32 val, int fast_timeout_us,
3458 int slow_timeout_ms);
3459 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3460 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3462 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3463 u32 reply_mask, u32 reply, int timeout_base_ms);
3465 /* intel_sideband.c */
3466 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3467 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3468 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3469 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3470 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3471 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3472 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3473 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3474 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3475 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3476 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3477 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3478 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3479 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3480 enum intel_sbi_destination destination);
3481 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3482 enum intel_sbi_destination destination);
3483 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3484 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3486 /* intel_dpio_phy.c */
3487 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3488 enum dpio_phy *phy, enum dpio_channel *ch);
3489 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3490 enum port port, u32 margin, u32 scale,
3491 u32 enable, u32 deemphasis);
3492 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3493 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3494 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3496 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3498 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3499 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3500 uint8_t lane_lat_optim_mask);
3501 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3503 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3504 u32 deemph_reg_value, u32 margin_reg_value,
3505 bool uniq_trans_scale);
3506 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3507 const struct intel_crtc_state *crtc_state,
3509 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3510 const struct intel_crtc_state *crtc_state);
3511 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3512 const struct intel_crtc_state *crtc_state);
3513 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3514 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3515 const struct intel_crtc_state *old_crtc_state);
3517 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3518 u32 demph_reg_value, u32 preemph_reg_value,
3519 u32 uniqtranscale_reg_value, u32 tx3_demph);
3520 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3521 const struct intel_crtc_state *crtc_state);
3522 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3523 const struct intel_crtc_state *crtc_state);
3524 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3525 const struct intel_crtc_state *old_crtc_state);
3527 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3528 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3529 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3530 const i915_reg_t reg);
3532 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3534 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3535 const i915_reg_t reg)
3537 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3540 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3541 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3543 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3544 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3545 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3546 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3548 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3549 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3550 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3551 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3553 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3554 * will be implemented using 2 32-bit writes in an arbitrary order with
3555 * an arbitrary delay between them. This can cause the hardware to
3556 * act upon the intermediate value, possibly leading to corruption and
3557 * machine death. For this reason we do not support I915_WRITE64, or
3558 * dev_priv->uncore.funcs.mmio_writeq.
3560 * When reading a 64-bit value as two 32-bit values, the delay may cause
3561 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3562 * occasionally a 64-bit register does not actualy support a full readq
3563 * and must be read using two 32-bit reads.
3565 * You have been warned.
3567 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3569 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3570 u32 upper, lower, old_upper, loop = 0; \
3571 upper = I915_READ(upper_reg); \
3573 old_upper = upper; \
3574 lower = I915_READ(lower_reg); \
3575 upper = I915_READ(upper_reg); \
3576 } while (upper != old_upper && loop++ < 2); \
3577 (u64)upper << 32 | lower; })
3579 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3580 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3582 #define __raw_read(x, s) \
3583 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3586 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3589 #define __raw_write(x, s) \
3590 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3591 i915_reg_t reg, uint##x##_t val) \
3593 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3608 /* These are untraced mmio-accessors that are only valid to be used inside
3609 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3612 * Think twice, and think again, before using these.
3614 * As an example, these accessors can possibly be used between:
3616 * spin_lock_irq(&dev_priv->uncore.lock);
3617 * intel_uncore_forcewake_get__locked();
3621 * intel_uncore_forcewake_put__locked();
3622 * spin_unlock_irq(&dev_priv->uncore.lock);
3625 * Note: some registers may not need forcewake held, so
3626 * intel_uncore_forcewake_{get,put} can be omitted, see
3627 * intel_uncore_forcewake_for_reg().
3629 * Certain architectures will die if the same cacheline is concurrently accessed
3630 * by different clients (e.g. on Ivybridge). Access to registers should
3631 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3632 * a more localised lock guarding all access to that bank of registers.
3634 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3635 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3636 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3637 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3639 /* "Broadcast RGB" property */
3640 #define INTEL_BROADCAST_RGB_AUTO 0
3641 #define INTEL_BROADCAST_RGB_FULL 1
3642 #define INTEL_BROADCAST_RGB_LIMITED 2
3644 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3646 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3647 return VLV_VGACNTRL;
3648 else if (INTEL_GEN(dev_priv) >= 5)
3649 return CPU_VGACNTRL;
3654 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3656 unsigned long j = msecs_to_jiffies(m);
3658 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3661 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3663 /* nsecs_to_jiffies64() does not guard against overflow */
3664 if (NSEC_PER_SEC % HZ &&
3665 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3666 return MAX_JIFFY_OFFSET;
3668 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3672 * If you need to wait X milliseconds between events A and B, but event B
3673 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3674 * when event A happened, then just before event B you call this function and
3675 * pass the timestamp as the first argument, and X as the second argument.
3678 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3680 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3683 * Don't re-read the value of "jiffies" every time since it may change
3684 * behind our back and break the math.
3686 tmp_jiffies = jiffies;
3687 target_jiffies = timestamp_jiffies +
3688 msecs_to_jiffies_timeout(to_wait_ms);
3690 if (time_after(target_jiffies, tmp_jiffies)) {
3691 remaining_jiffies = target_jiffies - tmp_jiffies;
3692 while (remaining_jiffies)
3694 schedule_timeout_uninterruptible(remaining_jiffies);
3699 __i915_request_irq_complete(const struct i915_request *rq)
3701 struct intel_engine_cs *engine = rq->engine;
3704 /* Note that the engine may have wrapped around the seqno, and
3705 * so our request->global_seqno will be ahead of the hardware,
3706 * even though it completed the request before wrapping. We catch
3707 * this by kicking all the waiters before resetting the seqno
3708 * in hardware, and also signal the fence.
3710 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3713 /* The request was dequeued before we were awoken. We check after
3714 * inspecting the hw to confirm that this was the same request
3715 * that generated the HWS update. The memory barriers within
3716 * the request execution are sufficient to ensure that a check
3717 * after reading the value from hw matches this request.
3719 seqno = i915_request_global_seqno(rq);
3723 /* Before we do the heavier coherent read of the seqno,
3724 * check the value (hopefully) in the CPU cacheline.
3726 if (__i915_request_completed(rq, seqno))
3729 /* Ensure our read of the seqno is coherent so that we
3730 * do not "miss an interrupt" (i.e. if this is the last
3731 * request and the seqno write from the GPU is not visible
3732 * by the time the interrupt fires, we will see that the
3733 * request is incomplete and go back to sleep awaiting
3734 * another interrupt that will never come.)
3736 * Strictly, we only need to do this once after an interrupt,
3737 * but it is easier and safer to do it every time the waiter
3740 if (engine->irq_seqno_barrier &&
3741 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3742 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3744 /* The ordering of irq_posted versus applying the barrier
3745 * is crucial. The clearing of the current irq_posted must
3746 * be visible before we perform the barrier operation,
3747 * such that if a subsequent interrupt arrives, irq_posted
3748 * is reasserted and our task rewoken (which causes us to
3749 * do another __i915_request_irq_complete() immediately
3750 * and reapply the barrier). Conversely, if the clear
3751 * occurs after the barrier, then an interrupt that arrived
3752 * whilst we waited on the barrier would not trigger a
3753 * barrier on the next pass, and the read may not see the
3756 engine->irq_seqno_barrier(engine);
3758 /* If we consume the irq, but we are no longer the bottom-half,
3759 * the real bottom-half may not have serialised their own
3760 * seqno check with the irq-barrier (i.e. may have inspected
3761 * the seqno before we believe it coherent since they see
3762 * irq_posted == false but we are still running).
3764 spin_lock_irq(&b->irq_lock);
3765 if (b->irq_wait && b->irq_wait->tsk != current)
3766 /* Note that if the bottom-half is changed as we
3767 * are sending the wake-up, the new bottom-half will
3768 * be woken by whomever made the change. We only have
3769 * to worry about when we steal the irq-posted for
3772 wake_up_process(b->irq_wait->tsk);
3773 spin_unlock_irq(&b->irq_lock);
3775 if (__i915_request_completed(rq, seqno))
3782 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3783 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3785 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3786 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3787 * perform the operation. To check beforehand, pass in the parameters to
3788 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3789 * you only need to pass in the minor offsets, page-aligned pointers are
3792 * For just checking for SSE4.1, in the foreknowledge that the future use
3793 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3795 #define i915_can_memcpy_from_wc(dst, src, len) \
3796 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3798 #define i915_has_memcpy_from_wc() \
3799 i915_memcpy_from_wc(NULL, NULL, 0)
3802 int remap_io_mapping(struct vm_area_struct *vma,
3803 unsigned long addr, unsigned long pfn, unsigned long size,
3804 struct io_mapping *iomap);
3806 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3808 if (INTEL_GEN(i915) >= 10)
3809 return CNL_HWS_CSB_WRITE_INDEX;
3811 return I915_HWS_CSB_WRITE_INDEX;