1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/apple-gmux.h>
39 #include <linux/console.h>
40 #include <linux/module.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/vgaarb.h>
43 #include <linux/vga_switcheroo.h>
44 #include <drm/drm_crtc_helper.h>
46 static struct drm_driver driver;
48 #define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
55 #define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
60 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
63 #define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
66 #define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
70 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
72 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
74 static const struct intel_device_info intel_i830_info = {
75 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
82 static const struct intel_device_info intel_845g_info = {
83 .gen = 2, .num_pipes = 1,
84 .has_overlay = 1, .overlay_needs_physical = 1,
85 .ring_mask = RENDER_RING,
86 GEN_DEFAULT_PIPEOFFSETS,
90 static const struct intel_device_info intel_i85x_info = {
91 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
92 .cursor_needs_physical = 1,
93 .has_overlay = 1, .overlay_needs_physical = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
100 static const struct intel_device_info intel_i865g_info = {
101 .gen = 2, .num_pipes = 1,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
108 static const struct intel_device_info intel_i915g_info = {
109 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
110 .has_overlay = 1, .overlay_needs_physical = 1,
111 .ring_mask = RENDER_RING,
112 GEN_DEFAULT_PIPEOFFSETS,
115 static const struct intel_device_info intel_i915gm_info = {
116 .gen = 3, .is_mobile = 1, .num_pipes = 2,
117 .cursor_needs_physical = 1,
118 .has_overlay = 1, .overlay_needs_physical = 1,
121 .ring_mask = RENDER_RING,
122 GEN_DEFAULT_PIPEOFFSETS,
125 static const struct intel_device_info intel_i945g_info = {
126 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
127 .has_overlay = 1, .overlay_needs_physical = 1,
128 .ring_mask = RENDER_RING,
129 GEN_DEFAULT_PIPEOFFSETS,
132 static const struct intel_device_info intel_i945gm_info = {
133 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
134 .has_hotplug = 1, .cursor_needs_physical = 1,
135 .has_overlay = 1, .overlay_needs_physical = 1,
138 .ring_mask = RENDER_RING,
139 GEN_DEFAULT_PIPEOFFSETS,
143 static const struct intel_device_info intel_i965g_info = {
144 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
147 .ring_mask = RENDER_RING,
148 GEN_DEFAULT_PIPEOFFSETS,
152 static const struct intel_device_info intel_i965gm_info = {
153 .gen = 4, .is_crestline = 1, .num_pipes = 2,
154 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
157 .ring_mask = RENDER_RING,
158 GEN_DEFAULT_PIPEOFFSETS,
162 static const struct intel_device_info intel_g33_info = {
163 .gen = 3, .is_g33 = 1, .num_pipes = 2,
164 .need_gfx_hws = 1, .has_hotplug = 1,
166 .ring_mask = RENDER_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
171 static const struct intel_device_info intel_g45_info = {
172 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
173 .has_pipe_cxsr = 1, .has_hotplug = 1,
174 .ring_mask = RENDER_RING | BSD_RING,
175 GEN_DEFAULT_PIPEOFFSETS,
179 static const struct intel_device_info intel_gm45_info = {
180 .gen = 4, .is_g4x = 1, .num_pipes = 2,
181 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
182 .has_pipe_cxsr = 1, .has_hotplug = 1,
184 .ring_mask = RENDER_RING | BSD_RING,
185 GEN_DEFAULT_PIPEOFFSETS,
189 static const struct intel_device_info intel_pineview_info = {
190 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
193 GEN_DEFAULT_PIPEOFFSETS,
197 static const struct intel_device_info intel_ironlake_d_info = {
198 .gen = 5, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
200 .ring_mask = RENDER_RING | BSD_RING,
201 GEN_DEFAULT_PIPEOFFSETS,
205 static const struct intel_device_info intel_ironlake_m_info = {
206 .gen = 5, .is_mobile = 1, .num_pipes = 2,
207 .need_gfx_hws = 1, .has_hotplug = 1,
209 .ring_mask = RENDER_RING | BSD_RING,
210 GEN_DEFAULT_PIPEOFFSETS,
214 static const struct intel_device_info intel_sandybridge_d_info = {
215 .gen = 6, .num_pipes = 2,
216 .need_gfx_hws = 1, .has_hotplug = 1,
218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
220 GEN_DEFAULT_PIPEOFFSETS,
224 static const struct intel_device_info intel_sandybridge_m_info = {
225 .gen = 6, .is_mobile = 1, .num_pipes = 2,
226 .need_gfx_hws = 1, .has_hotplug = 1,
228 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
230 GEN_DEFAULT_PIPEOFFSETS,
234 #define GEN7_FEATURES \
235 .gen = 7, .num_pipes = 3, \
236 .need_gfx_hws = 1, .has_hotplug = 1, \
238 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
240 GEN_DEFAULT_PIPEOFFSETS, \
243 static const struct intel_device_info intel_ivybridge_d_info = {
248 static const struct intel_device_info intel_ivybridge_m_info = {
254 static const struct intel_device_info intel_ivybridge_q_info = {
257 .num_pipes = 0, /* legal, last one wins */
260 #define VLV_FEATURES \
261 .gen = 7, .num_pipes = 2, \
262 .need_gfx_hws = 1, .has_hotplug = 1, \
263 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
264 .display_mmio_offset = VLV_DISPLAY_BASE, \
265 GEN_DEFAULT_PIPEOFFSETS, \
268 static const struct intel_device_info intel_valleyview_m_info = {
274 static const struct intel_device_info intel_valleyview_d_info = {
279 #define HSW_FEATURES \
281 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
285 static const struct intel_device_info intel_haswell_d_info = {
290 static const struct intel_device_info intel_haswell_m_info = {
296 #define BDW_FEATURES \
300 static const struct intel_device_info intel_broadwell_d_info = {
305 static const struct intel_device_info intel_broadwell_m_info = {
307 .gen = 8, .is_mobile = 1,
310 static const struct intel_device_info intel_broadwell_gt3d_info = {
313 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
316 static const struct intel_device_info intel_broadwell_gt3m_info = {
318 .gen = 8, .is_mobile = 1,
319 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
322 static const struct intel_device_info intel_cherryview_info = {
323 .gen = 8, .num_pipes = 3,
324 .need_gfx_hws = 1, .has_hotplug = 1,
325 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
327 .display_mmio_offset = VLV_DISPLAY_BASE,
333 static const struct intel_device_info intel_skylake_info = {
339 static const struct intel_device_info intel_skylake_gt3_info = {
343 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
346 static const struct intel_device_info intel_broxton_info = {
350 .need_gfx_hws = 1, .has_hotplug = 1,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
356 GEN_DEFAULT_PIPEOFFSETS,
361 static const struct intel_device_info intel_kabylake_info = {
367 static const struct intel_device_info intel_kabylake_gt3_info = {
371 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
375 * Make sure any device matches here are from most specific to most
376 * general. For example, since the Quanta match is based on the subsystem
377 * and subvendor IDs, we need it to come before the more general IVB
378 * PCI ID matches, otherwise we'll use the wrong info struct above.
380 static const struct pci_device_id pciidlist[] = {
381 INTEL_I830_IDS(&intel_i830_info),
382 INTEL_I845G_IDS(&intel_845g_info),
383 INTEL_I85X_IDS(&intel_i85x_info),
384 INTEL_I865G_IDS(&intel_i865g_info),
385 INTEL_I915G_IDS(&intel_i915g_info),
386 INTEL_I915GM_IDS(&intel_i915gm_info),
387 INTEL_I945G_IDS(&intel_i945g_info),
388 INTEL_I945GM_IDS(&intel_i945gm_info),
389 INTEL_I965G_IDS(&intel_i965g_info),
390 INTEL_G33_IDS(&intel_g33_info),
391 INTEL_I965GM_IDS(&intel_i965gm_info),
392 INTEL_GM45_IDS(&intel_gm45_info),
393 INTEL_G45_IDS(&intel_g45_info),
394 INTEL_PINEVIEW_IDS(&intel_pineview_info),
395 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
396 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
397 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
398 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
399 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
400 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
401 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
402 INTEL_HSW_D_IDS(&intel_haswell_d_info),
403 INTEL_HSW_M_IDS(&intel_haswell_m_info),
404 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
405 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
406 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
407 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
408 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
409 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
410 INTEL_CHV_IDS(&intel_cherryview_info),
411 INTEL_SKL_GT1_IDS(&intel_skylake_info),
412 INTEL_SKL_GT2_IDS(&intel_skylake_info),
413 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
414 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
415 INTEL_BXT_IDS(&intel_broxton_info),
416 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
417 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
418 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
419 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
423 MODULE_DEVICE_TABLE(pci, pciidlist);
425 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
427 enum intel_pch ret = PCH_NOP;
430 * In a virtualized passthrough environment we can be in a
431 * setup where the ISA bridge is not able to be passed through.
432 * In this case, a south bridge can be emulated and we have to
433 * make an educated guess as to which PCH is really there.
438 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
439 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
441 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
442 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
444 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
445 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
447 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
453 void intel_detect_pch(struct drm_device *dev)
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct pci_dev *pch = NULL;
458 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
459 * (which really amounts to a PCH but no South Display).
461 if (INTEL_INFO(dev)->num_pipes == 0) {
462 dev_priv->pch_type = PCH_NOP;
467 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
468 * make graphics device passthrough work easy for VMM, that only
469 * need to expose ISA bridge to let driver know the real hardware
470 * underneath. This is a requirement from virtualization team.
472 * In some virtualized environments (e.g. XEN), there is irrelevant
473 * ISA bridge in the system. To work reliably, we should scan trhough
474 * all the ISA bridge devices and check for the first match, instead
475 * of only checking the first one.
477 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
478 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
479 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
480 dev_priv->pch_id = id;
482 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
483 dev_priv->pch_type = PCH_IBX;
484 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
485 WARN_ON(!IS_GEN5(dev));
486 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
487 dev_priv->pch_type = PCH_CPT;
488 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
489 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
490 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
491 /* PantherPoint is CPT compatible */
492 dev_priv->pch_type = PCH_CPT;
493 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
494 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
495 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
496 dev_priv->pch_type = PCH_LPT;
497 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
498 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
499 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
500 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
501 dev_priv->pch_type = PCH_LPT;
502 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
503 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
504 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
505 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
506 dev_priv->pch_type = PCH_SPT;
507 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
508 WARN_ON(!IS_SKYLAKE(dev) &&
510 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
511 dev_priv->pch_type = PCH_SPT;
512 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
513 WARN_ON(!IS_SKYLAKE(dev) &&
515 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
516 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
517 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
518 pch->subsystem_vendor == 0x1af4 &&
519 pch->subsystem_device == 0x1100)) {
520 dev_priv->pch_type = intel_virt_detect_pch(dev);
528 DRM_DEBUG_KMS("No PCH found.\n");
533 bool i915_semaphore_is_enabled(struct drm_device *dev)
535 if (INTEL_INFO(dev)->gen < 6)
538 if (i915.semaphores >= 0)
539 return i915.semaphores;
541 /* TODO: make semaphores and Execlists play nicely together */
542 if (i915.enable_execlists)
545 #ifdef CONFIG_INTEL_IOMMU
546 /* Enable semaphores on SNB when IO remapping is off */
547 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
554 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
556 struct drm_device *dev = dev_priv->dev;
557 struct intel_encoder *encoder;
559 drm_modeset_lock_all(dev);
560 for_each_intel_encoder(dev, encoder)
561 if (encoder->suspend)
562 encoder->suspend(encoder);
563 drm_modeset_unlock_all(dev);
566 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
568 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
570 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
572 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
573 if (acpi_target_system_state() < ACPI_STATE_S3)
579 static int i915_drm_suspend(struct drm_device *dev)
581 struct drm_i915_private *dev_priv = dev->dev_private;
582 pci_power_t opregion_target_state;
585 /* ignore lid events during suspend */
586 mutex_lock(&dev_priv->modeset_restore_lock);
587 dev_priv->modeset_restore = MODESET_SUSPENDED;
588 mutex_unlock(&dev_priv->modeset_restore_lock);
590 disable_rpm_wakeref_asserts(dev_priv);
592 /* We do a lot of poking in a lot of registers, make sure they work
594 intel_display_set_init_power(dev_priv, true);
596 drm_kms_helper_poll_disable(dev);
598 pci_save_state(dev->pdev);
600 error = i915_gem_suspend(dev);
602 dev_err(&dev->pdev->dev,
603 "GEM idle failed, resume might fail\n");
607 intel_guc_suspend(dev);
609 intel_suspend_gt_powersave(dev);
611 intel_display_suspend(dev);
613 intel_dp_mst_suspend(dev);
615 intel_runtime_pm_disable_interrupts(dev_priv);
616 intel_hpd_cancel_work(dev_priv);
618 intel_suspend_encoders(dev_priv);
620 intel_suspend_hw(dev);
622 i915_gem_suspend_gtt_mappings(dev);
624 i915_save_state(dev);
626 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
627 intel_opregion_notify_adapter(dev, opregion_target_state);
629 intel_uncore_forcewake_reset(dev, false);
630 intel_opregion_fini(dev);
632 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
634 dev_priv->suspend_count++;
636 intel_display_set_init_power(dev_priv, false);
638 intel_csr_ucode_suspend(dev_priv);
641 enable_rpm_wakeref_asserts(dev_priv);
646 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
648 struct drm_i915_private *dev_priv = drm_dev->dev_private;
652 disable_rpm_wakeref_asserts(dev_priv);
654 fw_csr = !IS_BROXTON(dev_priv) &&
655 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
657 * In case of firmware assisted context save/restore don't manually
658 * deinit the power domains. This also means the CSR/DMC firmware will
659 * stay active, it will power down any HW resources as required and
660 * also enable deeper system power states that would be blocked if the
661 * firmware was inactive.
664 intel_power_domains_suspend(dev_priv);
667 if (IS_BROXTON(dev_priv))
668 bxt_enable_dc9(dev_priv);
669 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
670 hsw_enable_pc8(dev_priv);
671 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
672 ret = vlv_suspend_complete(dev_priv);
675 DRM_ERROR("Suspend complete failed: %d\n", ret);
677 intel_power_domains_init_hw(dev_priv, true);
682 pci_disable_device(drm_dev->pdev);
684 * During hibernation on some platforms the BIOS may try to access
685 * the device even though it's already in D3 and hang the machine. So
686 * leave the device in D0 on those platforms and hope the BIOS will
687 * power down the device properly. The issue was seen on multiple old
688 * GENs with different BIOS vendors, so having an explicit blacklist
689 * is inpractical; apply the workaround on everything pre GEN6. The
690 * platforms where the issue was seen:
691 * Lenovo Thinkpad X301, X61s, X60, T60, X41
695 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
696 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
698 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
701 enable_rpm_wakeref_asserts(dev_priv);
706 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
710 if (!dev || !dev->dev_private) {
711 DRM_ERROR("dev: %p\n", dev);
712 DRM_ERROR("DRM not initialized, aborting suspend.\n");
716 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
717 state.event != PM_EVENT_FREEZE))
720 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
723 error = i915_drm_suspend(dev);
727 return i915_drm_suspend_late(dev, false);
730 static int i915_drm_resume(struct drm_device *dev)
732 struct drm_i915_private *dev_priv = dev->dev_private;
734 disable_rpm_wakeref_asserts(dev_priv);
736 intel_csr_ucode_resume(dev_priv);
738 mutex_lock(&dev->struct_mutex);
739 i915_gem_restore_gtt_mappings(dev);
740 mutex_unlock(&dev->struct_mutex);
742 i915_restore_state(dev);
743 intel_opregion_setup(dev);
745 intel_init_pch_refclk(dev);
746 drm_mode_config_reset(dev);
749 * Interrupts have to be enabled before any batches are run. If not the
750 * GPU will hang. i915_gem_init_hw() will initiate batches to
751 * update/restore the context.
753 * Modeset enabling in intel_modeset_init_hw() also needs working
756 intel_runtime_pm_enable_interrupts(dev_priv);
758 mutex_lock(&dev->struct_mutex);
759 if (i915_gem_init_hw(dev)) {
760 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
761 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
763 mutex_unlock(&dev->struct_mutex);
765 intel_guc_resume(dev);
767 intel_modeset_init_hw(dev);
769 spin_lock_irq(&dev_priv->irq_lock);
770 if (dev_priv->display.hpd_irq_setup)
771 dev_priv->display.hpd_irq_setup(dev);
772 spin_unlock_irq(&dev_priv->irq_lock);
774 intel_dp_mst_resume(dev);
776 intel_display_resume(dev);
779 * ... but also need to make sure that hotplug processing
780 * doesn't cause havoc. Like in the driver load code we don't
781 * bother with the tiny race here where we might loose hotplug
784 intel_hpd_init(dev_priv);
785 /* Config may have changed between suspend and resume */
786 drm_helper_hpd_irq_event(dev);
788 intel_opregion_init(dev);
790 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
792 mutex_lock(&dev_priv->modeset_restore_lock);
793 dev_priv->modeset_restore = MODESET_DONE;
794 mutex_unlock(&dev_priv->modeset_restore_lock);
796 intel_opregion_notify_adapter(dev, PCI_D0);
798 drm_kms_helper_poll_enable(dev);
800 enable_rpm_wakeref_asserts(dev_priv);
805 static int i915_drm_resume_early(struct drm_device *dev)
807 struct drm_i915_private *dev_priv = dev->dev_private;
811 * We have a resume ordering issue with the snd-hda driver also
812 * requiring our device to be power up. Due to the lack of a
813 * parent/child relationship we currently solve this with an early
816 * FIXME: This should be solved with a special hdmi sink device or
817 * similar so that power domains can be employed.
821 * Note that we need to set the power state explicitly, since we
822 * powered off the device during freeze and the PCI core won't power
823 * it back up for us during thaw. Powering off the device during
824 * freeze is not a hard requirement though, and during the
825 * suspend/resume phases the PCI core makes sure we get here with the
826 * device powered on. So in case we change our freeze logic and keep
827 * the device powered we can also remove the following set power state
830 ret = pci_set_power_state(dev->pdev, PCI_D0);
832 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
837 * Note that pci_enable_device() first enables any parent bridge
838 * device and only then sets the power state for this device. The
839 * bridge enabling is a nop though, since bridge devices are resumed
840 * first. The order of enabling power and enabling the device is
841 * imposed by the PCI core as described above, so here we preserve the
842 * same order for the freeze/thaw phases.
844 * TODO: eventually we should remove pci_disable_device() /
845 * pci_enable_enable_device() from suspend/resume. Due to how they
846 * depend on the device enable refcount we can't anyway depend on them
847 * disabling/enabling the device.
849 if (pci_enable_device(dev->pdev)) {
854 pci_set_master(dev->pdev);
856 disable_rpm_wakeref_asserts(dev_priv);
858 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
859 ret = vlv_resume_prepare(dev_priv, false);
861 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
864 intel_uncore_early_sanitize(dev, true);
866 if (IS_BROXTON(dev)) {
867 if (!dev_priv->suspended_to_idle)
868 gen9_sanitize_dc_state(dev_priv);
869 bxt_disable_dc9(dev_priv);
870 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
871 hsw_disable_pc8(dev_priv);
874 intel_uncore_sanitize(dev);
876 if (IS_BROXTON(dev_priv) ||
877 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
878 intel_power_domains_init_hw(dev_priv, true);
880 enable_rpm_wakeref_asserts(dev_priv);
883 dev_priv->suspended_to_idle = false;
888 int i915_resume_switcheroo(struct drm_device *dev)
892 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
895 ret = i915_drm_resume_early(dev);
899 return i915_drm_resume(dev);
903 * i915_reset - reset chip after a hang
904 * @dev: drm device to reset
906 * Reset the chip. Useful if a hang is detected. Returns zero on successful
907 * reset or otherwise an error code.
909 * Procedure is fairly simple:
910 * - reset the chip using the reset reg
911 * - re-init context state
912 * - re-init hardware status page
913 * - re-init ring buffer
914 * - re-init interrupt state
917 int i915_reset(struct drm_device *dev)
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 struct i915_gpu_error *error = &dev_priv->gpu_error;
921 unsigned reset_counter;
924 intel_reset_gt_powersave(dev);
926 mutex_lock(&dev->struct_mutex);
928 /* Clear any previous failed attempts at recovery. Time to try again. */
929 atomic_andnot(I915_WEDGED, &error->reset_counter);
931 /* Clear the reset-in-progress flag and increment the reset epoch. */
932 reset_counter = atomic_inc_return(&error->reset_counter);
933 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
940 ret = intel_gpu_reset(dev, ALL_ENGINES);
942 /* Also reset the gpu hangman. */
943 if (error->stop_rings != 0) {
944 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
945 error->stop_rings = 0;
946 if (ret == -ENODEV) {
947 DRM_INFO("Reset not implemented, but ignoring "
948 "error for simulated gpu hangs\n");
953 if (i915_stop_ring_allow_warn(dev_priv))
954 pr_notice("drm/i915: Resetting chip after gpu hang\n");
958 DRM_ERROR("Failed to reset chip: %i\n", ret);
960 DRM_DEBUG_DRIVER("GPU reset disabled\n");
964 intel_overlay_reset(dev_priv);
966 /* Ok, now get things going again... */
969 * Everything depends on having the GTT running, so we need to start
970 * there. Fortunately we don't need to do this unless we reset the
971 * chip at a PCI level.
973 * Next we need to restore the context, but we don't use those
976 * Ring buffer needs to be re-initialized in the KMS case, or if X
977 * was running at the time of the reset (i.e. we weren't VT
980 ret = i915_gem_init_hw(dev);
982 DRM_ERROR("Failed hw init on reset %d\n", ret);
986 mutex_unlock(&dev->struct_mutex);
989 * rps/rc6 re-init is necessary to restore state lost after the
990 * reset and the re-install of gt irqs. Skip for ironlake per
991 * previous concerns that it doesn't respond well to some forms
992 * of re-init after reset.
994 if (INTEL_INFO(dev)->gen > 5)
995 intel_enable_gt_powersave(dev);
1000 atomic_or(I915_WEDGED, &error->reset_counter);
1001 mutex_unlock(&dev->struct_mutex);
1005 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1007 struct intel_device_info *intel_info =
1008 (struct intel_device_info *) ent->driver_data;
1010 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
1011 DRM_INFO("This hardware requires preliminary hardware support.\n"
1012 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1016 /* Only bind to function 0 of the device. Early generations
1017 * used function 1 as a placeholder for multi-head. This causes
1018 * us confusion instead, especially on the systems where both
1019 * functions have the same PCI-ID!
1021 if (PCI_FUNC(pdev->devfn))
1025 * apple-gmux is needed on dual GPU MacBook Pro
1026 * to probe the panel if we're the inactive GPU.
1028 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
1029 apple_gmux_present() && pdev != vga_default_device() &&
1030 !vga_switcheroo_handler_flags())
1031 return -EPROBE_DEFER;
1033 return drm_get_pci_dev(pdev, ent, &driver);
1037 i915_pci_remove(struct pci_dev *pdev)
1039 struct drm_device *dev = pci_get_drvdata(pdev);
1044 static int i915_pm_suspend(struct device *dev)
1046 struct pci_dev *pdev = to_pci_dev(dev);
1047 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1049 if (!drm_dev || !drm_dev->dev_private) {
1050 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1054 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1057 return i915_drm_suspend(drm_dev);
1060 static int i915_pm_suspend_late(struct device *dev)
1062 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1065 * We have a suspend ordering issue with the snd-hda driver also
1066 * requiring our device to be power up. Due to the lack of a
1067 * parent/child relationship we currently solve this with an late
1070 * FIXME: This should be solved with a special hdmi sink device or
1071 * similar so that power domains can be employed.
1073 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1076 return i915_drm_suspend_late(drm_dev, false);
1079 static int i915_pm_poweroff_late(struct device *dev)
1081 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1083 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1086 return i915_drm_suspend_late(drm_dev, true);
1089 static int i915_pm_resume_early(struct device *dev)
1091 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1093 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1096 return i915_drm_resume_early(drm_dev);
1099 static int i915_pm_resume(struct device *dev)
1101 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1103 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1106 return i915_drm_resume(drm_dev);
1110 * Save all Gunit registers that may be lost after a D3 and a subsequent
1111 * S0i[R123] transition. The list of registers needing a save/restore is
1112 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1113 * registers in the following way:
1114 * - Driver: saved/restored by the driver
1115 * - Punit : saved/restored by the Punit firmware
1116 * - No, w/o marking: no need to save/restore, since the register is R/O or
1117 * used internally by the HW in a way that doesn't depend
1118 * keeping the content across a suspend/resume.
1119 * - Debug : used for debugging
1121 * We save/restore all registers marked with 'Driver', with the following
1123 * - Registers out of use, including also registers marked with 'Debug'.
1124 * These have no effect on the driver's operation, so we don't save/restore
1125 * them to reduce the overhead.
1126 * - Registers that are fully setup by an initialization function called from
1127 * the resume path. For example many clock gating and RPS/RC6 registers.
1128 * - Registers that provide the right functionality with their reset defaults.
1130 * TODO: Except for registers that based on the above 3 criteria can be safely
1131 * ignored, we save/restore all others, practically treating the HW context as
1132 * a black-box for the driver. Further investigation is needed to reduce the
1133 * saved/restored registers even further, by following the same 3 criteria.
1135 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1137 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1140 /* GAM 0x4000-0x4770 */
1141 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1142 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1143 s->arb_mode = I915_READ(ARB_MODE);
1144 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1145 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1147 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1148 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1150 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1151 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1153 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1154 s->ecochk = I915_READ(GAM_ECOCHK);
1155 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1156 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1158 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1160 /* MBC 0x9024-0x91D0, 0x8500 */
1161 s->g3dctl = I915_READ(VLV_G3DCTL);
1162 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1163 s->mbctl = I915_READ(GEN6_MBCTL);
1165 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1166 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1167 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1168 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1169 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1170 s->rstctl = I915_READ(GEN6_RSTCTL);
1171 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1173 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1174 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1175 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1176 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1177 s->ecobus = I915_READ(ECOBUS);
1178 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1179 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1180 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1181 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1182 s->rcedata = I915_READ(VLV_RCEDATA);
1183 s->spare2gh = I915_READ(VLV_SPAREG2H);
1185 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1186 s->gt_imr = I915_READ(GTIMR);
1187 s->gt_ier = I915_READ(GTIER);
1188 s->pm_imr = I915_READ(GEN6_PMIMR);
1189 s->pm_ier = I915_READ(GEN6_PMIER);
1191 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1192 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1194 /* GT SA CZ domain, 0x100000-0x138124 */
1195 s->tilectl = I915_READ(TILECTL);
1196 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1197 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1198 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1199 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1201 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1202 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1203 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1204 s->pcbr = I915_READ(VLV_PCBR);
1205 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1208 * Not saving any of:
1209 * DFT, 0x9800-0x9EC0
1210 * SARB, 0xB000-0xB1FC
1211 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1216 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1218 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1222 /* GAM 0x4000-0x4770 */
1223 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1224 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1225 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1226 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1227 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1229 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1230 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1232 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1233 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1235 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1236 I915_WRITE(GAM_ECOCHK, s->ecochk);
1237 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1238 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1240 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1242 /* MBC 0x9024-0x91D0, 0x8500 */
1243 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1244 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1245 I915_WRITE(GEN6_MBCTL, s->mbctl);
1247 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1248 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1249 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1250 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1251 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1252 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1253 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1255 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1256 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1257 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1258 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1259 I915_WRITE(ECOBUS, s->ecobus);
1260 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1261 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1262 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1263 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1264 I915_WRITE(VLV_RCEDATA, s->rcedata);
1265 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1267 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1268 I915_WRITE(GTIMR, s->gt_imr);
1269 I915_WRITE(GTIER, s->gt_ier);
1270 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1271 I915_WRITE(GEN6_PMIER, s->pm_ier);
1273 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1274 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1276 /* GT SA CZ domain, 0x100000-0x138124 */
1277 I915_WRITE(TILECTL, s->tilectl);
1278 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1280 * Preserve the GT allow wake and GFX force clock bit, they are not
1281 * be restored, as they are used to control the s0ix suspend/resume
1282 * sequence by the caller.
1284 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1285 val &= VLV_GTLC_ALLOWWAKEREQ;
1286 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1287 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1289 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1290 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1291 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1292 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1294 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1296 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1297 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1298 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1299 I915_WRITE(VLV_PCBR, s->pcbr);
1300 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1303 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1308 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1310 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1311 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1313 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1314 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1319 err = wait_for(COND, 20);
1321 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1322 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1328 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1333 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1334 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1336 val |= VLV_GTLC_ALLOWWAKEREQ;
1337 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1338 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1340 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1342 err = wait_for(COND, 1);
1344 DRM_ERROR("timeout disabling GT waking\n");
1349 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1356 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1357 val = wait_for_on ? mask : 0;
1358 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1362 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1364 I915_READ(VLV_GTLC_PW_STATUS));
1367 * RC6 transitioning can be delayed up to 2 msec (see
1368 * valleyview_enable_rps), use 3 msec for safety.
1370 err = wait_for(COND, 3);
1372 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1373 onoff(wait_for_on));
1379 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1381 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1384 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1385 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1388 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1394 * Bspec defines the following GT well on flags as debug only, so
1395 * don't treat them as hard failures.
1397 (void)vlv_wait_for_gt_wells(dev_priv, false);
1399 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1400 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1402 vlv_check_no_gt_access(dev_priv);
1404 err = vlv_force_gfx_clock(dev_priv, true);
1408 err = vlv_allow_gt_wake(dev_priv, false);
1412 if (!IS_CHERRYVIEW(dev_priv))
1413 vlv_save_gunit_s0ix_state(dev_priv);
1415 err = vlv_force_gfx_clock(dev_priv, false);
1422 /* For safety always re-enable waking and disable gfx clock forcing */
1423 vlv_allow_gt_wake(dev_priv, true);
1425 vlv_force_gfx_clock(dev_priv, false);
1430 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1433 struct drm_device *dev = dev_priv->dev;
1438 * If any of the steps fail just try to continue, that's the best we
1439 * can do at this point. Return the first error code (which will also
1440 * leave RPM permanently disabled).
1442 ret = vlv_force_gfx_clock(dev_priv, true);
1444 if (!IS_CHERRYVIEW(dev_priv))
1445 vlv_restore_gunit_s0ix_state(dev_priv);
1447 err = vlv_allow_gt_wake(dev_priv, true);
1451 err = vlv_force_gfx_clock(dev_priv, false);
1455 vlv_check_no_gt_access(dev_priv);
1458 intel_init_clock_gating(dev);
1459 i915_gem_restore_fences(dev);
1465 static int intel_runtime_suspend(struct device *device)
1467 struct pci_dev *pdev = to_pci_dev(device);
1468 struct drm_device *dev = pci_get_drvdata(pdev);
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1472 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1475 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1478 DRM_DEBUG_KMS("Suspending device\n");
1481 * We could deadlock here in case another thread holding struct_mutex
1482 * calls RPM suspend concurrently, since the RPM suspend will wait
1483 * first for this RPM suspend to finish. In this case the concurrent
1484 * RPM resume will be followed by its RPM suspend counterpart. Still
1485 * for consistency return -EAGAIN, which will reschedule this suspend.
1487 if (!mutex_trylock(&dev->struct_mutex)) {
1488 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1490 * Bump the expiration timestamp, otherwise the suspend won't
1493 pm_runtime_mark_last_busy(device);
1498 disable_rpm_wakeref_asserts(dev_priv);
1501 * We are safe here against re-faults, since the fault handler takes
1504 i915_gem_release_all_mmaps(dev_priv);
1505 mutex_unlock(&dev->struct_mutex);
1507 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1509 intel_guc_suspend(dev);
1511 intel_suspend_gt_powersave(dev);
1512 intel_runtime_pm_disable_interrupts(dev_priv);
1515 if (IS_BROXTON(dev_priv)) {
1516 bxt_display_core_uninit(dev_priv);
1517 bxt_enable_dc9(dev_priv);
1518 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1519 hsw_enable_pc8(dev_priv);
1520 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1521 ret = vlv_suspend_complete(dev_priv);
1525 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1526 intel_runtime_pm_enable_interrupts(dev_priv);
1528 enable_rpm_wakeref_asserts(dev_priv);
1533 intel_uncore_forcewake_reset(dev, false);
1535 enable_rpm_wakeref_asserts(dev_priv);
1536 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1538 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1539 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1541 dev_priv->pm.suspended = true;
1544 * FIXME: We really should find a document that references the arguments
1547 if (IS_BROADWELL(dev)) {
1549 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1550 * being detected, and the call we do at intel_runtime_resume()
1551 * won't be able to restore them. Since PCI_D3hot matches the
1552 * actual specification and appears to be working, use it.
1554 intel_opregion_notify_adapter(dev, PCI_D3hot);
1557 * current versions of firmware which depend on this opregion
1558 * notification have repurposed the D1 definition to mean
1559 * "runtime suspended" vs. what you would normally expect (D3)
1560 * to distinguish it from notifications that might be sent via
1563 intel_opregion_notify_adapter(dev, PCI_D1);
1566 assert_forcewakes_inactive(dev_priv);
1568 DRM_DEBUG_KMS("Device suspended\n");
1572 static int intel_runtime_resume(struct device *device)
1574 struct pci_dev *pdev = to_pci_dev(device);
1575 struct drm_device *dev = pci_get_drvdata(pdev);
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1579 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1582 DRM_DEBUG_KMS("Resuming device\n");
1584 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1585 disable_rpm_wakeref_asserts(dev_priv);
1587 intel_opregion_notify_adapter(dev, PCI_D0);
1588 dev_priv->pm.suspended = false;
1589 if (intel_uncore_unclaimed_mmio(dev_priv))
1590 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1592 intel_guc_resume(dev);
1594 if (IS_GEN6(dev_priv))
1595 intel_init_pch_refclk(dev);
1597 if (IS_BROXTON(dev)) {
1598 bxt_disable_dc9(dev_priv);
1599 bxt_display_core_init(dev_priv, true);
1600 if (dev_priv->csr.dmc_payload &&
1601 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
1602 gen9_enable_dc5(dev_priv);
1603 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1604 hsw_disable_pc8(dev_priv);
1605 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1606 ret = vlv_resume_prepare(dev_priv, true);
1610 * No point of rolling back things in case of an error, as the best
1611 * we can do is to hope that things will still work (and disable RPM).
1613 i915_gem_init_swizzling(dev);
1614 gen6_update_ring_freq(dev);
1616 intel_runtime_pm_enable_interrupts(dev_priv);
1619 * On VLV/CHV display interrupts are part of the display
1620 * power well, so hpd is reinitialized from there. For
1621 * everyone else do it here.
1623 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1624 intel_hpd_init(dev_priv);
1626 intel_enable_gt_powersave(dev);
1628 enable_rpm_wakeref_asserts(dev_priv);
1631 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1633 DRM_DEBUG_KMS("Device resumed\n");
1638 static const struct dev_pm_ops i915_pm_ops = {
1640 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1643 .suspend = i915_pm_suspend,
1644 .suspend_late = i915_pm_suspend_late,
1645 .resume_early = i915_pm_resume_early,
1646 .resume = i915_pm_resume,
1650 * @freeze, @freeze_late : called (1) before creating the
1651 * hibernation image [PMSG_FREEZE] and
1652 * (2) after rebooting, before restoring
1653 * the image [PMSG_QUIESCE]
1654 * @thaw, @thaw_early : called (1) after creating the hibernation
1655 * image, before writing it [PMSG_THAW]
1656 * and (2) after failing to create or
1657 * restore the image [PMSG_RECOVER]
1658 * @poweroff, @poweroff_late: called after writing the hibernation
1659 * image, before rebooting [PMSG_HIBERNATE]
1660 * @restore, @restore_early : called after rebooting and restoring the
1661 * hibernation image [PMSG_RESTORE]
1663 .freeze = i915_pm_suspend,
1664 .freeze_late = i915_pm_suspend_late,
1665 .thaw_early = i915_pm_resume_early,
1666 .thaw = i915_pm_resume,
1667 .poweroff = i915_pm_suspend,
1668 .poweroff_late = i915_pm_poweroff_late,
1669 .restore_early = i915_pm_resume_early,
1670 .restore = i915_pm_resume,
1672 /* S0ix (via runtime suspend) event handlers */
1673 .runtime_suspend = intel_runtime_suspend,
1674 .runtime_resume = intel_runtime_resume,
1677 static const struct vm_operations_struct i915_gem_vm_ops = {
1678 .fault = i915_gem_fault,
1679 .open = drm_gem_vm_open,
1680 .close = drm_gem_vm_close,
1683 static const struct file_operations i915_driver_fops = {
1684 .owner = THIS_MODULE,
1686 .release = drm_release,
1687 .unlocked_ioctl = drm_ioctl,
1688 .mmap = drm_gem_mmap,
1691 #ifdef CONFIG_COMPAT
1692 .compat_ioctl = i915_compat_ioctl,
1694 .llseek = noop_llseek,
1697 static struct drm_driver driver = {
1698 /* Don't use MTRRs here; the Xserver or userspace app should
1699 * deal with them for Intel hardware.
1702 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1703 DRIVER_RENDER | DRIVER_MODESET,
1704 .load = i915_driver_load,
1705 .unload = i915_driver_unload,
1706 .open = i915_driver_open,
1707 .lastclose = i915_driver_lastclose,
1708 .preclose = i915_driver_preclose,
1709 .postclose = i915_driver_postclose,
1710 .set_busid = drm_pci_set_busid,
1712 #if defined(CONFIG_DEBUG_FS)
1713 .debugfs_init = i915_debugfs_init,
1714 .debugfs_cleanup = i915_debugfs_cleanup,
1716 .gem_free_object = i915_gem_free_object,
1717 .gem_vm_ops = &i915_gem_vm_ops,
1719 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1720 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1721 .gem_prime_export = i915_gem_prime_export,
1722 .gem_prime_import = i915_gem_prime_import,
1724 .dumb_create = i915_gem_dumb_create,
1725 .dumb_map_offset = i915_gem_mmap_gtt,
1726 .dumb_destroy = drm_gem_dumb_destroy,
1727 .ioctls = i915_ioctls,
1728 .fops = &i915_driver_fops,
1729 .name = DRIVER_NAME,
1730 .desc = DRIVER_DESC,
1731 .date = DRIVER_DATE,
1732 .major = DRIVER_MAJOR,
1733 .minor = DRIVER_MINOR,
1734 .patchlevel = DRIVER_PATCHLEVEL,
1737 static struct pci_driver i915_pci_driver = {
1738 .name = DRIVER_NAME,
1739 .id_table = pciidlist,
1740 .probe = i915_pci_probe,
1741 .remove = i915_pci_remove,
1742 .driver.pm = &i915_pm_ops,
1745 static int __init i915_init(void)
1747 driver.num_ioctls = i915_max_ioctl;
1750 * Enable KMS by default, unless explicitly overriden by
1751 * either the i915.modeset prarameter or by the
1752 * vga_text_mode_force boot option.
1755 if (i915.modeset == 0)
1756 driver.driver_features &= ~DRIVER_MODESET;
1758 #ifdef CONFIG_VGA_CONSOLE
1759 if (vgacon_text_force() && i915.modeset == -1)
1760 driver.driver_features &= ~DRIVER_MODESET;
1763 if (!(driver.driver_features & DRIVER_MODESET)) {
1764 /* Silently fail loading to not upset userspace. */
1765 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1769 if (i915.nuclear_pageflip)
1770 driver.driver_features |= DRIVER_ATOMIC;
1772 return drm_pci_init(&driver, &i915_pci_driver);
1775 static void __exit i915_exit(void)
1777 if (!(driver.driver_features & DRIVER_MODESET))
1778 return; /* Never loaded a driver. */
1780 drm_pci_exit(&driver, &i915_pci_driver);
1783 module_init(i915_init);
1784 module_exit(i915_exit);
1786 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1787 MODULE_AUTHOR("Intel Corporation");
1789 MODULE_DESCRIPTION(DRIVER_DESC);
1790 MODULE_LICENSE("GPL and additional rights");