1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
52 #include "i915_query.h"
53 #include "i915_vgpu.h"
54 #include "intel_drv.h"
56 #include "intel_workarounds.h"
58 static struct drm_driver driver;
60 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
61 static unsigned int i915_load_fail_count;
63 bool __i915_inject_load_failure(const char *func, int line)
65 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
68 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
69 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
70 i915_modparams.inject_load_failure, func, line);
71 i915_modparams.inject_load_failure = 0;
78 bool i915_error_injected(void)
80 return i915_load_fail_count && !i915_modparams.inject_load_failure;
85 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
86 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
87 "providing the dmesg log by booting with drm.debug=0xf"
90 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
93 static bool shown_bug_once;
94 struct device *kdev = dev_priv->drm.dev;
95 bool is_error = level[1] <= KERN_ERR[1];
96 bool is_debug = level[1] == KERN_DEBUG[1];
100 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
109 dev_printk(level, kdev, "%pV", &vaf);
111 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
112 __builtin_return_address(0), &vaf);
116 if (is_error && !shown_bug_once) {
118 * Ask the user to file a bug report for the error, except
119 * if they may have caused the bug by fiddling with unsafe
122 if (!test_taint(TAINT_USER))
123 dev_notice(kdev, "%s", FDO_BUG_MSG);
124 shown_bug_once = true;
128 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
129 static enum intel_pch
130 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
133 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
134 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
135 WARN_ON(!IS_GEN5(dev_priv));
137 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
138 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
139 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
141 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
142 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
143 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
144 /* PantherPoint is CPT compatible */
146 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
147 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
148 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
149 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
151 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
152 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
153 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
154 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
156 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
157 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
158 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
159 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
160 /* WildcatPoint is LPT compatible */
162 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
163 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
164 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
165 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
166 /* WildcatPoint is LPT compatible */
168 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
169 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
170 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
172 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
173 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
174 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
176 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
177 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
178 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
179 !IS_COFFEELAKE(dev_priv));
181 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
182 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
183 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
185 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
186 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
187 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
189 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
190 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
191 WARN_ON(!IS_ICELAKE(dev_priv));
198 static bool intel_is_virt_pch(unsigned short id,
199 unsigned short svendor, unsigned short sdevice)
201 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
202 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
203 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
204 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
205 sdevice == PCI_SUBDEVICE_ID_QEMU));
208 static unsigned short
209 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
211 unsigned short id = 0;
214 * In a virtualized passthrough environment we can be in a
215 * setup where the ISA bridge is not able to be passed through.
216 * In this case, a south bridge can be emulated and we have to
217 * make an educated guess as to which PCH is really there.
220 if (IS_GEN5(dev_priv))
221 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
222 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
223 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
224 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
225 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
226 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
227 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
228 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
229 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
230 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
231 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
232 else if (IS_ICELAKE(dev_priv))
233 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
236 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
238 DRM_DEBUG_KMS("Assuming no PCH\n");
243 static void intel_detect_pch(struct drm_i915_private *dev_priv)
245 struct pci_dev *pch = NULL;
248 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
249 * make graphics device passthrough work easy for VMM, that only
250 * need to expose ISA bridge to let driver know the real hardware
251 * underneath. This is a requirement from virtualization team.
253 * In some virtualized environments (e.g. XEN), there is irrelevant
254 * ISA bridge in the system. To work reliably, we should scan trhough
255 * all the ISA bridge devices and check for the first match, instead
256 * of only checking the first one.
258 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
260 enum intel_pch pch_type;
262 if (pch->vendor != PCI_VENDOR_ID_INTEL)
265 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
267 pch_type = intel_pch_type(dev_priv, id);
268 if (pch_type != PCH_NONE) {
269 dev_priv->pch_type = pch_type;
270 dev_priv->pch_id = id;
272 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
273 pch->subsystem_device)) {
274 id = intel_virt_detect_pch(dev_priv);
275 pch_type = intel_pch_type(dev_priv, id);
277 /* Sanity check virtual PCH id */
278 if (WARN_ON(id && pch_type == PCH_NONE))
281 dev_priv->pch_type = pch_type;
282 dev_priv->pch_id = id;
288 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
291 if (pch && !HAS_DISPLAY(dev_priv)) {
292 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
293 dev_priv->pch_type = PCH_NOP;
294 dev_priv->pch_id = 0;
298 DRM_DEBUG_KMS("No PCH found.\n");
303 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
304 struct drm_file *file_priv)
306 struct drm_i915_private *dev_priv = to_i915(dev);
307 struct pci_dev *pdev = dev_priv->drm.pdev;
308 drm_i915_getparam_t *param = data;
311 switch (param->param) {
312 case I915_PARAM_IRQ_ACTIVE:
313 case I915_PARAM_ALLOW_BATCHBUFFER:
314 case I915_PARAM_LAST_DISPATCH:
315 case I915_PARAM_HAS_EXEC_CONSTANTS:
316 /* Reject all old ums/dri params. */
318 case I915_PARAM_CHIPSET_ID:
319 value = pdev->device;
321 case I915_PARAM_REVISION:
322 value = pdev->revision;
324 case I915_PARAM_NUM_FENCES_AVAIL:
325 value = dev_priv->num_fence_regs;
327 case I915_PARAM_HAS_OVERLAY:
328 value = dev_priv->overlay ? 1 : 0;
330 case I915_PARAM_HAS_BSD:
331 value = !!dev_priv->engine[VCS];
333 case I915_PARAM_HAS_BLT:
334 value = !!dev_priv->engine[BCS];
336 case I915_PARAM_HAS_VEBOX:
337 value = !!dev_priv->engine[VECS];
339 case I915_PARAM_HAS_BSD2:
340 value = !!dev_priv->engine[VCS2];
342 case I915_PARAM_HAS_LLC:
343 value = HAS_LLC(dev_priv);
345 case I915_PARAM_HAS_WT:
346 value = HAS_WT(dev_priv);
348 case I915_PARAM_HAS_ALIASING_PPGTT:
349 value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
351 case I915_PARAM_HAS_SEMAPHORES:
352 value = HAS_LEGACY_SEMAPHORES(dev_priv);
354 case I915_PARAM_HAS_SECURE_BATCHES:
355 value = capable(CAP_SYS_ADMIN);
357 case I915_PARAM_CMD_PARSER_VERSION:
358 value = i915_cmd_parser_get_version(dev_priv);
360 case I915_PARAM_SUBSLICE_TOTAL:
361 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
365 case I915_PARAM_EU_TOTAL:
366 value = INTEL_INFO(dev_priv)->sseu.eu_total;
370 case I915_PARAM_HAS_GPU_RESET:
371 value = i915_modparams.enable_hangcheck &&
372 intel_has_gpu_reset(dev_priv);
373 if (value && intel_has_reset_engine(dev_priv))
376 case I915_PARAM_HAS_RESOURCE_STREAMER:
379 case I915_PARAM_HAS_POOLED_EU:
380 value = HAS_POOLED_EU(dev_priv);
382 case I915_PARAM_MIN_EU_IN_POOL:
383 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
385 case I915_PARAM_HUC_STATUS:
386 value = intel_huc_check_status(&dev_priv->huc);
390 case I915_PARAM_MMAP_GTT_VERSION:
391 /* Though we've started our numbering from 1, and so class all
392 * earlier versions as 0, in effect their value is undefined as
393 * the ioctl will report EINVAL for the unknown param!
395 value = i915_gem_mmap_gtt_version();
397 case I915_PARAM_HAS_SCHEDULER:
398 value = dev_priv->caps.scheduler;
401 case I915_PARAM_MMAP_VERSION:
402 /* Remember to bump this if the version changes! */
403 case I915_PARAM_HAS_GEM:
404 case I915_PARAM_HAS_PAGEFLIPPING:
405 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
406 case I915_PARAM_HAS_RELAXED_FENCING:
407 case I915_PARAM_HAS_COHERENT_RINGS:
408 case I915_PARAM_HAS_RELAXED_DELTA:
409 case I915_PARAM_HAS_GEN7_SOL_RESET:
410 case I915_PARAM_HAS_WAIT_TIMEOUT:
411 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
412 case I915_PARAM_HAS_PINNED_BATCHES:
413 case I915_PARAM_HAS_EXEC_NO_RELOC:
414 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
415 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
416 case I915_PARAM_HAS_EXEC_SOFTPIN:
417 case I915_PARAM_HAS_EXEC_ASYNC:
418 case I915_PARAM_HAS_EXEC_FENCE:
419 case I915_PARAM_HAS_EXEC_CAPTURE:
420 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
421 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
422 /* For the time being all of these are always true;
423 * if some supported hardware does not have one of these
424 * features this value needs to be provided from
425 * INTEL_INFO(), a feature macro, or similar.
429 case I915_PARAM_HAS_CONTEXT_ISOLATION:
430 value = intel_engines_has_context_isolation(dev_priv);
432 case I915_PARAM_SLICE_MASK:
433 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
437 case I915_PARAM_SUBSLICE_MASK:
438 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
442 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
443 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
445 case I915_PARAM_MMAP_GTT_COHERENT:
446 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
449 DRM_DEBUG("Unknown parameter %d\n", param->param);
453 if (put_user(value, param->value))
459 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
461 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
463 dev_priv->bridge_dev =
464 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
465 if (!dev_priv->bridge_dev) {
466 DRM_ERROR("bridge device not found\n");
472 /* Allocate space for the MCH regs if needed, return nonzero on error */
474 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
476 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
477 u32 temp_lo, temp_hi = 0;
481 if (INTEL_GEN(dev_priv) >= 4)
482 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
483 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
484 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
486 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
489 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
493 /* Get some space for it */
494 dev_priv->mch_res.name = "i915 MCHBAR";
495 dev_priv->mch_res.flags = IORESOURCE_MEM;
496 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
498 MCHBAR_SIZE, MCHBAR_SIZE,
500 0, pcibios_align_resource,
501 dev_priv->bridge_dev);
503 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
504 dev_priv->mch_res.start = 0;
508 if (INTEL_GEN(dev_priv) >= 4)
509 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
510 upper_32_bits(dev_priv->mch_res.start));
512 pci_write_config_dword(dev_priv->bridge_dev, reg,
513 lower_32_bits(dev_priv->mch_res.start));
517 /* Setup MCHBAR if possible, return true if we should disable it again */
519 intel_setup_mchbar(struct drm_i915_private *dev_priv)
521 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
525 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
528 dev_priv->mchbar_need_disable = false;
530 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
531 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
532 enabled = !!(temp & DEVEN_MCHBAR_EN);
534 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
538 /* If it's already enabled, don't have to do anything */
542 if (intel_alloc_mchbar_resource(dev_priv))
545 dev_priv->mchbar_need_disable = true;
547 /* Space is allocated or reserved, so enable it. */
548 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
549 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
550 temp | DEVEN_MCHBAR_EN);
552 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
553 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
558 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
560 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
562 if (dev_priv->mchbar_need_disable) {
563 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
566 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
568 deven_val &= ~DEVEN_MCHBAR_EN;
569 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
574 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
577 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
582 if (dev_priv->mch_res.start)
583 release_resource(&dev_priv->mch_res);
586 /* true = enable decode, false = disable decoder */
587 static unsigned int i915_vga_set_decode(void *cookie, bool state)
589 struct drm_i915_private *dev_priv = cookie;
591 intel_modeset_vga_set_state(dev_priv, state);
593 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
594 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
596 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
599 static int i915_resume_switcheroo(struct drm_device *dev);
600 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
602 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
604 struct drm_device *dev = pci_get_drvdata(pdev);
605 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
607 if (state == VGA_SWITCHEROO_ON) {
608 pr_info("switched on\n");
609 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
610 /* i915 resume handler doesn't set to D0 */
611 pci_set_power_state(pdev, PCI_D0);
612 i915_resume_switcheroo(dev);
613 dev->switch_power_state = DRM_SWITCH_POWER_ON;
615 pr_info("switched off\n");
616 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
617 i915_suspend_switcheroo(dev, pmm);
618 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
622 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
624 struct drm_device *dev = pci_get_drvdata(pdev);
627 * FIXME: open_count is protected by drm_global_mutex but that would lead to
628 * locking inversion with the driver load path. And the access here is
629 * completely racy anyway. So don't bother with locking for now.
631 return dev->open_count == 0;
634 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
635 .set_gpu_state = i915_switcheroo_set_state,
637 .can_switch = i915_switcheroo_can_switch,
640 static int i915_load_modeset_init(struct drm_device *dev)
642 struct drm_i915_private *dev_priv = to_i915(dev);
643 struct pci_dev *pdev = dev_priv->drm.pdev;
646 if (i915_inject_load_failure())
649 if (HAS_DISPLAY(dev_priv)) {
650 ret = drm_vblank_init(&dev_priv->drm,
651 INTEL_INFO(dev_priv)->num_pipes);
656 intel_bios_init(dev_priv);
658 /* If we have > 1 VGA cards, then we need to arbitrate access
659 * to the common VGA resources.
661 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
662 * then we do not take part in VGA arbitration and the
663 * vga_client_register() fails with -ENODEV.
665 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
666 if (ret && ret != -ENODEV)
669 intel_register_dsm_handler();
671 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
673 goto cleanup_vga_client;
675 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
676 intel_update_rawclk(dev_priv);
678 intel_power_domains_init_hw(dev_priv, false);
680 intel_csr_ucode_init(dev_priv);
682 ret = intel_irq_install(dev_priv);
686 intel_setup_gmbus(dev_priv);
688 /* Important: The output setup functions called by modeset_init need
689 * working irqs for e.g. gmbus and dp aux transfers. */
690 ret = intel_modeset_init(dev);
694 ret = i915_gem_init(dev_priv);
696 goto cleanup_modeset;
698 intel_overlay_setup(dev_priv);
700 if (!HAS_DISPLAY(dev_priv))
703 ret = intel_fbdev_init(dev);
707 /* Only enable hotplug handling once the fbdev is fully set up. */
708 intel_hpd_init(dev_priv);
710 intel_init_ipc(dev_priv);
715 if (i915_gem_suspend(dev_priv))
716 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
717 i915_gem_fini(dev_priv);
719 intel_modeset_cleanup(dev);
721 drm_irq_uninstall(dev);
722 intel_teardown_gmbus(dev_priv);
724 intel_csr_ucode_fini(dev_priv);
725 intel_power_domains_fini_hw(dev_priv);
726 vga_switcheroo_unregister_client(pdev);
728 vga_client_register(pdev, NULL, NULL, NULL);
733 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
735 struct apertures_struct *ap;
736 struct pci_dev *pdev = dev_priv->drm.pdev;
737 struct i915_ggtt *ggtt = &dev_priv->ggtt;
741 ap = alloc_apertures(1);
745 ap->ranges[0].base = ggtt->gmadr.start;
746 ap->ranges[0].size = ggtt->mappable_end;
749 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
751 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
758 #if !defined(CONFIG_VGA_CONSOLE)
759 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
763 #elif !defined(CONFIG_DUMMY_CONSOLE)
764 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
769 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
773 DRM_INFO("Replacing VGA console driver\n");
776 if (con_is_bound(&vga_con))
777 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
779 ret = do_unregister_con_driver(&vga_con);
781 /* Ignore "already unregistered". */
791 static void intel_init_dpio(struct drm_i915_private *dev_priv)
794 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
795 * CHV x1 PHY (DP/HDMI D)
796 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
798 if (IS_CHERRYVIEW(dev_priv)) {
799 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
800 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
801 } else if (IS_VALLEYVIEW(dev_priv)) {
802 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
806 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
809 * The i915 workqueue is primarily used for batched retirement of
810 * requests (and thus managing bo) once the task has been completed
811 * by the GPU. i915_retire_requests() is called directly when we
812 * need high-priority retirement, such as waiting for an explicit
815 * It is also used for periodic low-priority events, such as
816 * idle-timers and recording error state.
818 * All tasks on the workqueue are expected to acquire the dev mutex
819 * so there is no point in running more than one instance of the
820 * workqueue at any time. Use an ordered one.
822 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
823 if (dev_priv->wq == NULL)
826 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
827 if (dev_priv->hotplug.dp_wq == NULL)
833 destroy_workqueue(dev_priv->wq);
835 DRM_ERROR("Failed to allocate workqueues.\n");
840 static void i915_engines_cleanup(struct drm_i915_private *i915)
842 struct intel_engine_cs *engine;
843 enum intel_engine_id id;
845 for_each_engine(engine, i915, id)
849 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
851 destroy_workqueue(dev_priv->hotplug.dp_wq);
852 destroy_workqueue(dev_priv->wq);
856 * We don't keep the workarounds for pre-production hardware, so we expect our
857 * driver to fail on these machines in one way or another. A little warning on
858 * dmesg may help both the user and the bug triagers.
860 * Our policy for removing pre-production workarounds is to keep the
861 * current gen workarounds as a guide to the bring-up of the next gen
862 * (workarounds have a habit of persisting!). Anything older than that
863 * should be removed along with the complications they introduce.
865 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
869 pre |= IS_HSW_EARLY_SDV(dev_priv);
870 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
871 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
872 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
875 DRM_ERROR("This is a pre-production stepping. "
876 "It may not be fully functional.\n");
877 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
882 * i915_driver_init_early - setup state not requiring device access
883 * @dev_priv: device private
885 * Initialize everything that is a "SW-only" state, that is state not
886 * requiring accessing the device or exposing the driver via kernel internal
887 * or userspace interfaces. Example steps belonging here: lock initialization,
888 * system memory allocation, setting up device specific attributes and
889 * function hooks not requiring accessing the device.
891 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
895 if (i915_inject_load_failure())
898 spin_lock_init(&dev_priv->irq_lock);
899 spin_lock_init(&dev_priv->gpu_error.lock);
900 mutex_init(&dev_priv->backlight_lock);
901 spin_lock_init(&dev_priv->uncore.lock);
903 mutex_init(&dev_priv->sb_lock);
904 mutex_init(&dev_priv->av_mutex);
905 mutex_init(&dev_priv->wm.wm_mutex);
906 mutex_init(&dev_priv->pps_mutex);
908 i915_memcpy_init_early(dev_priv);
910 ret = i915_workqueues_init(dev_priv);
914 ret = i915_gem_init_early(dev_priv);
918 /* This must be called before any calls to HAS_PCH_* */
919 intel_detect_pch(dev_priv);
921 intel_wopcm_init_early(&dev_priv->wopcm);
922 intel_uc_init_early(dev_priv);
923 intel_pm_setup(dev_priv);
924 intel_init_dpio(dev_priv);
925 ret = intel_power_domains_init(dev_priv);
928 intel_irq_init(dev_priv);
929 intel_hangcheck_init(dev_priv);
930 intel_init_display_hooks(dev_priv);
931 intel_init_clock_gating_hooks(dev_priv);
932 intel_init_audio_hooks(dev_priv);
933 intel_display_crc_init(dev_priv);
935 intel_detect_preproduction_hw(dev_priv);
940 intel_uc_cleanup_early(dev_priv);
941 i915_gem_cleanup_early(dev_priv);
943 i915_workqueues_cleanup(dev_priv);
945 i915_engines_cleanup(dev_priv);
950 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
951 * @dev_priv: device private
953 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
955 intel_irq_fini(dev_priv);
956 intel_power_domains_cleanup(dev_priv);
957 intel_uc_cleanup_early(dev_priv);
958 i915_gem_cleanup_early(dev_priv);
959 i915_workqueues_cleanup(dev_priv);
960 i915_engines_cleanup(dev_priv);
963 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
965 struct pci_dev *pdev = dev_priv->drm.pdev;
969 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
971 * Before gen4, the registers and the GTT are behind different BARs.
972 * However, from gen4 onwards, the registers and the GTT are shared
973 * in the same BAR, so we want to restrict this ioremap from
974 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
975 * the register BAR remains the same size for all the earlier
976 * generations up to Ironlake.
978 if (INTEL_GEN(dev_priv) < 5)
979 mmio_size = 512 * 1024;
981 mmio_size = 2 * 1024 * 1024;
982 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
983 if (dev_priv->regs == NULL) {
984 DRM_ERROR("failed to map registers\n");
989 /* Try to make sure MCHBAR is enabled before poking at it */
990 intel_setup_mchbar(dev_priv);
995 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
997 struct pci_dev *pdev = dev_priv->drm.pdev;
999 intel_teardown_mchbar(dev_priv);
1000 pci_iounmap(pdev, dev_priv->regs);
1004 * i915_driver_init_mmio - setup device MMIO
1005 * @dev_priv: device private
1007 * Setup minimal device state necessary for MMIO accesses later in the
1008 * initialization sequence. The setup here should avoid any other device-wide
1009 * side effects or exposing the driver via kernel internal or user space
1012 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1016 if (i915_inject_load_failure())
1019 if (i915_get_bridge_dev(dev_priv))
1022 ret = i915_mmio_setup(dev_priv);
1026 intel_uncore_init(dev_priv);
1028 intel_device_info_init_mmio(dev_priv);
1030 intel_uncore_prune(dev_priv);
1032 intel_uc_init_mmio(dev_priv);
1034 ret = intel_engines_init_mmio(dev_priv);
1038 i915_gem_init_mmio(dev_priv);
1043 intel_uncore_fini(dev_priv);
1044 i915_mmio_cleanup(dev_priv);
1046 pci_dev_put(dev_priv->bridge_dev);
1052 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1053 * @dev_priv: device private
1055 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1057 intel_uncore_fini(dev_priv);
1058 i915_mmio_cleanup(dev_priv);
1059 pci_dev_put(dev_priv->bridge_dev);
1062 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1064 intel_gvt_sanitize_options(dev_priv);
1067 static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
1070 return I915_DRAM_RANK_INVALID;
1071 if (rank == SKL_DRAM_RANK_SINGLE)
1072 return I915_DRAM_RANK_SINGLE;
1073 else if (rank == SKL_DRAM_RANK_DUAL)
1074 return I915_DRAM_RANK_DUAL;
1076 return I915_DRAM_RANK_INVALID;
1080 skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
1082 if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
1084 else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
1086 else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
1088 else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
1095 skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
1098 u32 s_val = val >> SKL_DRAM_S_SHIFT;
1103 tmp_l = val & SKL_DRAM_SIZE_MASK;
1104 tmp_s = s_val & SKL_DRAM_SIZE_MASK;
1106 if (tmp_l == 0 && tmp_s == 0)
1109 ch->l_info.size = tmp_l;
1110 ch->s_info.size = tmp_s;
1112 tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1113 tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1114 ch->l_info.width = (1 << tmp_l) * 8;
1115 ch->s_info.width = (1 << tmp_s) * 8;
1117 tmp_l = val & SKL_DRAM_RANK_MASK;
1118 tmp_s = s_val & SKL_DRAM_RANK_MASK;
1119 ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
1120 ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
1122 if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
1123 ch->s_info.rank == I915_DRAM_RANK_DUAL)
1124 ch->rank = I915_DRAM_RANK_DUAL;
1125 else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
1126 ch->s_info.rank == I915_DRAM_RANK_SINGLE)
1127 ch->rank = I915_DRAM_RANK_DUAL;
1129 ch->rank = I915_DRAM_RANK_SINGLE;
1131 ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
1132 ch->l_info.width) ||
1133 skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
1136 DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
1137 ch->l_info.size, ch->l_info.width,
1138 ch->l_info.rank ? "dual" : "single",
1139 ch->s_info.size, ch->s_info.width,
1140 ch->s_info.rank ? "dual" : "single");
1146 intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
1147 struct dram_channel_info *ch0)
1149 return (val_ch0 == val_ch1 &&
1150 (ch0->s_info.size == 0 ||
1151 (ch0->l_info.size == ch0->s_info.size &&
1152 ch0->l_info.width == ch0->s_info.width &&
1153 ch0->l_info.rank == ch0->s_info.rank)));
1157 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1159 struct dram_info *dram_info = &dev_priv->dram_info;
1160 struct dram_channel_info ch0, ch1;
1161 u32 val_ch0, val_ch1;
1164 val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1165 ret = skl_dram_get_channel_info(&ch0, val_ch0);
1167 dram_info->num_channels++;
1169 val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1170 ret = skl_dram_get_channel_info(&ch1, val_ch1);
1172 dram_info->num_channels++;
1174 if (dram_info->num_channels == 0) {
1175 DRM_INFO("Number of memory channels is zero\n");
1180 * If any of the channel is single rank channel, worst case output
1181 * will be same as if single rank memory, so consider single rank
1184 if (ch0.rank == I915_DRAM_RANK_SINGLE ||
1185 ch1.rank == I915_DRAM_RANK_SINGLE)
1186 dram_info->rank = I915_DRAM_RANK_SINGLE;
1188 dram_info->rank = max(ch0.rank, ch1.rank);
1190 if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1191 DRM_INFO("couldn't get memory rank information\n");
1195 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1197 dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1201 DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
1202 dev_priv->dram_info.symmetric_memory ? "" : "not ");
1207 skl_get_dram_info(struct drm_i915_private *dev_priv)
1209 struct dram_info *dram_info = &dev_priv->dram_info;
1210 u32 mem_freq_khz, val;
1213 ret = skl_dram_get_channels_info(dev_priv);
1217 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1218 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1219 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1221 dram_info->bandwidth_kbps = dram_info->num_channels *
1224 if (dram_info->bandwidth_kbps == 0) {
1225 DRM_INFO("Couldn't get system memory bandwidth\n");
1229 dram_info->valid = true;
1234 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1236 struct dram_info *dram_info = &dev_priv->dram_info;
1238 u32 mem_freq_khz, val;
1239 u8 num_active_channels;
1242 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1243 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1244 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1246 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1247 num_active_channels = hweight32(dram_channels);
1249 /* Each active bit represents 4-byte channel */
1250 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1252 if (dram_info->bandwidth_kbps == 0) {
1253 DRM_INFO("Couldn't get system memory bandwidth\n");
1258 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1260 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1262 enum dram_rank rank;
1265 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1266 if (val == 0xFFFFFFFF)
1269 dram_info->num_channels++;
1270 tmp = val & BXT_DRAM_RANK_MASK;
1272 if (tmp == BXT_DRAM_RANK_SINGLE)
1273 rank = I915_DRAM_RANK_SINGLE;
1274 else if (tmp == BXT_DRAM_RANK_DUAL)
1275 rank = I915_DRAM_RANK_DUAL;
1277 rank = I915_DRAM_RANK_INVALID;
1279 tmp = val & BXT_DRAM_SIZE_MASK;
1280 if (tmp == BXT_DRAM_SIZE_4GB)
1282 else if (tmp == BXT_DRAM_SIZE_6GB)
1284 else if (tmp == BXT_DRAM_SIZE_8GB)
1286 else if (tmp == BXT_DRAM_SIZE_12GB)
1288 else if (tmp == BXT_DRAM_SIZE_16GB)
1293 tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1294 width = (1 << tmp) * 8;
1295 DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
1296 width, rank == I915_DRAM_RANK_SINGLE ? "single" :
1297 rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
1300 * If any of the channel is single rank channel,
1301 * worst case output will be same as if single rank
1302 * memory, so consider single rank memory.
1304 if (dram_info->rank == I915_DRAM_RANK_INVALID)
1305 dram_info->rank = rank;
1306 else if (rank == I915_DRAM_RANK_SINGLE)
1307 dram_info->rank = I915_DRAM_RANK_SINGLE;
1310 if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1311 DRM_INFO("couldn't get memory rank information\n");
1315 dram_info->valid = true;
1320 intel_get_dram_info(struct drm_i915_private *dev_priv)
1322 struct dram_info *dram_info = &dev_priv->dram_info;
1323 char bandwidth_str[32];
1326 dram_info->valid = false;
1327 dram_info->rank = I915_DRAM_RANK_INVALID;
1328 dram_info->bandwidth_kbps = 0;
1329 dram_info->num_channels = 0;
1332 * Assume 16Gb DIMMs are present until proven otherwise.
1333 * This is only used for the level 0 watermark latency
1334 * w/a which does not apply to bxt/glk.
1336 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1338 if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
1341 /* Need to calculate bandwidth only for Gen9 */
1342 if (IS_BROXTON(dev_priv))
1343 ret = bxt_get_dram_info(dev_priv);
1344 else if (IS_GEN9(dev_priv))
1345 ret = skl_get_dram_info(dev_priv);
1347 ret = skl_dram_get_channels_info(dev_priv);
1351 if (dram_info->bandwidth_kbps)
1352 sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
1354 sprintf(bandwidth_str, "unknown");
1355 DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
1356 bandwidth_str, dram_info->num_channels);
1357 DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
1358 (dram_info->rank == I915_DRAM_RANK_DUAL) ?
1359 "dual" : "single", yesno(dram_info->is_16gb_dimm));
1363 * i915_driver_init_hw - setup state requiring device access
1364 * @dev_priv: device private
1366 * Setup state that requires accessing the device, but doesn't require
1367 * exposing the driver via kernel internal or userspace interfaces.
1369 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1371 struct pci_dev *pdev = dev_priv->drm.pdev;
1374 if (i915_inject_load_failure())
1377 intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1379 if (HAS_PPGTT(dev_priv)) {
1380 if (intel_vgpu_active(dev_priv) &&
1381 !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
1382 i915_report_error(dev_priv,
1383 "incompatible vGPU found, support for isolated ppGTT required\n");
1388 if (HAS_EXECLISTS(dev_priv)) {
1390 * Older GVT emulation depends upon intercepting CSB mmio,
1391 * which we no longer use, preferring to use the HWSP cache
1394 if (intel_vgpu_active(dev_priv) &&
1395 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1396 i915_report_error(dev_priv,
1397 "old vGPU host found, support for HWSP emulation required\n");
1402 intel_sanitize_options(dev_priv);
1404 i915_perf_init(dev_priv);
1406 ret = i915_ggtt_probe_hw(dev_priv);
1411 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1412 * otherwise the vga fbdev driver falls over.
1414 ret = i915_kick_out_firmware_fb(dev_priv);
1416 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1420 ret = i915_kick_out_vgacon(dev_priv);
1422 DRM_ERROR("failed to remove conflicting VGA console\n");
1426 ret = i915_ggtt_init_hw(dev_priv);
1430 ret = i915_ggtt_enable_hw(dev_priv);
1432 DRM_ERROR("failed to enable GGTT\n");
1436 pci_set_master(pdev);
1438 /* overlay on gen2 is broken and can't address above 1G */
1439 if (IS_GEN2(dev_priv)) {
1440 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1442 DRM_ERROR("failed to set DMA mask\n");
1448 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1449 * using 32bit addressing, overwriting memory if HWS is located
1452 * The documentation also mentions an issue with undefined
1453 * behaviour if any general state is accessed within a page above 4GB,
1454 * which also needs to be handled carefully.
1456 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1457 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1460 DRM_ERROR("failed to set DMA mask\n");
1466 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1467 PM_QOS_DEFAULT_VALUE);
1469 intel_uncore_sanitize(dev_priv);
1471 intel_gt_init_workarounds(dev_priv);
1472 i915_gem_load_init_fences(dev_priv);
1474 /* On the 945G/GM, the chipset reports the MSI capability on the
1475 * integrated graphics even though the support isn't actually there
1476 * according to the published specs. It doesn't appear to function
1477 * correctly in testing on 945G.
1478 * This may be a side effect of MSI having been made available for PEG
1479 * and the registers being closely associated.
1481 * According to chipset errata, on the 965GM, MSI interrupts may
1482 * be lost or delayed, and was defeatured. MSI interrupts seem to
1483 * get lost on g4x as well, and interrupt delivery seems to stay
1484 * properly dead afterwards. So we'll just disable them for all
1485 * pre-gen5 chipsets.
1487 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1488 * interrupts even when in MSI mode. This results in spurious
1489 * interrupt warnings if the legacy irq no. is shared with another
1490 * device. The kernel then disables that interrupt source and so
1491 * prevents the other device from working properly.
1493 if (INTEL_GEN(dev_priv) >= 5) {
1494 if (pci_enable_msi(pdev) < 0)
1495 DRM_DEBUG_DRIVER("can't enable MSI");
1498 ret = intel_gvt_init(dev_priv);
1502 intel_opregion_setup(dev_priv);
1504 * Fill the dram structure to get the system raw bandwidth and
1505 * dram info. This will be used for memory latency calculation.
1507 intel_get_dram_info(dev_priv);
1513 if (pdev->msi_enabled)
1514 pci_disable_msi(pdev);
1515 pm_qos_remove_request(&dev_priv->pm_qos);
1517 i915_ggtt_cleanup_hw(dev_priv);
1519 i915_perf_fini(dev_priv);
1524 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1525 * @dev_priv: device private
1527 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1529 struct pci_dev *pdev = dev_priv->drm.pdev;
1531 i915_perf_fini(dev_priv);
1533 if (pdev->msi_enabled)
1534 pci_disable_msi(pdev);
1536 pm_qos_remove_request(&dev_priv->pm_qos);
1537 i915_ggtt_cleanup_hw(dev_priv);
1541 * i915_driver_register - register the driver with the rest of the system
1542 * @dev_priv: device private
1544 * Perform any steps necessary to make the driver available via kernel
1545 * internal or userspace interfaces.
1547 static void i915_driver_register(struct drm_i915_private *dev_priv)
1549 struct drm_device *dev = &dev_priv->drm;
1551 i915_gem_shrinker_register(dev_priv);
1552 i915_pmu_register(dev_priv);
1555 * Notify a valid surface after modesetting,
1556 * when running inside a VM.
1558 if (intel_vgpu_active(dev_priv))
1559 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1561 /* Reveal our presence to userspace */
1562 if (drm_dev_register(dev, 0) == 0) {
1563 i915_debugfs_register(dev_priv);
1564 i915_setup_sysfs(dev_priv);
1566 /* Depends on sysfs having been initialized */
1567 i915_perf_register(dev_priv);
1569 DRM_ERROR("Failed to register driver for userspace access!\n");
1571 if (HAS_DISPLAY(dev_priv)) {
1572 /* Must be done after probing outputs */
1573 intel_opregion_register(dev_priv);
1574 acpi_video_register();
1577 if (IS_GEN5(dev_priv))
1578 intel_gpu_ips_init(dev_priv);
1580 intel_audio_init(dev_priv);
1583 * Some ports require correctly set-up hpd registers for detection to
1584 * work properly (leading to ghost connected connector status), e.g. VGA
1585 * on gm45. Hence we can only set up the initial fbdev config after hpd
1586 * irqs are fully enabled. We do it last so that the async config
1587 * cannot run before the connectors are registered.
1589 intel_fbdev_initial_config_async(dev);
1592 * We need to coordinate the hotplugs with the asynchronous fbdev
1593 * configuration, for which we use the fbdev->async_cookie.
1595 if (HAS_DISPLAY(dev_priv))
1596 drm_kms_helper_poll_init(dev);
1598 intel_power_domains_enable(dev_priv);
1599 intel_runtime_pm_enable(dev_priv);
1603 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1604 * @dev_priv: device private
1606 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1608 intel_runtime_pm_disable(dev_priv);
1609 intel_power_domains_disable(dev_priv);
1611 intel_fbdev_unregister(dev_priv);
1612 intel_audio_deinit(dev_priv);
1615 * After flushing the fbdev (incl. a late async config which will
1616 * have delayed queuing of a hotplug event), then flush the hotplug
1619 drm_kms_helper_poll_fini(&dev_priv->drm);
1621 intel_gpu_ips_teardown();
1622 acpi_video_unregister();
1623 intel_opregion_unregister(dev_priv);
1625 i915_perf_unregister(dev_priv);
1626 i915_pmu_unregister(dev_priv);
1628 i915_teardown_sysfs(dev_priv);
1629 drm_dev_unregister(&dev_priv->drm);
1631 i915_gem_shrinker_unregister(dev_priv);
1634 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1636 if (drm_debug & DRM_UT_DRIVER) {
1637 struct drm_printer p = drm_debug_printer("i915 device info:");
1639 intel_device_info_dump(&dev_priv->info, &p);
1640 intel_device_info_dump_runtime(&dev_priv->info, &p);
1643 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1644 DRM_INFO("DRM_I915_DEBUG enabled\n");
1645 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1646 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1647 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1648 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1651 static struct drm_i915_private *
1652 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1654 const struct intel_device_info *match_info =
1655 (struct intel_device_info *)ent->driver_data;
1656 struct intel_device_info *device_info;
1657 struct drm_i915_private *i915;
1660 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1662 return ERR_PTR(-ENOMEM);
1664 err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1667 return ERR_PTR(err);
1670 i915->drm.pdev = pdev;
1671 i915->drm.dev_private = i915;
1672 pci_set_drvdata(pdev, &i915->drm);
1674 /* Setup the write-once "constant" device info */
1675 device_info = mkwrite_device_info(i915);
1676 memcpy(device_info, match_info, sizeof(*device_info));
1677 device_info->device_id = pdev->device;
1679 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1680 BITS_PER_TYPE(device_info->platform_mask));
1681 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1686 static void i915_driver_destroy(struct drm_i915_private *i915)
1688 struct pci_dev *pdev = i915->drm.pdev;
1690 drm_dev_fini(&i915->drm);
1693 /* And make sure we never chase our dangling pointer from pci_dev */
1694 pci_set_drvdata(pdev, NULL);
1698 * i915_driver_load - setup chip and create an initial config
1700 * @ent: matching PCI ID entry
1702 * The driver load routine has to do several things:
1703 * - drive output discovery via intel_modeset_init()
1704 * - initialize the memory manager
1705 * - allocate initial config memory
1706 * - setup the DRM framebuffer with the allocated memory
1708 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1710 const struct intel_device_info *match_info =
1711 (struct intel_device_info *)ent->driver_data;
1712 struct drm_i915_private *dev_priv;
1715 dev_priv = i915_driver_create(pdev, ent);
1716 if (IS_ERR(dev_priv))
1717 return PTR_ERR(dev_priv);
1719 /* Disable nuclear pageflip by default on pre-ILK */
1720 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1721 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1723 ret = pci_enable_device(pdev);
1727 ret = i915_driver_init_early(dev_priv);
1729 goto out_pci_disable;
1731 disable_rpm_wakeref_asserts(dev_priv);
1733 ret = i915_driver_init_mmio(dev_priv);
1735 goto out_runtime_pm_put;
1737 ret = i915_driver_init_hw(dev_priv);
1739 goto out_cleanup_mmio;
1741 ret = i915_load_modeset_init(&dev_priv->drm);
1743 goto out_cleanup_hw;
1745 i915_driver_register(dev_priv);
1747 enable_rpm_wakeref_asserts(dev_priv);
1749 i915_welcome_messages(dev_priv);
1754 i915_driver_cleanup_hw(dev_priv);
1756 i915_driver_cleanup_mmio(dev_priv);
1758 enable_rpm_wakeref_asserts(dev_priv);
1759 i915_driver_cleanup_early(dev_priv);
1761 pci_disable_device(pdev);
1763 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1764 i915_driver_destroy(dev_priv);
1768 void i915_driver_unload(struct drm_device *dev)
1770 struct drm_i915_private *dev_priv = to_i915(dev);
1771 struct pci_dev *pdev = dev_priv->drm.pdev;
1773 disable_rpm_wakeref_asserts(dev_priv);
1775 i915_driver_unregister(dev_priv);
1777 if (i915_gem_suspend(dev_priv))
1778 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1780 drm_atomic_helper_shutdown(dev);
1782 intel_gvt_cleanup(dev_priv);
1784 intel_modeset_cleanup(dev);
1786 intel_bios_cleanup(dev_priv);
1788 vga_switcheroo_unregister_client(pdev);
1789 vga_client_register(pdev, NULL, NULL, NULL);
1791 intel_csr_ucode_fini(dev_priv);
1793 /* Free error state after interrupts are fully disabled. */
1794 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1795 i915_reset_error_state(dev_priv);
1797 i915_gem_fini(dev_priv);
1799 intel_power_domains_fini_hw(dev_priv);
1801 i915_driver_cleanup_hw(dev_priv);
1802 i915_driver_cleanup_mmio(dev_priv);
1804 enable_rpm_wakeref_asserts(dev_priv);
1806 WARN_ON(atomic_read(&dev_priv->runtime_pm.wakeref_count));
1809 static void i915_driver_release(struct drm_device *dev)
1811 struct drm_i915_private *dev_priv = to_i915(dev);
1813 i915_driver_cleanup_early(dev_priv);
1814 i915_driver_destroy(dev_priv);
1817 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1819 struct drm_i915_private *i915 = to_i915(dev);
1822 ret = i915_gem_open(i915, file);
1830 * i915_driver_lastclose - clean up after all DRM clients have exited
1833 * Take care of cleaning up after all DRM clients have exited. In the
1834 * mode setting case, we want to restore the kernel's initial mode (just
1835 * in case the last client left us in a bad state).
1837 * Additionally, in the non-mode setting case, we'll tear down the GTT
1838 * and DMA structures, since the kernel won't be using them, and clea
1841 static void i915_driver_lastclose(struct drm_device *dev)
1843 intel_fbdev_restore_mode(dev);
1844 vga_switcheroo_process_delayed_switch();
1847 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1849 struct drm_i915_file_private *file_priv = file->driver_priv;
1851 mutex_lock(&dev->struct_mutex);
1852 i915_gem_context_close(file);
1853 i915_gem_release(dev, file);
1854 mutex_unlock(&dev->struct_mutex);
1859 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1861 struct drm_device *dev = &dev_priv->drm;
1862 struct intel_encoder *encoder;
1864 drm_modeset_lock_all(dev);
1865 for_each_intel_encoder(dev, encoder)
1866 if (encoder->suspend)
1867 encoder->suspend(encoder);
1868 drm_modeset_unlock_all(dev);
1871 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1873 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1875 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1877 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1878 if (acpi_target_system_state() < ACPI_STATE_S3)
1884 static int i915_drm_prepare(struct drm_device *dev)
1886 struct drm_i915_private *i915 = to_i915(dev);
1890 * NB intel_display_suspend() may issue new requests after we've
1891 * ostensibly marked the GPU as ready-to-sleep here. We need to
1892 * split out that work and pull it forward so that after point,
1893 * the GPU is not woken again.
1895 err = i915_gem_suspend(i915);
1897 dev_err(&i915->drm.pdev->dev,
1898 "GEM idle failed, suspend/resume might fail\n");
1903 static int i915_drm_suspend(struct drm_device *dev)
1905 struct drm_i915_private *dev_priv = to_i915(dev);
1906 struct pci_dev *pdev = dev_priv->drm.pdev;
1907 pci_power_t opregion_target_state;
1909 disable_rpm_wakeref_asserts(dev_priv);
1911 /* We do a lot of poking in a lot of registers, make sure they work
1913 intel_power_domains_disable(dev_priv);
1915 drm_kms_helper_poll_disable(dev);
1917 pci_save_state(pdev);
1919 intel_display_suspend(dev);
1921 intel_dp_mst_suspend(dev_priv);
1923 intel_runtime_pm_disable_interrupts(dev_priv);
1924 intel_hpd_cancel_work(dev_priv);
1926 intel_suspend_encoders(dev_priv);
1928 intel_suspend_hw(dev_priv);
1930 i915_gem_suspend_gtt_mappings(dev_priv);
1932 i915_save_state(dev_priv);
1934 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1935 intel_opregion_suspend(dev_priv, opregion_target_state);
1937 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1939 dev_priv->suspend_count++;
1941 intel_csr_ucode_suspend(dev_priv);
1943 enable_rpm_wakeref_asserts(dev_priv);
1948 static enum i915_drm_suspend_mode
1949 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1952 return I915_DRM_SUSPEND_HIBERNATE;
1954 if (suspend_to_idle(dev_priv))
1955 return I915_DRM_SUSPEND_IDLE;
1957 return I915_DRM_SUSPEND_MEM;
1960 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1962 struct drm_i915_private *dev_priv = to_i915(dev);
1963 struct pci_dev *pdev = dev_priv->drm.pdev;
1966 disable_rpm_wakeref_asserts(dev_priv);
1968 i915_gem_suspend_late(dev_priv);
1970 intel_uncore_suspend(dev_priv);
1972 intel_power_domains_suspend(dev_priv,
1973 get_suspend_mode(dev_priv, hibernation));
1976 if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
1977 bxt_enable_dc9(dev_priv);
1978 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1979 hsw_enable_pc8(dev_priv);
1980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1981 ret = vlv_suspend_complete(dev_priv);
1984 DRM_ERROR("Suspend complete failed: %d\n", ret);
1985 intel_power_domains_resume(dev_priv);
1990 pci_disable_device(pdev);
1992 * During hibernation on some platforms the BIOS may try to access
1993 * the device even though it's already in D3 and hang the machine. So
1994 * leave the device in D0 on those platforms and hope the BIOS will
1995 * power down the device properly. The issue was seen on multiple old
1996 * GENs with different BIOS vendors, so having an explicit blacklist
1997 * is inpractical; apply the workaround on everything pre GEN6. The
1998 * platforms where the issue was seen:
1999 * Lenovo Thinkpad X301, X61s, X60, T60, X41
2003 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2004 pci_set_power_state(pdev, PCI_D3hot);
2007 enable_rpm_wakeref_asserts(dev_priv);
2012 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2017 DRM_ERROR("dev: %p\n", dev);
2018 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2022 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2023 state.event != PM_EVENT_FREEZE))
2026 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2029 error = i915_drm_suspend(dev);
2033 return i915_drm_suspend_late(dev, false);
2036 static int i915_drm_resume(struct drm_device *dev)
2038 struct drm_i915_private *dev_priv = to_i915(dev);
2041 disable_rpm_wakeref_asserts(dev_priv);
2042 intel_sanitize_gt_powersave(dev_priv);
2044 i915_gem_sanitize(dev_priv);
2046 ret = i915_ggtt_enable_hw(dev_priv);
2048 DRM_ERROR("failed to re-enable GGTT\n");
2050 intel_csr_ucode_resume(dev_priv);
2052 i915_restore_state(dev_priv);
2053 intel_pps_unlock_regs_wa(dev_priv);
2055 intel_init_pch_refclk(dev_priv);
2058 * Interrupts have to be enabled before any batches are run. If not the
2059 * GPU will hang. i915_gem_init_hw() will initiate batches to
2060 * update/restore the context.
2062 * drm_mode_config_reset() needs AUX interrupts.
2064 * Modeset enabling in intel_modeset_init_hw() also needs working
2067 intel_runtime_pm_enable_interrupts(dev_priv);
2069 drm_mode_config_reset(dev);
2071 i915_gem_resume(dev_priv);
2073 intel_modeset_init_hw(dev);
2074 intel_init_clock_gating(dev_priv);
2076 spin_lock_irq(&dev_priv->irq_lock);
2077 if (dev_priv->display.hpd_irq_setup)
2078 dev_priv->display.hpd_irq_setup(dev_priv);
2079 spin_unlock_irq(&dev_priv->irq_lock);
2081 intel_dp_mst_resume(dev_priv);
2083 intel_display_resume(dev);
2085 drm_kms_helper_poll_enable(dev);
2088 * ... but also need to make sure that hotplug processing
2089 * doesn't cause havoc. Like in the driver load code we don't
2090 * bother with the tiny race here where we might lose hotplug
2093 intel_hpd_init(dev_priv);
2095 intel_opregion_resume(dev_priv);
2097 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2099 intel_power_domains_enable(dev_priv);
2101 enable_rpm_wakeref_asserts(dev_priv);
2106 static int i915_drm_resume_early(struct drm_device *dev)
2108 struct drm_i915_private *dev_priv = to_i915(dev);
2109 struct pci_dev *pdev = dev_priv->drm.pdev;
2113 * We have a resume ordering issue with the snd-hda driver also
2114 * requiring our device to be power up. Due to the lack of a
2115 * parent/child relationship we currently solve this with an early
2118 * FIXME: This should be solved with a special hdmi sink device or
2119 * similar so that power domains can be employed.
2123 * Note that we need to set the power state explicitly, since we
2124 * powered off the device during freeze and the PCI core won't power
2125 * it back up for us during thaw. Powering off the device during
2126 * freeze is not a hard requirement though, and during the
2127 * suspend/resume phases the PCI core makes sure we get here with the
2128 * device powered on. So in case we change our freeze logic and keep
2129 * the device powered we can also remove the following set power state
2132 ret = pci_set_power_state(pdev, PCI_D0);
2134 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2139 * Note that pci_enable_device() first enables any parent bridge
2140 * device and only then sets the power state for this device. The
2141 * bridge enabling is a nop though, since bridge devices are resumed
2142 * first. The order of enabling power and enabling the device is
2143 * imposed by the PCI core as described above, so here we preserve the
2144 * same order for the freeze/thaw phases.
2146 * TODO: eventually we should remove pci_disable_device() /
2147 * pci_enable_enable_device() from suspend/resume. Due to how they
2148 * depend on the device enable refcount we can't anyway depend on them
2149 * disabling/enabling the device.
2151 if (pci_enable_device(pdev))
2154 pci_set_master(pdev);
2156 disable_rpm_wakeref_asserts(dev_priv);
2158 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2159 ret = vlv_resume_prepare(dev_priv, false);
2161 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2164 intel_uncore_resume_early(dev_priv);
2166 if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2167 gen9_sanitize_dc_state(dev_priv);
2168 bxt_disable_dc9(dev_priv);
2169 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2170 hsw_disable_pc8(dev_priv);
2173 intel_uncore_sanitize(dev_priv);
2175 intel_power_domains_resume(dev_priv);
2177 intel_engines_sanitize(dev_priv);
2179 enable_rpm_wakeref_asserts(dev_priv);
2184 static int i915_resume_switcheroo(struct drm_device *dev)
2188 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2191 ret = i915_drm_resume_early(dev);
2195 return i915_drm_resume(dev);
2199 * i915_reset - reset chip after a hang
2200 * @i915: #drm_i915_private to reset
2201 * @stalled_mask: mask of the stalled engines with the guilty requests
2202 * @reason: user error message for why we are resetting
2204 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
2207 * Caller must hold the struct_mutex.
2209 * Procedure is fairly simple:
2210 * - reset the chip using the reset reg
2211 * - re-init context state
2212 * - re-init hardware status page
2213 * - re-init ring buffer
2214 * - re-init interrupt state
2217 void i915_reset(struct drm_i915_private *i915,
2218 unsigned int stalled_mask,
2221 struct i915_gpu_error *error = &i915->gpu_error;
2225 GEM_TRACE("flags=%lx\n", error->flags);
2228 lockdep_assert_held(&i915->drm.struct_mutex);
2229 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
2231 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
2234 /* Clear any previous failed attempts at recovery. Time to try again. */
2235 if (!i915_gem_unset_wedged(i915))
2239 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
2240 error->reset_count++;
2242 ret = i915_gem_reset_prepare(i915);
2244 dev_err(i915->drm.dev, "GPU recovery failed\n");
2248 if (!intel_has_gpu_reset(i915)) {
2249 if (i915_modparams.reset)
2250 dev_err(i915->drm.dev, "GPU reset not supported\n");
2252 DRM_DEBUG_DRIVER("GPU reset disabled\n");
2256 for (i = 0; i < 3; i++) {
2257 ret = intel_gpu_reset(i915, ALL_ENGINES);
2264 dev_err(i915->drm.dev, "Failed to reset chip\n");
2268 /* Ok, now get things going again... */
2271 * Everything depends on having the GTT running, so we need to start
2274 ret = i915_ggtt_enable_hw(i915);
2276 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
2281 i915_gem_reset(i915, stalled_mask);
2282 intel_overlay_reset(i915);
2285 * Next we need to restore the context, but we don't use those
2288 * Ring buffer needs to be re-initialized in the KMS case, or if X
2289 * was running at the time of the reset (i.e. we weren't VT
2292 ret = i915_gem_init_hw(i915);
2294 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
2299 i915_queue_hangcheck(i915);
2302 i915_gem_reset_finish(i915);
2304 clear_bit(I915_RESET_HANDOFF, &error->flags);
2305 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
2310 * History tells us that if we cannot reset the GPU now, we
2311 * never will. This then impacts everything that is run
2312 * subsequently. On failing the reset, we mark the driver
2313 * as wedged, preventing further execution on the GPU.
2314 * We also want to go one step further and add a taint to the
2315 * kernel so that any subsequent faults can be traced back to
2316 * this failure. This is important for CI, where if the
2317 * GPU/driver fails we would like to reboot and restart testing
2318 * rather than continue on into oblivion. For everyone else,
2319 * the system should still plod along, but they have been warned!
2321 add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2323 i915_gem_set_wedged(i915);
2324 i915_retire_requests(i915);
2328 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2329 struct intel_engine_cs *engine)
2331 return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2335 * i915_reset_engine - reset GPU engine to recover from a hang
2336 * @engine: engine to reset
2337 * @msg: reason for GPU reset; or NULL for no dev_notice()
2339 * Reset a specific GPU engine. Useful if a hang is detected.
2340 * Returns zero on successful reset or otherwise an error code.
2343 * - identifies the request that caused the hang and it is dropped
2344 * - reset engine (which will force the engine to idle)
2345 * - re-init/configure engine
2347 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2349 struct i915_gpu_error *error = &engine->i915->gpu_error;
2350 struct i915_request *active_request;
2353 GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2354 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2356 active_request = i915_gem_reset_prepare_engine(engine);
2357 if (IS_ERR_OR_NULL(active_request)) {
2358 /* Either the previous reset failed, or we pardon the reset. */
2359 ret = PTR_ERR(active_request);
2364 dev_notice(engine->i915->drm.dev,
2365 "Resetting %s for %s\n", engine->name, msg);
2366 error->reset_engine_count[engine->id]++;
2368 if (!engine->i915->guc.execbuf_client)
2369 ret = intel_gt_reset_engine(engine->i915, engine);
2371 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2373 /* If we fail here, we expect to fallback to a global reset */
2374 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2375 engine->i915->guc.execbuf_client ? "GuC " : "",
2381 * The request that caused the hang is stuck on elsp, we know the
2382 * active request and can drop it, adjust head to skip the offending
2383 * request to resume executing remaining requests in the queue.
2385 i915_gem_reset_engine(engine, active_request, true);
2388 * The engine and its registers (and workarounds in case of render)
2389 * have been reset to their default values. Follow the init_ring
2390 * process to program RING_MODE, HWSP and re-enable submission.
2392 ret = engine->init_hw(engine);
2397 intel_engine_cancel_stop_cs(engine);
2398 i915_gem_reset_finish_engine(engine);
2402 static int i915_pm_prepare(struct device *kdev)
2404 struct pci_dev *pdev = to_pci_dev(kdev);
2405 struct drm_device *dev = pci_get_drvdata(pdev);
2408 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2412 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2415 return i915_drm_prepare(dev);
2418 static int i915_pm_suspend(struct device *kdev)
2420 struct pci_dev *pdev = to_pci_dev(kdev);
2421 struct drm_device *dev = pci_get_drvdata(pdev);
2424 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2428 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2431 return i915_drm_suspend(dev);
2434 static int i915_pm_suspend_late(struct device *kdev)
2436 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2439 * We have a suspend ordering issue with the snd-hda driver also
2440 * requiring our device to be power up. Due to the lack of a
2441 * parent/child relationship we currently solve this with an late
2444 * FIXME: This should be solved with a special hdmi sink device or
2445 * similar so that power domains can be employed.
2447 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2450 return i915_drm_suspend_late(dev, false);
2453 static int i915_pm_poweroff_late(struct device *kdev)
2455 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2457 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2460 return i915_drm_suspend_late(dev, true);
2463 static int i915_pm_resume_early(struct device *kdev)
2465 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2467 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2470 return i915_drm_resume_early(dev);
2473 static int i915_pm_resume(struct device *kdev)
2475 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2477 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2480 return i915_drm_resume(dev);
2483 /* freeze: before creating the hibernation_image */
2484 static int i915_pm_freeze(struct device *kdev)
2486 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2489 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2490 ret = i915_drm_suspend(dev);
2495 ret = i915_gem_freeze(kdev_to_i915(kdev));
2502 static int i915_pm_freeze_late(struct device *kdev)
2504 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2507 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2508 ret = i915_drm_suspend_late(dev, true);
2513 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2520 /* thaw: called after creating the hibernation image, but before turning off. */
2521 static int i915_pm_thaw_early(struct device *kdev)
2523 return i915_pm_resume_early(kdev);
2526 static int i915_pm_thaw(struct device *kdev)
2528 return i915_pm_resume(kdev);
2531 /* restore: called after loading the hibernation image. */
2532 static int i915_pm_restore_early(struct device *kdev)
2534 return i915_pm_resume_early(kdev);
2537 static int i915_pm_restore(struct device *kdev)
2539 return i915_pm_resume(kdev);
2543 * Save all Gunit registers that may be lost after a D3 and a subsequent
2544 * S0i[R123] transition. The list of registers needing a save/restore is
2545 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2546 * registers in the following way:
2547 * - Driver: saved/restored by the driver
2548 * - Punit : saved/restored by the Punit firmware
2549 * - No, w/o marking: no need to save/restore, since the register is R/O or
2550 * used internally by the HW in a way that doesn't depend
2551 * keeping the content across a suspend/resume.
2552 * - Debug : used for debugging
2554 * We save/restore all registers marked with 'Driver', with the following
2556 * - Registers out of use, including also registers marked with 'Debug'.
2557 * These have no effect on the driver's operation, so we don't save/restore
2558 * them to reduce the overhead.
2559 * - Registers that are fully setup by an initialization function called from
2560 * the resume path. For example many clock gating and RPS/RC6 registers.
2561 * - Registers that provide the right functionality with their reset defaults.
2563 * TODO: Except for registers that based on the above 3 criteria can be safely
2564 * ignored, we save/restore all others, practically treating the HW context as
2565 * a black-box for the driver. Further investigation is needed to reduce the
2566 * saved/restored registers even further, by following the same 3 criteria.
2568 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2570 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2573 /* GAM 0x4000-0x4770 */
2574 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2575 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2576 s->arb_mode = I915_READ(ARB_MODE);
2577 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2578 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2580 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2581 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2583 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2584 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2586 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2587 s->ecochk = I915_READ(GAM_ECOCHK);
2588 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2589 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2591 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2593 /* MBC 0x9024-0x91D0, 0x8500 */
2594 s->g3dctl = I915_READ(VLV_G3DCTL);
2595 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2596 s->mbctl = I915_READ(GEN6_MBCTL);
2598 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2599 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2600 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2601 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2602 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2603 s->rstctl = I915_READ(GEN6_RSTCTL);
2604 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2606 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2607 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2608 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2609 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2610 s->ecobus = I915_READ(ECOBUS);
2611 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2612 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2613 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2614 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2615 s->rcedata = I915_READ(VLV_RCEDATA);
2616 s->spare2gh = I915_READ(VLV_SPAREG2H);
2618 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2619 s->gt_imr = I915_READ(GTIMR);
2620 s->gt_ier = I915_READ(GTIER);
2621 s->pm_imr = I915_READ(GEN6_PMIMR);
2622 s->pm_ier = I915_READ(GEN6_PMIER);
2624 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2625 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2627 /* GT SA CZ domain, 0x100000-0x138124 */
2628 s->tilectl = I915_READ(TILECTL);
2629 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2630 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2631 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2632 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2634 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2635 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2636 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2637 s->pcbr = I915_READ(VLV_PCBR);
2638 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2641 * Not saving any of:
2642 * DFT, 0x9800-0x9EC0
2643 * SARB, 0xB000-0xB1FC
2644 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2649 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2651 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2655 /* GAM 0x4000-0x4770 */
2656 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2657 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2658 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2659 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2660 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2662 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2663 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2665 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2666 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2668 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2669 I915_WRITE(GAM_ECOCHK, s->ecochk);
2670 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2671 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2673 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2675 /* MBC 0x9024-0x91D0, 0x8500 */
2676 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2677 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2678 I915_WRITE(GEN6_MBCTL, s->mbctl);
2680 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2681 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2682 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2683 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2684 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2685 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2686 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2688 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2689 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2690 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2691 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2692 I915_WRITE(ECOBUS, s->ecobus);
2693 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2694 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2695 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2696 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2697 I915_WRITE(VLV_RCEDATA, s->rcedata);
2698 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2700 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2701 I915_WRITE(GTIMR, s->gt_imr);
2702 I915_WRITE(GTIER, s->gt_ier);
2703 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2704 I915_WRITE(GEN6_PMIER, s->pm_ier);
2706 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2707 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2709 /* GT SA CZ domain, 0x100000-0x138124 */
2710 I915_WRITE(TILECTL, s->tilectl);
2711 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2713 * Preserve the GT allow wake and GFX force clock bit, they are not
2714 * be restored, as they are used to control the s0ix suspend/resume
2715 * sequence by the caller.
2717 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2718 val &= VLV_GTLC_ALLOWWAKEREQ;
2719 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2720 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2722 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2723 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2724 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2725 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2727 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2729 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2730 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2731 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2732 I915_WRITE(VLV_PCBR, s->pcbr);
2733 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2736 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2739 /* The HW does not like us polling for PW_STATUS frequently, so
2740 * use the sleeping loop rather than risk the busy spin within
2741 * intel_wait_for_register().
2743 * Transitioning between RC6 states should be at most 2ms (see
2744 * valleyview_enable_rps) so use a 3ms timeout.
2746 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2750 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2755 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2756 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2758 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2759 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2764 err = intel_wait_for_register(dev_priv,
2765 VLV_GTLC_SURVIVABILITY_REG,
2766 VLV_GFX_CLK_STATUS_BIT,
2767 VLV_GFX_CLK_STATUS_BIT,
2770 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2771 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2776 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2782 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2783 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2785 val |= VLV_GTLC_ALLOWWAKEREQ;
2786 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2787 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2789 mask = VLV_GTLC_ALLOWWAKEACK;
2790 val = allow ? mask : 0;
2792 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2794 DRM_ERROR("timeout disabling GT waking\n");
2799 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2805 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2806 val = wait_for_on ? mask : 0;
2809 * RC6 transitioning can be delayed up to 2 msec (see
2810 * valleyview_enable_rps), use 3 msec for safety.
2812 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2813 * reset and we are trying to force the machine to sleep.
2815 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2816 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2817 onoff(wait_for_on));
2820 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2822 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2825 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2826 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2829 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2835 * Bspec defines the following GT well on flags as debug only, so
2836 * don't treat them as hard failures.
2838 vlv_wait_for_gt_wells(dev_priv, false);
2840 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2841 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2843 vlv_check_no_gt_access(dev_priv);
2845 err = vlv_force_gfx_clock(dev_priv, true);
2849 err = vlv_allow_gt_wake(dev_priv, false);
2853 if (!IS_CHERRYVIEW(dev_priv))
2854 vlv_save_gunit_s0ix_state(dev_priv);
2856 err = vlv_force_gfx_clock(dev_priv, false);
2863 /* For safety always re-enable waking and disable gfx clock forcing */
2864 vlv_allow_gt_wake(dev_priv, true);
2866 vlv_force_gfx_clock(dev_priv, false);
2871 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2878 * If any of the steps fail just try to continue, that's the best we
2879 * can do at this point. Return the first error code (which will also
2880 * leave RPM permanently disabled).
2882 ret = vlv_force_gfx_clock(dev_priv, true);
2884 if (!IS_CHERRYVIEW(dev_priv))
2885 vlv_restore_gunit_s0ix_state(dev_priv);
2887 err = vlv_allow_gt_wake(dev_priv, true);
2891 err = vlv_force_gfx_clock(dev_priv, false);
2895 vlv_check_no_gt_access(dev_priv);
2898 intel_init_clock_gating(dev_priv);
2903 static int intel_runtime_suspend(struct device *kdev)
2905 struct pci_dev *pdev = to_pci_dev(kdev);
2906 struct drm_device *dev = pci_get_drvdata(pdev);
2907 struct drm_i915_private *dev_priv = to_i915(dev);
2910 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2913 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2916 DRM_DEBUG_KMS("Suspending device\n");
2918 disable_rpm_wakeref_asserts(dev_priv);
2921 * We are safe here against re-faults, since the fault handler takes
2924 i915_gem_runtime_suspend(dev_priv);
2926 intel_uc_suspend(dev_priv);
2928 intel_runtime_pm_disable_interrupts(dev_priv);
2930 intel_uncore_suspend(dev_priv);
2933 if (INTEL_GEN(dev_priv) >= 11) {
2934 icl_display_core_uninit(dev_priv);
2935 bxt_enable_dc9(dev_priv);
2936 } else if (IS_GEN9_LP(dev_priv)) {
2937 bxt_display_core_uninit(dev_priv);
2938 bxt_enable_dc9(dev_priv);
2939 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2940 hsw_enable_pc8(dev_priv);
2941 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2942 ret = vlv_suspend_complete(dev_priv);
2946 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2947 intel_uncore_runtime_resume(dev_priv);
2949 intel_runtime_pm_enable_interrupts(dev_priv);
2951 intel_uc_resume(dev_priv);
2953 i915_gem_init_swizzling(dev_priv);
2954 i915_gem_restore_fences(dev_priv);
2956 enable_rpm_wakeref_asserts(dev_priv);
2961 enable_rpm_wakeref_asserts(dev_priv);
2962 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2964 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2965 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2967 dev_priv->runtime_pm.suspended = true;
2970 * FIXME: We really should find a document that references the arguments
2973 if (IS_BROADWELL(dev_priv)) {
2975 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2976 * being detected, and the call we do at intel_runtime_resume()
2977 * won't be able to restore them. Since PCI_D3hot matches the
2978 * actual specification and appears to be working, use it.
2980 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2983 * current versions of firmware which depend on this opregion
2984 * notification have repurposed the D1 definition to mean
2985 * "runtime suspended" vs. what you would normally expect (D3)
2986 * to distinguish it from notifications that might be sent via
2989 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2992 assert_forcewakes_inactive(dev_priv);
2994 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2995 intel_hpd_poll_init(dev_priv);
2997 DRM_DEBUG_KMS("Device suspended\n");
3001 static int intel_runtime_resume(struct device *kdev)
3003 struct pci_dev *pdev = to_pci_dev(kdev);
3004 struct drm_device *dev = pci_get_drvdata(pdev);
3005 struct drm_i915_private *dev_priv = to_i915(dev);
3008 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
3011 DRM_DEBUG_KMS("Resuming device\n");
3013 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
3014 disable_rpm_wakeref_asserts(dev_priv);
3016 intel_opregion_notify_adapter(dev_priv, PCI_D0);
3017 dev_priv->runtime_pm.suspended = false;
3018 if (intel_uncore_unclaimed_mmio(dev_priv))
3019 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
3021 if (INTEL_GEN(dev_priv) >= 11) {
3022 bxt_disable_dc9(dev_priv);
3023 icl_display_core_init(dev_priv, true);
3024 if (dev_priv->csr.dmc_payload) {
3025 if (dev_priv->csr.allowed_dc_mask &
3026 DC_STATE_EN_UPTO_DC6)
3027 skl_enable_dc6(dev_priv);
3028 else if (dev_priv->csr.allowed_dc_mask &
3029 DC_STATE_EN_UPTO_DC5)
3030 gen9_enable_dc5(dev_priv);
3032 } else if (IS_GEN9_LP(dev_priv)) {
3033 bxt_disable_dc9(dev_priv);
3034 bxt_display_core_init(dev_priv, true);
3035 if (dev_priv->csr.dmc_payload &&
3036 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
3037 gen9_enable_dc5(dev_priv);
3038 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3039 hsw_disable_pc8(dev_priv);
3040 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3041 ret = vlv_resume_prepare(dev_priv, true);
3044 intel_uncore_runtime_resume(dev_priv);
3046 intel_runtime_pm_enable_interrupts(dev_priv);
3048 intel_uc_resume(dev_priv);
3051 * No point of rolling back things in case of an error, as the best
3052 * we can do is to hope that things will still work (and disable RPM).
3054 i915_gem_init_swizzling(dev_priv);
3055 i915_gem_restore_fences(dev_priv);
3058 * On VLV/CHV display interrupts are part of the display
3059 * power well, so hpd is reinitialized from there. For
3060 * everyone else do it here.
3062 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
3063 intel_hpd_init(dev_priv);
3065 intel_enable_ipc(dev_priv);
3067 enable_rpm_wakeref_asserts(dev_priv);
3070 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
3072 DRM_DEBUG_KMS("Device resumed\n");
3077 const struct dev_pm_ops i915_pm_ops = {
3079 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3082 .prepare = i915_pm_prepare,
3083 .suspend = i915_pm_suspend,
3084 .suspend_late = i915_pm_suspend_late,
3085 .resume_early = i915_pm_resume_early,
3086 .resume = i915_pm_resume,
3090 * @freeze, @freeze_late : called (1) before creating the
3091 * hibernation image [PMSG_FREEZE] and
3092 * (2) after rebooting, before restoring
3093 * the image [PMSG_QUIESCE]
3094 * @thaw, @thaw_early : called (1) after creating the hibernation
3095 * image, before writing it [PMSG_THAW]
3096 * and (2) after failing to create or
3097 * restore the image [PMSG_RECOVER]
3098 * @poweroff, @poweroff_late: called after writing the hibernation
3099 * image, before rebooting [PMSG_HIBERNATE]
3100 * @restore, @restore_early : called after rebooting and restoring the
3101 * hibernation image [PMSG_RESTORE]
3103 .freeze = i915_pm_freeze,
3104 .freeze_late = i915_pm_freeze_late,
3105 .thaw_early = i915_pm_thaw_early,
3106 .thaw = i915_pm_thaw,
3107 .poweroff = i915_pm_suspend,
3108 .poweroff_late = i915_pm_poweroff_late,
3109 .restore_early = i915_pm_restore_early,
3110 .restore = i915_pm_restore,
3112 /* S0ix (via runtime suspend) event handlers */
3113 .runtime_suspend = intel_runtime_suspend,
3114 .runtime_resume = intel_runtime_resume,
3117 static const struct vm_operations_struct i915_gem_vm_ops = {
3118 .fault = i915_gem_fault,
3119 .open = drm_gem_vm_open,
3120 .close = drm_gem_vm_close,
3123 static const struct file_operations i915_driver_fops = {
3124 .owner = THIS_MODULE,
3126 .release = drm_release,
3127 .unlocked_ioctl = drm_ioctl,
3128 .mmap = drm_gem_mmap,
3131 .compat_ioctl = i915_compat_ioctl,
3132 .llseek = noop_llseek,
3136 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3137 struct drm_file *file)
3142 static const struct drm_ioctl_desc i915_ioctls[] = {
3143 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3144 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3145 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3146 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3147 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3148 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3149 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3150 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3151 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3152 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3153 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3154 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3155 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3156 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3157 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
3158 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3159 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3160 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3161 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3162 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3163 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3164 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3165 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3166 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3167 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3168 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3169 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3170 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3171 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3172 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3173 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3174 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3175 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3176 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3177 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3178 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3179 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3180 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3181 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3182 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3183 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3184 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3185 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3186 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3187 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3188 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3189 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3190 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3191 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3192 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3193 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3194 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3195 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3196 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3197 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3198 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3201 static struct drm_driver driver = {
3202 /* Don't use MTRRs here; the Xserver or userspace app should
3203 * deal with them for Intel hardware.
3206 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
3207 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3208 .release = i915_driver_release,
3209 .open = i915_driver_open,
3210 .lastclose = i915_driver_lastclose,
3211 .postclose = i915_driver_postclose,
3213 .gem_close_object = i915_gem_close_object,
3214 .gem_free_object_unlocked = i915_gem_free_object,
3215 .gem_vm_ops = &i915_gem_vm_ops,
3217 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3218 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3219 .gem_prime_export = i915_gem_prime_export,
3220 .gem_prime_import = i915_gem_prime_import,
3222 .dumb_create = i915_gem_dumb_create,
3223 .dumb_map_offset = i915_gem_mmap_gtt,
3224 .ioctls = i915_ioctls,
3225 .num_ioctls = ARRAY_SIZE(i915_ioctls),
3226 .fops = &i915_driver_fops,
3227 .name = DRIVER_NAME,
3228 .desc = DRIVER_DESC,
3229 .date = DRIVER_DATE,
3230 .major = DRIVER_MAJOR,
3231 .minor = DRIVER_MINOR,
3232 .patchlevel = DRIVER_PATCHLEVEL,
3235 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3236 #include "selftests/mock_drm.c"