1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/apple-gmux.h>
39 #include <linux/console.h>
40 #include <linux/module.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/vgaarb.h>
43 #include <linux/vga_switcheroo.h>
44 #include <drm/drm_crtc_helper.h>
46 static struct drm_driver driver;
48 #define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
55 #define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
60 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
63 #define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
66 #define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
70 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
72 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
74 static const struct intel_device_info intel_i830_info = {
75 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
82 static const struct intel_device_info intel_845g_info = {
83 .gen = 2, .num_pipes = 1,
84 .has_overlay = 1, .overlay_needs_physical = 1,
85 .ring_mask = RENDER_RING,
86 GEN_DEFAULT_PIPEOFFSETS,
90 static const struct intel_device_info intel_i85x_info = {
91 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
92 .cursor_needs_physical = 1,
93 .has_overlay = 1, .overlay_needs_physical = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
100 static const struct intel_device_info intel_i865g_info = {
101 .gen = 2, .num_pipes = 1,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
108 static const struct intel_device_info intel_i915g_info = {
109 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
110 .has_overlay = 1, .overlay_needs_physical = 1,
111 .ring_mask = RENDER_RING,
112 GEN_DEFAULT_PIPEOFFSETS,
115 static const struct intel_device_info intel_i915gm_info = {
116 .gen = 3, .is_mobile = 1, .num_pipes = 2,
117 .cursor_needs_physical = 1,
118 .has_overlay = 1, .overlay_needs_physical = 1,
121 .ring_mask = RENDER_RING,
122 GEN_DEFAULT_PIPEOFFSETS,
125 static const struct intel_device_info intel_i945g_info = {
126 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
127 .has_overlay = 1, .overlay_needs_physical = 1,
128 .ring_mask = RENDER_RING,
129 GEN_DEFAULT_PIPEOFFSETS,
132 static const struct intel_device_info intel_i945gm_info = {
133 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
134 .has_hotplug = 1, .cursor_needs_physical = 1,
135 .has_overlay = 1, .overlay_needs_physical = 1,
138 .ring_mask = RENDER_RING,
139 GEN_DEFAULT_PIPEOFFSETS,
143 static const struct intel_device_info intel_i965g_info = {
144 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
147 .ring_mask = RENDER_RING,
148 GEN_DEFAULT_PIPEOFFSETS,
152 static const struct intel_device_info intel_i965gm_info = {
153 .gen = 4, .is_crestline = 1, .num_pipes = 2,
154 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
157 .ring_mask = RENDER_RING,
158 GEN_DEFAULT_PIPEOFFSETS,
162 static const struct intel_device_info intel_g33_info = {
163 .gen = 3, .is_g33 = 1, .num_pipes = 2,
164 .need_gfx_hws = 1, .has_hotplug = 1,
166 .ring_mask = RENDER_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
171 static const struct intel_device_info intel_g45_info = {
172 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
173 .has_pipe_cxsr = 1, .has_hotplug = 1,
174 .ring_mask = RENDER_RING | BSD_RING,
175 GEN_DEFAULT_PIPEOFFSETS,
179 static const struct intel_device_info intel_gm45_info = {
180 .gen = 4, .is_g4x = 1, .num_pipes = 2,
181 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
182 .has_pipe_cxsr = 1, .has_hotplug = 1,
184 .ring_mask = RENDER_RING | BSD_RING,
185 GEN_DEFAULT_PIPEOFFSETS,
189 static const struct intel_device_info intel_pineview_info = {
190 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
193 GEN_DEFAULT_PIPEOFFSETS,
197 static const struct intel_device_info intel_ironlake_d_info = {
198 .gen = 5, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
200 .ring_mask = RENDER_RING | BSD_RING,
201 GEN_DEFAULT_PIPEOFFSETS,
205 static const struct intel_device_info intel_ironlake_m_info = {
206 .gen = 5, .is_mobile = 1, .num_pipes = 2,
207 .need_gfx_hws = 1, .has_hotplug = 1,
209 .ring_mask = RENDER_RING | BSD_RING,
210 GEN_DEFAULT_PIPEOFFSETS,
214 static const struct intel_device_info intel_sandybridge_d_info = {
215 .gen = 6, .num_pipes = 2,
216 .need_gfx_hws = 1, .has_hotplug = 1,
218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
220 GEN_DEFAULT_PIPEOFFSETS,
224 static const struct intel_device_info intel_sandybridge_m_info = {
225 .gen = 6, .is_mobile = 1, .num_pipes = 2,
226 .need_gfx_hws = 1, .has_hotplug = 1,
228 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
230 GEN_DEFAULT_PIPEOFFSETS,
234 #define GEN7_FEATURES \
235 .gen = 7, .num_pipes = 3, \
236 .need_gfx_hws = 1, .has_hotplug = 1, \
238 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
240 GEN_DEFAULT_PIPEOFFSETS, \
243 static const struct intel_device_info intel_ivybridge_d_info = {
248 static const struct intel_device_info intel_ivybridge_m_info = {
254 static const struct intel_device_info intel_ivybridge_q_info = {
257 .num_pipes = 0, /* legal, last one wins */
260 #define VLV_FEATURES \
261 .gen = 7, .num_pipes = 2, \
262 .need_gfx_hws = 1, .has_hotplug = 1, \
263 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
264 .display_mmio_offset = VLV_DISPLAY_BASE, \
265 GEN_DEFAULT_PIPEOFFSETS, \
268 static const struct intel_device_info intel_valleyview_m_info = {
274 static const struct intel_device_info intel_valleyview_d_info = {
279 #define HSW_FEATURES \
281 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
285 static const struct intel_device_info intel_haswell_d_info = {
290 static const struct intel_device_info intel_haswell_m_info = {
296 #define BDW_FEATURES \
300 static const struct intel_device_info intel_broadwell_d_info = {
305 static const struct intel_device_info intel_broadwell_m_info = {
307 .gen = 8, .is_mobile = 1,
310 static const struct intel_device_info intel_broadwell_gt3d_info = {
313 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
316 static const struct intel_device_info intel_broadwell_gt3m_info = {
318 .gen = 8, .is_mobile = 1,
319 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
322 static const struct intel_device_info intel_cherryview_info = {
323 .gen = 8, .num_pipes = 3,
324 .need_gfx_hws = 1, .has_hotplug = 1,
325 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
327 .display_mmio_offset = VLV_DISPLAY_BASE,
333 static const struct intel_device_info intel_skylake_info = {
339 static const struct intel_device_info intel_skylake_gt3_info = {
343 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
346 static const struct intel_device_info intel_broxton_info = {
350 .need_gfx_hws = 1, .has_hotplug = 1,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
356 GEN_DEFAULT_PIPEOFFSETS,
361 static const struct intel_device_info intel_kabylake_info = {
367 static const struct intel_device_info intel_kabylake_gt3_info = {
371 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
375 * Make sure any device matches here are from most specific to most
376 * general. For example, since the Quanta match is based on the subsystem
377 * and subvendor IDs, we need it to come before the more general IVB
378 * PCI ID matches, otherwise we'll use the wrong info struct above.
380 static const struct pci_device_id pciidlist[] = {
381 INTEL_I830_IDS(&intel_i830_info),
382 INTEL_I845G_IDS(&intel_845g_info),
383 INTEL_I85X_IDS(&intel_i85x_info),
384 INTEL_I865G_IDS(&intel_i865g_info),
385 INTEL_I915G_IDS(&intel_i915g_info),
386 INTEL_I915GM_IDS(&intel_i915gm_info),
387 INTEL_I945G_IDS(&intel_i945g_info),
388 INTEL_I945GM_IDS(&intel_i945gm_info),
389 INTEL_I965G_IDS(&intel_i965g_info),
390 INTEL_G33_IDS(&intel_g33_info),
391 INTEL_I965GM_IDS(&intel_i965gm_info),
392 INTEL_GM45_IDS(&intel_gm45_info),
393 INTEL_G45_IDS(&intel_g45_info),
394 INTEL_PINEVIEW_IDS(&intel_pineview_info),
395 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
396 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
397 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
398 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
399 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
400 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
401 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
402 INTEL_HSW_D_IDS(&intel_haswell_d_info),
403 INTEL_HSW_M_IDS(&intel_haswell_m_info),
404 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
405 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
406 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
407 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
408 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
409 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
410 INTEL_CHV_IDS(&intel_cherryview_info),
411 INTEL_SKL_GT1_IDS(&intel_skylake_info),
412 INTEL_SKL_GT2_IDS(&intel_skylake_info),
413 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
414 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
415 INTEL_BXT_IDS(&intel_broxton_info),
416 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
417 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
418 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
419 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
423 MODULE_DEVICE_TABLE(pci, pciidlist);
425 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
427 enum intel_pch ret = PCH_NOP;
430 * In a virtualized passthrough environment we can be in a
431 * setup where the ISA bridge is not able to be passed through.
432 * In this case, a south bridge can be emulated and we have to
433 * make an educated guess as to which PCH is really there.
438 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
439 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
441 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
442 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
444 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
445 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
447 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
453 void intel_detect_pch(struct drm_device *dev)
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct pci_dev *pch = NULL;
458 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
459 * (which really amounts to a PCH but no South Display).
461 if (INTEL_INFO(dev)->num_pipes == 0) {
462 dev_priv->pch_type = PCH_NOP;
467 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
468 * make graphics device passthrough work easy for VMM, that only
469 * need to expose ISA bridge to let driver know the real hardware
470 * underneath. This is a requirement from virtualization team.
472 * In some virtualized environments (e.g. XEN), there is irrelevant
473 * ISA bridge in the system. To work reliably, we should scan trhough
474 * all the ISA bridge devices and check for the first match, instead
475 * of only checking the first one.
477 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
478 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
479 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
480 dev_priv->pch_id = id;
482 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
483 dev_priv->pch_type = PCH_IBX;
484 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
485 WARN_ON(!IS_GEN5(dev));
486 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
487 dev_priv->pch_type = PCH_CPT;
488 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
489 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
490 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
491 /* PantherPoint is CPT compatible */
492 dev_priv->pch_type = PCH_CPT;
493 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
494 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
495 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
496 dev_priv->pch_type = PCH_LPT;
497 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
498 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
499 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
500 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
501 dev_priv->pch_type = PCH_LPT;
502 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
503 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
504 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
505 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
506 dev_priv->pch_type = PCH_SPT;
507 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
508 WARN_ON(!IS_SKYLAKE(dev) &&
510 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
511 dev_priv->pch_type = PCH_SPT;
512 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
513 WARN_ON(!IS_SKYLAKE(dev) &&
515 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
516 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
517 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
518 pch->subsystem_vendor == 0x1af4 &&
519 pch->subsystem_device == 0x1100)) {
520 dev_priv->pch_type = intel_virt_detect_pch(dev);
528 DRM_DEBUG_KMS("No PCH found.\n");
533 bool i915_semaphore_is_enabled(struct drm_device *dev)
535 if (INTEL_INFO(dev)->gen < 6)
538 if (i915.semaphores >= 0)
539 return i915.semaphores;
541 /* TODO: make semaphores and Execlists play nicely together */
542 if (i915.enable_execlists)
545 /* Until we get further testing... */
549 #ifdef CONFIG_INTEL_IOMMU
550 /* Enable semaphores on SNB when IO remapping is off */
551 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
558 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
560 struct drm_device *dev = dev_priv->dev;
561 struct intel_encoder *encoder;
563 drm_modeset_lock_all(dev);
564 for_each_intel_encoder(dev, encoder)
565 if (encoder->suspend)
566 encoder->suspend(encoder);
567 drm_modeset_unlock_all(dev);
570 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
571 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
573 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
575 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
577 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
578 if (acpi_target_system_state() < ACPI_STATE_S3)
584 static int i915_drm_suspend(struct drm_device *dev)
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 pci_power_t opregion_target_state;
590 /* ignore lid events during suspend */
591 mutex_lock(&dev_priv->modeset_restore_lock);
592 dev_priv->modeset_restore = MODESET_SUSPENDED;
593 mutex_unlock(&dev_priv->modeset_restore_lock);
595 disable_rpm_wakeref_asserts(dev_priv);
597 /* We do a lot of poking in a lot of registers, make sure they work
599 intel_display_set_init_power(dev_priv, true);
601 drm_kms_helper_poll_disable(dev);
603 pci_save_state(dev->pdev);
605 error = i915_gem_suspend(dev);
607 dev_err(&dev->pdev->dev,
608 "GEM idle failed, resume might fail\n");
612 intel_guc_suspend(dev);
614 intel_suspend_gt_powersave(dev);
616 intel_display_suspend(dev);
618 intel_dp_mst_suspend(dev);
620 intel_runtime_pm_disable_interrupts(dev_priv);
621 intel_hpd_cancel_work(dev_priv);
623 intel_suspend_encoders(dev_priv);
625 intel_suspend_hw(dev);
627 i915_gem_suspend_gtt_mappings(dev);
629 i915_save_state(dev);
631 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
632 intel_opregion_notify_adapter(dev, opregion_target_state);
634 intel_uncore_forcewake_reset(dev, false);
635 intel_opregion_fini(dev);
637 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
639 dev_priv->suspend_count++;
641 intel_display_set_init_power(dev_priv, false);
643 if (HAS_CSR(dev_priv))
644 flush_work(&dev_priv->csr.work);
647 enable_rpm_wakeref_asserts(dev_priv);
652 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
654 struct drm_i915_private *dev_priv = drm_dev->dev_private;
658 disable_rpm_wakeref_asserts(dev_priv);
660 fw_csr = !IS_BROXTON(dev_priv) &&
661 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
663 * In case of firmware assisted context save/restore don't manually
664 * deinit the power domains. This also means the CSR/DMC firmware will
665 * stay active, it will power down any HW resources as required and
666 * also enable deeper system power states that would be blocked if the
667 * firmware was inactive.
670 intel_power_domains_suspend(dev_priv);
672 ret = intel_suspend_complete(dev_priv);
675 DRM_ERROR("Suspend complete failed: %d\n", ret);
677 intel_power_domains_init_hw(dev_priv, true);
682 pci_disable_device(drm_dev->pdev);
684 * During hibernation on some platforms the BIOS may try to access
685 * the device even though it's already in D3 and hang the machine. So
686 * leave the device in D0 on those platforms and hope the BIOS will
687 * power down the device properly. The issue was seen on multiple old
688 * GENs with different BIOS vendors, so having an explicit blacklist
689 * is inpractical; apply the workaround on everything pre GEN6. The
690 * platforms where the issue was seen:
691 * Lenovo Thinkpad X301, X61s, X60, T60, X41
695 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
696 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
698 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
701 enable_rpm_wakeref_asserts(dev_priv);
706 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
710 if (!dev || !dev->dev_private) {
711 DRM_ERROR("dev: %p\n", dev);
712 DRM_ERROR("DRM not initialized, aborting suspend.\n");
716 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
717 state.event != PM_EVENT_FREEZE))
720 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
723 error = i915_drm_suspend(dev);
727 return i915_drm_suspend_late(dev, false);
730 static int i915_drm_resume(struct drm_device *dev)
732 struct drm_i915_private *dev_priv = dev->dev_private;
734 disable_rpm_wakeref_asserts(dev_priv);
736 mutex_lock(&dev->struct_mutex);
737 i915_gem_restore_gtt_mappings(dev);
738 mutex_unlock(&dev->struct_mutex);
740 i915_restore_state(dev);
741 intel_opregion_setup(dev);
743 intel_init_pch_refclk(dev);
744 drm_mode_config_reset(dev);
747 * Interrupts have to be enabled before any batches are run. If not the
748 * GPU will hang. i915_gem_init_hw() will initiate batches to
749 * update/restore the context.
751 * Modeset enabling in intel_modeset_init_hw() also needs working
754 intel_runtime_pm_enable_interrupts(dev_priv);
756 mutex_lock(&dev->struct_mutex);
757 if (i915_gem_init_hw(dev)) {
758 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
759 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
761 mutex_unlock(&dev->struct_mutex);
763 intel_guc_resume(dev);
765 intel_modeset_init_hw(dev);
767 spin_lock_irq(&dev_priv->irq_lock);
768 if (dev_priv->display.hpd_irq_setup)
769 dev_priv->display.hpd_irq_setup(dev);
770 spin_unlock_irq(&dev_priv->irq_lock);
772 intel_dp_mst_resume(dev);
774 intel_display_resume(dev);
777 * ... but also need to make sure that hotplug processing
778 * doesn't cause havoc. Like in the driver load code we don't
779 * bother with the tiny race here where we might loose hotplug
782 intel_hpd_init(dev_priv);
783 /* Config may have changed between suspend and resume */
784 drm_helper_hpd_irq_event(dev);
786 intel_opregion_init(dev);
788 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
790 mutex_lock(&dev_priv->modeset_restore_lock);
791 dev_priv->modeset_restore = MODESET_DONE;
792 mutex_unlock(&dev_priv->modeset_restore_lock);
794 intel_opregion_notify_adapter(dev, PCI_D0);
796 drm_kms_helper_poll_enable(dev);
798 enable_rpm_wakeref_asserts(dev_priv);
803 static int i915_drm_resume_early(struct drm_device *dev)
805 struct drm_i915_private *dev_priv = dev->dev_private;
809 * We have a resume ordering issue with the snd-hda driver also
810 * requiring our device to be power up. Due to the lack of a
811 * parent/child relationship we currently solve this with an early
814 * FIXME: This should be solved with a special hdmi sink device or
815 * similar so that power domains can be employed.
817 if (pci_enable_device(dev->pdev)) {
822 pci_set_master(dev->pdev);
824 disable_rpm_wakeref_asserts(dev_priv);
826 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
827 ret = vlv_resume_prepare(dev_priv, false);
829 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
832 intel_uncore_early_sanitize(dev, true);
835 ret = bxt_resume_prepare(dev_priv);
836 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
837 hsw_disable_pc8(dev_priv);
839 intel_uncore_sanitize(dev);
841 if (IS_BROXTON(dev_priv) ||
842 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
843 intel_power_domains_init_hw(dev_priv, true);
846 dev_priv->suspended_to_idle = false;
848 enable_rpm_wakeref_asserts(dev_priv);
853 int i915_resume_switcheroo(struct drm_device *dev)
857 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
860 ret = i915_drm_resume_early(dev);
864 return i915_drm_resume(dev);
868 * i915_reset - reset chip after a hang
869 * @dev: drm device to reset
871 * Reset the chip. Useful if a hang is detected. Returns zero on successful
872 * reset or otherwise an error code.
874 * Procedure is fairly simple:
875 * - reset the chip using the reset reg
876 * - re-init context state
877 * - re-init hardware status page
878 * - re-init ring buffer
879 * - re-init interrupt state
882 int i915_reset(struct drm_device *dev)
884 struct drm_i915_private *dev_priv = dev->dev_private;
885 struct i915_gpu_error *error = &dev_priv->gpu_error;
886 unsigned reset_counter;
889 intel_reset_gt_powersave(dev);
891 mutex_lock(&dev->struct_mutex);
893 /* Clear any previous failed attempts at recovery. Time to try again. */
894 atomic_andnot(I915_WEDGED, &error->reset_counter);
896 /* Clear the reset-in-progress flag and increment the reset epoch. */
897 reset_counter = atomic_inc_return(&error->reset_counter);
898 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
905 ret = intel_gpu_reset(dev, ALL_ENGINES);
907 /* Also reset the gpu hangman. */
908 if (error->stop_rings != 0) {
909 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
910 error->stop_rings = 0;
911 if (ret == -ENODEV) {
912 DRM_INFO("Reset not implemented, but ignoring "
913 "error for simulated gpu hangs\n");
918 if (i915_stop_ring_allow_warn(dev_priv))
919 pr_notice("drm/i915: Resetting chip after gpu hang\n");
923 DRM_ERROR("Failed to reset chip: %i\n", ret);
925 DRM_DEBUG_DRIVER("GPU reset disabled\n");
929 intel_overlay_reset(dev_priv);
931 /* Ok, now get things going again... */
934 * Everything depends on having the GTT running, so we need to start
935 * there. Fortunately we don't need to do this unless we reset the
936 * chip at a PCI level.
938 * Next we need to restore the context, but we don't use those
941 * Ring buffer needs to be re-initialized in the KMS case, or if X
942 * was running at the time of the reset (i.e. we weren't VT
945 ret = i915_gem_init_hw(dev);
947 DRM_ERROR("Failed hw init on reset %d\n", ret);
951 mutex_unlock(&dev->struct_mutex);
954 * rps/rc6 re-init is necessary to restore state lost after the
955 * reset and the re-install of gt irqs. Skip for ironlake per
956 * previous concerns that it doesn't respond well to some forms
957 * of re-init after reset.
959 if (INTEL_INFO(dev)->gen > 5)
960 intel_enable_gt_powersave(dev);
965 atomic_or(I915_WEDGED, &error->reset_counter);
966 mutex_unlock(&dev->struct_mutex);
970 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
972 struct intel_device_info *intel_info =
973 (struct intel_device_info *) ent->driver_data;
975 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
976 DRM_INFO("This hardware requires preliminary hardware support.\n"
977 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
981 /* Only bind to function 0 of the device. Early generations
982 * used function 1 as a placeholder for multi-head. This causes
983 * us confusion instead, especially on the systems where both
984 * functions have the same PCI-ID!
986 if (PCI_FUNC(pdev->devfn))
990 * apple-gmux is needed on dual GPU MacBook Pro
991 * to probe the panel if we're the inactive GPU.
993 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
994 apple_gmux_present() && pdev != vga_default_device() &&
995 !vga_switcheroo_handler_flags())
996 return -EPROBE_DEFER;
998 return drm_get_pci_dev(pdev, ent, &driver);
1002 i915_pci_remove(struct pci_dev *pdev)
1004 struct drm_device *dev = pci_get_drvdata(pdev);
1009 static int i915_pm_suspend(struct device *dev)
1011 struct pci_dev *pdev = to_pci_dev(dev);
1012 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1014 if (!drm_dev || !drm_dev->dev_private) {
1015 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1019 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1022 return i915_drm_suspend(drm_dev);
1025 static int i915_pm_suspend_late(struct device *dev)
1027 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1030 * We have a suspend ordering issue with the snd-hda driver also
1031 * requiring our device to be power up. Due to the lack of a
1032 * parent/child relationship we currently solve this with an late
1035 * FIXME: This should be solved with a special hdmi sink device or
1036 * similar so that power domains can be employed.
1038 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1041 return i915_drm_suspend_late(drm_dev, false);
1044 static int i915_pm_poweroff_late(struct device *dev)
1046 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1048 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1051 return i915_drm_suspend_late(drm_dev, true);
1054 static int i915_pm_resume_early(struct device *dev)
1056 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1058 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1061 return i915_drm_resume_early(drm_dev);
1064 static int i915_pm_resume(struct device *dev)
1066 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1068 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1071 return i915_drm_resume(drm_dev);
1074 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1076 hsw_enable_pc8(dev_priv);
1081 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1083 struct drm_device *dev = dev_priv->dev;
1085 /* TODO: when DC5 support is added disable DC5 here. */
1087 broxton_ddi_phy_uninit(dev);
1088 broxton_uninit_cdclk(dev);
1089 bxt_enable_dc9(dev_priv);
1094 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1096 struct drm_device *dev = dev_priv->dev;
1098 /* TODO: when CSR FW support is added make sure the FW is loaded */
1100 bxt_disable_dc9(dev_priv);
1103 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1106 broxton_init_cdclk(dev);
1107 broxton_ddi_phy_init(dev);
1113 * Save all Gunit registers that may be lost after a D3 and a subsequent
1114 * S0i[R123] transition. The list of registers needing a save/restore is
1115 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1116 * registers in the following way:
1117 * - Driver: saved/restored by the driver
1118 * - Punit : saved/restored by the Punit firmware
1119 * - No, w/o marking: no need to save/restore, since the register is R/O or
1120 * used internally by the HW in a way that doesn't depend
1121 * keeping the content across a suspend/resume.
1122 * - Debug : used for debugging
1124 * We save/restore all registers marked with 'Driver', with the following
1126 * - Registers out of use, including also registers marked with 'Debug'.
1127 * These have no effect on the driver's operation, so we don't save/restore
1128 * them to reduce the overhead.
1129 * - Registers that are fully setup by an initialization function called from
1130 * the resume path. For example many clock gating and RPS/RC6 registers.
1131 * - Registers that provide the right functionality with their reset defaults.
1133 * TODO: Except for registers that based on the above 3 criteria can be safely
1134 * ignored, we save/restore all others, practically treating the HW context as
1135 * a black-box for the driver. Further investigation is needed to reduce the
1136 * saved/restored registers even further, by following the same 3 criteria.
1138 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1140 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1143 /* GAM 0x4000-0x4770 */
1144 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1145 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1146 s->arb_mode = I915_READ(ARB_MODE);
1147 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1148 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1150 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1151 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1153 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1154 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1156 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1157 s->ecochk = I915_READ(GAM_ECOCHK);
1158 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1159 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1161 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1163 /* MBC 0x9024-0x91D0, 0x8500 */
1164 s->g3dctl = I915_READ(VLV_G3DCTL);
1165 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1166 s->mbctl = I915_READ(GEN6_MBCTL);
1168 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1169 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1170 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1171 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1172 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1173 s->rstctl = I915_READ(GEN6_RSTCTL);
1174 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1176 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1177 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1178 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1179 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1180 s->ecobus = I915_READ(ECOBUS);
1181 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1182 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1183 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1184 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1185 s->rcedata = I915_READ(VLV_RCEDATA);
1186 s->spare2gh = I915_READ(VLV_SPAREG2H);
1188 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1189 s->gt_imr = I915_READ(GTIMR);
1190 s->gt_ier = I915_READ(GTIER);
1191 s->pm_imr = I915_READ(GEN6_PMIMR);
1192 s->pm_ier = I915_READ(GEN6_PMIER);
1194 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1195 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1197 /* GT SA CZ domain, 0x100000-0x138124 */
1198 s->tilectl = I915_READ(TILECTL);
1199 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1200 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1201 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1202 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1204 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1205 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1206 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1207 s->pcbr = I915_READ(VLV_PCBR);
1208 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1211 * Not saving any of:
1212 * DFT, 0x9800-0x9EC0
1213 * SARB, 0xB000-0xB1FC
1214 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1219 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1221 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1225 /* GAM 0x4000-0x4770 */
1226 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1227 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1228 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1229 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1230 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1232 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1233 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1235 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1236 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1238 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1239 I915_WRITE(GAM_ECOCHK, s->ecochk);
1240 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1241 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1243 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1245 /* MBC 0x9024-0x91D0, 0x8500 */
1246 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1247 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1248 I915_WRITE(GEN6_MBCTL, s->mbctl);
1250 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1251 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1252 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1253 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1254 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1255 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1256 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1258 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1259 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1260 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1261 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1262 I915_WRITE(ECOBUS, s->ecobus);
1263 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1264 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1265 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1266 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1267 I915_WRITE(VLV_RCEDATA, s->rcedata);
1268 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1270 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1271 I915_WRITE(GTIMR, s->gt_imr);
1272 I915_WRITE(GTIER, s->gt_ier);
1273 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1274 I915_WRITE(GEN6_PMIER, s->pm_ier);
1276 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1277 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1279 /* GT SA CZ domain, 0x100000-0x138124 */
1280 I915_WRITE(TILECTL, s->tilectl);
1281 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1283 * Preserve the GT allow wake and GFX force clock bit, they are not
1284 * be restored, as they are used to control the s0ix suspend/resume
1285 * sequence by the caller.
1287 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1288 val &= VLV_GTLC_ALLOWWAKEREQ;
1289 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1290 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1292 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1293 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1294 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1295 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1297 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1299 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1300 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1301 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1302 I915_WRITE(VLV_PCBR, s->pcbr);
1303 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1306 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1311 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1313 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1314 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1316 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1317 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1322 err = wait_for(COND, 20);
1324 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1325 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1331 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1336 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1337 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1339 val |= VLV_GTLC_ALLOWWAKEREQ;
1340 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1341 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1343 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1345 err = wait_for(COND, 1);
1347 DRM_ERROR("timeout disabling GT waking\n");
1352 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1359 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1360 val = wait_for_on ? mask : 0;
1361 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1365 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1367 I915_READ(VLV_GTLC_PW_STATUS));
1370 * RC6 transitioning can be delayed up to 2 msec (see
1371 * valleyview_enable_rps), use 3 msec for safety.
1373 err = wait_for(COND, 3);
1375 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1376 onoff(wait_for_on));
1382 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1384 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1387 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1388 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1391 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1397 * Bspec defines the following GT well on flags as debug only, so
1398 * don't treat them as hard failures.
1400 (void)vlv_wait_for_gt_wells(dev_priv, false);
1402 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1403 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1405 vlv_check_no_gt_access(dev_priv);
1407 err = vlv_force_gfx_clock(dev_priv, true);
1411 err = vlv_allow_gt_wake(dev_priv, false);
1415 if (!IS_CHERRYVIEW(dev_priv))
1416 vlv_save_gunit_s0ix_state(dev_priv);
1418 err = vlv_force_gfx_clock(dev_priv, false);
1425 /* For safety always re-enable waking and disable gfx clock forcing */
1426 vlv_allow_gt_wake(dev_priv, true);
1428 vlv_force_gfx_clock(dev_priv, false);
1433 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1436 struct drm_device *dev = dev_priv->dev;
1441 * If any of the steps fail just try to continue, that's the best we
1442 * can do at this point. Return the first error code (which will also
1443 * leave RPM permanently disabled).
1445 ret = vlv_force_gfx_clock(dev_priv, true);
1447 if (!IS_CHERRYVIEW(dev_priv))
1448 vlv_restore_gunit_s0ix_state(dev_priv);
1450 err = vlv_allow_gt_wake(dev_priv, true);
1454 err = vlv_force_gfx_clock(dev_priv, false);
1458 vlv_check_no_gt_access(dev_priv);
1461 intel_init_clock_gating(dev);
1462 i915_gem_restore_fences(dev);
1468 static int intel_runtime_suspend(struct device *device)
1470 struct pci_dev *pdev = to_pci_dev(device);
1471 struct drm_device *dev = pci_get_drvdata(pdev);
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1475 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1478 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1481 DRM_DEBUG_KMS("Suspending device\n");
1484 * We could deadlock here in case another thread holding struct_mutex
1485 * calls RPM suspend concurrently, since the RPM suspend will wait
1486 * first for this RPM suspend to finish. In this case the concurrent
1487 * RPM resume will be followed by its RPM suspend counterpart. Still
1488 * for consistency return -EAGAIN, which will reschedule this suspend.
1490 if (!mutex_trylock(&dev->struct_mutex)) {
1491 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1493 * Bump the expiration timestamp, otherwise the suspend won't
1496 pm_runtime_mark_last_busy(device);
1501 disable_rpm_wakeref_asserts(dev_priv);
1504 * We are safe here against re-faults, since the fault handler takes
1507 i915_gem_release_all_mmaps(dev_priv);
1508 mutex_unlock(&dev->struct_mutex);
1510 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1512 intel_guc_suspend(dev);
1514 intel_suspend_gt_powersave(dev);
1515 intel_runtime_pm_disable_interrupts(dev_priv);
1517 ret = intel_suspend_complete(dev_priv);
1519 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1520 intel_runtime_pm_enable_interrupts(dev_priv);
1522 enable_rpm_wakeref_asserts(dev_priv);
1527 intel_uncore_forcewake_reset(dev, false);
1529 enable_rpm_wakeref_asserts(dev_priv);
1530 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1532 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1533 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1535 dev_priv->pm.suspended = true;
1538 * FIXME: We really should find a document that references the arguments
1541 if (IS_BROADWELL(dev)) {
1543 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1544 * being detected, and the call we do at intel_runtime_resume()
1545 * won't be able to restore them. Since PCI_D3hot matches the
1546 * actual specification and appears to be working, use it.
1548 intel_opregion_notify_adapter(dev, PCI_D3hot);
1551 * current versions of firmware which depend on this opregion
1552 * notification have repurposed the D1 definition to mean
1553 * "runtime suspended" vs. what you would normally expect (D3)
1554 * to distinguish it from notifications that might be sent via
1557 intel_opregion_notify_adapter(dev, PCI_D1);
1560 assert_forcewakes_inactive(dev_priv);
1562 DRM_DEBUG_KMS("Device suspended\n");
1566 static int intel_runtime_resume(struct device *device)
1568 struct pci_dev *pdev = to_pci_dev(device);
1569 struct drm_device *dev = pci_get_drvdata(pdev);
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1573 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1576 DRM_DEBUG_KMS("Resuming device\n");
1578 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1579 disable_rpm_wakeref_asserts(dev_priv);
1581 intel_opregion_notify_adapter(dev, PCI_D0);
1582 dev_priv->pm.suspended = false;
1583 if (intel_uncore_unclaimed_mmio(dev_priv))
1584 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1586 intel_guc_resume(dev);
1588 if (IS_GEN6(dev_priv))
1589 intel_init_pch_refclk(dev);
1591 if (IS_BROXTON(dev))
1592 ret = bxt_resume_prepare(dev_priv);
1593 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1594 hsw_disable_pc8(dev_priv);
1595 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1596 ret = vlv_resume_prepare(dev_priv, true);
1599 * No point of rolling back things in case of an error, as the best
1600 * we can do is to hope that things will still work (and disable RPM).
1602 i915_gem_init_swizzling(dev);
1603 gen6_update_ring_freq(dev);
1605 intel_runtime_pm_enable_interrupts(dev_priv);
1608 * On VLV/CHV display interrupts are part of the display
1609 * power well, so hpd is reinitialized from there. For
1610 * everyone else do it here.
1612 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1613 intel_hpd_init(dev_priv);
1615 intel_enable_gt_powersave(dev);
1617 enable_rpm_wakeref_asserts(dev_priv);
1620 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1622 DRM_DEBUG_KMS("Device resumed\n");
1628 * This function implements common functionality of runtime and system
1631 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1635 if (IS_BROXTON(dev_priv))
1636 ret = bxt_suspend_complete(dev_priv);
1637 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1638 ret = hsw_suspend_complete(dev_priv);
1639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1640 ret = vlv_suspend_complete(dev_priv);
1647 static const struct dev_pm_ops i915_pm_ops = {
1649 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1652 .suspend = i915_pm_suspend,
1653 .suspend_late = i915_pm_suspend_late,
1654 .resume_early = i915_pm_resume_early,
1655 .resume = i915_pm_resume,
1659 * @freeze, @freeze_late : called (1) before creating the
1660 * hibernation image [PMSG_FREEZE] and
1661 * (2) after rebooting, before restoring
1662 * the image [PMSG_QUIESCE]
1663 * @thaw, @thaw_early : called (1) after creating the hibernation
1664 * image, before writing it [PMSG_THAW]
1665 * and (2) after failing to create or
1666 * restore the image [PMSG_RECOVER]
1667 * @poweroff, @poweroff_late: called after writing the hibernation
1668 * image, before rebooting [PMSG_HIBERNATE]
1669 * @restore, @restore_early : called after rebooting and restoring the
1670 * hibernation image [PMSG_RESTORE]
1672 .freeze = i915_pm_suspend,
1673 .freeze_late = i915_pm_suspend_late,
1674 .thaw_early = i915_pm_resume_early,
1675 .thaw = i915_pm_resume,
1676 .poweroff = i915_pm_suspend,
1677 .poweroff_late = i915_pm_poweroff_late,
1678 .restore_early = i915_pm_resume_early,
1679 .restore = i915_pm_resume,
1681 /* S0ix (via runtime suspend) event handlers */
1682 .runtime_suspend = intel_runtime_suspend,
1683 .runtime_resume = intel_runtime_resume,
1686 static const struct vm_operations_struct i915_gem_vm_ops = {
1687 .fault = i915_gem_fault,
1688 .open = drm_gem_vm_open,
1689 .close = drm_gem_vm_close,
1692 static const struct file_operations i915_driver_fops = {
1693 .owner = THIS_MODULE,
1695 .release = drm_release,
1696 .unlocked_ioctl = drm_ioctl,
1697 .mmap = drm_gem_mmap,
1700 #ifdef CONFIG_COMPAT
1701 .compat_ioctl = i915_compat_ioctl,
1703 .llseek = noop_llseek,
1706 static struct drm_driver driver = {
1707 /* Don't use MTRRs here; the Xserver or userspace app should
1708 * deal with them for Intel hardware.
1711 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1712 DRIVER_RENDER | DRIVER_MODESET,
1713 .load = i915_driver_load,
1714 .unload = i915_driver_unload,
1715 .open = i915_driver_open,
1716 .lastclose = i915_driver_lastclose,
1717 .preclose = i915_driver_preclose,
1718 .postclose = i915_driver_postclose,
1719 .set_busid = drm_pci_set_busid,
1721 #if defined(CONFIG_DEBUG_FS)
1722 .debugfs_init = i915_debugfs_init,
1723 .debugfs_cleanup = i915_debugfs_cleanup,
1725 .gem_free_object = i915_gem_free_object,
1726 .gem_vm_ops = &i915_gem_vm_ops,
1728 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1729 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1730 .gem_prime_export = i915_gem_prime_export,
1731 .gem_prime_import = i915_gem_prime_import,
1733 .dumb_create = i915_gem_dumb_create,
1734 .dumb_map_offset = i915_gem_mmap_gtt,
1735 .dumb_destroy = drm_gem_dumb_destroy,
1736 .ioctls = i915_ioctls,
1737 .fops = &i915_driver_fops,
1738 .name = DRIVER_NAME,
1739 .desc = DRIVER_DESC,
1740 .date = DRIVER_DATE,
1741 .major = DRIVER_MAJOR,
1742 .minor = DRIVER_MINOR,
1743 .patchlevel = DRIVER_PATCHLEVEL,
1746 static struct pci_driver i915_pci_driver = {
1747 .name = DRIVER_NAME,
1748 .id_table = pciidlist,
1749 .probe = i915_pci_probe,
1750 .remove = i915_pci_remove,
1751 .driver.pm = &i915_pm_ops,
1754 static int __init i915_init(void)
1756 driver.num_ioctls = i915_max_ioctl;
1759 * Enable KMS by default, unless explicitly overriden by
1760 * either the i915.modeset prarameter or by the
1761 * vga_text_mode_force boot option.
1764 if (i915.modeset == 0)
1765 driver.driver_features &= ~DRIVER_MODESET;
1767 #ifdef CONFIG_VGA_CONSOLE
1768 if (vgacon_text_force() && i915.modeset == -1)
1769 driver.driver_features &= ~DRIVER_MODESET;
1772 if (!(driver.driver_features & DRIVER_MODESET)) {
1773 /* Silently fail loading to not upset userspace. */
1774 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1778 if (i915.nuclear_pageflip)
1779 driver.driver_features |= DRIVER_ATOMIC;
1781 return drm_pci_init(&driver, &i915_pci_driver);
1784 static void __exit i915_exit(void)
1786 if (!(driver.driver_features & DRIVER_MODESET))
1787 return; /* Never loaded a driver. */
1789 drm_pci_exit(&driver, &i915_pci_driver);
1792 module_init(i915_init);
1793 module_exit(i915_exit);
1795 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1796 MODULE_AUTHOR("Intel Corporation");
1798 MODULE_DESCRIPTION(DRIVER_DESC);
1799 MODULE_LICENSE("GPL and additional rights");