1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
55 static struct drm_driver driver;
57 static unsigned int i915_load_fail_count;
59 bool __i915_inject_load_failure(const char *func, int line)
61 if (i915_load_fail_count >= i915.inject_load_failure)
64 if (++i915_load_fail_count == i915.inject_load_failure) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915.inject_load_failure, func, line);
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
81 static bool shown_bug_once;
82 struct device *kdev = dev_priv->drm.dev;
83 bool is_error = level[1] <= KERN_ERR[1];
84 bool is_debug = level[1] == KERN_DEBUG[1];
88 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
96 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
97 __builtin_return_address(0), &vaf);
99 if (is_error && !shown_bug_once) {
100 dev_notice(kdev, "%s", FDO_BUG_MSG);
101 shown_bug_once = true;
107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
109 return i915.inject_load_failure &&
110 i915_load_fail_count == i915.inject_load_failure;
113 #define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
121 enum intel_pch ret = PCH_NOP;
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
130 if (IS_GEN5(dev_priv)) {
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
135 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
136 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
138 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
139 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
141 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
142 } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
144 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
150 static void intel_detect_pch(struct drm_i915_private *dev_priv)
152 struct pci_dev *pch = NULL;
154 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
155 * (which really amounts to a PCH but no South Display).
157 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
158 dev_priv->pch_type = PCH_NOP;
163 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
164 * make graphics device passthrough work easy for VMM, that only
165 * need to expose ISA bridge to let driver know the real hardware
166 * underneath. This is a requirement from virtualization team.
168 * In some virtualized environments (e.g. XEN), there is irrelevant
169 * ISA bridge in the system. To work reliably, we should scan trhough
170 * all the ISA bridge devices and check for the first match, instead
171 * of only checking the first one.
173 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
174 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
175 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
176 unsigned short id_ext = pch->device &
177 INTEL_PCH_DEVICE_ID_MASK_EXT;
179 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
180 dev_priv->pch_id = id;
181 dev_priv->pch_type = PCH_IBX;
182 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
183 WARN_ON(!IS_GEN5(dev_priv));
184 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
185 dev_priv->pch_id = id;
186 dev_priv->pch_type = PCH_CPT;
187 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
188 WARN_ON(!(IS_GEN6(dev_priv) ||
189 IS_IVYBRIDGE(dev_priv)));
190 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
191 /* PantherPoint is CPT compatible */
192 dev_priv->pch_id = id;
193 dev_priv->pch_type = PCH_CPT;
194 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
195 WARN_ON(!(IS_GEN6(dev_priv) ||
196 IS_IVYBRIDGE(dev_priv)));
197 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
198 dev_priv->pch_id = id;
199 dev_priv->pch_type = PCH_LPT;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
201 WARN_ON(!IS_HASWELL(dev_priv) &&
202 !IS_BROADWELL(dev_priv));
203 WARN_ON(IS_HSW_ULT(dev_priv) ||
204 IS_BDW_ULT(dev_priv));
205 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
206 dev_priv->pch_id = id;
207 dev_priv->pch_type = PCH_LPT;
208 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
209 WARN_ON(!IS_HASWELL(dev_priv) &&
210 !IS_BROADWELL(dev_priv));
211 WARN_ON(!IS_HSW_ULT(dev_priv) &&
212 !IS_BDW_ULT(dev_priv));
213 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
214 dev_priv->pch_id = id;
215 dev_priv->pch_type = PCH_SPT;
216 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
217 WARN_ON(!IS_SKYLAKE(dev_priv) &&
218 !IS_KABYLAKE(dev_priv));
219 } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
220 dev_priv->pch_id = id_ext;
221 dev_priv->pch_type = PCH_SPT;
222 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
223 WARN_ON(!IS_SKYLAKE(dev_priv) &&
224 !IS_KABYLAKE(dev_priv));
225 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
226 dev_priv->pch_id = id;
227 dev_priv->pch_type = PCH_KBP;
228 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
229 WARN_ON(!IS_SKYLAKE(dev_priv) &&
230 !IS_KABYLAKE(dev_priv));
231 } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
232 dev_priv->pch_id = id;
233 dev_priv->pch_type = PCH_CNP;
234 DRM_DEBUG_KMS("Found CannonPoint PCH\n");
235 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
236 !IS_COFFEELAKE(dev_priv));
237 } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
238 dev_priv->pch_id = id_ext;
239 dev_priv->pch_type = PCH_CNP;
240 DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
241 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
242 !IS_COFFEELAKE(dev_priv));
243 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
244 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
245 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
246 pch->subsystem_vendor ==
247 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
248 pch->subsystem_device ==
249 PCI_SUBDEVICE_ID_QEMU)) {
250 dev_priv->pch_id = id;
252 intel_virt_detect_pch(dev_priv);
260 DRM_DEBUG_KMS("No PCH found.\n");
265 static int i915_getparam(struct drm_device *dev, void *data,
266 struct drm_file *file_priv)
268 struct drm_i915_private *dev_priv = to_i915(dev);
269 struct pci_dev *pdev = dev_priv->drm.pdev;
270 drm_i915_getparam_t *param = data;
273 switch (param->param) {
274 case I915_PARAM_IRQ_ACTIVE:
275 case I915_PARAM_ALLOW_BATCHBUFFER:
276 case I915_PARAM_LAST_DISPATCH:
277 case I915_PARAM_HAS_EXEC_CONSTANTS:
278 /* Reject all old ums/dri params. */
280 case I915_PARAM_CHIPSET_ID:
281 value = pdev->device;
283 case I915_PARAM_REVISION:
284 value = pdev->revision;
286 case I915_PARAM_NUM_FENCES_AVAIL:
287 value = dev_priv->num_fence_regs;
289 case I915_PARAM_HAS_OVERLAY:
290 value = dev_priv->overlay ? 1 : 0;
292 case I915_PARAM_HAS_BSD:
293 value = !!dev_priv->engine[VCS];
295 case I915_PARAM_HAS_BLT:
296 value = !!dev_priv->engine[BCS];
298 case I915_PARAM_HAS_VEBOX:
299 value = !!dev_priv->engine[VECS];
301 case I915_PARAM_HAS_BSD2:
302 value = !!dev_priv->engine[VCS2];
304 case I915_PARAM_HAS_LLC:
305 value = HAS_LLC(dev_priv);
307 case I915_PARAM_HAS_WT:
308 value = HAS_WT(dev_priv);
310 case I915_PARAM_HAS_ALIASING_PPGTT:
311 value = USES_PPGTT(dev_priv);
313 case I915_PARAM_HAS_SEMAPHORES:
314 value = i915.semaphores;
316 case I915_PARAM_HAS_SECURE_BATCHES:
317 value = capable(CAP_SYS_ADMIN);
319 case I915_PARAM_CMD_PARSER_VERSION:
320 value = i915_cmd_parser_get_version(dev_priv);
322 case I915_PARAM_SUBSLICE_TOTAL:
323 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
327 case I915_PARAM_EU_TOTAL:
328 value = INTEL_INFO(dev_priv)->sseu.eu_total;
332 case I915_PARAM_HAS_GPU_RESET:
333 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
335 case I915_PARAM_HAS_RESOURCE_STREAMER:
336 value = HAS_RESOURCE_STREAMER(dev_priv);
338 case I915_PARAM_HAS_POOLED_EU:
339 value = HAS_POOLED_EU(dev_priv);
341 case I915_PARAM_MIN_EU_IN_POOL:
342 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
344 case I915_PARAM_HUC_STATUS:
345 intel_runtime_pm_get(dev_priv);
346 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
347 intel_runtime_pm_put(dev_priv);
349 case I915_PARAM_MMAP_GTT_VERSION:
350 /* Though we've started our numbering from 1, and so class all
351 * earlier versions as 0, in effect their value is undefined as
352 * the ioctl will report EINVAL for the unknown param!
354 value = i915_gem_mmap_gtt_version();
356 case I915_PARAM_HAS_SCHEDULER:
357 value = dev_priv->engine[RCS] &&
358 dev_priv->engine[RCS]->schedule;
360 case I915_PARAM_MMAP_VERSION:
361 /* Remember to bump this if the version changes! */
362 case I915_PARAM_HAS_GEM:
363 case I915_PARAM_HAS_PAGEFLIPPING:
364 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
365 case I915_PARAM_HAS_RELAXED_FENCING:
366 case I915_PARAM_HAS_COHERENT_RINGS:
367 case I915_PARAM_HAS_RELAXED_DELTA:
368 case I915_PARAM_HAS_GEN7_SOL_RESET:
369 case I915_PARAM_HAS_WAIT_TIMEOUT:
370 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
371 case I915_PARAM_HAS_PINNED_BATCHES:
372 case I915_PARAM_HAS_EXEC_NO_RELOC:
373 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
374 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
375 case I915_PARAM_HAS_EXEC_SOFTPIN:
376 case I915_PARAM_HAS_EXEC_ASYNC:
377 case I915_PARAM_HAS_EXEC_FENCE:
378 case I915_PARAM_HAS_EXEC_CAPTURE:
379 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
380 /* For the time being all of these are always true;
381 * if some supported hardware does not have one of these
382 * features this value needs to be provided from
383 * INTEL_INFO(), a feature macro, or similar.
387 case I915_PARAM_SLICE_MASK:
388 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
392 case I915_PARAM_SUBSLICE_MASK:
393 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
398 DRM_DEBUG("Unknown parameter %d\n", param->param);
402 if (put_user(value, param->value))
408 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
410 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
411 if (!dev_priv->bridge_dev) {
412 DRM_ERROR("bridge device not found\n");
418 /* Allocate space for the MCH regs if needed, return nonzero on error */
420 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
422 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
423 u32 temp_lo, temp_hi = 0;
427 if (INTEL_GEN(dev_priv) >= 4)
428 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
429 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
430 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
432 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
435 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
439 /* Get some space for it */
440 dev_priv->mch_res.name = "i915 MCHBAR";
441 dev_priv->mch_res.flags = IORESOURCE_MEM;
442 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
444 MCHBAR_SIZE, MCHBAR_SIZE,
446 0, pcibios_align_resource,
447 dev_priv->bridge_dev);
449 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
450 dev_priv->mch_res.start = 0;
454 if (INTEL_GEN(dev_priv) >= 4)
455 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
456 upper_32_bits(dev_priv->mch_res.start));
458 pci_write_config_dword(dev_priv->bridge_dev, reg,
459 lower_32_bits(dev_priv->mch_res.start));
463 /* Setup MCHBAR if possible, return true if we should disable it again */
465 intel_setup_mchbar(struct drm_i915_private *dev_priv)
467 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
471 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
474 dev_priv->mchbar_need_disable = false;
476 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
477 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
478 enabled = !!(temp & DEVEN_MCHBAR_EN);
480 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
484 /* If it's already enabled, don't have to do anything */
488 if (intel_alloc_mchbar_resource(dev_priv))
491 dev_priv->mchbar_need_disable = true;
493 /* Space is allocated or reserved, so enable it. */
494 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
495 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
496 temp | DEVEN_MCHBAR_EN);
498 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
499 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
504 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
506 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
508 if (dev_priv->mchbar_need_disable) {
509 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
512 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
514 deven_val &= ~DEVEN_MCHBAR_EN;
515 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
520 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
523 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
528 if (dev_priv->mch_res.start)
529 release_resource(&dev_priv->mch_res);
532 /* true = enable decode, false = disable decoder */
533 static unsigned int i915_vga_set_decode(void *cookie, bool state)
535 struct drm_i915_private *dev_priv = cookie;
537 intel_modeset_vga_set_state(dev_priv, state);
539 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
540 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
542 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
545 static int i915_resume_switcheroo(struct drm_device *dev);
546 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
548 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
550 struct drm_device *dev = pci_get_drvdata(pdev);
551 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
553 if (state == VGA_SWITCHEROO_ON) {
554 pr_info("switched on\n");
555 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
556 /* i915 resume handler doesn't set to D0 */
557 pci_set_power_state(pdev, PCI_D0);
558 i915_resume_switcheroo(dev);
559 dev->switch_power_state = DRM_SWITCH_POWER_ON;
561 pr_info("switched off\n");
562 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
563 i915_suspend_switcheroo(dev, pmm);
564 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
568 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
570 struct drm_device *dev = pci_get_drvdata(pdev);
573 * FIXME: open_count is protected by drm_global_mutex but that would lead to
574 * locking inversion with the driver load path. And the access here is
575 * completely racy anyway. So don't bother with locking for now.
577 return dev->open_count == 0;
580 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
581 .set_gpu_state = i915_switcheroo_set_state,
583 .can_switch = i915_switcheroo_can_switch,
586 static void i915_gem_fini(struct drm_i915_private *dev_priv)
588 mutex_lock(&dev_priv->drm.struct_mutex);
589 intel_uc_fini_hw(dev_priv);
590 i915_gem_cleanup_engines(dev_priv);
591 i915_gem_context_fini(dev_priv);
592 i915_gem_cleanup_userptr(dev_priv);
593 mutex_unlock(&dev_priv->drm.struct_mutex);
595 i915_gem_drain_freed_objects(dev_priv);
597 WARN_ON(!list_empty(&dev_priv->context_list));
600 static int i915_load_modeset_init(struct drm_device *dev)
602 struct drm_i915_private *dev_priv = to_i915(dev);
603 struct pci_dev *pdev = dev_priv->drm.pdev;
606 if (i915_inject_load_failure())
609 intel_bios_init(dev_priv);
611 /* If we have > 1 VGA cards, then we need to arbitrate access
612 * to the common VGA resources.
614 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
615 * then we do not take part in VGA arbitration and the
616 * vga_client_register() fails with -ENODEV.
618 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
619 if (ret && ret != -ENODEV)
622 intel_register_dsm_handler();
624 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
626 goto cleanup_vga_client;
628 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
629 intel_update_rawclk(dev_priv);
631 intel_power_domains_init_hw(dev_priv, false);
633 intel_csr_ucode_init(dev_priv);
635 ret = intel_irq_install(dev_priv);
639 intel_setup_gmbus(dev_priv);
641 /* Important: The output setup functions called by modeset_init need
642 * working irqs for e.g. gmbus and dp aux transfers. */
643 ret = intel_modeset_init(dev);
647 intel_uc_init_fw(dev_priv);
649 ret = i915_gem_init(dev_priv);
653 intel_modeset_gem_init(dev);
655 if (INTEL_INFO(dev_priv)->num_pipes == 0)
658 ret = intel_fbdev_init(dev);
662 /* Only enable hotplug handling once the fbdev is fully set up. */
663 intel_hpd_init(dev_priv);
665 drm_kms_helper_poll_init(dev);
670 if (i915_gem_suspend(dev_priv))
671 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
672 i915_gem_fini(dev_priv);
674 intel_uc_fini_fw(dev_priv);
676 drm_irq_uninstall(dev);
677 intel_teardown_gmbus(dev_priv);
679 intel_csr_ucode_fini(dev_priv);
680 intel_power_domains_fini(dev_priv);
681 vga_switcheroo_unregister_client(pdev);
683 vga_client_register(pdev, NULL, NULL, NULL);
688 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
690 struct apertures_struct *ap;
691 struct pci_dev *pdev = dev_priv->drm.pdev;
692 struct i915_ggtt *ggtt = &dev_priv->ggtt;
696 ap = alloc_apertures(1);
700 ap->ranges[0].base = ggtt->mappable_base;
701 ap->ranges[0].size = ggtt->mappable_end;
704 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
706 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
713 #if !defined(CONFIG_VGA_CONSOLE)
714 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
718 #elif !defined(CONFIG_DUMMY_CONSOLE)
719 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
724 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
728 DRM_INFO("Replacing VGA console driver\n");
731 if (con_is_bound(&vga_con))
732 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
734 ret = do_unregister_con_driver(&vga_con);
736 /* Ignore "already unregistered". */
746 static void intel_init_dpio(struct drm_i915_private *dev_priv)
749 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
750 * CHV x1 PHY (DP/HDMI D)
751 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
753 if (IS_CHERRYVIEW(dev_priv)) {
754 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
755 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
756 } else if (IS_VALLEYVIEW(dev_priv)) {
757 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
761 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
764 * The i915 workqueue is primarily used for batched retirement of
765 * requests (and thus managing bo) once the task has been completed
766 * by the GPU. i915_gem_retire_requests() is called directly when we
767 * need high-priority retirement, such as waiting for an explicit
770 * It is also used for periodic low-priority events, such as
771 * idle-timers and recording error state.
773 * All tasks on the workqueue are expected to acquire the dev mutex
774 * so there is no point in running more than one instance of the
775 * workqueue at any time. Use an ordered one.
777 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
778 if (dev_priv->wq == NULL)
781 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
782 if (dev_priv->hotplug.dp_wq == NULL)
788 destroy_workqueue(dev_priv->wq);
790 DRM_ERROR("Failed to allocate workqueues.\n");
795 static void i915_engines_cleanup(struct drm_i915_private *i915)
797 struct intel_engine_cs *engine;
798 enum intel_engine_id id;
800 for_each_engine(engine, i915, id)
804 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
806 destroy_workqueue(dev_priv->hotplug.dp_wq);
807 destroy_workqueue(dev_priv->wq);
811 * We don't keep the workarounds for pre-production hardware, so we expect our
812 * driver to fail on these machines in one way or another. A little warning on
813 * dmesg may help both the user and the bug triagers.
815 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
819 pre |= IS_HSW_EARLY_SDV(dev_priv);
820 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
821 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
824 DRM_ERROR("This is a pre-production stepping. "
825 "It may not be fully functional.\n");
826 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
831 * i915_driver_init_early - setup state not requiring device access
832 * @dev_priv: device private
834 * Initialize everything that is a "SW-only" state, that is state not
835 * requiring accessing the device or exposing the driver via kernel internal
836 * or userspace interfaces. Example steps belonging here: lock initialization,
837 * system memory allocation, setting up device specific attributes and
838 * function hooks not requiring accessing the device.
840 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
841 const struct pci_device_id *ent)
843 const struct intel_device_info *match_info =
844 (struct intel_device_info *)ent->driver_data;
845 struct intel_device_info *device_info;
848 if (i915_inject_load_failure())
851 /* Setup the write-once "constant" device info */
852 device_info = mkwrite_device_info(dev_priv);
853 memcpy(device_info, match_info, sizeof(*device_info));
854 device_info->device_id = dev_priv->drm.pdev->device;
856 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
857 device_info->gen_mask = BIT(device_info->gen - 1);
859 spin_lock_init(&dev_priv->irq_lock);
860 spin_lock_init(&dev_priv->gpu_error.lock);
861 mutex_init(&dev_priv->backlight_lock);
862 spin_lock_init(&dev_priv->uncore.lock);
864 spin_lock_init(&dev_priv->mm.object_stat_lock);
865 spin_lock_init(&dev_priv->mmio_flip_lock);
866 mutex_init(&dev_priv->sb_lock);
867 mutex_init(&dev_priv->modeset_restore_lock);
868 mutex_init(&dev_priv->av_mutex);
869 mutex_init(&dev_priv->wm.wm_mutex);
870 mutex_init(&dev_priv->pps_mutex);
872 intel_uc_init_early(dev_priv);
873 i915_memcpy_init_early(dev_priv);
875 ret = i915_workqueues_init(dev_priv);
879 /* This must be called before any calls to HAS_PCH_* */
880 intel_detect_pch(dev_priv);
882 intel_pm_setup(dev_priv);
883 intel_init_dpio(dev_priv);
884 intel_power_domains_init(dev_priv);
885 intel_irq_init(dev_priv);
886 intel_hangcheck_init(dev_priv);
887 intel_init_display_hooks(dev_priv);
888 intel_init_clock_gating_hooks(dev_priv);
889 intel_init_audio_hooks(dev_priv);
890 ret = i915_gem_load_init(dev_priv);
894 intel_display_crc_init(dev_priv);
896 intel_device_info_dump(dev_priv);
898 intel_detect_preproduction_hw(dev_priv);
900 i915_perf_init(dev_priv);
905 intel_irq_fini(dev_priv);
906 i915_workqueues_cleanup(dev_priv);
908 i915_engines_cleanup(dev_priv);
913 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
914 * @dev_priv: device private
916 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
918 i915_perf_fini(dev_priv);
919 i915_gem_load_cleanup(dev_priv);
920 intel_irq_fini(dev_priv);
921 i915_workqueues_cleanup(dev_priv);
922 i915_engines_cleanup(dev_priv);
925 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
927 struct pci_dev *pdev = dev_priv->drm.pdev;
931 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
933 * Before gen4, the registers and the GTT are behind different BARs.
934 * However, from gen4 onwards, the registers and the GTT are shared
935 * in the same BAR, so we want to restrict this ioremap from
936 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
937 * the register BAR remains the same size for all the earlier
938 * generations up to Ironlake.
940 if (INTEL_GEN(dev_priv) < 5)
941 mmio_size = 512 * 1024;
943 mmio_size = 2 * 1024 * 1024;
944 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
945 if (dev_priv->regs == NULL) {
946 DRM_ERROR("failed to map registers\n");
951 /* Try to make sure MCHBAR is enabled before poking at it */
952 intel_setup_mchbar(dev_priv);
957 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
959 struct pci_dev *pdev = dev_priv->drm.pdev;
961 intel_teardown_mchbar(dev_priv);
962 pci_iounmap(pdev, dev_priv->regs);
966 * i915_driver_init_mmio - setup device MMIO
967 * @dev_priv: device private
969 * Setup minimal device state necessary for MMIO accesses later in the
970 * initialization sequence. The setup here should avoid any other device-wide
971 * side effects or exposing the driver via kernel internal or user space
974 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
978 if (i915_inject_load_failure())
981 if (i915_get_bridge_dev(dev_priv))
984 ret = i915_mmio_setup(dev_priv);
988 intel_uncore_init(dev_priv);
990 ret = intel_engines_init_mmio(dev_priv);
994 i915_gem_init_mmio(dev_priv);
999 intel_uncore_fini(dev_priv);
1001 pci_dev_put(dev_priv->bridge_dev);
1007 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1008 * @dev_priv: device private
1010 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1012 intel_uncore_fini(dev_priv);
1013 i915_mmio_cleanup(dev_priv);
1014 pci_dev_put(dev_priv->bridge_dev);
1017 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1019 i915.enable_execlists =
1020 intel_sanitize_enable_execlists(dev_priv,
1021 i915.enable_execlists);
1024 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1025 * user's requested state against the hardware/driver capabilities. We
1026 * do this now so that we can print out any log messages once rather
1027 * than every time we check intel_enable_ppgtt().
1030 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1031 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1033 i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1034 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1036 intel_uc_sanitize_options(dev_priv);
1038 intel_gvt_sanitize_options(dev_priv);
1042 * i915_driver_init_hw - setup state requiring device access
1043 * @dev_priv: device private
1045 * Setup state that requires accessing the device, but doesn't require
1046 * exposing the driver via kernel internal or userspace interfaces.
1048 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1050 struct pci_dev *pdev = dev_priv->drm.pdev;
1053 if (i915_inject_load_failure())
1056 intel_device_info_runtime_init(dev_priv);
1058 intel_sanitize_options(dev_priv);
1060 ret = i915_ggtt_probe_hw(dev_priv);
1064 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1065 * otherwise the vga fbdev driver falls over. */
1066 ret = i915_kick_out_firmware_fb(dev_priv);
1068 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1072 ret = i915_kick_out_vgacon(dev_priv);
1074 DRM_ERROR("failed to remove conflicting VGA console\n");
1078 ret = i915_ggtt_init_hw(dev_priv);
1082 ret = i915_ggtt_enable_hw(dev_priv);
1084 DRM_ERROR("failed to enable GGTT\n");
1088 pci_set_master(pdev);
1090 /* overlay on gen2 is broken and can't address above 1G */
1091 if (IS_GEN2(dev_priv)) {
1092 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1094 DRM_ERROR("failed to set DMA mask\n");
1100 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1101 * using 32bit addressing, overwriting memory if HWS is located
1104 * The documentation also mentions an issue with undefined
1105 * behaviour if any general state is accessed within a page above 4GB,
1106 * which also needs to be handled carefully.
1108 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1109 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1112 DRM_ERROR("failed to set DMA mask\n");
1118 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1119 PM_QOS_DEFAULT_VALUE);
1121 intel_uncore_sanitize(dev_priv);
1123 intel_opregion_setup(dev_priv);
1125 i915_gem_load_init_fences(dev_priv);
1127 /* On the 945G/GM, the chipset reports the MSI capability on the
1128 * integrated graphics even though the support isn't actually there
1129 * according to the published specs. It doesn't appear to function
1130 * correctly in testing on 945G.
1131 * This may be a side effect of MSI having been made available for PEG
1132 * and the registers being closely associated.
1134 * According to chipset errata, on the 965GM, MSI interrupts may
1135 * be lost or delayed, but we use them anyways to avoid
1136 * stuck interrupts on some machines.
1138 if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1139 if (pci_enable_msi(pdev) < 0)
1140 DRM_DEBUG_DRIVER("can't enable MSI");
1143 ret = intel_gvt_init(dev_priv);
1150 i915_ggtt_cleanup_hw(dev_priv);
1156 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1157 * @dev_priv: device private
1159 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1161 struct pci_dev *pdev = dev_priv->drm.pdev;
1163 if (pdev->msi_enabled)
1164 pci_disable_msi(pdev);
1166 pm_qos_remove_request(&dev_priv->pm_qos);
1167 i915_ggtt_cleanup_hw(dev_priv);
1171 * i915_driver_register - register the driver with the rest of the system
1172 * @dev_priv: device private
1174 * Perform any steps necessary to make the driver available via kernel
1175 * internal or userspace interfaces.
1177 static void i915_driver_register(struct drm_i915_private *dev_priv)
1179 struct drm_device *dev = &dev_priv->drm;
1181 i915_gem_shrinker_init(dev_priv);
1184 * Notify a valid surface after modesetting,
1185 * when running inside a VM.
1187 if (intel_vgpu_active(dev_priv))
1188 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1190 /* Reveal our presence to userspace */
1191 if (drm_dev_register(dev, 0) == 0) {
1192 i915_debugfs_register(dev_priv);
1193 i915_guc_log_register(dev_priv);
1194 i915_setup_sysfs(dev_priv);
1196 /* Depends on sysfs having been initialized */
1197 i915_perf_register(dev_priv);
1199 DRM_ERROR("Failed to register driver for userspace access!\n");
1201 if (INTEL_INFO(dev_priv)->num_pipes) {
1202 /* Must be done after probing outputs */
1203 intel_opregion_register(dev_priv);
1204 acpi_video_register();
1207 if (IS_GEN5(dev_priv))
1208 intel_gpu_ips_init(dev_priv);
1210 intel_audio_init(dev_priv);
1213 * Some ports require correctly set-up hpd registers for detection to
1214 * work properly (leading to ghost connected connector status), e.g. VGA
1215 * on gm45. Hence we can only set up the initial fbdev config after hpd
1216 * irqs are fully enabled. We do it last so that the async config
1217 * cannot run before the connectors are registered.
1219 intel_fbdev_initial_config_async(dev);
1223 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1224 * @dev_priv: device private
1226 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1228 intel_audio_deinit(dev_priv);
1230 intel_gpu_ips_teardown();
1231 acpi_video_unregister();
1232 intel_opregion_unregister(dev_priv);
1234 i915_perf_unregister(dev_priv);
1236 i915_teardown_sysfs(dev_priv);
1237 i915_guc_log_unregister(dev_priv);
1238 drm_dev_unregister(&dev_priv->drm);
1240 i915_gem_shrinker_cleanup(dev_priv);
1244 * i915_driver_load - setup chip and create an initial config
1246 * @ent: matching PCI ID entry
1248 * The driver load routine has to do several things:
1249 * - drive output discovery via intel_modeset_init()
1250 * - initialize the memory manager
1251 * - allocate initial config memory
1252 * - setup the DRM framebuffer with the allocated memory
1254 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1256 const struct intel_device_info *match_info =
1257 (struct intel_device_info *)ent->driver_data;
1258 struct drm_i915_private *dev_priv;
1261 /* Enable nuclear pageflip on ILK+ */
1262 if (!i915.nuclear_pageflip && match_info->gen < 5)
1263 driver.driver_features &= ~DRIVER_ATOMIC;
1266 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1268 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1270 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1274 dev_priv->drm.pdev = pdev;
1275 dev_priv->drm.dev_private = dev_priv;
1277 ret = pci_enable_device(pdev);
1281 pci_set_drvdata(pdev, &dev_priv->drm);
1283 * Disable the system suspend direct complete optimization, which can
1284 * leave the device suspended skipping the driver's suspend handlers
1285 * if the device was already runtime suspended. This is needed due to
1286 * the difference in our runtime and system suspend sequence and
1287 * becaue the HDA driver may require us to enable the audio power
1288 * domain during system suspend.
1290 pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1292 ret = i915_driver_init_early(dev_priv, ent);
1294 goto out_pci_disable;
1296 intel_runtime_pm_get(dev_priv);
1298 ret = i915_driver_init_mmio(dev_priv);
1300 goto out_runtime_pm_put;
1302 ret = i915_driver_init_hw(dev_priv);
1304 goto out_cleanup_mmio;
1307 * TODO: move the vblank init and parts of modeset init steps into one
1308 * of the i915_driver_init_/i915_driver_register functions according
1309 * to the role/effect of the given init step.
1311 if (INTEL_INFO(dev_priv)->num_pipes) {
1312 ret = drm_vblank_init(&dev_priv->drm,
1313 INTEL_INFO(dev_priv)->num_pipes);
1315 goto out_cleanup_hw;
1318 ret = i915_load_modeset_init(&dev_priv->drm);
1320 goto out_cleanup_vblank;
1322 i915_driver_register(dev_priv);
1324 intel_runtime_pm_enable(dev_priv);
1326 dev_priv->ipc_enabled = false;
1328 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1329 DRM_INFO("DRM_I915_DEBUG enabled\n");
1330 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1331 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1333 intel_runtime_pm_put(dev_priv);
1338 drm_vblank_cleanup(&dev_priv->drm);
1340 i915_driver_cleanup_hw(dev_priv);
1342 i915_driver_cleanup_mmio(dev_priv);
1344 intel_runtime_pm_put(dev_priv);
1345 i915_driver_cleanup_early(dev_priv);
1347 pci_disable_device(pdev);
1349 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1350 drm_dev_fini(&dev_priv->drm);
1356 void i915_driver_unload(struct drm_device *dev)
1358 struct drm_i915_private *dev_priv = to_i915(dev);
1359 struct pci_dev *pdev = dev_priv->drm.pdev;
1361 intel_fbdev_fini(dev);
1363 if (i915_gem_suspend(dev_priv))
1364 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1366 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1368 drm_atomic_helper_shutdown(dev);
1370 intel_gvt_cleanup(dev_priv);
1372 i915_driver_unregister(dev_priv);
1374 drm_vblank_cleanup(dev);
1376 intel_modeset_cleanup(dev);
1379 * free the memory space allocated for the child device
1380 * config parsed from VBT
1382 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1383 kfree(dev_priv->vbt.child_dev);
1384 dev_priv->vbt.child_dev = NULL;
1385 dev_priv->vbt.child_dev_num = 0;
1387 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1388 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1389 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1390 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1392 vga_switcheroo_unregister_client(pdev);
1393 vga_client_register(pdev, NULL, NULL, NULL);
1395 intel_csr_ucode_fini(dev_priv);
1397 /* Free error state after interrupts are fully disabled. */
1398 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1399 i915_reset_error_state(dev_priv);
1401 /* Flush any outstanding unpin_work. */
1402 drain_workqueue(dev_priv->wq);
1404 i915_gem_fini(dev_priv);
1405 intel_uc_fini_fw(dev_priv);
1406 intel_fbc_cleanup_cfb(dev_priv);
1408 intel_power_domains_fini(dev_priv);
1410 i915_driver_cleanup_hw(dev_priv);
1411 i915_driver_cleanup_mmio(dev_priv);
1413 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1416 static void i915_driver_release(struct drm_device *dev)
1418 struct drm_i915_private *dev_priv = to_i915(dev);
1420 i915_driver_cleanup_early(dev_priv);
1421 drm_dev_fini(&dev_priv->drm);
1426 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1430 ret = i915_gem_open(dev, file);
1438 * i915_driver_lastclose - clean up after all DRM clients have exited
1441 * Take care of cleaning up after all DRM clients have exited. In the
1442 * mode setting case, we want to restore the kernel's initial mode (just
1443 * in case the last client left us in a bad state).
1445 * Additionally, in the non-mode setting case, we'll tear down the GTT
1446 * and DMA structures, since the kernel won't be using them, and clea
1449 static void i915_driver_lastclose(struct drm_device *dev)
1451 intel_fbdev_restore_mode(dev);
1452 vga_switcheroo_process_delayed_switch();
1455 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1457 struct drm_i915_file_private *file_priv = file->driver_priv;
1459 mutex_lock(&dev->struct_mutex);
1460 i915_gem_context_close(dev, file);
1461 i915_gem_release(dev, file);
1462 mutex_unlock(&dev->struct_mutex);
1467 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1469 struct drm_device *dev = &dev_priv->drm;
1470 struct intel_encoder *encoder;
1472 drm_modeset_lock_all(dev);
1473 for_each_intel_encoder(dev, encoder)
1474 if (encoder->suspend)
1475 encoder->suspend(encoder);
1476 drm_modeset_unlock_all(dev);
1479 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1481 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1483 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1485 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1486 if (acpi_target_system_state() < ACPI_STATE_S3)
1492 static int i915_drm_suspend(struct drm_device *dev)
1494 struct drm_i915_private *dev_priv = to_i915(dev);
1495 struct pci_dev *pdev = dev_priv->drm.pdev;
1496 pci_power_t opregion_target_state;
1499 /* ignore lid events during suspend */
1500 mutex_lock(&dev_priv->modeset_restore_lock);
1501 dev_priv->modeset_restore = MODESET_SUSPENDED;
1502 mutex_unlock(&dev_priv->modeset_restore_lock);
1504 disable_rpm_wakeref_asserts(dev_priv);
1506 /* We do a lot of poking in a lot of registers, make sure they work
1508 intel_display_set_init_power(dev_priv, true);
1510 drm_kms_helper_poll_disable(dev);
1512 pci_save_state(pdev);
1514 error = i915_gem_suspend(dev_priv);
1517 "GEM idle failed, resume might fail\n");
1521 intel_display_suspend(dev);
1523 intel_dp_mst_suspend(dev);
1525 intel_runtime_pm_disable_interrupts(dev_priv);
1526 intel_hpd_cancel_work(dev_priv);
1528 intel_suspend_encoders(dev_priv);
1530 intel_suspend_hw(dev_priv);
1532 i915_gem_suspend_gtt_mappings(dev_priv);
1534 i915_save_state(dev_priv);
1536 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1537 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1539 intel_uncore_suspend(dev_priv);
1540 intel_opregion_unregister(dev_priv);
1542 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1544 dev_priv->suspend_count++;
1546 intel_csr_ucode_suspend(dev_priv);
1549 enable_rpm_wakeref_asserts(dev_priv);
1554 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1556 struct drm_i915_private *dev_priv = to_i915(dev);
1557 struct pci_dev *pdev = dev_priv->drm.pdev;
1561 disable_rpm_wakeref_asserts(dev_priv);
1563 intel_display_set_init_power(dev_priv, false);
1565 fw_csr = !IS_GEN9_LP(dev_priv) &&
1566 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1568 * In case of firmware assisted context save/restore don't manually
1569 * deinit the power domains. This also means the CSR/DMC firmware will
1570 * stay active, it will power down any HW resources as required and
1571 * also enable deeper system power states that would be blocked if the
1572 * firmware was inactive.
1575 intel_power_domains_suspend(dev_priv);
1578 if (IS_GEN9_LP(dev_priv))
1579 bxt_enable_dc9(dev_priv);
1580 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1581 hsw_enable_pc8(dev_priv);
1582 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1583 ret = vlv_suspend_complete(dev_priv);
1586 DRM_ERROR("Suspend complete failed: %d\n", ret);
1588 intel_power_domains_init_hw(dev_priv, true);
1593 pci_disable_device(pdev);
1595 * During hibernation on some platforms the BIOS may try to access
1596 * the device even though it's already in D3 and hang the machine. So
1597 * leave the device in D0 on those platforms and hope the BIOS will
1598 * power down the device properly. The issue was seen on multiple old
1599 * GENs with different BIOS vendors, so having an explicit blacklist
1600 * is inpractical; apply the workaround on everything pre GEN6. The
1601 * platforms where the issue was seen:
1602 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1606 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1607 pci_set_power_state(pdev, PCI_D3hot);
1609 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1612 enable_rpm_wakeref_asserts(dev_priv);
1617 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1622 DRM_ERROR("dev: %p\n", dev);
1623 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1627 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1628 state.event != PM_EVENT_FREEZE))
1631 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1634 error = i915_drm_suspend(dev);
1638 return i915_drm_suspend_late(dev, false);
1641 static int i915_drm_resume(struct drm_device *dev)
1643 struct drm_i915_private *dev_priv = to_i915(dev);
1646 disable_rpm_wakeref_asserts(dev_priv);
1647 intel_sanitize_gt_powersave(dev_priv);
1649 ret = i915_ggtt_enable_hw(dev_priv);
1651 DRM_ERROR("failed to re-enable GGTT\n");
1653 intel_csr_ucode_resume(dev_priv);
1655 i915_gem_resume(dev_priv);
1657 i915_restore_state(dev_priv);
1658 intel_pps_unlock_regs_wa(dev_priv);
1659 intel_opregion_setup(dev_priv);
1661 intel_init_pch_refclk(dev_priv);
1664 * Interrupts have to be enabled before any batches are run. If not the
1665 * GPU will hang. i915_gem_init_hw() will initiate batches to
1666 * update/restore the context.
1668 * drm_mode_config_reset() needs AUX interrupts.
1670 * Modeset enabling in intel_modeset_init_hw() also needs working
1673 intel_runtime_pm_enable_interrupts(dev_priv);
1675 drm_mode_config_reset(dev);
1677 mutex_lock(&dev->struct_mutex);
1678 if (i915_gem_init_hw(dev_priv)) {
1679 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1680 i915_gem_set_wedged(dev_priv);
1682 mutex_unlock(&dev->struct_mutex);
1684 intel_guc_resume(dev_priv);
1686 intel_modeset_init_hw(dev);
1688 spin_lock_irq(&dev_priv->irq_lock);
1689 if (dev_priv->display.hpd_irq_setup)
1690 dev_priv->display.hpd_irq_setup(dev_priv);
1691 spin_unlock_irq(&dev_priv->irq_lock);
1693 intel_dp_mst_resume(dev);
1695 intel_display_resume(dev);
1697 drm_kms_helper_poll_enable(dev);
1700 * ... but also need to make sure that hotplug processing
1701 * doesn't cause havoc. Like in the driver load code we don't
1702 * bother with the tiny race here where we might loose hotplug
1705 intel_hpd_init(dev_priv);
1707 intel_opregion_register(dev_priv);
1709 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1711 mutex_lock(&dev_priv->modeset_restore_lock);
1712 dev_priv->modeset_restore = MODESET_DONE;
1713 mutex_unlock(&dev_priv->modeset_restore_lock);
1715 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1717 intel_autoenable_gt_powersave(dev_priv);
1719 enable_rpm_wakeref_asserts(dev_priv);
1724 static int i915_drm_resume_early(struct drm_device *dev)
1726 struct drm_i915_private *dev_priv = to_i915(dev);
1727 struct pci_dev *pdev = dev_priv->drm.pdev;
1731 * We have a resume ordering issue with the snd-hda driver also
1732 * requiring our device to be power up. Due to the lack of a
1733 * parent/child relationship we currently solve this with an early
1736 * FIXME: This should be solved with a special hdmi sink device or
1737 * similar so that power domains can be employed.
1741 * Note that we need to set the power state explicitly, since we
1742 * powered off the device during freeze and the PCI core won't power
1743 * it back up for us during thaw. Powering off the device during
1744 * freeze is not a hard requirement though, and during the
1745 * suspend/resume phases the PCI core makes sure we get here with the
1746 * device powered on. So in case we change our freeze logic and keep
1747 * the device powered we can also remove the following set power state
1750 ret = pci_set_power_state(pdev, PCI_D0);
1752 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1757 * Note that pci_enable_device() first enables any parent bridge
1758 * device and only then sets the power state for this device. The
1759 * bridge enabling is a nop though, since bridge devices are resumed
1760 * first. The order of enabling power and enabling the device is
1761 * imposed by the PCI core as described above, so here we preserve the
1762 * same order for the freeze/thaw phases.
1764 * TODO: eventually we should remove pci_disable_device() /
1765 * pci_enable_enable_device() from suspend/resume. Due to how they
1766 * depend on the device enable refcount we can't anyway depend on them
1767 * disabling/enabling the device.
1769 if (pci_enable_device(pdev)) {
1774 pci_set_master(pdev);
1776 disable_rpm_wakeref_asserts(dev_priv);
1778 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1779 ret = vlv_resume_prepare(dev_priv, false);
1781 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1784 intel_uncore_resume_early(dev_priv);
1786 if (IS_GEN9_LP(dev_priv)) {
1787 if (!dev_priv->suspended_to_idle)
1788 gen9_sanitize_dc_state(dev_priv);
1789 bxt_disable_dc9(dev_priv);
1790 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1791 hsw_disable_pc8(dev_priv);
1794 intel_uncore_sanitize(dev_priv);
1796 if (IS_GEN9_LP(dev_priv) ||
1797 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1798 intel_power_domains_init_hw(dev_priv, true);
1800 i915_gem_sanitize(dev_priv);
1802 enable_rpm_wakeref_asserts(dev_priv);
1805 dev_priv->suspended_to_idle = false;
1810 static int i915_resume_switcheroo(struct drm_device *dev)
1814 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1817 ret = i915_drm_resume_early(dev);
1821 return i915_drm_resume(dev);
1825 * i915_reset - reset chip after a hang
1826 * @dev_priv: device private to reset
1828 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1831 * Caller must hold the struct_mutex.
1833 * Procedure is fairly simple:
1834 * - reset the chip using the reset reg
1835 * - re-init context state
1836 * - re-init hardware status page
1837 * - re-init ring buffer
1838 * - re-init interrupt state
1841 void i915_reset(struct drm_i915_private *dev_priv)
1843 struct i915_gpu_error *error = &dev_priv->gpu_error;
1846 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1847 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1849 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1852 /* Clear any previous failed attempts at recovery. Time to try again. */
1853 if (!i915_gem_unset_wedged(dev_priv))
1856 error->reset_count++;
1858 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1859 disable_irq(dev_priv->drm.irq);
1860 ret = i915_gem_reset_prepare(dev_priv);
1862 DRM_ERROR("GPU recovery failed\n");
1863 intel_gpu_reset(dev_priv, ALL_ENGINES);
1867 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1870 DRM_ERROR("Failed to reset chip: %i\n", ret);
1872 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1876 i915_gem_reset(dev_priv);
1877 intel_overlay_reset(dev_priv);
1879 /* Ok, now get things going again... */
1882 * Everything depends on having the GTT running, so we need to start
1883 * there. Fortunately we don't need to do this unless we reset the
1884 * chip at a PCI level.
1886 * Next we need to restore the context, but we don't use those
1889 * Ring buffer needs to be re-initialized in the KMS case, or if X
1890 * was running at the time of the reset (i.e. we weren't VT
1893 ret = i915_gem_init_hw(dev_priv);
1895 DRM_ERROR("Failed hw init on reset %d\n", ret);
1899 i915_queue_hangcheck(dev_priv);
1902 i915_gem_reset_finish(dev_priv);
1903 enable_irq(dev_priv->drm.irq);
1906 clear_bit(I915_RESET_HANDOFF, &error->flags);
1907 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1911 i915_gem_set_wedged(dev_priv);
1915 static int i915_pm_suspend(struct device *kdev)
1917 struct pci_dev *pdev = to_pci_dev(kdev);
1918 struct drm_device *dev = pci_get_drvdata(pdev);
1921 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1925 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1928 return i915_drm_suspend(dev);
1931 static int i915_pm_suspend_late(struct device *kdev)
1933 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1936 * We have a suspend ordering issue with the snd-hda driver also
1937 * requiring our device to be power up. Due to the lack of a
1938 * parent/child relationship we currently solve this with an late
1941 * FIXME: This should be solved with a special hdmi sink device or
1942 * similar so that power domains can be employed.
1944 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1947 return i915_drm_suspend_late(dev, false);
1950 static int i915_pm_poweroff_late(struct device *kdev)
1952 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1954 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1957 return i915_drm_suspend_late(dev, true);
1960 static int i915_pm_resume_early(struct device *kdev)
1962 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1964 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1967 return i915_drm_resume_early(dev);
1970 static int i915_pm_resume(struct device *kdev)
1972 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1974 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1977 return i915_drm_resume(dev);
1980 /* freeze: before creating the hibernation_image */
1981 static int i915_pm_freeze(struct device *kdev)
1985 ret = i915_pm_suspend(kdev);
1989 ret = i915_gem_freeze(kdev_to_i915(kdev));
1996 static int i915_pm_freeze_late(struct device *kdev)
2000 ret = i915_pm_suspend_late(kdev);
2004 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2011 /* thaw: called after creating the hibernation image, but before turning off. */
2012 static int i915_pm_thaw_early(struct device *kdev)
2014 return i915_pm_resume_early(kdev);
2017 static int i915_pm_thaw(struct device *kdev)
2019 return i915_pm_resume(kdev);
2022 /* restore: called after loading the hibernation image. */
2023 static int i915_pm_restore_early(struct device *kdev)
2025 return i915_pm_resume_early(kdev);
2028 static int i915_pm_restore(struct device *kdev)
2030 return i915_pm_resume(kdev);
2034 * Save all Gunit registers that may be lost after a D3 and a subsequent
2035 * S0i[R123] transition. The list of registers needing a save/restore is
2036 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2037 * registers in the following way:
2038 * - Driver: saved/restored by the driver
2039 * - Punit : saved/restored by the Punit firmware
2040 * - No, w/o marking: no need to save/restore, since the register is R/O or
2041 * used internally by the HW in a way that doesn't depend
2042 * keeping the content across a suspend/resume.
2043 * - Debug : used for debugging
2045 * We save/restore all registers marked with 'Driver', with the following
2047 * - Registers out of use, including also registers marked with 'Debug'.
2048 * These have no effect on the driver's operation, so we don't save/restore
2049 * them to reduce the overhead.
2050 * - Registers that are fully setup by an initialization function called from
2051 * the resume path. For example many clock gating and RPS/RC6 registers.
2052 * - Registers that provide the right functionality with their reset defaults.
2054 * TODO: Except for registers that based on the above 3 criteria can be safely
2055 * ignored, we save/restore all others, practically treating the HW context as
2056 * a black-box for the driver. Further investigation is needed to reduce the
2057 * saved/restored registers even further, by following the same 3 criteria.
2059 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2061 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2064 /* GAM 0x4000-0x4770 */
2065 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2066 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2067 s->arb_mode = I915_READ(ARB_MODE);
2068 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2069 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2071 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2072 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2074 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2075 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2077 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2078 s->ecochk = I915_READ(GAM_ECOCHK);
2079 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2080 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2082 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2084 /* MBC 0x9024-0x91D0, 0x8500 */
2085 s->g3dctl = I915_READ(VLV_G3DCTL);
2086 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2087 s->mbctl = I915_READ(GEN6_MBCTL);
2089 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2090 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2091 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2092 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2093 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2094 s->rstctl = I915_READ(GEN6_RSTCTL);
2095 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2097 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2098 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2099 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2100 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2101 s->ecobus = I915_READ(ECOBUS);
2102 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2103 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2104 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2105 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2106 s->rcedata = I915_READ(VLV_RCEDATA);
2107 s->spare2gh = I915_READ(VLV_SPAREG2H);
2109 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2110 s->gt_imr = I915_READ(GTIMR);
2111 s->gt_ier = I915_READ(GTIER);
2112 s->pm_imr = I915_READ(GEN6_PMIMR);
2113 s->pm_ier = I915_READ(GEN6_PMIER);
2115 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2116 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2118 /* GT SA CZ domain, 0x100000-0x138124 */
2119 s->tilectl = I915_READ(TILECTL);
2120 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2121 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2122 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2123 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2125 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2126 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2127 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2128 s->pcbr = I915_READ(VLV_PCBR);
2129 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2132 * Not saving any of:
2133 * DFT, 0x9800-0x9EC0
2134 * SARB, 0xB000-0xB1FC
2135 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2140 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2142 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2146 /* GAM 0x4000-0x4770 */
2147 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2148 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2149 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2150 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2151 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2153 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2154 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2156 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2157 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2159 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2160 I915_WRITE(GAM_ECOCHK, s->ecochk);
2161 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2162 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2164 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2166 /* MBC 0x9024-0x91D0, 0x8500 */
2167 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2168 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2169 I915_WRITE(GEN6_MBCTL, s->mbctl);
2171 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2172 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2173 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2174 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2175 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2176 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2177 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2179 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2180 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2181 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2182 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2183 I915_WRITE(ECOBUS, s->ecobus);
2184 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2185 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2186 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2187 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2188 I915_WRITE(VLV_RCEDATA, s->rcedata);
2189 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2191 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2192 I915_WRITE(GTIMR, s->gt_imr);
2193 I915_WRITE(GTIER, s->gt_ier);
2194 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2195 I915_WRITE(GEN6_PMIER, s->pm_ier);
2197 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2198 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2200 /* GT SA CZ domain, 0x100000-0x138124 */
2201 I915_WRITE(TILECTL, s->tilectl);
2202 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2204 * Preserve the GT allow wake and GFX force clock bit, they are not
2205 * be restored, as they are used to control the s0ix suspend/resume
2206 * sequence by the caller.
2208 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2209 val &= VLV_GTLC_ALLOWWAKEREQ;
2210 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2211 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2213 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2214 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2215 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2216 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2218 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2220 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2221 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2222 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2223 I915_WRITE(VLV_PCBR, s->pcbr);
2224 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2227 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2230 /* The HW does not like us polling for PW_STATUS frequently, so
2231 * use the sleeping loop rather than risk the busy spin within
2232 * intel_wait_for_register().
2234 * Transitioning between RC6 states should be at most 2ms (see
2235 * valleyview_enable_rps) so use a 3ms timeout.
2237 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2241 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2246 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2247 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2249 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2250 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2255 err = intel_wait_for_register(dev_priv,
2256 VLV_GTLC_SURVIVABILITY_REG,
2257 VLV_GFX_CLK_STATUS_BIT,
2258 VLV_GFX_CLK_STATUS_BIT,
2261 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2262 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2267 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2273 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2274 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2276 val |= VLV_GTLC_ALLOWWAKEREQ;
2277 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2278 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2280 mask = VLV_GTLC_ALLOWWAKEACK;
2281 val = allow ? mask : 0;
2283 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2285 DRM_ERROR("timeout disabling GT waking\n");
2290 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2296 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2297 val = wait_for_on ? mask : 0;
2300 * RC6 transitioning can be delayed up to 2 msec (see
2301 * valleyview_enable_rps), use 3 msec for safety.
2303 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2304 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2305 onoff(wait_for_on));
2308 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2310 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2313 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2314 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2317 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2323 * Bspec defines the following GT well on flags as debug only, so
2324 * don't treat them as hard failures.
2326 vlv_wait_for_gt_wells(dev_priv, false);
2328 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2329 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2331 vlv_check_no_gt_access(dev_priv);
2333 err = vlv_force_gfx_clock(dev_priv, true);
2337 err = vlv_allow_gt_wake(dev_priv, false);
2341 if (!IS_CHERRYVIEW(dev_priv))
2342 vlv_save_gunit_s0ix_state(dev_priv);
2344 err = vlv_force_gfx_clock(dev_priv, false);
2351 /* For safety always re-enable waking and disable gfx clock forcing */
2352 vlv_allow_gt_wake(dev_priv, true);
2354 vlv_force_gfx_clock(dev_priv, false);
2359 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2366 * If any of the steps fail just try to continue, that's the best we
2367 * can do at this point. Return the first error code (which will also
2368 * leave RPM permanently disabled).
2370 ret = vlv_force_gfx_clock(dev_priv, true);
2372 if (!IS_CHERRYVIEW(dev_priv))
2373 vlv_restore_gunit_s0ix_state(dev_priv);
2375 err = vlv_allow_gt_wake(dev_priv, true);
2379 err = vlv_force_gfx_clock(dev_priv, false);
2383 vlv_check_no_gt_access(dev_priv);
2386 intel_init_clock_gating(dev_priv);
2391 static int intel_runtime_suspend(struct device *kdev)
2393 struct pci_dev *pdev = to_pci_dev(kdev);
2394 struct drm_device *dev = pci_get_drvdata(pdev);
2395 struct drm_i915_private *dev_priv = to_i915(dev);
2398 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2401 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2404 DRM_DEBUG_KMS("Suspending device\n");
2406 disable_rpm_wakeref_asserts(dev_priv);
2409 * We are safe here against re-faults, since the fault handler takes
2412 i915_gem_runtime_suspend(dev_priv);
2414 intel_guc_suspend(dev_priv);
2416 intel_runtime_pm_disable_interrupts(dev_priv);
2419 if (IS_GEN9_LP(dev_priv)) {
2420 bxt_display_core_uninit(dev_priv);
2421 bxt_enable_dc9(dev_priv);
2422 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2423 hsw_enable_pc8(dev_priv);
2424 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2425 ret = vlv_suspend_complete(dev_priv);
2429 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2430 intel_runtime_pm_enable_interrupts(dev_priv);
2432 enable_rpm_wakeref_asserts(dev_priv);
2437 intel_uncore_suspend(dev_priv);
2439 enable_rpm_wakeref_asserts(dev_priv);
2440 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2442 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2443 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2445 dev_priv->pm.suspended = true;
2448 * FIXME: We really should find a document that references the arguments
2451 if (IS_BROADWELL(dev_priv)) {
2453 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2454 * being detected, and the call we do at intel_runtime_resume()
2455 * won't be able to restore them. Since PCI_D3hot matches the
2456 * actual specification and appears to be working, use it.
2458 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2461 * current versions of firmware which depend on this opregion
2462 * notification have repurposed the D1 definition to mean
2463 * "runtime suspended" vs. what you would normally expect (D3)
2464 * to distinguish it from notifications that might be sent via
2467 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2470 assert_forcewakes_inactive(dev_priv);
2472 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2473 intel_hpd_poll_init(dev_priv);
2475 DRM_DEBUG_KMS("Device suspended\n");
2479 static int intel_runtime_resume(struct device *kdev)
2481 struct pci_dev *pdev = to_pci_dev(kdev);
2482 struct drm_device *dev = pci_get_drvdata(pdev);
2483 struct drm_i915_private *dev_priv = to_i915(dev);
2486 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2489 DRM_DEBUG_KMS("Resuming device\n");
2491 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2492 disable_rpm_wakeref_asserts(dev_priv);
2494 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2495 dev_priv->pm.suspended = false;
2496 if (intel_uncore_unclaimed_mmio(dev_priv))
2497 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2499 intel_guc_resume(dev_priv);
2501 if (IS_GEN9_LP(dev_priv)) {
2502 bxt_disable_dc9(dev_priv);
2503 bxt_display_core_init(dev_priv, true);
2504 if (dev_priv->csr.dmc_payload &&
2505 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2506 gen9_enable_dc5(dev_priv);
2507 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2508 hsw_disable_pc8(dev_priv);
2509 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2510 ret = vlv_resume_prepare(dev_priv, true);
2514 * No point of rolling back things in case of an error, as the best
2515 * we can do is to hope that things will still work (and disable RPM).
2517 i915_gem_init_swizzling(dev_priv);
2518 i915_gem_restore_fences(dev_priv);
2520 intel_runtime_pm_enable_interrupts(dev_priv);
2523 * On VLV/CHV display interrupts are part of the display
2524 * power well, so hpd is reinitialized from there. For
2525 * everyone else do it here.
2527 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2528 intel_hpd_init(dev_priv);
2530 enable_rpm_wakeref_asserts(dev_priv);
2533 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2535 DRM_DEBUG_KMS("Device resumed\n");
2540 const struct dev_pm_ops i915_pm_ops = {
2542 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2545 .suspend = i915_pm_suspend,
2546 .suspend_late = i915_pm_suspend_late,
2547 .resume_early = i915_pm_resume_early,
2548 .resume = i915_pm_resume,
2552 * @freeze, @freeze_late : called (1) before creating the
2553 * hibernation image [PMSG_FREEZE] and
2554 * (2) after rebooting, before restoring
2555 * the image [PMSG_QUIESCE]
2556 * @thaw, @thaw_early : called (1) after creating the hibernation
2557 * image, before writing it [PMSG_THAW]
2558 * and (2) after failing to create or
2559 * restore the image [PMSG_RECOVER]
2560 * @poweroff, @poweroff_late: called after writing the hibernation
2561 * image, before rebooting [PMSG_HIBERNATE]
2562 * @restore, @restore_early : called after rebooting and restoring the
2563 * hibernation image [PMSG_RESTORE]
2565 .freeze = i915_pm_freeze,
2566 .freeze_late = i915_pm_freeze_late,
2567 .thaw_early = i915_pm_thaw_early,
2568 .thaw = i915_pm_thaw,
2569 .poweroff = i915_pm_suspend,
2570 .poweroff_late = i915_pm_poweroff_late,
2571 .restore_early = i915_pm_restore_early,
2572 .restore = i915_pm_restore,
2574 /* S0ix (via runtime suspend) event handlers */
2575 .runtime_suspend = intel_runtime_suspend,
2576 .runtime_resume = intel_runtime_resume,
2579 static const struct vm_operations_struct i915_gem_vm_ops = {
2580 .fault = i915_gem_fault,
2581 .open = drm_gem_vm_open,
2582 .close = drm_gem_vm_close,
2585 static const struct file_operations i915_driver_fops = {
2586 .owner = THIS_MODULE,
2588 .release = drm_release,
2589 .unlocked_ioctl = drm_ioctl,
2590 .mmap = drm_gem_mmap,
2593 .compat_ioctl = i915_compat_ioctl,
2594 .llseek = noop_llseek,
2598 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2599 struct drm_file *file)
2604 static const struct drm_ioctl_desc i915_ioctls[] = {
2605 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2606 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2607 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2608 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2609 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2610 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2611 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2612 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2613 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2614 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2615 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2616 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2617 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2618 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2619 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2620 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2621 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2622 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2623 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2624 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2625 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2626 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2627 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2628 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2629 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2630 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2631 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2632 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2633 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2634 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2635 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2636 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2637 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2638 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2639 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2640 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2641 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2642 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2643 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2644 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2645 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2646 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2647 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2648 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2649 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2650 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2651 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2652 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2653 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2654 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2655 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2656 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2657 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2660 static struct drm_driver driver = {
2661 /* Don't use MTRRs here; the Xserver or userspace app should
2662 * deal with them for Intel hardware.
2665 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2666 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2667 .release = i915_driver_release,
2668 .open = i915_driver_open,
2669 .lastclose = i915_driver_lastclose,
2670 .postclose = i915_driver_postclose,
2671 .set_busid = drm_pci_set_busid,
2673 .gem_close_object = i915_gem_close_object,
2674 .gem_free_object_unlocked = i915_gem_free_object,
2675 .gem_vm_ops = &i915_gem_vm_ops,
2677 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2678 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2679 .gem_prime_export = i915_gem_prime_export,
2680 .gem_prime_import = i915_gem_prime_import,
2682 .dumb_create = i915_gem_dumb_create,
2683 .dumb_map_offset = i915_gem_mmap_gtt,
2684 .dumb_destroy = drm_gem_dumb_destroy,
2685 .ioctls = i915_ioctls,
2686 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2687 .fops = &i915_driver_fops,
2688 .name = DRIVER_NAME,
2689 .desc = DRIVER_DESC,
2690 .date = DRIVER_DATE,
2691 .major = DRIVER_MAJOR,
2692 .minor = DRIVER_MINOR,
2693 .patchlevel = DRIVER_PATCHLEVEL,
2696 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2697 #include "selftests/mock_drm.c"