drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 140                 ret = PCH_SPT;
 141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 142         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 143                 ret = PCH_CNP;
 144                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 145         }
 146
 147         return ret;
 148 }
 149
 150 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 151 {
 152         struct pci_dev *pch = NULL;
 153
 154         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 155          * (which really amounts to a PCH but no South Display).
 156          */
 157         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 158                 dev_priv->pch_type = PCH_NOP;
 159                 return;
 160         }
 161
 162         /*
 163          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 164          * make graphics device passthrough work easy for VMM, that only
 165          * need to expose ISA bridge to let driver know the real hardware
 166          * underneath. This is a requirement from virtualization team.
 167          *
 168          * In some virtualized environments (e.g. XEN), there is irrelevant
 169          * ISA bridge in the system. To work reliably, we should scan trhough
 170          * all the ISA bridge devices and check for the first match, instead
 171          * of only checking the first one.
 172          */
 173         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 174                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 175                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 176                         unsigned short id_ext = pch->device &
 177                                 INTEL_PCH_DEVICE_ID_MASK_EXT;
 178
 179                         dev_priv->pch_id = id;
 180
 181                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 182                                 dev_priv->pch_type = PCH_IBX;
 183                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 184                                 WARN_ON(!IS_GEN5(dev_priv));
 185                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 186                                 dev_priv->pch_type = PCH_CPT;
 187                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 189                                         IS_IVYBRIDGE(dev_priv)));
 190                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 191                                 /* PantherPoint is CPT compatible */
 192                                 dev_priv->pch_type = PCH_CPT;
 193                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 194                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 195                                         IS_IVYBRIDGE(dev_priv)));
 196                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 197                                 dev_priv->pch_type = PCH_LPT;
 198                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 199                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 200                                         !IS_BROADWELL(dev_priv));
 201                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 202                                         IS_BDW_ULT(dev_priv));
 203                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 204                                 dev_priv->pch_type = PCH_LPT;
 205                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 206                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 207                                         !IS_BROADWELL(dev_priv));
 208                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 209                                         !IS_BDW_ULT(dev_priv));
 210                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 211                                 dev_priv->pch_type = PCH_SPT;
 212                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 213                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 214                                         !IS_KABYLAKE(dev_priv));
 215                         } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 216                                 dev_priv->pch_type = PCH_SPT;
 217                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 218                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 219                                         !IS_KABYLAKE(dev_priv));
 220                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 221                                 dev_priv->pch_type = PCH_KBP;
 222                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 223                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 224                                         !IS_KABYLAKE(dev_priv));
 225                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 226                                 dev_priv->pch_type = PCH_CNP;
 227                                 DRM_DEBUG_KMS("Found CannonPoint PCH\n");
 228                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 229                                         !IS_COFFEELAKE(dev_priv));
 230                         } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 231                                 dev_priv->pch_type = PCH_CNP;
 232                                 DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
 233                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 234                                         !IS_COFFEELAKE(dev_priv));
 235                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 236                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 237                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 238                                     pch->subsystem_vendor ==
 239                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 240                                     pch->subsystem_device ==
 241                                             PCI_SUBDEVICE_ID_QEMU)) {
 242                                 dev_priv->pch_type =
 243                                         intel_virt_detect_pch(dev_priv);
 244                         } else
 245                                 continue;
 246
 247                         break;
 248                 }
 249         }
 250         if (!pch)
 251                 DRM_DEBUG_KMS("No PCH found.\n");
 252
 253         pci_dev_put(pch);
 254 }
 255
 256 static int i915_getparam(struct drm_device *dev, void *data,
 257                          struct drm_file *file_priv)
 258 {
 259         struct drm_i915_private *dev_priv = to_i915(dev);
 260         struct pci_dev *pdev = dev_priv->drm.pdev;
 261         drm_i915_getparam_t *param = data;
 262         int value;
 263
 264         switch (param->param) {
 265         case I915_PARAM_IRQ_ACTIVE:
 266         case I915_PARAM_ALLOW_BATCHBUFFER:
 267         case I915_PARAM_LAST_DISPATCH:
 268         case I915_PARAM_HAS_EXEC_CONSTANTS:
 269                 /* Reject all old ums/dri params. */
 270                 return -ENODEV;
 271         case I915_PARAM_CHIPSET_ID:
 272                 value = pdev->device;
 273                 break;
 274         case I915_PARAM_REVISION:
 275                 value = pdev->revision;
 276                 break;
 277         case I915_PARAM_NUM_FENCES_AVAIL:
 278                 value = dev_priv->num_fence_regs;
 279                 break;
 280         case I915_PARAM_HAS_OVERLAY:
 281                 value = dev_priv->overlay ? 1 : 0;
 282                 break;
 283         case I915_PARAM_HAS_BSD:
 284                 value = !!dev_priv->engine[VCS];
 285                 break;
 286         case I915_PARAM_HAS_BLT:
 287                 value = !!dev_priv->engine[BCS];
 288                 break;
 289         case I915_PARAM_HAS_VEBOX:
 290                 value = !!dev_priv->engine[VECS];
 291                 break;
 292         case I915_PARAM_HAS_BSD2:
 293                 value = !!dev_priv->engine[VCS2];
 294                 break;
 295         case I915_PARAM_HAS_LLC:
 296                 value = HAS_LLC(dev_priv);
 297                 break;
 298         case I915_PARAM_HAS_WT:
 299                 value = HAS_WT(dev_priv);
 300                 break;
 301         case I915_PARAM_HAS_ALIASING_PPGTT:
 302                 value = USES_PPGTT(dev_priv);
 303                 break;
 304         case I915_PARAM_HAS_SEMAPHORES:
 305                 value = i915.semaphores;
 306                 break;
 307         case I915_PARAM_HAS_SECURE_BATCHES:
 308                 value = capable(CAP_SYS_ADMIN);
 309                 break;
 310         case I915_PARAM_CMD_PARSER_VERSION:
 311                 value = i915_cmd_parser_get_version(dev_priv);
 312                 break;
 313         case I915_PARAM_SUBSLICE_TOTAL:
 314                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 315                 if (!value)
 316                         return -ENODEV;
 317                 break;
 318         case I915_PARAM_EU_TOTAL:
 319                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 320                 if (!value)
 321                         return -ENODEV;
 322                 break;
 323         case I915_PARAM_HAS_GPU_RESET:
 324                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 325                 break;
 326         case I915_PARAM_HAS_RESOURCE_STREAMER:
 327                 value = HAS_RESOURCE_STREAMER(dev_priv);
 328                 break;
 329         case I915_PARAM_HAS_POOLED_EU:
 330                 value = HAS_POOLED_EU(dev_priv);
 331                 break;
 332         case I915_PARAM_MIN_EU_IN_POOL:
 333                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 334                 break;
 335         case I915_PARAM_HUC_STATUS:
 336                 intel_runtime_pm_get(dev_priv);
 337                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 338                 intel_runtime_pm_put(dev_priv);
 339                 break;
 340         case I915_PARAM_MMAP_GTT_VERSION:
 341                 /* Though we've started our numbering from 1, and so class all
 342                  * earlier versions as 0, in effect their value is undefined as
 343                  * the ioctl will report EINVAL for the unknown param!
 344                  */
 345                 value = i915_gem_mmap_gtt_version();
 346                 break;
 347         case I915_PARAM_HAS_SCHEDULER:
 348                 value = dev_priv->engine[RCS] &&
 349                         dev_priv->engine[RCS]->schedule;
 350                 break;
 351         case I915_PARAM_MMAP_VERSION:
 352                 /* Remember to bump this if the version changes! */
 353         case I915_PARAM_HAS_GEM:
 354         case I915_PARAM_HAS_PAGEFLIPPING:
 355         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 356         case I915_PARAM_HAS_RELAXED_FENCING:
 357         case I915_PARAM_HAS_COHERENT_RINGS:
 358         case I915_PARAM_HAS_RELAXED_DELTA:
 359         case I915_PARAM_HAS_GEN7_SOL_RESET:
 360         case I915_PARAM_HAS_WAIT_TIMEOUT:
 361         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 362         case I915_PARAM_HAS_PINNED_BATCHES:
 363         case I915_PARAM_HAS_EXEC_NO_RELOC:
 364         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 365         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 366         case I915_PARAM_HAS_EXEC_SOFTPIN:
 367         case I915_PARAM_HAS_EXEC_ASYNC:
 368         case I915_PARAM_HAS_EXEC_FENCE:
 369         case I915_PARAM_HAS_EXEC_CAPTURE:
 370         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 371                 /* For the time being all of these are always true;
 372                  * if some supported hardware does not have one of these
 373                  * features this value needs to be provided from
 374                  * INTEL_INFO(), a feature macro, or similar.
 375                  */
 376                 value = 1;
 377                 break;
 378         case I915_PARAM_SLICE_MASK:
 379                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 380                 if (!value)
 381                         return -ENODEV;
 382                 break;
 383         case I915_PARAM_SUBSLICE_MASK:
 384                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 385                 if (!value)
 386                         return -ENODEV;
 387                 break;
 388         default:
 389                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 390                 return -EINVAL;
 391         }
 392
 393         if (put_user(value, param->value))
 394                 return -EFAULT;
 395
 396         return 0;
 397 }
 398
 399 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 400 {
 401         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 402         if (!dev_priv->bridge_dev) {
 403                 DRM_ERROR("bridge device not found\n");
 404                 return -1;
 405         }
 406         return 0;
 407 }
 408
 409 /* Allocate space for the MCH regs if needed, return nonzero on error */
 410 static int
 411 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 412 {
 413         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 414         u32 temp_lo, temp_hi = 0;
 415         u64 mchbar_addr;
 416         int ret;
 417
 418         if (INTEL_GEN(dev_priv) >= 4)
 419                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 420         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 421         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 422
 423         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 424 #ifdef CONFIG_PNP
 425         if (mchbar_addr &&
 426             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 427                 return 0;
 428 #endif
 429
 430         /* Get some space for it */
 431         dev_priv->mch_res.name = "i915 MCHBAR";
 432         dev_priv->mch_res.flags = IORESOURCE_MEM;
 433         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 434                                      &dev_priv->mch_res,
 435                                      MCHBAR_SIZE, MCHBAR_SIZE,
 436                                      PCIBIOS_MIN_MEM,
 437                                      0, pcibios_align_resource,
 438                                      dev_priv->bridge_dev);
 439         if (ret) {
 440                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 441                 dev_priv->mch_res.start = 0;
 442                 return ret;
 443         }
 444
 445         if (INTEL_GEN(dev_priv) >= 4)
 446                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 447                                        upper_32_bits(dev_priv->mch_res.start));
 448
 449         pci_write_config_dword(dev_priv->bridge_dev, reg,
 450                                lower_32_bits(dev_priv->mch_res.start));
 451         return 0;
 452 }
 453
 454 /* Setup MCHBAR if possible, return true if we should disable it again */
 455 static void
 456 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 457 {
 458         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 459         u32 temp;
 460         bool enabled;
 461
 462         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 463                 return;
 464
 465         dev_priv->mchbar_need_disable = false;
 466
 467         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 468                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 469                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 470         } else {
 471                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 472                 enabled = temp & 1;
 473         }
 474
 475         /* If it's already enabled, don't have to do anything */
 476         if (enabled)
 477                 return;
 478
 479         if (intel_alloc_mchbar_resource(dev_priv))
 480                 return;
 481
 482         dev_priv->mchbar_need_disable = true;
 483
 484         /* Space is allocated or reserved, so enable it. */
 485         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 486                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 487                                        temp | DEVEN_MCHBAR_EN);
 488         } else {
 489                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 490                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 491         }
 492 }
 493
 494 static void
 495 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 496 {
 497         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 498
 499         if (dev_priv->mchbar_need_disable) {
 500                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 501                         u32 deven_val;
 502
 503                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 504                                               &deven_val);
 505                         deven_val &= ~DEVEN_MCHBAR_EN;
 506                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 507                                                deven_val);
 508                 } else {
 509                         u32 mchbar_val;
 510
 511                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 512                                               &mchbar_val);
 513                         mchbar_val &= ~1;
 514                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 515                                                mchbar_val);
 516                 }
 517         }
 518
 519         if (dev_priv->mch_res.start)
 520                 release_resource(&dev_priv->mch_res);
 521 }
 522
 523 /* true = enable decode, false = disable decoder */
 524 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 525 {
 526         struct drm_i915_private *dev_priv = cookie;
 527
 528         intel_modeset_vga_set_state(dev_priv, state);
 529         if (state)
 530                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 531                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 532         else
 533                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 534 }
 535
 536 static int i915_resume_switcheroo(struct drm_device *dev);
 537 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 538
 539 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 540 {
 541         struct drm_device *dev = pci_get_drvdata(pdev);
 542         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 543
 544         if (state == VGA_SWITCHEROO_ON) {
 545                 pr_info("switched on\n");
 546                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 547                 /* i915 resume handler doesn't set to D0 */
 548                 pci_set_power_state(pdev, PCI_D0);
 549                 i915_resume_switcheroo(dev);
 550                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 551         } else {
 552                 pr_info("switched off\n");
 553                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 554                 i915_suspend_switcheroo(dev, pmm);
 555                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 556         }
 557 }
 558
 559 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 560 {
 561         struct drm_device *dev = pci_get_drvdata(pdev);
 562
 563         /*
 564          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 565          * locking inversion with the driver load path. And the access here is
 566          * completely racy anyway. So don't bother with locking for now.
 567          */
 568         return dev->open_count == 0;
 569 }
 570
 571 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 572         .set_gpu_state = i915_switcheroo_set_state,
 573         .reprobe = NULL,
 574         .can_switch = i915_switcheroo_can_switch,
 575 };
 576
 577 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 578 {
 579         mutex_lock(&dev_priv->drm.struct_mutex);
 580         intel_uc_fini_hw(dev_priv);
 581         i915_gem_cleanup_engines(dev_priv);
 582         i915_gem_context_fini(dev_priv);
 583         i915_gem_cleanup_userptr(dev_priv);
 584         mutex_unlock(&dev_priv->drm.struct_mutex);
 585
 586         i915_gem_drain_freed_objects(dev_priv);
 587
 588         WARN_ON(!list_empty(&dev_priv->context_list));
 589 }
 590
 591 static int i915_load_modeset_init(struct drm_device *dev)
 592 {
 593         struct drm_i915_private *dev_priv = to_i915(dev);
 594         struct pci_dev *pdev = dev_priv->drm.pdev;
 595         int ret;
 596
 597         if (i915_inject_load_failure())
 598                 return -ENODEV;
 599
 600         intel_bios_init(dev_priv);
 601
 602         /* If we have > 1 VGA cards, then we need to arbitrate access
 603          * to the common VGA resources.
 604          *
 605          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 606          * then we do not take part in VGA arbitration and the
 607          * vga_client_register() fails with -ENODEV.
 608          */
 609         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 610         if (ret && ret != -ENODEV)
 611                 goto out;
 612
 613         intel_register_dsm_handler();
 614
 615         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 616         if (ret)
 617                 goto cleanup_vga_client;
 618
 619         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 620         intel_update_rawclk(dev_priv);
 621
 622         intel_power_domains_init_hw(dev_priv, false);
 623
 624         intel_csr_ucode_init(dev_priv);
 625
 626         ret = intel_irq_install(dev_priv);
 627         if (ret)
 628                 goto cleanup_csr;
 629
 630         intel_setup_gmbus(dev_priv);
 631
 632         /* Important: The output setup functions called by modeset_init need
 633          * working irqs for e.g. gmbus and dp aux transfers. */
 634         ret = intel_modeset_init(dev);
 635         if (ret)
 636                 goto cleanup_irq;
 637
 638         intel_uc_init_fw(dev_priv);
 639
 640         ret = i915_gem_init(dev_priv);
 641         if (ret)
 642                 goto cleanup_uc;
 643
 644         intel_modeset_gem_init(dev);
 645
 646         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 647                 return 0;
 648
 649         ret = intel_fbdev_init(dev);
 650         if (ret)
 651                 goto cleanup_gem;
 652
 653         /* Only enable hotplug handling once the fbdev is fully set up. */
 654         intel_hpd_init(dev_priv);
 655
 656         drm_kms_helper_poll_init(dev);
 657
 658         return 0;
 659
 660 cleanup_gem:
 661         if (i915_gem_suspend(dev_priv))
 662                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 663         i915_gem_fini(dev_priv);
 664 cleanup_uc:
 665         intel_uc_fini_fw(dev_priv);
 666 cleanup_irq:
 667         drm_irq_uninstall(dev);
 668         intel_teardown_gmbus(dev_priv);
 669 cleanup_csr:
 670         intel_csr_ucode_fini(dev_priv);
 671         intel_power_domains_fini(dev_priv);
 672         vga_switcheroo_unregister_client(pdev);
 673 cleanup_vga_client:
 674         vga_client_register(pdev, NULL, NULL, NULL);
 675 out:
 676         return ret;
 677 }
 678
 679 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 680 {
 681         struct apertures_struct *ap;
 682         struct pci_dev *pdev = dev_priv->drm.pdev;
 683         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 684         bool primary;
 685         int ret;
 686
 687         ap = alloc_apertures(1);
 688         if (!ap)
 689                 return -ENOMEM;
 690
 691         ap->ranges[0].base = ggtt->mappable_base;
 692         ap->ranges[0].size = ggtt->mappable_end;
 693
 694         primary =
 695                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 696
 697         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 698
 699         kfree(ap);
 700
 701         return ret;
 702 }
 703
 704 #if !defined(CONFIG_VGA_CONSOLE)
 705 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 706 {
 707         return 0;
 708 }
 709 #elif !defined(CONFIG_DUMMY_CONSOLE)
 710 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 711 {
 712         return -ENODEV;
 713 }
 714 #else
 715 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 716 {
 717         int ret = 0;
 718
 719         DRM_INFO("Replacing VGA console driver\n");
 720
 721         console_lock();
 722         if (con_is_bound(&vga_con))
 723                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 724         if (ret == 0) {
 725                 ret = do_unregister_con_driver(&vga_con);
 726
 727                 /* Ignore "already unregistered". */
 728                 if (ret == -ENODEV)
 729                         ret = 0;
 730         }
 731         console_unlock();
 732
 733         return ret;
 734 }
 735 #endif
 736
 737 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 738 {
 739         /*
 740          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 741          * CHV x1 PHY (DP/HDMI D)
 742          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 743          */
 744         if (IS_CHERRYVIEW(dev_priv)) {
 745                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 746                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 747         } else if (IS_VALLEYVIEW(dev_priv)) {
 748                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 749         }
 750 }
 751
 752 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 753 {
 754         /*
 755          * The i915 workqueue is primarily used for batched retirement of
 756          * requests (and thus managing bo) once the task has been completed
 757          * by the GPU. i915_gem_retire_requests() is called directly when we
 758          * need high-priority retirement, such as waiting for an explicit
 759          * bo.
 760          *
 761          * It is also used for periodic low-priority events, such as
 762          * idle-timers and recording error state.
 763          *
 764          * All tasks on the workqueue are expected to acquire the dev mutex
 765          * so there is no point in running more than one instance of the
 766          * workqueue at any time.  Use an ordered one.
 767          */
 768         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 769         if (dev_priv->wq == NULL)
 770                 goto out_err;
 771
 772         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 773         if (dev_priv->hotplug.dp_wq == NULL)
 774                 goto out_free_wq;
 775
 776         return 0;
 777
 778 out_free_wq:
 779         destroy_workqueue(dev_priv->wq);
 780 out_err:
 781         DRM_ERROR("Failed to allocate workqueues.\n");
 782
 783         return -ENOMEM;
 784 }
 785
 786 static void i915_engines_cleanup(struct drm_i915_private *i915)
 787 {
 788         struct intel_engine_cs *engine;
 789         enum intel_engine_id id;
 790
 791         for_each_engine(engine, i915, id)
 792                 kfree(engine);
 793 }
 794
 795 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 796 {
 797         destroy_workqueue(dev_priv->hotplug.dp_wq);
 798         destroy_workqueue(dev_priv->wq);
 799 }
 800
 801 /*
 802  * We don't keep the workarounds for pre-production hardware, so we expect our
 803  * driver to fail on these machines in one way or another. A little warning on
 804  * dmesg may help both the user and the bug triagers.
 805  */
 806 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 807 {
 808         bool pre = false;
 809
 810         pre |= IS_HSW_EARLY_SDV(dev_priv);
 811         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 812         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 813
 814         if (pre) {
 815                 DRM_ERROR("This is a pre-production stepping. "
 816                           "It may not be fully functional.\n");
 817                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 818         }
 819 }
 820
 821 /**
 822  * i915_driver_init_early - setup state not requiring device access
 823  * @dev_priv: device private
 824  *
 825  * Initialize everything that is a "SW-only" state, that is state not
 826  * requiring accessing the device or exposing the driver via kernel internal
 827  * or userspace interfaces. Example steps belonging here: lock initialization,
 828  * system memory allocation, setting up device specific attributes and
 829  * function hooks not requiring accessing the device.
 830  */
 831 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 832                                   const struct pci_device_id *ent)
 833 {
 834         const struct intel_device_info *match_info =
 835                 (struct intel_device_info *)ent->driver_data;
 836         struct intel_device_info *device_info;
 837         int ret = 0;
 838
 839         if (i915_inject_load_failure())
 840                 return -ENODEV;
 841
 842         /* Setup the write-once "constant" device info */
 843         device_info = mkwrite_device_info(dev_priv);
 844         memcpy(device_info, match_info, sizeof(*device_info));
 845         device_info->device_id = dev_priv->drm.pdev->device;
 846
 847         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 848         device_info->gen_mask = BIT(device_info->gen - 1);
 849
 850         spin_lock_init(&dev_priv->irq_lock);
 851         spin_lock_init(&dev_priv->gpu_error.lock);
 852         mutex_init(&dev_priv->backlight_lock);
 853         spin_lock_init(&dev_priv->uncore.lock);
 854
 855         spin_lock_init(&dev_priv->mm.object_stat_lock);
 856         spin_lock_init(&dev_priv->mmio_flip_lock);
 857         mutex_init(&dev_priv->sb_lock);
 858         mutex_init(&dev_priv->modeset_restore_lock);
 859         mutex_init(&dev_priv->av_mutex);
 860         mutex_init(&dev_priv->wm.wm_mutex);
 861         mutex_init(&dev_priv->pps_mutex);
 862
 863         intel_uc_init_early(dev_priv);
 864         i915_memcpy_init_early(dev_priv);
 865
 866         ret = i915_workqueues_init(dev_priv);
 867         if (ret < 0)
 868                 goto err_engines;
 869
 870         /* This must be called before any calls to HAS_PCH_* */
 871         intel_detect_pch(dev_priv);
 872
 873         intel_pm_setup(dev_priv);
 874         intel_init_dpio(dev_priv);
 875         intel_power_domains_init(dev_priv);
 876         intel_irq_init(dev_priv);
 877         intel_hangcheck_init(dev_priv);
 878         intel_init_display_hooks(dev_priv);
 879         intel_init_clock_gating_hooks(dev_priv);
 880         intel_init_audio_hooks(dev_priv);
 881         ret = i915_gem_load_init(dev_priv);
 882         if (ret < 0)
 883                 goto err_irq;
 884
 885         intel_display_crc_init(dev_priv);
 886
 887         intel_device_info_dump(dev_priv);
 888
 889         intel_detect_preproduction_hw(dev_priv);
 890
 891         i915_perf_init(dev_priv);
 892
 893         return 0;
 894
 895 err_irq:
 896         intel_irq_fini(dev_priv);
 897         i915_workqueues_cleanup(dev_priv);
 898 err_engines:
 899         i915_engines_cleanup(dev_priv);
 900         return ret;
 901 }
 902
 903 /**
 904  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 905  * @dev_priv: device private
 906  */
 907 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 908 {
 909         i915_perf_fini(dev_priv);
 910         i915_gem_load_cleanup(dev_priv);
 911         intel_irq_fini(dev_priv);
 912         i915_workqueues_cleanup(dev_priv);
 913         i915_engines_cleanup(dev_priv);
 914 }
 915
 916 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 917 {
 918         struct pci_dev *pdev = dev_priv->drm.pdev;
 919         int mmio_bar;
 920         int mmio_size;
 921
 922         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 923         /*
 924          * Before gen4, the registers and the GTT are behind different BARs.
 925          * However, from gen4 onwards, the registers and the GTT are shared
 926          * in the same BAR, so we want to restrict this ioremap from
 927          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 928          * the register BAR remains the same size for all the earlier
 929          * generations up to Ironlake.
 930          */
 931         if (INTEL_GEN(dev_priv) < 5)
 932                 mmio_size = 512 * 1024;
 933         else
 934                 mmio_size = 2 * 1024 * 1024;
 935         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 936         if (dev_priv->regs == NULL) {
 937                 DRM_ERROR("failed to map registers\n");
 938
 939                 return -EIO;
 940         }
 941
 942         /* Try to make sure MCHBAR is enabled before poking at it */
 943         intel_setup_mchbar(dev_priv);
 944
 945         return 0;
 946 }
 947
 948 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 949 {
 950         struct pci_dev *pdev = dev_priv->drm.pdev;
 951
 952         intel_teardown_mchbar(dev_priv);
 953         pci_iounmap(pdev, dev_priv->regs);
 954 }
 955
 956 /**
 957  * i915_driver_init_mmio - setup device MMIO
 958  * @dev_priv: device private
 959  *
 960  * Setup minimal device state necessary for MMIO accesses later in the
 961  * initialization sequence. The setup here should avoid any other device-wide
 962  * side effects or exposing the driver via kernel internal or user space
 963  * interfaces.
 964  */
 965 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 966 {
 967         int ret;
 968
 969         if (i915_inject_load_failure())
 970                 return -ENODEV;
 971
 972         if (i915_get_bridge_dev(dev_priv))
 973                 return -EIO;
 974
 975         ret = i915_mmio_setup(dev_priv);
 976         if (ret < 0)
 977                 goto err_bridge;
 978
 979         intel_uncore_init(dev_priv);
 980
 981         ret = intel_engines_init_mmio(dev_priv);
 982         if (ret)
 983                 goto err_uncore;
 984
 985         i915_gem_init_mmio(dev_priv);
 986
 987         return 0;
 988
 989 err_uncore:
 990         intel_uncore_fini(dev_priv);
 991 err_bridge:
 992         pci_dev_put(dev_priv->bridge_dev);
 993
 994         return ret;
 995 }
 996
 997 /**
 998  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 999  * @dev_priv: device private
1000  */
1001 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1002 {
1003         intel_uncore_fini(dev_priv);
1004         i915_mmio_cleanup(dev_priv);
1005         pci_dev_put(dev_priv->bridge_dev);
1006 }
1007
1008 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1009 {
1010         i915.enable_execlists =
1011                 intel_sanitize_enable_execlists(dev_priv,
1012                                                 i915.enable_execlists);
1013
1014         /*
1015          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1016          * user's requested state against the hardware/driver capabilities.  We
1017          * do this now so that we can print out any log messages once rather
1018          * than every time we check intel_enable_ppgtt().
1019          */
1020         i915.enable_ppgtt =
1021                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1022         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1023
1024         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1025         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1026
1027         intel_uc_sanitize_options(dev_priv);
1028
1029         intel_gvt_sanitize_options(dev_priv);
1030 }
1031
1032 /**
1033  * i915_driver_init_hw - setup state requiring device access
1034  * @dev_priv: device private
1035  *
1036  * Setup state that requires accessing the device, but doesn't require
1037  * exposing the driver via kernel internal or userspace interfaces.
1038  */
1039 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1040 {
1041         struct pci_dev *pdev = dev_priv->drm.pdev;
1042         int ret;
1043
1044         if (i915_inject_load_failure())
1045                 return -ENODEV;
1046
1047         intel_device_info_runtime_init(dev_priv);
1048
1049         intel_sanitize_options(dev_priv);
1050
1051         ret = i915_ggtt_probe_hw(dev_priv);
1052         if (ret)
1053                 return ret;
1054
1055         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1056          * otherwise the vga fbdev driver falls over. */
1057         ret = i915_kick_out_firmware_fb(dev_priv);
1058         if (ret) {
1059                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1060                 goto out_ggtt;
1061         }
1062
1063         ret = i915_kick_out_vgacon(dev_priv);
1064         if (ret) {
1065                 DRM_ERROR("failed to remove conflicting VGA console\n");
1066                 goto out_ggtt;
1067         }
1068
1069         ret = i915_ggtt_init_hw(dev_priv);
1070         if (ret)
1071                 return ret;
1072
1073         ret = i915_ggtt_enable_hw(dev_priv);
1074         if (ret) {
1075                 DRM_ERROR("failed to enable GGTT\n");
1076                 goto out_ggtt;
1077         }
1078
1079         pci_set_master(pdev);
1080
1081         /* overlay on gen2 is broken and can't address above 1G */
1082         if (IS_GEN2(dev_priv)) {
1083                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1084                 if (ret) {
1085                         DRM_ERROR("failed to set DMA mask\n");
1086
1087                         goto out_ggtt;
1088                 }
1089         }
1090
1091         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1092          * using 32bit addressing, overwriting memory if HWS is located
1093          * above 4GB.
1094          *
1095          * The documentation also mentions an issue with undefined
1096          * behaviour if any general state is accessed within a page above 4GB,
1097          * which also needs to be handled carefully.
1098          */
1099         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1100                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1101
1102                 if (ret) {
1103                         DRM_ERROR("failed to set DMA mask\n");
1104
1105                         goto out_ggtt;
1106                 }
1107         }
1108
1109         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1110                            PM_QOS_DEFAULT_VALUE);
1111
1112         intel_uncore_sanitize(dev_priv);
1113
1114         intel_opregion_setup(dev_priv);
1115
1116         i915_gem_load_init_fences(dev_priv);
1117
1118         /* On the 945G/GM, the chipset reports the MSI capability on the
1119          * integrated graphics even though the support isn't actually there
1120          * according to the published specs.  It doesn't appear to function
1121          * correctly in testing on 945G.
1122          * This may be a side effect of MSI having been made available for PEG
1123          * and the registers being closely associated.
1124          *
1125          * According to chipset errata, on the 965GM, MSI interrupts may
1126          * be lost or delayed, but we use them anyways to avoid
1127          * stuck interrupts on some machines.
1128          */
1129         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1130                 if (pci_enable_msi(pdev) < 0)
1131                         DRM_DEBUG_DRIVER("can't enable MSI");
1132         }
1133
1134         ret = intel_gvt_init(dev_priv);
1135         if (ret)
1136                 goto out_ggtt;
1137
1138         return 0;
1139
1140 out_ggtt:
1141         i915_ggtt_cleanup_hw(dev_priv);
1142
1143         return ret;
1144 }
1145
1146 /**
1147  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1148  * @dev_priv: device private
1149  */
1150 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1151 {
1152         struct pci_dev *pdev = dev_priv->drm.pdev;
1153
1154         if (pdev->msi_enabled)
1155                 pci_disable_msi(pdev);
1156
1157         pm_qos_remove_request(&dev_priv->pm_qos);
1158         i915_ggtt_cleanup_hw(dev_priv);
1159 }
1160
1161 /**
1162  * i915_driver_register - register the driver with the rest of the system
1163  * @dev_priv: device private
1164  *
1165  * Perform any steps necessary to make the driver available via kernel
1166  * internal or userspace interfaces.
1167  */
1168 static void i915_driver_register(struct drm_i915_private *dev_priv)
1169 {
1170         struct drm_device *dev = &dev_priv->drm;
1171
1172         i915_gem_shrinker_init(dev_priv);
1173
1174         /*
1175          * Notify a valid surface after modesetting,
1176          * when running inside a VM.
1177          */
1178         if (intel_vgpu_active(dev_priv))
1179                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1180
1181         /* Reveal our presence to userspace */
1182         if (drm_dev_register(dev, 0) == 0) {
1183                 i915_debugfs_register(dev_priv);
1184                 i915_guc_log_register(dev_priv);
1185                 i915_setup_sysfs(dev_priv);
1186
1187                 /* Depends on sysfs having been initialized */
1188                 i915_perf_register(dev_priv);
1189         } else
1190                 DRM_ERROR("Failed to register driver for userspace access!\n");
1191
1192         if (INTEL_INFO(dev_priv)->num_pipes) {
1193                 /* Must be done after probing outputs */
1194                 intel_opregion_register(dev_priv);
1195                 acpi_video_register();
1196         }
1197
1198         if (IS_GEN5(dev_priv))
1199                 intel_gpu_ips_init(dev_priv);
1200
1201         intel_audio_init(dev_priv);
1202
1203         /*
1204          * Some ports require correctly set-up hpd registers for detection to
1205          * work properly (leading to ghost connected connector status), e.g. VGA
1206          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1207          * irqs are fully enabled. We do it last so that the async config
1208          * cannot run before the connectors are registered.
1209          */
1210         intel_fbdev_initial_config_async(dev);
1211 }
1212
1213 /**
1214  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1215  * @dev_priv: device private
1216  */
1217 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1218 {
1219         intel_audio_deinit(dev_priv);
1220
1221         intel_gpu_ips_teardown();
1222         acpi_video_unregister();
1223         intel_opregion_unregister(dev_priv);
1224
1225         i915_perf_unregister(dev_priv);
1226
1227         i915_teardown_sysfs(dev_priv);
1228         i915_guc_log_unregister(dev_priv);
1229         drm_dev_unregister(&dev_priv->drm);
1230
1231         i915_gem_shrinker_cleanup(dev_priv);
1232 }
1233
1234 /**
1235  * i915_driver_load - setup chip and create an initial config
1236  * @pdev: PCI device
1237  * @ent: matching PCI ID entry
1238  *
1239  * The driver load routine has to do several things:
1240  *   - drive output discovery via intel_modeset_init()
1241  *   - initialize the memory manager
1242  *   - allocate initial config memory
1243  *   - setup the DRM framebuffer with the allocated memory
1244  */
1245 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1246 {
1247         const struct intel_device_info *match_info =
1248                 (struct intel_device_info *)ent->driver_data;
1249         struct drm_i915_private *dev_priv;
1250         int ret;
1251
1252         /* Enable nuclear pageflip on ILK+ */
1253         if (!i915.nuclear_pageflip && match_info->gen < 5)
1254                 driver.driver_features &= ~DRIVER_ATOMIC;
1255
1256         ret = -ENOMEM;
1257         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1258         if (dev_priv)
1259                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1260         if (ret) {
1261                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1262                 goto out_free;
1263         }
1264
1265         dev_priv->drm.pdev = pdev;
1266         dev_priv->drm.dev_private = dev_priv;
1267
1268         ret = pci_enable_device(pdev);
1269         if (ret)
1270                 goto out_fini;
1271
1272         pci_set_drvdata(pdev, &dev_priv->drm);
1273         /*
1274          * Disable the system suspend direct complete optimization, which can
1275          * leave the device suspended skipping the driver's suspend handlers
1276          * if the device was already runtime suspended. This is needed due to
1277          * the difference in our runtime and system suspend sequence and
1278          * becaue the HDA driver may require us to enable the audio power
1279          * domain during system suspend.
1280          */
1281         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1282
1283         ret = i915_driver_init_early(dev_priv, ent);
1284         if (ret < 0)
1285                 goto out_pci_disable;
1286
1287         intel_runtime_pm_get(dev_priv);
1288
1289         ret = i915_driver_init_mmio(dev_priv);
1290         if (ret < 0)
1291                 goto out_runtime_pm_put;
1292
1293         ret = i915_driver_init_hw(dev_priv);
1294         if (ret < 0)
1295                 goto out_cleanup_mmio;
1296
1297         /*
1298          * TODO: move the vblank init and parts of modeset init steps into one
1299          * of the i915_driver_init_/i915_driver_register functions according
1300          * to the role/effect of the given init step.
1301          */
1302         if (INTEL_INFO(dev_priv)->num_pipes) {
1303                 ret = drm_vblank_init(&dev_priv->drm,
1304                                       INTEL_INFO(dev_priv)->num_pipes);
1305                 if (ret)
1306                         goto out_cleanup_hw;
1307         }
1308
1309         ret = i915_load_modeset_init(&dev_priv->drm);
1310         if (ret < 0)
1311                 goto out_cleanup_vblank;
1312
1313         i915_driver_register(dev_priv);
1314
1315         intel_runtime_pm_enable(dev_priv);
1316
1317         dev_priv->ipc_enabled = false;
1318
1319         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1320                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1321         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1322                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1323
1324         intel_runtime_pm_put(dev_priv);
1325
1326         return 0;
1327
1328 out_cleanup_vblank:
1329         drm_vblank_cleanup(&dev_priv->drm);
1330 out_cleanup_hw:
1331         i915_driver_cleanup_hw(dev_priv);
1332 out_cleanup_mmio:
1333         i915_driver_cleanup_mmio(dev_priv);
1334 out_runtime_pm_put:
1335         intel_runtime_pm_put(dev_priv);
1336         i915_driver_cleanup_early(dev_priv);
1337 out_pci_disable:
1338         pci_disable_device(pdev);
1339 out_fini:
1340         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1341         drm_dev_fini(&dev_priv->drm);
1342 out_free:
1343         kfree(dev_priv);
1344         return ret;
1345 }
1346
1347 void i915_driver_unload(struct drm_device *dev)
1348 {
1349         struct drm_i915_private *dev_priv = to_i915(dev);
1350         struct pci_dev *pdev = dev_priv->drm.pdev;
1351
1352         intel_fbdev_fini(dev);
1353
1354         if (i915_gem_suspend(dev_priv))
1355                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1356
1357         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1358
1359         drm_atomic_helper_shutdown(dev);
1360
1361         intel_gvt_cleanup(dev_priv);
1362
1363         i915_driver_unregister(dev_priv);
1364
1365         drm_vblank_cleanup(dev);
1366
1367         intel_modeset_cleanup(dev);
1368
1369         /*
1370          * free the memory space allocated for the child device
1371          * config parsed from VBT
1372          */
1373         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1374                 kfree(dev_priv->vbt.child_dev);
1375                 dev_priv->vbt.child_dev = NULL;
1376                 dev_priv->vbt.child_dev_num = 0;
1377         }
1378         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1379         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1380         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1381         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1382
1383         vga_switcheroo_unregister_client(pdev);
1384         vga_client_register(pdev, NULL, NULL, NULL);
1385
1386         intel_csr_ucode_fini(dev_priv);
1387
1388         /* Free error state after interrupts are fully disabled. */
1389         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1390         i915_reset_error_state(dev_priv);
1391
1392         /* Flush any outstanding unpin_work. */
1393         drain_workqueue(dev_priv->wq);
1394
1395         i915_gem_fini(dev_priv);
1396         intel_uc_fini_fw(dev_priv);
1397         intel_fbc_cleanup_cfb(dev_priv);
1398
1399         intel_power_domains_fini(dev_priv);
1400
1401         i915_driver_cleanup_hw(dev_priv);
1402         i915_driver_cleanup_mmio(dev_priv);
1403
1404         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1405 }
1406
1407 static void i915_driver_release(struct drm_device *dev)
1408 {
1409         struct drm_i915_private *dev_priv = to_i915(dev);
1410
1411         i915_driver_cleanup_early(dev_priv);
1412         drm_dev_fini(&dev_priv->drm);
1413
1414         kfree(dev_priv);
1415 }
1416
1417 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1418 {
1419         int ret;
1420
1421         ret = i915_gem_open(dev, file);
1422         if (ret)
1423                 return ret;
1424
1425         return 0;
1426 }
1427
1428 /**
1429  * i915_driver_lastclose - clean up after all DRM clients have exited
1430  * @dev: DRM device
1431  *
1432  * Take care of cleaning up after all DRM clients have exited.  In the
1433  * mode setting case, we want to restore the kernel's initial mode (just
1434  * in case the last client left us in a bad state).
1435  *
1436  * Additionally, in the non-mode setting case, we'll tear down the GTT
1437  * and DMA structures, since the kernel won't be using them, and clea
1438  * up any GEM state.
1439  */
1440 static void i915_driver_lastclose(struct drm_device *dev)
1441 {
1442         intel_fbdev_restore_mode(dev);
1443         vga_switcheroo_process_delayed_switch();
1444 }
1445
1446 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1447 {
1448         struct drm_i915_file_private *file_priv = file->driver_priv;
1449
1450         mutex_lock(&dev->struct_mutex);
1451         i915_gem_context_close(dev, file);
1452         i915_gem_release(dev, file);
1453         mutex_unlock(&dev->struct_mutex);
1454
1455         kfree(file_priv);
1456 }
1457
1458 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1459 {
1460         struct drm_device *dev = &dev_priv->drm;
1461         struct intel_encoder *encoder;
1462
1463         drm_modeset_lock_all(dev);
1464         for_each_intel_encoder(dev, encoder)
1465                 if (encoder->suspend)
1466                         encoder->suspend(encoder);
1467         drm_modeset_unlock_all(dev);
1468 }
1469
1470 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1471                               bool rpm_resume);
1472 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1473
1474 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1475 {
1476 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1477         if (acpi_target_system_state() < ACPI_STATE_S3)
1478                 return true;
1479 #endif
1480         return false;
1481 }
1482
1483 static int i915_drm_suspend(struct drm_device *dev)
1484 {
1485         struct drm_i915_private *dev_priv = to_i915(dev);
1486         struct pci_dev *pdev = dev_priv->drm.pdev;
1487         pci_power_t opregion_target_state;
1488         int error;
1489
1490         /* ignore lid events during suspend */
1491         mutex_lock(&dev_priv->modeset_restore_lock);
1492         dev_priv->modeset_restore = MODESET_SUSPENDED;
1493         mutex_unlock(&dev_priv->modeset_restore_lock);
1494
1495         disable_rpm_wakeref_asserts(dev_priv);
1496
1497         /* We do a lot of poking in a lot of registers, make sure they work
1498          * properly. */
1499         intel_display_set_init_power(dev_priv, true);
1500
1501         drm_kms_helper_poll_disable(dev);
1502
1503         pci_save_state(pdev);
1504
1505         error = i915_gem_suspend(dev_priv);
1506         if (error) {
1507                 dev_err(&pdev->dev,
1508                         "GEM idle failed, resume might fail\n");
1509                 goto out;
1510         }
1511
1512         intel_display_suspend(dev);
1513
1514         intel_dp_mst_suspend(dev);
1515
1516         intel_runtime_pm_disable_interrupts(dev_priv);
1517         intel_hpd_cancel_work(dev_priv);
1518
1519         intel_suspend_encoders(dev_priv);
1520
1521         intel_suspend_hw(dev_priv);
1522
1523         i915_gem_suspend_gtt_mappings(dev_priv);
1524
1525         i915_save_state(dev_priv);
1526
1527         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1528         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1529
1530         intel_uncore_suspend(dev_priv);
1531         intel_opregion_unregister(dev_priv);
1532
1533         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1534
1535         dev_priv->suspend_count++;
1536
1537         intel_csr_ucode_suspend(dev_priv);
1538
1539 out:
1540         enable_rpm_wakeref_asserts(dev_priv);
1541
1542         return error;
1543 }
1544
1545 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1546 {
1547         struct drm_i915_private *dev_priv = to_i915(dev);
1548         struct pci_dev *pdev = dev_priv->drm.pdev;
1549         bool fw_csr;
1550         int ret;
1551
1552         disable_rpm_wakeref_asserts(dev_priv);
1553
1554         intel_display_set_init_power(dev_priv, false);
1555
1556         fw_csr = !IS_GEN9_LP(dev_priv) &&
1557                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1558         /*
1559          * In case of firmware assisted context save/restore don't manually
1560          * deinit the power domains. This also means the CSR/DMC firmware will
1561          * stay active, it will power down any HW resources as required and
1562          * also enable deeper system power states that would be blocked if the
1563          * firmware was inactive.
1564          */
1565         if (!fw_csr)
1566                 intel_power_domains_suspend(dev_priv);
1567
1568         ret = 0;
1569         if (IS_GEN9_LP(dev_priv))
1570                 bxt_enable_dc9(dev_priv);
1571         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1572                 hsw_enable_pc8(dev_priv);
1573         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1574                 ret = vlv_suspend_complete(dev_priv);
1575
1576         if (ret) {
1577                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1578                 if (!fw_csr)
1579                         intel_power_domains_init_hw(dev_priv, true);
1580
1581                 goto out;
1582         }
1583
1584         pci_disable_device(pdev);
1585         /*
1586          * During hibernation on some platforms the BIOS may try to access
1587          * the device even though it's already in D3 and hang the machine. So
1588          * leave the device in D0 on those platforms and hope the BIOS will
1589          * power down the device properly. The issue was seen on multiple old
1590          * GENs with different BIOS vendors, so having an explicit blacklist
1591          * is inpractical; apply the workaround on everything pre GEN6. The
1592          * platforms where the issue was seen:
1593          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1594          * Fujitsu FSC S7110
1595          * Acer Aspire 1830T
1596          */
1597         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1598                 pci_set_power_state(pdev, PCI_D3hot);
1599
1600         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1601
1602 out:
1603         enable_rpm_wakeref_asserts(dev_priv);
1604
1605         return ret;
1606 }
1607
1608 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1609 {
1610         int error;
1611
1612         if (!dev) {
1613                 DRM_ERROR("dev: %p\n", dev);
1614                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1615                 return -ENODEV;
1616         }
1617
1618         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1619                          state.event != PM_EVENT_FREEZE))
1620                 return -EINVAL;
1621
1622         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1623                 return 0;
1624
1625         error = i915_drm_suspend(dev);
1626         if (error)
1627                 return error;
1628
1629         return i915_drm_suspend_late(dev, false);
1630 }
1631
1632 static int i915_drm_resume(struct drm_device *dev)
1633 {
1634         struct drm_i915_private *dev_priv = to_i915(dev);
1635         int ret;
1636
1637         disable_rpm_wakeref_asserts(dev_priv);
1638         intel_sanitize_gt_powersave(dev_priv);
1639
1640         ret = i915_ggtt_enable_hw(dev_priv);
1641         if (ret)
1642                 DRM_ERROR("failed to re-enable GGTT\n");
1643
1644         intel_csr_ucode_resume(dev_priv);
1645
1646         i915_gem_resume(dev_priv);
1647
1648         i915_restore_state(dev_priv);
1649         intel_pps_unlock_regs_wa(dev_priv);
1650         intel_opregion_setup(dev_priv);
1651
1652         intel_init_pch_refclk(dev_priv);
1653
1654         /*
1655          * Interrupts have to be enabled before any batches are run. If not the
1656          * GPU will hang. i915_gem_init_hw() will initiate batches to
1657          * update/restore the context.
1658          *
1659          * drm_mode_config_reset() needs AUX interrupts.
1660          *
1661          * Modeset enabling in intel_modeset_init_hw() also needs working
1662          * interrupts.
1663          */
1664         intel_runtime_pm_enable_interrupts(dev_priv);
1665
1666         drm_mode_config_reset(dev);
1667
1668         mutex_lock(&dev->struct_mutex);
1669         if (i915_gem_init_hw(dev_priv)) {
1670                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1671                 i915_gem_set_wedged(dev_priv);
1672         }
1673         mutex_unlock(&dev->struct_mutex);
1674
1675         intel_guc_resume(dev_priv);
1676
1677         intel_modeset_init_hw(dev);
1678
1679         spin_lock_irq(&dev_priv->irq_lock);
1680         if (dev_priv->display.hpd_irq_setup)
1681                 dev_priv->display.hpd_irq_setup(dev_priv);
1682         spin_unlock_irq(&dev_priv->irq_lock);
1683
1684         intel_dp_mst_resume(dev);
1685
1686         intel_display_resume(dev);
1687
1688         drm_kms_helper_poll_enable(dev);
1689
1690         /*
1691          * ... but also need to make sure that hotplug processing
1692          * doesn't cause havoc. Like in the driver load code we don't
1693          * bother with the tiny race here where we might loose hotplug
1694          * notifications.
1695          * */
1696         intel_hpd_init(dev_priv);
1697
1698         intel_opregion_register(dev_priv);
1699
1700         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1701
1702         mutex_lock(&dev_priv->modeset_restore_lock);
1703         dev_priv->modeset_restore = MODESET_DONE;
1704         mutex_unlock(&dev_priv->modeset_restore_lock);
1705
1706         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1707
1708         intel_autoenable_gt_powersave(dev_priv);
1709
1710         enable_rpm_wakeref_asserts(dev_priv);
1711
1712         return 0;
1713 }
1714
1715 static int i915_drm_resume_early(struct drm_device *dev)
1716 {
1717         struct drm_i915_private *dev_priv = to_i915(dev);
1718         struct pci_dev *pdev = dev_priv->drm.pdev;
1719         int ret;
1720
1721         /*
1722          * We have a resume ordering issue with the snd-hda driver also
1723          * requiring our device to be power up. Due to the lack of a
1724          * parent/child relationship we currently solve this with an early
1725          * resume hook.
1726          *
1727          * FIXME: This should be solved with a special hdmi sink device or
1728          * similar so that power domains can be employed.
1729          */
1730
1731         /*
1732          * Note that we need to set the power state explicitly, since we
1733          * powered off the device during freeze and the PCI core won't power
1734          * it back up for us during thaw. Powering off the device during
1735          * freeze is not a hard requirement though, and during the
1736          * suspend/resume phases the PCI core makes sure we get here with the
1737          * device powered on. So in case we change our freeze logic and keep
1738          * the device powered we can also remove the following set power state
1739          * call.
1740          */
1741         ret = pci_set_power_state(pdev, PCI_D0);
1742         if (ret) {
1743                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1744                 goto out;
1745         }
1746
1747         /*
1748          * Note that pci_enable_device() first enables any parent bridge
1749          * device and only then sets the power state for this device. The
1750          * bridge enabling is a nop though, since bridge devices are resumed
1751          * first. The order of enabling power and enabling the device is
1752          * imposed by the PCI core as described above, so here we preserve the
1753          * same order for the freeze/thaw phases.
1754          *
1755          * TODO: eventually we should remove pci_disable_device() /
1756          * pci_enable_enable_device() from suspend/resume. Due to how they
1757          * depend on the device enable refcount we can't anyway depend on them
1758          * disabling/enabling the device.
1759          */
1760         if (pci_enable_device(pdev)) {
1761                 ret = -EIO;
1762                 goto out;
1763         }
1764
1765         pci_set_master(pdev);
1766
1767         disable_rpm_wakeref_asserts(dev_priv);
1768
1769         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1770                 ret = vlv_resume_prepare(dev_priv, false);
1771         if (ret)
1772                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1773                           ret);
1774
1775         intel_uncore_resume_early(dev_priv);
1776
1777         if (IS_GEN9_LP(dev_priv)) {
1778                 if (!dev_priv->suspended_to_idle)
1779                         gen9_sanitize_dc_state(dev_priv);
1780                 bxt_disable_dc9(dev_priv);
1781         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1782                 hsw_disable_pc8(dev_priv);
1783         }
1784
1785         intel_uncore_sanitize(dev_priv);
1786
1787         if (IS_GEN9_LP(dev_priv) ||
1788             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1789                 intel_power_domains_init_hw(dev_priv, true);
1790
1791         i915_gem_sanitize(dev_priv);
1792
1793         enable_rpm_wakeref_asserts(dev_priv);
1794
1795 out:
1796         dev_priv->suspended_to_idle = false;
1797
1798         return ret;
1799 }
1800
1801 static int i915_resume_switcheroo(struct drm_device *dev)
1802 {
1803         int ret;
1804
1805         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1806                 return 0;
1807
1808         ret = i915_drm_resume_early(dev);
1809         if (ret)
1810                 return ret;
1811
1812         return i915_drm_resume(dev);
1813 }
1814
1815 /**
1816  * i915_reset - reset chip after a hang
1817  * @dev_priv: device private to reset
1818  *
1819  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1820  * on failure.
1821  *
1822  * Caller must hold the struct_mutex.
1823  *
1824  * Procedure is fairly simple:
1825  *   - reset the chip using the reset reg
1826  *   - re-init context state
1827  *   - re-init hardware status page
1828  *   - re-init ring buffer
1829  *   - re-init interrupt state
1830  *   - re-init display
1831  */
1832 void i915_reset(struct drm_i915_private *dev_priv)
1833 {
1834         struct i915_gpu_error *error = &dev_priv->gpu_error;
1835         int ret;
1836
1837         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1838         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1839
1840         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1841                 return;
1842
1843         /* Clear any previous failed attempts at recovery. Time to try again. */
1844         if (!i915_gem_unset_wedged(dev_priv))
1845                 goto wakeup;
1846
1847         error->reset_count++;
1848
1849         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1850         disable_irq(dev_priv->drm.irq);
1851         ret = i915_gem_reset_prepare(dev_priv);
1852         if (ret) {
1853                 DRM_ERROR("GPU recovery failed\n");
1854                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1855                 goto error;
1856         }
1857
1858         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1859         if (ret) {
1860                 if (ret != -ENODEV)
1861                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1862                 else
1863                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1864                 goto error;
1865         }
1866
1867         i915_gem_reset(dev_priv);
1868         intel_overlay_reset(dev_priv);
1869
1870         /* Ok, now get things going again... */
1871
1872         /*
1873          * Everything depends on having the GTT running, so we need to start
1874          * there.  Fortunately we don't need to do this unless we reset the
1875          * chip at a PCI level.
1876          *
1877          * Next we need to restore the context, but we don't use those
1878          * yet either...
1879          *
1880          * Ring buffer needs to be re-initialized in the KMS case, or if X
1881          * was running at the time of the reset (i.e. we weren't VT
1882          * switched away).
1883          */
1884         ret = i915_gem_init_hw(dev_priv);
1885         if (ret) {
1886                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1887                 goto error;
1888         }
1889
1890         i915_queue_hangcheck(dev_priv);
1891
1892 finish:
1893         i915_gem_reset_finish(dev_priv);
1894         enable_irq(dev_priv->drm.irq);
1895
1896 wakeup:
1897         clear_bit(I915_RESET_HANDOFF, &error->flags);
1898         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1899         return;
1900
1901 error:
1902         i915_gem_set_wedged(dev_priv);
1903         goto finish;
1904 }
1905
1906 static int i915_pm_suspend(struct device *kdev)
1907 {
1908         struct pci_dev *pdev = to_pci_dev(kdev);
1909         struct drm_device *dev = pci_get_drvdata(pdev);
1910
1911         if (!dev) {
1912                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1913                 return -ENODEV;
1914         }
1915
1916         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1917                 return 0;
1918
1919         return i915_drm_suspend(dev);
1920 }
1921
1922 static int i915_pm_suspend_late(struct device *kdev)
1923 {
1924         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1925
1926         /*
1927          * We have a suspend ordering issue with the snd-hda driver also
1928          * requiring our device to be power up. Due to the lack of a
1929          * parent/child relationship we currently solve this with an late
1930          * suspend hook.
1931          *
1932          * FIXME: This should be solved with a special hdmi sink device or
1933          * similar so that power domains can be employed.
1934          */
1935         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1936                 return 0;
1937
1938         return i915_drm_suspend_late(dev, false);
1939 }
1940
1941 static int i915_pm_poweroff_late(struct device *kdev)
1942 {
1943         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1944
1945         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1946                 return 0;
1947
1948         return i915_drm_suspend_late(dev, true);
1949 }
1950
1951 static int i915_pm_resume_early(struct device *kdev)
1952 {
1953         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1954
1955         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1956                 return 0;
1957
1958         return i915_drm_resume_early(dev);
1959 }
1960
1961 static int i915_pm_resume(struct device *kdev)
1962 {
1963         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1964
1965         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1966                 return 0;
1967
1968         return i915_drm_resume(dev);
1969 }
1970
1971 /* freeze: before creating the hibernation_image */
1972 static int i915_pm_freeze(struct device *kdev)
1973 {
1974         int ret;
1975
1976         ret = i915_pm_suspend(kdev);
1977         if (ret)
1978                 return ret;
1979
1980         ret = i915_gem_freeze(kdev_to_i915(kdev));
1981         if (ret)
1982                 return ret;
1983
1984         return 0;
1985 }
1986
1987 static int i915_pm_freeze_late(struct device *kdev)
1988 {
1989         int ret;
1990
1991         ret = i915_pm_suspend_late(kdev);
1992         if (ret)
1993                 return ret;
1994
1995         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1996         if (ret)
1997                 return ret;
1998
1999         return 0;
2000 }
2001
2002 /* thaw: called after creating the hibernation image, but before turning off. */
2003 static int i915_pm_thaw_early(struct device *kdev)
2004 {
2005         return i915_pm_resume_early(kdev);
2006 }
2007
2008 static int i915_pm_thaw(struct device *kdev)
2009 {
2010         return i915_pm_resume(kdev);
2011 }
2012
2013 /* restore: called after loading the hibernation image. */
2014 static int i915_pm_restore_early(struct device *kdev)
2015 {
2016         return i915_pm_resume_early(kdev);
2017 }
2018
2019 static int i915_pm_restore(struct device *kdev)
2020 {
2021         return i915_pm_resume(kdev);
2022 }
2023
2024 /*
2025  * Save all Gunit registers that may be lost after a D3 and a subsequent
2026  * S0i[R123] transition. The list of registers needing a save/restore is
2027  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2028  * registers in the following way:
2029  * - Driver: saved/restored by the driver
2030  * - Punit : saved/restored by the Punit firmware
2031  * - No, w/o marking: no need to save/restore, since the register is R/O or
2032  *                    used internally by the HW in a way that doesn't depend
2033  *                    keeping the content across a suspend/resume.
2034  * - Debug : used for debugging
2035  *
2036  * We save/restore all registers marked with 'Driver', with the following
2037  * exceptions:
2038  * - Registers out of use, including also registers marked with 'Debug'.
2039  *   These have no effect on the driver's operation, so we don't save/restore
2040  *   them to reduce the overhead.
2041  * - Registers that are fully setup by an initialization function called from
2042  *   the resume path. For example many clock gating and RPS/RC6 registers.
2043  * - Registers that provide the right functionality with their reset defaults.
2044  *
2045  * TODO: Except for registers that based on the above 3 criteria can be safely
2046  * ignored, we save/restore all others, practically treating the HW context as
2047  * a black-box for the driver. Further investigation is needed to reduce the
2048  * saved/restored registers even further, by following the same 3 criteria.
2049  */
2050 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2051 {
2052         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2053         int i;
2054
2055         /* GAM 0x4000-0x4770 */
2056         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2057         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2058         s->arb_mode             = I915_READ(ARB_MODE);
2059         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2060         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2061
2062         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2063                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2064
2065         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2066         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2067
2068         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2069         s->ecochk               = I915_READ(GAM_ECOCHK);
2070         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2071         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2072
2073         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2074
2075         /* MBC 0x9024-0x91D0, 0x8500 */
2076         s->g3dctl               = I915_READ(VLV_G3DCTL);
2077         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2078         s->mbctl                = I915_READ(GEN6_MBCTL);
2079
2080         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2081         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2082         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2083         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2084         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2085         s->rstctl               = I915_READ(GEN6_RSTCTL);
2086         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2087
2088         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2089         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2090         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2091         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2092         s->ecobus               = I915_READ(ECOBUS);
2093         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2094         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2095         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2096         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2097         s->rcedata              = I915_READ(VLV_RCEDATA);
2098         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2099
2100         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2101         s->gt_imr               = I915_READ(GTIMR);
2102         s->gt_ier               = I915_READ(GTIER);
2103         s->pm_imr               = I915_READ(GEN6_PMIMR);
2104         s->pm_ier               = I915_READ(GEN6_PMIER);
2105
2106         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2107                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2108
2109         /* GT SA CZ domain, 0x100000-0x138124 */
2110         s->tilectl              = I915_READ(TILECTL);
2111         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2112         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2113         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2114         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2115
2116         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2117         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2118         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2119         s->pcbr                 = I915_READ(VLV_PCBR);
2120         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2121
2122         /*
2123          * Not saving any of:
2124          * DFT,         0x9800-0x9EC0
2125          * SARB,        0xB000-0xB1FC
2126          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2127          * PCI CFG
2128          */
2129 }
2130
2131 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2132 {
2133         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2134         u32 val;
2135         int i;
2136
2137         /* GAM 0x4000-0x4770 */
2138         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2139         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2140         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2141         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2142         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2143
2144         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2145                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2146
2147         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2148         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2149
2150         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2151         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2152         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2153         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2154
2155         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2156
2157         /* MBC 0x9024-0x91D0, 0x8500 */
2158         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2159         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2160         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2161
2162         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2163         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2164         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2165         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2166         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2167         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2168         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2169
2170         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2171         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2172         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2173         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2174         I915_WRITE(ECOBUS,              s->ecobus);
2175         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2176         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2177         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2178         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2179         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2180         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2181
2182         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2183         I915_WRITE(GTIMR,               s->gt_imr);
2184         I915_WRITE(GTIER,               s->gt_ier);
2185         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2186         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2187
2188         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2189                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2190
2191         /* GT SA CZ domain, 0x100000-0x138124 */
2192         I915_WRITE(TILECTL,                     s->tilectl);
2193         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2194         /*
2195          * Preserve the GT allow wake and GFX force clock bit, they are not
2196          * be restored, as they are used to control the s0ix suspend/resume
2197          * sequence by the caller.
2198          */
2199         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2200         val &= VLV_GTLC_ALLOWWAKEREQ;
2201         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2202         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2203
2204         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2205         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2206         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2207         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2208
2209         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2210
2211         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2212         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2213         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2214         I915_WRITE(VLV_PCBR,                    s->pcbr);
2215         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2216 }
2217
2218 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2219                                   u32 mask, u32 val)
2220 {
2221         /* The HW does not like us polling for PW_STATUS frequently, so
2222          * use the sleeping loop rather than risk the busy spin within
2223          * intel_wait_for_register().
2224          *
2225          * Transitioning between RC6 states should be at most 2ms (see
2226          * valleyview_enable_rps) so use a 3ms timeout.
2227          */
2228         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2229                         3);
2230 }
2231
2232 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2233 {
2234         u32 val;
2235         int err;
2236
2237         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2238         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2239         if (force_on)
2240                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2241         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2242
2243         if (!force_on)
2244                 return 0;
2245
2246         err = intel_wait_for_register(dev_priv,
2247                                       VLV_GTLC_SURVIVABILITY_REG,
2248                                       VLV_GFX_CLK_STATUS_BIT,
2249                                       VLV_GFX_CLK_STATUS_BIT,
2250                                       20);
2251         if (err)
2252                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2253                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2254
2255         return err;
2256 }
2257
2258 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2259 {
2260         u32 mask;
2261         u32 val;
2262         int err;
2263
2264         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2265         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2266         if (allow)
2267                 val |= VLV_GTLC_ALLOWWAKEREQ;
2268         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2269         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2270
2271         mask = VLV_GTLC_ALLOWWAKEACK;
2272         val = allow ? mask : 0;
2273
2274         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2275         if (err)
2276                 DRM_ERROR("timeout disabling GT waking\n");
2277
2278         return err;
2279 }
2280
2281 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2282                                   bool wait_for_on)
2283 {
2284         u32 mask;
2285         u32 val;
2286
2287         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2288         val = wait_for_on ? mask : 0;
2289
2290         /*
2291          * RC6 transitioning can be delayed up to 2 msec (see
2292          * valleyview_enable_rps), use 3 msec for safety.
2293          */
2294         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2295                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2296                           onoff(wait_for_on));
2297 }
2298
2299 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2300 {
2301         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2302                 return;
2303
2304         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2305         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2306 }
2307
2308 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2309 {
2310         u32 mask;
2311         int err;
2312
2313         /*
2314          * Bspec defines the following GT well on flags as debug only, so
2315          * don't treat them as hard failures.
2316          */
2317         vlv_wait_for_gt_wells(dev_priv, false);
2318
2319         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2320         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2321
2322         vlv_check_no_gt_access(dev_priv);
2323
2324         err = vlv_force_gfx_clock(dev_priv, true);
2325         if (err)
2326                 goto err1;
2327
2328         err = vlv_allow_gt_wake(dev_priv, false);
2329         if (err)
2330                 goto err2;
2331
2332         if (!IS_CHERRYVIEW(dev_priv))
2333                 vlv_save_gunit_s0ix_state(dev_priv);
2334
2335         err = vlv_force_gfx_clock(dev_priv, false);
2336         if (err)
2337                 goto err2;
2338
2339         return 0;
2340
2341 err2:
2342         /* For safety always re-enable waking and disable gfx clock forcing */
2343         vlv_allow_gt_wake(dev_priv, true);
2344 err1:
2345         vlv_force_gfx_clock(dev_priv, false);
2346
2347         return err;
2348 }
2349
2350 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2351                                 bool rpm_resume)
2352 {
2353         int err;
2354         int ret;
2355
2356         /*
2357          * If any of the steps fail just try to continue, that's the best we
2358          * can do at this point. Return the first error code (which will also
2359          * leave RPM permanently disabled).
2360          */
2361         ret = vlv_force_gfx_clock(dev_priv, true);
2362
2363         if (!IS_CHERRYVIEW(dev_priv))
2364                 vlv_restore_gunit_s0ix_state(dev_priv);
2365
2366         err = vlv_allow_gt_wake(dev_priv, true);
2367         if (!ret)
2368                 ret = err;
2369
2370         err = vlv_force_gfx_clock(dev_priv, false);
2371         if (!ret)
2372                 ret = err;
2373
2374         vlv_check_no_gt_access(dev_priv);
2375
2376         if (rpm_resume)
2377                 intel_init_clock_gating(dev_priv);
2378
2379         return ret;
2380 }
2381
2382 static int intel_runtime_suspend(struct device *kdev)
2383 {
2384         struct pci_dev *pdev = to_pci_dev(kdev);
2385         struct drm_device *dev = pci_get_drvdata(pdev);
2386         struct drm_i915_private *dev_priv = to_i915(dev);
2387         int ret;
2388
2389         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2390                 return -ENODEV;
2391
2392         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2393                 return -ENODEV;
2394
2395         DRM_DEBUG_KMS("Suspending device\n");
2396
2397         disable_rpm_wakeref_asserts(dev_priv);
2398
2399         /*
2400          * We are safe here against re-faults, since the fault handler takes
2401          * an RPM reference.
2402          */
2403         i915_gem_runtime_suspend(dev_priv);
2404
2405         intel_guc_suspend(dev_priv);
2406
2407         intel_runtime_pm_disable_interrupts(dev_priv);
2408
2409         ret = 0;
2410         if (IS_GEN9_LP(dev_priv)) {
2411                 bxt_display_core_uninit(dev_priv);
2412                 bxt_enable_dc9(dev_priv);
2413         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2414                 hsw_enable_pc8(dev_priv);
2415         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2416                 ret = vlv_suspend_complete(dev_priv);
2417         }
2418
2419         if (ret) {
2420                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2421                 intel_runtime_pm_enable_interrupts(dev_priv);
2422
2423                 enable_rpm_wakeref_asserts(dev_priv);
2424
2425                 return ret;
2426         }
2427
2428         intel_uncore_suspend(dev_priv);
2429
2430         enable_rpm_wakeref_asserts(dev_priv);
2431         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2432
2433         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2434                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2435
2436         dev_priv->pm.suspended = true;
2437
2438         /*
2439          * FIXME: We really should find a document that references the arguments
2440          * used below!
2441          */
2442         if (IS_BROADWELL(dev_priv)) {
2443                 /*
2444                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2445                  * being detected, and the call we do at intel_runtime_resume()
2446                  * won't be able to restore them. Since PCI_D3hot matches the
2447                  * actual specification and appears to be working, use it.
2448                  */
2449                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2450         } else {
2451                 /*
2452                  * current versions of firmware which depend on this opregion
2453                  * notification have repurposed the D1 definition to mean
2454                  * "runtime suspended" vs. what you would normally expect (D3)
2455                  * to distinguish it from notifications that might be sent via
2456                  * the suspend path.
2457                  */
2458                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2459         }
2460
2461         assert_forcewakes_inactive(dev_priv);
2462
2463         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2464                 intel_hpd_poll_init(dev_priv);
2465
2466         DRM_DEBUG_KMS("Device suspended\n");
2467         return 0;
2468 }
2469
2470 static int intel_runtime_resume(struct device *kdev)
2471 {
2472         struct pci_dev *pdev = to_pci_dev(kdev);
2473         struct drm_device *dev = pci_get_drvdata(pdev);
2474         struct drm_i915_private *dev_priv = to_i915(dev);
2475         int ret = 0;
2476
2477         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2478                 return -ENODEV;
2479
2480         DRM_DEBUG_KMS("Resuming device\n");
2481
2482         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2483         disable_rpm_wakeref_asserts(dev_priv);
2484
2485         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2486         dev_priv->pm.suspended = false;
2487         if (intel_uncore_unclaimed_mmio(dev_priv))
2488                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2489
2490         intel_guc_resume(dev_priv);
2491
2492         if (IS_GEN9_LP(dev_priv)) {
2493                 bxt_disable_dc9(dev_priv);
2494                 bxt_display_core_init(dev_priv, true);
2495                 if (dev_priv->csr.dmc_payload &&
2496                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2497                         gen9_enable_dc5(dev_priv);
2498         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2499                 hsw_disable_pc8(dev_priv);
2500         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2501                 ret = vlv_resume_prepare(dev_priv, true);
2502         }
2503
2504         /*
2505          * No point of rolling back things in case of an error, as the best
2506          * we can do is to hope that things will still work (and disable RPM).
2507          */
2508         i915_gem_init_swizzling(dev_priv);
2509         i915_gem_restore_fences(dev_priv);
2510
2511         intel_runtime_pm_enable_interrupts(dev_priv);
2512
2513         /*
2514          * On VLV/CHV display interrupts are part of the display
2515          * power well, so hpd is reinitialized from there. For
2516          * everyone else do it here.
2517          */
2518         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2519                 intel_hpd_init(dev_priv);
2520
2521         enable_rpm_wakeref_asserts(dev_priv);
2522
2523         if (ret)
2524                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2525         else
2526                 DRM_DEBUG_KMS("Device resumed\n");
2527
2528         return ret;
2529 }
2530
2531 const struct dev_pm_ops i915_pm_ops = {
2532         /*
2533          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2534          * PMSG_RESUME]
2535          */
2536         .suspend = i915_pm_suspend,
2537         .suspend_late = i915_pm_suspend_late,
2538         .resume_early = i915_pm_resume_early,
2539         .resume = i915_pm_resume,
2540
2541         /*
2542          * S4 event handlers
2543          * @freeze, @freeze_late    : called (1) before creating the
2544          *                            hibernation image [PMSG_FREEZE] and
2545          *                            (2) after rebooting, before restoring
2546          *                            the image [PMSG_QUIESCE]
2547          * @thaw, @thaw_early       : called (1) after creating the hibernation
2548          *                            image, before writing it [PMSG_THAW]
2549          *                            and (2) after failing to create or
2550          *                            restore the image [PMSG_RECOVER]
2551          * @poweroff, @poweroff_late: called after writing the hibernation
2552          *                            image, before rebooting [PMSG_HIBERNATE]
2553          * @restore, @restore_early : called after rebooting and restoring the
2554          *                            hibernation image [PMSG_RESTORE]
2555          */
2556         .freeze = i915_pm_freeze,
2557         .freeze_late = i915_pm_freeze_late,
2558         .thaw_early = i915_pm_thaw_early,
2559         .thaw = i915_pm_thaw,
2560         .poweroff = i915_pm_suspend,
2561         .poweroff_late = i915_pm_poweroff_late,
2562         .restore_early = i915_pm_restore_early,
2563         .restore = i915_pm_restore,
2564
2565         /* S0ix (via runtime suspend) event handlers */
2566         .runtime_suspend = intel_runtime_suspend,
2567         .runtime_resume = intel_runtime_resume,
2568 };
2569
2570 static const struct vm_operations_struct i915_gem_vm_ops = {
2571         .fault = i915_gem_fault,
2572         .open = drm_gem_vm_open,
2573         .close = drm_gem_vm_close,
2574 };
2575
2576 static const struct file_operations i915_driver_fops = {
2577         .owner = THIS_MODULE,
2578         .open = drm_open,
2579         .release = drm_release,
2580         .unlocked_ioctl = drm_ioctl,
2581         .mmap = drm_gem_mmap,
2582         .poll = drm_poll,
2583         .read = drm_read,
2584         .compat_ioctl = i915_compat_ioctl,
2585         .llseek = noop_llseek,
2586 };
2587
2588 static int
2589 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2590                           struct drm_file *file)
2591 {
2592         return -ENODEV;
2593 }
2594
2595 static const struct drm_ioctl_desc i915_ioctls[] = {
2596         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2597         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2598         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2599         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2600         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2601         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2602         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2603         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2604         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2605         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2606         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2607         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2608         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2609         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2610         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2611         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2612         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2613         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2614         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2615         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2616         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2617         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2618         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2619         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2620         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2621         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2622         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2623         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2624         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2625         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2626         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2627         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2628         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2629         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2630         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2631         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2632         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2633         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2634         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2635         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2636         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2637         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2638         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2639         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2640         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2641         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2642         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2643         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2644         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2645         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2646         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2647         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2648         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2649 };
2650
2651 static struct drm_driver driver = {
2652         /* Don't use MTRRs here; the Xserver or userspace app should
2653          * deal with them for Intel hardware.
2654          */
2655         .driver_features =
2656             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2657             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2658         .release = i915_driver_release,
2659         .open = i915_driver_open,
2660         .lastclose = i915_driver_lastclose,
2661         .postclose = i915_driver_postclose,
2662         .set_busid = drm_pci_set_busid,
2663
2664         .gem_close_object = i915_gem_close_object,
2665         .gem_free_object_unlocked = i915_gem_free_object,
2666         .gem_vm_ops = &i915_gem_vm_ops,
2667
2668         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2669         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2670         .gem_prime_export = i915_gem_prime_export,
2671         .gem_prime_import = i915_gem_prime_import,
2672
2673         .dumb_create = i915_gem_dumb_create,
2674         .dumb_map_offset = i915_gem_mmap_gtt,
2675         .dumb_destroy = drm_gem_dumb_destroy,
2676         .ioctls = i915_ioctls,
2677         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2678         .fops = &i915_driver_fops,
2679         .name = DRIVER_NAME,
2680         .desc = DRIVER_DESC,
2681         .date = DRIVER_DATE,
2682         .major = DRIVER_MAJOR,
2683         .minor = DRIVER_MINOR,
2684         .patchlevel = DRIVER_PATCHLEVEL,
2685 };
2686
2687 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2688 #include "selftests/mock_drm.c"
2689 #endif