1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
41 #include <acpi/video.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_irq.h>
46 #include <drm/drm_probe_helper.h>
47 #include <drm/i915_drm.h>
49 #include "display/intel_acpi.h"
50 #include "display/intel_audio.h"
51 #include "display/intel_bw.h"
52 #include "display/intel_cdclk.h"
53 #include "display/intel_display_types.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_fbdev.h"
56 #include "display/intel_hotplug.h"
57 #include "display/intel_overlay.h"
58 #include "display/intel_pipe_crc.h"
59 #include "display/intel_sprite.h"
60 #include "display/intel_vga.h"
62 #include "gem/i915_gem_context.h"
63 #include "gem/i915_gem_ioctls.h"
64 #include "gem/i915_gem_mman.h"
65 #include "gt/intel_gt.h"
66 #include "gt/intel_gt_pm.h"
67 #include "gt/intel_rc6.h"
69 #include "i915_debugfs.h"
72 #include "i915_memcpy.h"
73 #include "i915_perf.h"
74 #include "i915_query.h"
75 #include "i915_suspend.h"
76 #include "i915_switcheroo.h"
77 #include "i915_sysfs.h"
78 #include "i915_trace.h"
79 #include "i915_vgpu.h"
80 #include "intel_csr.h"
81 #include "intel_memory_region.h"
84 static struct drm_driver driver;
86 struct vlv_s0ix_state {
93 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
94 u32 media_max_req_count;
95 u32 gfx_max_req_count;
127 /* Display 1 CZ domain */
132 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
134 /* GT SA CZ domain */
141 /* Display 2 CZ domain */
148 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
150 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
152 dev_priv->bridge_dev =
153 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
154 if (!dev_priv->bridge_dev) {
155 DRM_ERROR("bridge device not found\n");
161 /* Allocate space for the MCH regs if needed, return nonzero on error */
163 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
165 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
166 u32 temp_lo, temp_hi = 0;
170 if (INTEL_GEN(dev_priv) >= 4)
171 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
172 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
173 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
175 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
178 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
182 /* Get some space for it */
183 dev_priv->mch_res.name = "i915 MCHBAR";
184 dev_priv->mch_res.flags = IORESOURCE_MEM;
185 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
187 MCHBAR_SIZE, MCHBAR_SIZE,
189 0, pcibios_align_resource,
190 dev_priv->bridge_dev);
192 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
193 dev_priv->mch_res.start = 0;
197 if (INTEL_GEN(dev_priv) >= 4)
198 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
199 upper_32_bits(dev_priv->mch_res.start));
201 pci_write_config_dword(dev_priv->bridge_dev, reg,
202 lower_32_bits(dev_priv->mch_res.start));
206 /* Setup MCHBAR if possible, return true if we should disable it again */
208 intel_setup_mchbar(struct drm_i915_private *dev_priv)
210 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
214 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
217 dev_priv->mchbar_need_disable = false;
219 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
220 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
221 enabled = !!(temp & DEVEN_MCHBAR_EN);
223 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
227 /* If it's already enabled, don't have to do anything */
231 if (intel_alloc_mchbar_resource(dev_priv))
234 dev_priv->mchbar_need_disable = true;
236 /* Space is allocated or reserved, so enable it. */
237 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
238 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
239 temp | DEVEN_MCHBAR_EN);
241 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
242 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
247 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
249 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
251 if (dev_priv->mchbar_need_disable) {
252 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
255 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
257 deven_val &= ~DEVEN_MCHBAR_EN;
258 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
263 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
266 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
271 if (dev_priv->mch_res.start)
272 release_resource(&dev_priv->mch_res);
275 static int i915_driver_modeset_probe(struct drm_i915_private *i915)
279 if (i915_inject_probe_failure(i915))
282 if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
283 ret = drm_vblank_init(&i915->drm,
284 INTEL_NUM_PIPES(i915));
289 intel_bios_init(i915);
291 ret = intel_vga_register(i915);
295 intel_register_dsm_handler();
297 ret = i915_switcheroo_register(i915);
299 goto cleanup_vga_client;
301 intel_power_domains_init_hw(i915, false);
303 intel_csr_ucode_init(i915);
305 ret = intel_irq_install(i915);
309 /* Important: The output setup functions called by modeset_init need
310 * working irqs for e.g. gmbus and dp aux transfers. */
311 ret = intel_modeset_init(i915);
315 ret = i915_gem_init(i915);
317 goto cleanup_modeset;
319 intel_overlay_setup(i915);
321 if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
324 ret = intel_fbdev_init(&i915->drm);
328 /* Only enable hotplug handling once the fbdev is fully set up. */
329 intel_hpd_init(i915);
331 intel_init_ipc(i915);
336 i915_gem_suspend(i915);
337 i915_gem_driver_remove(i915);
338 i915_gem_driver_release(i915);
340 intel_modeset_driver_remove(i915);
342 intel_irq_uninstall(i915);
344 intel_csr_ucode_fini(i915);
345 intel_power_domains_driver_remove(i915);
346 i915_switcheroo_unregister(i915);
348 intel_vga_unregister(i915);
353 static void i915_driver_modeset_remove(struct drm_i915_private *i915)
355 intel_modeset_driver_remove(i915);
357 intel_irq_uninstall(i915);
359 intel_bios_driver_remove(i915);
361 i915_switcheroo_unregister(i915);
363 intel_vga_unregister(i915);
365 intel_csr_ucode_fini(i915);
368 static void intel_init_dpio(struct drm_i915_private *dev_priv)
371 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
372 * CHV x1 PHY (DP/HDMI D)
373 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
375 if (IS_CHERRYVIEW(dev_priv)) {
376 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
377 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
378 } else if (IS_VALLEYVIEW(dev_priv)) {
379 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
383 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
386 * The i915 workqueue is primarily used for batched retirement of
387 * requests (and thus managing bo) once the task has been completed
388 * by the GPU. i915_retire_requests() is called directly when we
389 * need high-priority retirement, such as waiting for an explicit
392 * It is also used for periodic low-priority events, such as
393 * idle-timers and recording error state.
395 * All tasks on the workqueue are expected to acquire the dev mutex
396 * so there is no point in running more than one instance of the
397 * workqueue at any time. Use an ordered one.
399 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
400 if (dev_priv->wq == NULL)
403 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
404 if (dev_priv->hotplug.dp_wq == NULL)
410 destroy_workqueue(dev_priv->wq);
412 DRM_ERROR("Failed to allocate workqueues.\n");
417 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
419 destroy_workqueue(dev_priv->hotplug.dp_wq);
420 destroy_workqueue(dev_priv->wq);
424 * We don't keep the workarounds for pre-production hardware, so we expect our
425 * driver to fail on these machines in one way or another. A little warning on
426 * dmesg may help both the user and the bug triagers.
428 * Our policy for removing pre-production workarounds is to keep the
429 * current gen workarounds as a guide to the bring-up of the next gen
430 * (workarounds have a habit of persisting!). Anything older than that
431 * should be removed along with the complications they introduce.
433 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
437 pre |= IS_HSW_EARLY_SDV(dev_priv);
438 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
439 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
440 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
443 DRM_ERROR("This is a pre-production stepping. "
444 "It may not be fully functional.\n");
445 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
449 static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
451 if (!IS_VALLEYVIEW(i915))
454 /* we write all the values in the struct, so no need to zero it out */
455 i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
457 if (!i915->vlv_s0ix_state)
463 static void vlv_free_s0ix_state(struct drm_i915_private *i915)
465 if (!i915->vlv_s0ix_state)
468 kfree(i915->vlv_s0ix_state);
469 i915->vlv_s0ix_state = NULL;
472 static void sanitize_gpu(struct drm_i915_private *i915)
474 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
475 __intel_gt_reset(&i915->gt, ALL_ENGINES);
479 * i915_driver_early_probe - setup state not requiring device access
480 * @dev_priv: device private
482 * Initialize everything that is a "SW-only" state, that is state not
483 * requiring accessing the device or exposing the driver via kernel internal
484 * or userspace interfaces. Example steps belonging here: lock initialization,
485 * system memory allocation, setting up device specific attributes and
486 * function hooks not requiring accessing the device.
488 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
492 if (i915_inject_probe_failure(dev_priv))
495 intel_device_info_subplatform_init(dev_priv);
497 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
498 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
500 spin_lock_init(&dev_priv->irq_lock);
501 spin_lock_init(&dev_priv->gpu_error.lock);
502 mutex_init(&dev_priv->backlight_lock);
504 mutex_init(&dev_priv->sb_lock);
505 pm_qos_add_request(&dev_priv->sb_qos,
506 PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
508 mutex_init(&dev_priv->av_mutex);
509 mutex_init(&dev_priv->wm.wm_mutex);
510 mutex_init(&dev_priv->pps_mutex);
511 mutex_init(&dev_priv->hdcp_comp_mutex);
513 i915_memcpy_init_early(dev_priv);
514 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
516 ret = i915_workqueues_init(dev_priv);
520 ret = vlv_alloc_s0ix_state(dev_priv);
524 intel_wopcm_init_early(&dev_priv->wopcm);
526 intel_gt_init_early(&dev_priv->gt, dev_priv);
528 i915_gem_init_early(dev_priv);
530 /* This must be called before any calls to HAS_PCH_* */
531 intel_detect_pch(dev_priv);
533 intel_pm_setup(dev_priv);
534 intel_init_dpio(dev_priv);
535 ret = intel_power_domains_init(dev_priv);
538 intel_irq_init(dev_priv);
539 intel_init_display_hooks(dev_priv);
540 intel_init_clock_gating_hooks(dev_priv);
541 intel_init_audio_hooks(dev_priv);
542 intel_display_crc_init(dev_priv);
544 intel_detect_preproduction_hw(dev_priv);
549 i915_gem_cleanup_early(dev_priv);
550 intel_gt_driver_late_release(&dev_priv->gt);
551 vlv_free_s0ix_state(dev_priv);
553 i915_workqueues_cleanup(dev_priv);
558 * i915_driver_late_release - cleanup the setup done in
559 * i915_driver_early_probe()
560 * @dev_priv: device private
562 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
564 intel_irq_fini(dev_priv);
565 intel_power_domains_cleanup(dev_priv);
566 i915_gem_cleanup_early(dev_priv);
567 intel_gt_driver_late_release(&dev_priv->gt);
568 vlv_free_s0ix_state(dev_priv);
569 i915_workqueues_cleanup(dev_priv);
571 pm_qos_remove_request(&dev_priv->sb_qos);
572 mutex_destroy(&dev_priv->sb_lock);
576 * i915_driver_mmio_probe - setup device MMIO
577 * @dev_priv: device private
579 * Setup minimal device state necessary for MMIO accesses later in the
580 * initialization sequence. The setup here should avoid any other device-wide
581 * side effects or exposing the driver via kernel internal or user space
584 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
588 if (i915_inject_probe_failure(dev_priv))
591 if (i915_get_bridge_dev(dev_priv))
594 ret = intel_uncore_init_mmio(&dev_priv->uncore);
598 /* Try to make sure MCHBAR is enabled before poking at it */
599 intel_setup_mchbar(dev_priv);
601 intel_device_info_init_mmio(dev_priv);
603 intel_uncore_prune_mmio_domains(&dev_priv->uncore);
605 intel_uc_init_mmio(&dev_priv->gt.uc);
607 ret = intel_engines_init_mmio(&dev_priv->gt);
611 /* As early as possible, scrub existing GPU state before clobbering */
612 sanitize_gpu(dev_priv);
617 intel_teardown_mchbar(dev_priv);
618 intel_uncore_fini_mmio(&dev_priv->uncore);
620 pci_dev_put(dev_priv->bridge_dev);
626 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
627 * @dev_priv: device private
629 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
631 intel_teardown_mchbar(dev_priv);
632 intel_uncore_fini_mmio(&dev_priv->uncore);
633 pci_dev_put(dev_priv->bridge_dev);
636 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
638 intel_gvt_sanitize_options(dev_priv);
641 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
643 static const char *intel_dram_type_str(enum intel_dram_type type)
645 static const char * const str[] = {
646 DRAM_TYPE_STR(UNKNOWN),
649 DRAM_TYPE_STR(LPDDR3),
650 DRAM_TYPE_STR(LPDDR4),
653 if (type >= ARRAY_SIZE(str))
654 type = INTEL_DRAM_UNKNOWN;
661 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
663 return dimm->ranks * 64 / (dimm->width ?: 1);
666 /* Returns total GB for the whole DIMM */
667 static int skl_get_dimm_size(u16 val)
669 return val & SKL_DRAM_SIZE_MASK;
672 static int skl_get_dimm_width(u16 val)
674 if (skl_get_dimm_size(val) == 0)
677 switch (val & SKL_DRAM_WIDTH_MASK) {
678 case SKL_DRAM_WIDTH_X8:
679 case SKL_DRAM_WIDTH_X16:
680 case SKL_DRAM_WIDTH_X32:
681 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
689 static int skl_get_dimm_ranks(u16 val)
691 if (skl_get_dimm_size(val) == 0)
694 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
699 /* Returns total GB for the whole DIMM */
700 static int cnl_get_dimm_size(u16 val)
702 return (val & CNL_DRAM_SIZE_MASK) / 2;
705 static int cnl_get_dimm_width(u16 val)
707 if (cnl_get_dimm_size(val) == 0)
710 switch (val & CNL_DRAM_WIDTH_MASK) {
711 case CNL_DRAM_WIDTH_X8:
712 case CNL_DRAM_WIDTH_X16:
713 case CNL_DRAM_WIDTH_X32:
714 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
722 static int cnl_get_dimm_ranks(u16 val)
724 if (cnl_get_dimm_size(val) == 0)
727 val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
733 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
735 /* Convert total GB to Gb per DRAM device */
736 return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
740 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
741 struct dram_dimm_info *dimm,
742 int channel, char dimm_name, u16 val)
744 if (INTEL_GEN(dev_priv) >= 10) {
745 dimm->size = cnl_get_dimm_size(val);
746 dimm->width = cnl_get_dimm_width(val);
747 dimm->ranks = cnl_get_dimm_ranks(val);
749 dimm->size = skl_get_dimm_size(val);
750 dimm->width = skl_get_dimm_width(val);
751 dimm->ranks = skl_get_dimm_ranks(val);
754 DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
755 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
756 yesno(skl_is_16gb_dimm(dimm)));
760 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
761 struct dram_channel_info *ch,
762 int channel, u32 val)
764 skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
765 channel, 'L', val & 0xffff);
766 skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
767 channel, 'S', val >> 16);
769 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
770 DRM_DEBUG_KMS("CH%u not populated\n", channel);
774 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
776 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
782 skl_is_16gb_dimm(&ch->dimm_l) ||
783 skl_is_16gb_dimm(&ch->dimm_s);
785 DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
786 channel, ch->ranks, yesno(ch->is_16gb_dimm));
792 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
793 const struct dram_channel_info *ch1)
795 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
796 (ch0->dimm_s.size == 0 ||
797 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
801 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
803 struct dram_info *dram_info = &dev_priv->dram_info;
804 struct dram_channel_info ch0 = {}, ch1 = {};
808 val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
809 ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
811 dram_info->num_channels++;
813 val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
814 ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
816 dram_info->num_channels++;
818 if (dram_info->num_channels == 0) {
819 DRM_INFO("Number of memory channels is zero\n");
824 * If any of the channel is single rank channel, worst case output
825 * will be same as if single rank memory, so consider single rank
828 if (ch0.ranks == 1 || ch1.ranks == 1)
829 dram_info->ranks = 1;
831 dram_info->ranks = max(ch0.ranks, ch1.ranks);
833 if (dram_info->ranks == 0) {
834 DRM_INFO("couldn't get memory rank information\n");
838 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
840 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
842 DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
843 yesno(dram_info->symmetric_memory));
847 static enum intel_dram_type
848 skl_get_dram_type(struct drm_i915_private *dev_priv)
852 val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
854 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
855 case SKL_DRAM_DDR_TYPE_DDR3:
856 return INTEL_DRAM_DDR3;
857 case SKL_DRAM_DDR_TYPE_DDR4:
858 return INTEL_DRAM_DDR4;
859 case SKL_DRAM_DDR_TYPE_LPDDR3:
860 return INTEL_DRAM_LPDDR3;
861 case SKL_DRAM_DDR_TYPE_LPDDR4:
862 return INTEL_DRAM_LPDDR4;
865 return INTEL_DRAM_UNKNOWN;
870 skl_get_dram_info(struct drm_i915_private *dev_priv)
872 struct dram_info *dram_info = &dev_priv->dram_info;
873 u32 mem_freq_khz, val;
876 dram_info->type = skl_get_dram_type(dev_priv);
877 DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
879 ret = skl_dram_get_channels_info(dev_priv);
883 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
884 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
885 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
887 dram_info->bandwidth_kbps = dram_info->num_channels *
890 if (dram_info->bandwidth_kbps == 0) {
891 DRM_INFO("Couldn't get system memory bandwidth\n");
895 dram_info->valid = true;
899 /* Returns Gb per DRAM device */
900 static int bxt_get_dimm_size(u32 val)
902 switch (val & BXT_DRAM_SIZE_MASK) {
903 case BXT_DRAM_SIZE_4GBIT:
905 case BXT_DRAM_SIZE_6GBIT:
907 case BXT_DRAM_SIZE_8GBIT:
909 case BXT_DRAM_SIZE_12GBIT:
911 case BXT_DRAM_SIZE_16GBIT:
919 static int bxt_get_dimm_width(u32 val)
921 if (!bxt_get_dimm_size(val))
924 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
929 static int bxt_get_dimm_ranks(u32 val)
931 if (!bxt_get_dimm_size(val))
934 switch (val & BXT_DRAM_RANK_MASK) {
935 case BXT_DRAM_RANK_SINGLE:
937 case BXT_DRAM_RANK_DUAL:
945 static enum intel_dram_type bxt_get_dimm_type(u32 val)
947 if (!bxt_get_dimm_size(val))
948 return INTEL_DRAM_UNKNOWN;
950 switch (val & BXT_DRAM_TYPE_MASK) {
951 case BXT_DRAM_TYPE_DDR3:
952 return INTEL_DRAM_DDR3;
953 case BXT_DRAM_TYPE_LPDDR3:
954 return INTEL_DRAM_LPDDR3;
955 case BXT_DRAM_TYPE_DDR4:
956 return INTEL_DRAM_DDR4;
957 case BXT_DRAM_TYPE_LPDDR4:
958 return INTEL_DRAM_LPDDR4;
961 return INTEL_DRAM_UNKNOWN;
965 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
968 dimm->width = bxt_get_dimm_width(val);
969 dimm->ranks = bxt_get_dimm_ranks(val);
972 * Size in register is Gb per DRAM device. Convert to total
973 * GB to match the way we report this for non-LP platforms.
975 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
979 bxt_get_dram_info(struct drm_i915_private *dev_priv)
981 struct dram_info *dram_info = &dev_priv->dram_info;
983 u32 mem_freq_khz, val;
984 u8 num_active_channels;
987 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
988 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
989 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
991 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
992 num_active_channels = hweight32(dram_channels);
994 /* Each active bit represents 4-byte channel */
995 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
997 if (dram_info->bandwidth_kbps == 0) {
998 DRM_INFO("Couldn't get system memory bandwidth\n");
1003 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1005 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1006 struct dram_dimm_info dimm;
1007 enum intel_dram_type type;
1009 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1010 if (val == 0xFFFFFFFF)
1013 dram_info->num_channels++;
1015 bxt_get_dimm_info(&dimm, val);
1016 type = bxt_get_dimm_type(val);
1018 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1019 dram_info->type != INTEL_DRAM_UNKNOWN &&
1020 dram_info->type != type);
1022 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1023 i - BXT_D_CR_DRP0_DUNIT_START,
1024 dimm.size, dimm.width, dimm.ranks,
1025 intel_dram_type_str(type));
1028 * If any of the channel is single rank channel,
1029 * worst case output will be same as if single rank
1030 * memory, so consider single rank memory.
1032 if (dram_info->ranks == 0)
1033 dram_info->ranks = dimm.ranks;
1034 else if (dimm.ranks == 1)
1035 dram_info->ranks = 1;
1037 if (type != INTEL_DRAM_UNKNOWN)
1038 dram_info->type = type;
1041 if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1042 dram_info->ranks == 0) {
1043 DRM_INFO("couldn't get memory information\n");
1047 dram_info->valid = true;
1052 intel_get_dram_info(struct drm_i915_private *dev_priv)
1054 struct dram_info *dram_info = &dev_priv->dram_info;
1058 * Assume 16Gb DIMMs are present until proven otherwise.
1059 * This is only used for the level 0 watermark latency
1060 * w/a which does not apply to bxt/glk.
1062 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1064 if (INTEL_GEN(dev_priv) < 9 || !HAS_DISPLAY(dev_priv))
1067 if (IS_GEN9_LP(dev_priv))
1068 ret = bxt_get_dram_info(dev_priv);
1070 ret = skl_get_dram_info(dev_priv);
1074 DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1075 dram_info->bandwidth_kbps,
1076 dram_info->num_channels);
1078 DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1079 dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1082 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1084 static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1085 static const u8 sets[4] = { 1, 1, 2, 2 };
1087 return EDRAM_NUM_BANKS(cap) *
1088 ways[EDRAM_WAYS_IDX(cap)] *
1089 sets[EDRAM_SETS_IDX(cap)];
1092 static void edram_detect(struct drm_i915_private *dev_priv)
1096 if (!(IS_HASWELL(dev_priv) ||
1097 IS_BROADWELL(dev_priv) ||
1098 INTEL_GEN(dev_priv) >= 9))
1101 edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1103 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1105 if (!(edram_cap & EDRAM_ENABLED))
1109 * The needed capability bits for size calculation are not there with
1110 * pre gen9 so return 128MB always.
1112 if (INTEL_GEN(dev_priv) < 9)
1113 dev_priv->edram_size_mb = 128;
1115 dev_priv->edram_size_mb =
1116 gen9_edram_size_mb(dev_priv, edram_cap);
1118 dev_info(dev_priv->drm.dev,
1119 "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1123 * i915_driver_hw_probe - setup state requiring device access
1124 * @dev_priv: device private
1126 * Setup state that requires accessing the device, but doesn't require
1127 * exposing the driver via kernel internal or userspace interfaces.
1129 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1131 struct pci_dev *pdev = dev_priv->drm.pdev;
1134 if (i915_inject_probe_failure(dev_priv))
1137 intel_device_info_runtime_init(dev_priv);
1139 if (HAS_PPGTT(dev_priv)) {
1140 if (intel_vgpu_active(dev_priv) &&
1141 !intel_vgpu_has_full_ppgtt(dev_priv)) {
1142 i915_report_error(dev_priv,
1143 "incompatible vGPU found, support for isolated ppGTT required\n");
1148 if (HAS_EXECLISTS(dev_priv)) {
1150 * Older GVT emulation depends upon intercepting CSB mmio,
1151 * which we no longer use, preferring to use the HWSP cache
1154 if (intel_vgpu_active(dev_priv) &&
1155 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1156 i915_report_error(dev_priv,
1157 "old vGPU host found, support for HWSP emulation required\n");
1162 intel_sanitize_options(dev_priv);
1164 /* needs to be done before ggtt probe */
1165 edram_detect(dev_priv);
1167 i915_perf_init(dev_priv);
1169 ret = i915_ggtt_probe_hw(dev_priv);
1173 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
1177 ret = i915_ggtt_init_hw(dev_priv);
1181 ret = intel_memory_regions_hw_probe(dev_priv);
1185 intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
1187 ret = i915_ggtt_enable_hw(dev_priv);
1189 DRM_ERROR("failed to enable GGTT\n");
1190 goto err_mem_regions;
1193 pci_set_master(pdev);
1196 * We don't have a max segment size, so set it to the max so sg's
1197 * debugging layer doesn't complain
1199 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1201 /* overlay on gen2 is broken and can't address above 1G */
1202 if (IS_GEN(dev_priv, 2)) {
1203 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1205 DRM_ERROR("failed to set DMA mask\n");
1207 goto err_mem_regions;
1211 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1212 * using 32bit addressing, overwriting memory if HWS is located
1215 * The documentation also mentions an issue with undefined
1216 * behaviour if any general state is accessed within a page above 4GB,
1217 * which also needs to be handled carefully.
1219 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1220 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1223 DRM_ERROR("failed to set DMA mask\n");
1225 goto err_mem_regions;
1229 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1230 PM_QOS_DEFAULT_VALUE);
1232 intel_gt_init_workarounds(dev_priv);
1234 /* On the 945G/GM, the chipset reports the MSI capability on the
1235 * integrated graphics even though the support isn't actually there
1236 * according to the published specs. It doesn't appear to function
1237 * correctly in testing on 945G.
1238 * This may be a side effect of MSI having been made available for PEG
1239 * and the registers being closely associated.
1241 * According to chipset errata, on the 965GM, MSI interrupts may
1242 * be lost or delayed, and was defeatured. MSI interrupts seem to
1243 * get lost on g4x as well, and interrupt delivery seems to stay
1244 * properly dead afterwards. So we'll just disable them for all
1245 * pre-gen5 chipsets.
1247 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1248 * interrupts even when in MSI mode. This results in spurious
1249 * interrupt warnings if the legacy irq no. is shared with another
1250 * device. The kernel then disables that interrupt source and so
1251 * prevents the other device from working properly.
1253 if (INTEL_GEN(dev_priv) >= 5) {
1254 if (pci_enable_msi(pdev) < 0)
1255 DRM_DEBUG_DRIVER("can't enable MSI");
1258 ret = intel_gvt_init(dev_priv);
1262 intel_opregion_setup(dev_priv);
1264 * Fill the dram structure to get the system raw bandwidth and
1265 * dram info. This will be used for memory latency calculation.
1267 intel_get_dram_info(dev_priv);
1269 intel_bw_init_hw(dev_priv);
1274 if (pdev->msi_enabled)
1275 pci_disable_msi(pdev);
1276 pm_qos_remove_request(&dev_priv->pm_qos);
1278 intel_memory_regions_driver_release(dev_priv);
1280 i915_ggtt_driver_release(dev_priv);
1282 i915_perf_fini(dev_priv);
1287 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1288 * @dev_priv: device private
1290 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1292 struct pci_dev *pdev = dev_priv->drm.pdev;
1294 i915_perf_fini(dev_priv);
1296 if (pdev->msi_enabled)
1297 pci_disable_msi(pdev);
1299 pm_qos_remove_request(&dev_priv->pm_qos);
1303 * i915_driver_register - register the driver with the rest of the system
1304 * @dev_priv: device private
1306 * Perform any steps necessary to make the driver available via kernel
1307 * internal or userspace interfaces.
1309 static void i915_driver_register(struct drm_i915_private *dev_priv)
1311 struct drm_device *dev = &dev_priv->drm;
1313 i915_gem_driver_register(dev_priv);
1314 i915_pmu_register(dev_priv);
1317 * Notify a valid surface after modesetting,
1318 * when running inside a VM.
1320 if (intel_vgpu_active(dev_priv))
1321 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1323 /* Reveal our presence to userspace */
1324 if (drm_dev_register(dev, 0) == 0) {
1325 i915_debugfs_register(dev_priv);
1326 i915_setup_sysfs(dev_priv);
1328 /* Depends on sysfs having been initialized */
1329 i915_perf_register(dev_priv);
1331 DRM_ERROR("Failed to register driver for userspace access!\n");
1333 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
1334 /* Must be done after probing outputs */
1335 intel_opregion_register(dev_priv);
1336 acpi_video_register();
1339 intel_gt_driver_register(&dev_priv->gt);
1341 intel_audio_init(dev_priv);
1344 * Some ports require correctly set-up hpd registers for detection to
1345 * work properly (leading to ghost connected connector status), e.g. VGA
1346 * on gm45. Hence we can only set up the initial fbdev config after hpd
1347 * irqs are fully enabled. We do it last so that the async config
1348 * cannot run before the connectors are registered.
1350 intel_fbdev_initial_config_async(dev);
1353 * We need to coordinate the hotplugs with the asynchronous fbdev
1354 * configuration, for which we use the fbdev->async_cookie.
1356 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
1357 drm_kms_helper_poll_init(dev);
1359 intel_power_domains_enable(dev_priv);
1360 intel_runtime_pm_enable(&dev_priv->runtime_pm);
1364 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1365 * @dev_priv: device private
1367 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1369 intel_runtime_pm_disable(&dev_priv->runtime_pm);
1370 intel_power_domains_disable(dev_priv);
1372 intel_fbdev_unregister(dev_priv);
1373 intel_audio_deinit(dev_priv);
1376 * After flushing the fbdev (incl. a late async config which will
1377 * have delayed queuing of a hotplug event), then flush the hotplug
1380 drm_kms_helper_poll_fini(&dev_priv->drm);
1382 intel_gt_driver_unregister(&dev_priv->gt);
1383 acpi_video_unregister();
1384 intel_opregion_unregister(dev_priv);
1386 i915_perf_unregister(dev_priv);
1387 i915_pmu_unregister(dev_priv);
1389 i915_teardown_sysfs(dev_priv);
1390 drm_dev_unplug(&dev_priv->drm);
1392 i915_gem_driver_unregister(dev_priv);
1395 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1397 if (drm_debug_enabled(DRM_UT_DRIVER)) {
1398 struct drm_printer p = drm_debug_printer("i915 device info:");
1400 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1401 INTEL_DEVID(dev_priv),
1402 INTEL_REVID(dev_priv),
1403 intel_platform_name(INTEL_INFO(dev_priv)->platform),
1404 intel_subplatform(RUNTIME_INFO(dev_priv),
1405 INTEL_INFO(dev_priv)->platform),
1406 INTEL_GEN(dev_priv));
1408 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
1409 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
1412 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1413 DRM_INFO("DRM_I915_DEBUG enabled\n");
1414 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1415 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1416 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1417 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1420 static struct drm_i915_private *
1421 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1423 const struct intel_device_info *match_info =
1424 (struct intel_device_info *)ent->driver_data;
1425 struct intel_device_info *device_info;
1426 struct drm_i915_private *i915;
1429 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1431 return ERR_PTR(-ENOMEM);
1433 err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1436 return ERR_PTR(err);
1439 i915->drm.dev_private = i915;
1441 i915->drm.pdev = pdev;
1442 pci_set_drvdata(pdev, i915);
1444 /* Setup the write-once "constant" device info */
1445 device_info = mkwrite_device_info(i915);
1446 memcpy(device_info, match_info, sizeof(*device_info));
1447 RUNTIME_INFO(i915)->device_id = pdev->device;
1449 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1454 static void i915_driver_destroy(struct drm_i915_private *i915)
1456 struct pci_dev *pdev = i915->drm.pdev;
1458 drm_dev_fini(&i915->drm);
1461 /* And make sure we never chase our dangling pointer from pci_dev */
1462 pci_set_drvdata(pdev, NULL);
1466 * i915_driver_probe - setup chip and create an initial config
1468 * @ent: matching PCI ID entry
1470 * The driver probe routine has to do several things:
1471 * - drive output discovery via intel_modeset_init()
1472 * - initialize the memory manager
1473 * - allocate initial config memory
1474 * - setup the DRM framebuffer with the allocated memory
1476 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1478 const struct intel_device_info *match_info =
1479 (struct intel_device_info *)ent->driver_data;
1480 struct drm_i915_private *dev_priv;
1483 dev_priv = i915_driver_create(pdev, ent);
1484 if (IS_ERR(dev_priv))
1485 return PTR_ERR(dev_priv);
1487 /* Disable nuclear pageflip by default on pre-ILK */
1488 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1489 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1492 * Check if we support fake LMEM -- for now we only unleash this for
1493 * the live selftests(test-and-exit).
1495 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1496 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
1497 if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live < 0 &&
1498 i915_modparams.fake_lmem_start) {
1499 mkwrite_device_info(dev_priv)->memory_regions =
1500 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
1501 mkwrite_device_info(dev_priv)->is_dgfx = true;
1502 GEM_BUG_ON(!HAS_LMEM(dev_priv));
1503 GEM_BUG_ON(!IS_DGFX(dev_priv));
1508 ret = pci_enable_device(pdev);
1512 ret = i915_driver_early_probe(dev_priv);
1514 goto out_pci_disable;
1516 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1518 i915_detect_vgpu(dev_priv);
1520 ret = i915_driver_mmio_probe(dev_priv);
1522 goto out_runtime_pm_put;
1524 ret = i915_driver_hw_probe(dev_priv);
1526 goto out_cleanup_mmio;
1528 ret = i915_driver_modeset_probe(dev_priv);
1530 goto out_cleanup_hw;
1532 i915_driver_register(dev_priv);
1534 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1536 i915_welcome_messages(dev_priv);
1541 i915_driver_hw_remove(dev_priv);
1542 intel_memory_regions_driver_release(dev_priv);
1543 i915_ggtt_driver_release(dev_priv);
1545 i915_driver_mmio_release(dev_priv);
1547 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1548 i915_driver_late_release(dev_priv);
1550 pci_disable_device(pdev);
1552 i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
1553 i915_driver_destroy(dev_priv);
1557 void i915_driver_remove(struct drm_i915_private *i915)
1559 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1561 i915_driver_unregister(i915);
1564 * After unregistering the device to prevent any new users, cancel
1565 * all in-flight requests so that we can quickly unbind the active
1568 intel_gt_set_wedged(&i915->gt);
1570 /* Flush any external code that still may be under the RCU lock */
1573 i915_gem_suspend(i915);
1575 drm_atomic_helper_shutdown(&i915->drm);
1577 intel_gvt_driver_remove(i915);
1579 i915_driver_modeset_remove(i915);
1581 i915_reset_error_state(i915);
1582 i915_gem_driver_remove(i915);
1584 intel_power_domains_driver_remove(i915);
1586 i915_driver_hw_remove(i915);
1588 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1591 static void i915_driver_release(struct drm_device *dev)
1593 struct drm_i915_private *dev_priv = to_i915(dev);
1594 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1596 disable_rpm_wakeref_asserts(rpm);
1598 i915_gem_driver_release(dev_priv);
1600 intel_memory_regions_driver_release(dev_priv);
1601 i915_ggtt_driver_release(dev_priv);
1603 i915_driver_mmio_release(dev_priv);
1605 enable_rpm_wakeref_asserts(rpm);
1606 intel_runtime_pm_driver_release(rpm);
1608 i915_driver_late_release(dev_priv);
1609 i915_driver_destroy(dev_priv);
1612 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1614 struct drm_i915_private *i915 = to_i915(dev);
1617 ret = i915_gem_open(i915, file);
1625 * i915_driver_lastclose - clean up after all DRM clients have exited
1628 * Take care of cleaning up after all DRM clients have exited. In the
1629 * mode setting case, we want to restore the kernel's initial mode (just
1630 * in case the last client left us in a bad state).
1632 * Additionally, in the non-mode setting case, we'll tear down the GTT
1633 * and DMA structures, since the kernel won't be using them, and clea
1636 static void i915_driver_lastclose(struct drm_device *dev)
1638 intel_fbdev_restore_mode(dev);
1639 vga_switcheroo_process_delayed_switch();
1642 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1644 struct drm_i915_file_private *file_priv = file->driver_priv;
1646 i915_gem_context_close(file);
1647 i915_gem_release(dev, file);
1649 kfree_rcu(file_priv, rcu);
1651 /* Catch up with all the deferred frees from "this" client */
1652 i915_gem_flush_free_objects(to_i915(dev));
1655 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1657 struct drm_device *dev = &dev_priv->drm;
1658 struct intel_encoder *encoder;
1660 drm_modeset_lock_all(dev);
1661 for_each_intel_encoder(dev, encoder)
1662 if (encoder->suspend)
1663 encoder->suspend(encoder);
1664 drm_modeset_unlock_all(dev);
1667 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1669 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1671 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1673 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1674 if (acpi_target_system_state() < ACPI_STATE_S3)
1680 static int i915_drm_prepare(struct drm_device *dev)
1682 struct drm_i915_private *i915 = to_i915(dev);
1685 * NB intel_display_suspend() may issue new requests after we've
1686 * ostensibly marked the GPU as ready-to-sleep here. We need to
1687 * split out that work and pull it forward so that after point,
1688 * the GPU is not woken again.
1690 i915_gem_suspend(i915);
1695 static int i915_drm_suspend(struct drm_device *dev)
1697 struct drm_i915_private *dev_priv = to_i915(dev);
1698 struct pci_dev *pdev = dev_priv->drm.pdev;
1699 pci_power_t opregion_target_state;
1701 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1703 /* We do a lot of poking in a lot of registers, make sure they work
1705 intel_power_domains_disable(dev_priv);
1707 drm_kms_helper_poll_disable(dev);
1709 pci_save_state(pdev);
1711 intel_display_suspend(dev);
1713 intel_dp_mst_suspend(dev_priv);
1715 intel_runtime_pm_disable_interrupts(dev_priv);
1716 intel_hpd_cancel_work(dev_priv);
1718 intel_suspend_encoders(dev_priv);
1720 intel_suspend_hw(dev_priv);
1722 i915_gem_suspend_gtt_mappings(dev_priv);
1724 i915_save_state(dev_priv);
1726 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1727 intel_opregion_suspend(dev_priv, opregion_target_state);
1729 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1731 dev_priv->suspend_count++;
1733 intel_csr_ucode_suspend(dev_priv);
1735 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1740 static enum i915_drm_suspend_mode
1741 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1744 return I915_DRM_SUSPEND_HIBERNATE;
1746 if (suspend_to_idle(dev_priv))
1747 return I915_DRM_SUSPEND_IDLE;
1749 return I915_DRM_SUSPEND_MEM;
1752 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1754 struct drm_i915_private *dev_priv = to_i915(dev);
1755 struct pci_dev *pdev = dev_priv->drm.pdev;
1756 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1759 disable_rpm_wakeref_asserts(rpm);
1761 i915_gem_suspend_late(dev_priv);
1763 intel_uncore_suspend(&dev_priv->uncore);
1765 intel_power_domains_suspend(dev_priv,
1766 get_suspend_mode(dev_priv, hibernation));
1768 intel_display_power_suspend_late(dev_priv);
1770 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1771 ret = vlv_suspend_complete(dev_priv);
1774 DRM_ERROR("Suspend complete failed: %d\n", ret);
1775 intel_power_domains_resume(dev_priv);
1780 pci_disable_device(pdev);
1782 * During hibernation on some platforms the BIOS may try to access
1783 * the device even though it's already in D3 and hang the machine. So
1784 * leave the device in D0 on those platforms and hope the BIOS will
1785 * power down the device properly. The issue was seen on multiple old
1786 * GENs with different BIOS vendors, so having an explicit blacklist
1787 * is inpractical; apply the workaround on everything pre GEN6. The
1788 * platforms where the issue was seen:
1789 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1793 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1794 pci_set_power_state(pdev, PCI_D3hot);
1797 enable_rpm_wakeref_asserts(rpm);
1798 if (!dev_priv->uncore.user_forcewake_count)
1799 intel_runtime_pm_driver_release(rpm);
1804 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1808 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1809 state.event != PM_EVENT_FREEZE))
1812 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1815 error = i915_drm_suspend(&i915->drm);
1819 return i915_drm_suspend_late(&i915->drm, false);
1822 static int i915_drm_resume(struct drm_device *dev)
1824 struct drm_i915_private *dev_priv = to_i915(dev);
1827 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1829 sanitize_gpu(dev_priv);
1831 ret = i915_ggtt_enable_hw(dev_priv);
1833 DRM_ERROR("failed to re-enable GGTT\n");
1835 i915_gem_restore_gtt_mappings(dev_priv);
1836 i915_gem_restore_fences(&dev_priv->ggtt);
1838 intel_csr_ucode_resume(dev_priv);
1840 i915_restore_state(dev_priv);
1841 intel_pps_unlock_regs_wa(dev_priv);
1843 intel_init_pch_refclk(dev_priv);
1846 * Interrupts have to be enabled before any batches are run. If not the
1847 * GPU will hang. i915_gem_init_hw() will initiate batches to
1848 * update/restore the context.
1850 * drm_mode_config_reset() needs AUX interrupts.
1852 * Modeset enabling in intel_modeset_init_hw() also needs working
1855 intel_runtime_pm_enable_interrupts(dev_priv);
1857 drm_mode_config_reset(dev);
1859 i915_gem_resume(dev_priv);
1861 intel_modeset_init_hw(dev_priv);
1862 intel_init_clock_gating(dev_priv);
1864 spin_lock_irq(&dev_priv->irq_lock);
1865 if (dev_priv->display.hpd_irq_setup)
1866 dev_priv->display.hpd_irq_setup(dev_priv);
1867 spin_unlock_irq(&dev_priv->irq_lock);
1869 intel_dp_mst_resume(dev_priv);
1871 intel_display_resume(dev);
1873 drm_kms_helper_poll_enable(dev);
1876 * ... but also need to make sure that hotplug processing
1877 * doesn't cause havoc. Like in the driver load code we don't
1878 * bother with the tiny race here where we might lose hotplug
1881 intel_hpd_init(dev_priv);
1883 intel_opregion_resume(dev_priv);
1885 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1887 intel_power_domains_enable(dev_priv);
1889 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1894 static int i915_drm_resume_early(struct drm_device *dev)
1896 struct drm_i915_private *dev_priv = to_i915(dev);
1897 struct pci_dev *pdev = dev_priv->drm.pdev;
1901 * We have a resume ordering issue with the snd-hda driver also
1902 * requiring our device to be power up. Due to the lack of a
1903 * parent/child relationship we currently solve this with an early
1906 * FIXME: This should be solved with a special hdmi sink device or
1907 * similar so that power domains can be employed.
1911 * Note that we need to set the power state explicitly, since we
1912 * powered off the device during freeze and the PCI core won't power
1913 * it back up for us during thaw. Powering off the device during
1914 * freeze is not a hard requirement though, and during the
1915 * suspend/resume phases the PCI core makes sure we get here with the
1916 * device powered on. So in case we change our freeze logic and keep
1917 * the device powered we can also remove the following set power state
1920 ret = pci_set_power_state(pdev, PCI_D0);
1922 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1927 * Note that pci_enable_device() first enables any parent bridge
1928 * device and only then sets the power state for this device. The
1929 * bridge enabling is a nop though, since bridge devices are resumed
1930 * first. The order of enabling power and enabling the device is
1931 * imposed by the PCI core as described above, so here we preserve the
1932 * same order for the freeze/thaw phases.
1934 * TODO: eventually we should remove pci_disable_device() /
1935 * pci_enable_enable_device() from suspend/resume. Due to how they
1936 * depend on the device enable refcount we can't anyway depend on them
1937 * disabling/enabling the device.
1939 if (pci_enable_device(pdev))
1942 pci_set_master(pdev);
1944 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1946 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1947 ret = vlv_resume_prepare(dev_priv, false);
1949 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1952 intel_uncore_resume_early(&dev_priv->uncore);
1954 intel_gt_check_and_clear_faults(&dev_priv->gt);
1956 intel_display_power_resume_early(dev_priv);
1958 intel_power_domains_resume(dev_priv);
1960 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1965 int i915_resume_switcheroo(struct drm_i915_private *i915)
1969 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1972 ret = i915_drm_resume_early(&i915->drm);
1976 return i915_drm_resume(&i915->drm);
1979 static int i915_pm_prepare(struct device *kdev)
1981 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1984 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1988 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1991 return i915_drm_prepare(&i915->drm);
1994 static int i915_pm_suspend(struct device *kdev)
1996 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1999 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2003 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2006 return i915_drm_suspend(&i915->drm);
2009 static int i915_pm_suspend_late(struct device *kdev)
2011 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2014 * We have a suspend ordering issue with the snd-hda driver also
2015 * requiring our device to be power up. Due to the lack of a
2016 * parent/child relationship we currently solve this with an late
2019 * FIXME: This should be solved with a special hdmi sink device or
2020 * similar so that power domains can be employed.
2022 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2025 return i915_drm_suspend_late(&i915->drm, false);
2028 static int i915_pm_poweroff_late(struct device *kdev)
2030 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2032 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2035 return i915_drm_suspend_late(&i915->drm, true);
2038 static int i915_pm_resume_early(struct device *kdev)
2040 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2042 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2045 return i915_drm_resume_early(&i915->drm);
2048 static int i915_pm_resume(struct device *kdev)
2050 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2052 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2055 return i915_drm_resume(&i915->drm);
2058 /* freeze: before creating the hibernation_image */
2059 static int i915_pm_freeze(struct device *kdev)
2061 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2064 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2065 ret = i915_drm_suspend(&i915->drm);
2070 ret = i915_gem_freeze(i915);
2077 static int i915_pm_freeze_late(struct device *kdev)
2079 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2082 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2083 ret = i915_drm_suspend_late(&i915->drm, true);
2088 ret = i915_gem_freeze_late(i915);
2095 /* thaw: called after creating the hibernation image, but before turning off. */
2096 static int i915_pm_thaw_early(struct device *kdev)
2098 return i915_pm_resume_early(kdev);
2101 static int i915_pm_thaw(struct device *kdev)
2103 return i915_pm_resume(kdev);
2106 /* restore: called after loading the hibernation image. */
2107 static int i915_pm_restore_early(struct device *kdev)
2109 return i915_pm_resume_early(kdev);
2112 static int i915_pm_restore(struct device *kdev)
2114 return i915_pm_resume(kdev);
2118 * Save all Gunit registers that may be lost after a D3 and a subsequent
2119 * S0i[R123] transition. The list of registers needing a save/restore is
2120 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2121 * registers in the following way:
2122 * - Driver: saved/restored by the driver
2123 * - Punit : saved/restored by the Punit firmware
2124 * - No, w/o marking: no need to save/restore, since the register is R/O or
2125 * used internally by the HW in a way that doesn't depend
2126 * keeping the content across a suspend/resume.
2127 * - Debug : used for debugging
2129 * We save/restore all registers marked with 'Driver', with the following
2131 * - Registers out of use, including also registers marked with 'Debug'.
2132 * These have no effect on the driver's operation, so we don't save/restore
2133 * them to reduce the overhead.
2134 * - Registers that are fully setup by an initialization function called from
2135 * the resume path. For example many clock gating and RPS/RC6 registers.
2136 * - Registers that provide the right functionality with their reset defaults.
2138 * TODO: Except for registers that based on the above 3 criteria can be safely
2139 * ignored, we save/restore all others, practically treating the HW context as
2140 * a black-box for the driver. Further investigation is needed to reduce the
2141 * saved/restored registers even further, by following the same 3 criteria.
2143 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2145 struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2151 /* GAM 0x4000-0x4770 */
2152 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2153 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2154 s->arb_mode = I915_READ(ARB_MODE);
2155 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2156 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2158 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2159 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2161 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2162 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2164 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2165 s->ecochk = I915_READ(GAM_ECOCHK);
2166 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2167 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2169 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2171 /* MBC 0x9024-0x91D0, 0x8500 */
2172 s->g3dctl = I915_READ(VLV_G3DCTL);
2173 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2174 s->mbctl = I915_READ(GEN6_MBCTL);
2176 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2177 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2178 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2179 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2180 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2181 s->rstctl = I915_READ(GEN6_RSTCTL);
2182 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2184 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2185 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2186 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2187 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2188 s->ecobus = I915_READ(ECOBUS);
2189 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2190 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2191 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2192 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2193 s->rcedata = I915_READ(VLV_RCEDATA);
2194 s->spare2gh = I915_READ(VLV_SPAREG2H);
2196 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2197 s->gt_imr = I915_READ(GTIMR);
2198 s->gt_ier = I915_READ(GTIER);
2199 s->pm_imr = I915_READ(GEN6_PMIMR);
2200 s->pm_ier = I915_READ(GEN6_PMIER);
2202 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2203 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2205 /* GT SA CZ domain, 0x100000-0x138124 */
2206 s->tilectl = I915_READ(TILECTL);
2207 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2208 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2209 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2210 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2212 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2213 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2214 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2215 s->pcbr = I915_READ(VLV_PCBR);
2216 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2219 * Not saving any of:
2220 * DFT, 0x9800-0x9EC0
2221 * SARB, 0xB000-0xB1FC
2222 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2227 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2229 struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2236 /* GAM 0x4000-0x4770 */
2237 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2238 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2239 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2240 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2241 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2243 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2244 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2246 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2247 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2249 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2250 I915_WRITE(GAM_ECOCHK, s->ecochk);
2251 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2252 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2254 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2256 /* MBC 0x9024-0x91D0, 0x8500 */
2257 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2258 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2259 I915_WRITE(GEN6_MBCTL, s->mbctl);
2261 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2262 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2263 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2264 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2265 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2266 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2267 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2269 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2270 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2271 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2272 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2273 I915_WRITE(ECOBUS, s->ecobus);
2274 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2275 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2276 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2277 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2278 I915_WRITE(VLV_RCEDATA, s->rcedata);
2279 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2281 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2282 I915_WRITE(GTIMR, s->gt_imr);
2283 I915_WRITE(GTIER, s->gt_ier);
2284 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2285 I915_WRITE(GEN6_PMIER, s->pm_ier);
2287 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2288 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2290 /* GT SA CZ domain, 0x100000-0x138124 */
2291 I915_WRITE(TILECTL, s->tilectl);
2292 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2294 * Preserve the GT allow wake and GFX force clock bit, they are not
2295 * be restored, as they are used to control the s0ix suspend/resume
2296 * sequence by the caller.
2298 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2299 val &= VLV_GTLC_ALLOWWAKEREQ;
2300 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2301 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2303 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2304 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2305 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2306 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2308 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2310 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2311 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2312 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2313 I915_WRITE(VLV_PCBR, s->pcbr);
2314 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2317 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2320 i915_reg_t reg = VLV_GTLC_PW_STATUS;
2324 /* The HW does not like us polling for PW_STATUS frequently, so
2325 * use the sleeping loop rather than risk the busy spin within
2326 * intel_wait_for_register().
2328 * Transitioning between RC6 states should be at most 2ms (see
2329 * valleyview_enable_rps) so use a 3ms timeout.
2331 ret = wait_for(((reg_value =
2332 intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2335 /* just trace the final value */
2336 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2341 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2346 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2347 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2349 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2350 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2355 err = intel_wait_for_register(&dev_priv->uncore,
2356 VLV_GTLC_SURVIVABILITY_REG,
2357 VLV_GFX_CLK_STATUS_BIT,
2358 VLV_GFX_CLK_STATUS_BIT,
2361 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2362 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2367 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2373 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2374 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2376 val |= VLV_GTLC_ALLOWWAKEREQ;
2377 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2378 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2380 mask = VLV_GTLC_ALLOWWAKEACK;
2381 val = allow ? mask : 0;
2383 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2385 DRM_ERROR("timeout disabling GT waking\n");
2390 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2396 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2397 val = wait_for_on ? mask : 0;
2400 * RC6 transitioning can be delayed up to 2 msec (see
2401 * valleyview_enable_rps), use 3 msec for safety.
2403 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2404 * reset and we are trying to force the machine to sleep.
2406 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2407 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2408 onoff(wait_for_on));
2411 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2413 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2416 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2417 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2420 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2426 * Bspec defines the following GT well on flags as debug only, so
2427 * don't treat them as hard failures.
2429 vlv_wait_for_gt_wells(dev_priv, false);
2431 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2432 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2434 vlv_check_no_gt_access(dev_priv);
2436 err = vlv_force_gfx_clock(dev_priv, true);
2440 err = vlv_allow_gt_wake(dev_priv, false);
2444 vlv_save_gunit_s0ix_state(dev_priv);
2446 err = vlv_force_gfx_clock(dev_priv, false);
2453 /* For safety always re-enable waking and disable gfx clock forcing */
2454 vlv_allow_gt_wake(dev_priv, true);
2456 vlv_force_gfx_clock(dev_priv, false);
2461 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2468 * If any of the steps fail just try to continue, that's the best we
2469 * can do at this point. Return the first error code (which will also
2470 * leave RPM permanently disabled).
2472 ret = vlv_force_gfx_clock(dev_priv, true);
2474 vlv_restore_gunit_s0ix_state(dev_priv);
2476 err = vlv_allow_gt_wake(dev_priv, true);
2480 err = vlv_force_gfx_clock(dev_priv, false);
2484 vlv_check_no_gt_access(dev_priv);
2487 intel_init_clock_gating(dev_priv);
2492 static int intel_runtime_suspend(struct device *kdev)
2494 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2495 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2498 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2501 DRM_DEBUG_KMS("Suspending device\n");
2503 disable_rpm_wakeref_asserts(rpm);
2506 * We are safe here against re-faults, since the fault handler takes
2509 i915_gem_runtime_suspend(dev_priv);
2511 intel_gt_runtime_suspend(&dev_priv->gt);
2513 intel_runtime_pm_disable_interrupts(dev_priv);
2515 intel_uncore_suspend(&dev_priv->uncore);
2517 intel_display_power_suspend(dev_priv);
2519 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2520 ret = vlv_suspend_complete(dev_priv);
2523 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2524 intel_uncore_runtime_resume(&dev_priv->uncore);
2526 intel_runtime_pm_enable_interrupts(dev_priv);
2528 intel_gt_runtime_resume(&dev_priv->gt);
2530 i915_gem_restore_fences(&dev_priv->ggtt);
2532 enable_rpm_wakeref_asserts(rpm);
2537 enable_rpm_wakeref_asserts(rpm);
2538 intel_runtime_pm_driver_release(rpm);
2540 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2541 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2543 rpm->suspended = true;
2546 * FIXME: We really should find a document that references the arguments
2549 if (IS_BROADWELL(dev_priv)) {
2551 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2552 * being detected, and the call we do at intel_runtime_resume()
2553 * won't be able to restore them. Since PCI_D3hot matches the
2554 * actual specification and appears to be working, use it.
2556 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2559 * current versions of firmware which depend on this opregion
2560 * notification have repurposed the D1 definition to mean
2561 * "runtime suspended" vs. what you would normally expect (D3)
2562 * to distinguish it from notifications that might be sent via
2565 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2568 assert_forcewakes_inactive(&dev_priv->uncore);
2570 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2571 intel_hpd_poll_init(dev_priv);
2573 DRM_DEBUG_KMS("Device suspended\n");
2577 static int intel_runtime_resume(struct device *kdev)
2579 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2580 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2583 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2586 DRM_DEBUG_KMS("Resuming device\n");
2588 WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
2589 disable_rpm_wakeref_asserts(rpm);
2591 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2592 rpm->suspended = false;
2593 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2594 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2596 intel_display_power_resume(dev_priv);
2598 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2599 ret = vlv_resume_prepare(dev_priv, true);
2601 intel_uncore_runtime_resume(&dev_priv->uncore);
2603 intel_runtime_pm_enable_interrupts(dev_priv);
2606 * No point of rolling back things in case of an error, as the best
2607 * we can do is to hope that things will still work (and disable RPM).
2609 intel_gt_runtime_resume(&dev_priv->gt);
2610 i915_gem_restore_fences(&dev_priv->ggtt);
2613 * On VLV/CHV display interrupts are part of the display
2614 * power well, so hpd is reinitialized from there. For
2615 * everyone else do it here.
2617 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2618 intel_hpd_init(dev_priv);
2620 intel_enable_ipc(dev_priv);
2622 enable_rpm_wakeref_asserts(rpm);
2625 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2627 DRM_DEBUG_KMS("Device resumed\n");
2632 const struct dev_pm_ops i915_pm_ops = {
2634 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2637 .prepare = i915_pm_prepare,
2638 .suspend = i915_pm_suspend,
2639 .suspend_late = i915_pm_suspend_late,
2640 .resume_early = i915_pm_resume_early,
2641 .resume = i915_pm_resume,
2645 * @freeze, @freeze_late : called (1) before creating the
2646 * hibernation image [PMSG_FREEZE] and
2647 * (2) after rebooting, before restoring
2648 * the image [PMSG_QUIESCE]
2649 * @thaw, @thaw_early : called (1) after creating the hibernation
2650 * image, before writing it [PMSG_THAW]
2651 * and (2) after failing to create or
2652 * restore the image [PMSG_RECOVER]
2653 * @poweroff, @poweroff_late: called after writing the hibernation
2654 * image, before rebooting [PMSG_HIBERNATE]
2655 * @restore, @restore_early : called after rebooting and restoring the
2656 * hibernation image [PMSG_RESTORE]
2658 .freeze = i915_pm_freeze,
2659 .freeze_late = i915_pm_freeze_late,
2660 .thaw_early = i915_pm_thaw_early,
2661 .thaw = i915_pm_thaw,
2662 .poweroff = i915_pm_suspend,
2663 .poweroff_late = i915_pm_poweroff_late,
2664 .restore_early = i915_pm_restore_early,
2665 .restore = i915_pm_restore,
2667 /* S0ix (via runtime suspend) event handlers */
2668 .runtime_suspend = intel_runtime_suspend,
2669 .runtime_resume = intel_runtime_resume,
2672 static const struct file_operations i915_driver_fops = {
2673 .owner = THIS_MODULE,
2675 .release = drm_release,
2676 .unlocked_ioctl = drm_ioctl,
2677 .mmap = i915_gem_mmap,
2680 .compat_ioctl = i915_compat_ioctl,
2681 .llseek = noop_llseek,
2685 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2686 struct drm_file *file)
2691 static const struct drm_ioctl_desc i915_ioctls[] = {
2692 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2693 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2694 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2695 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2696 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2697 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2698 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2699 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2700 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2701 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2702 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2703 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2704 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2705 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2706 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2707 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2708 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2709 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2710 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2711 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2712 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2713 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2714 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2715 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2716 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2717 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2718 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2719 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2720 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2721 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2722 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2723 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2724 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
2725 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2726 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2727 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2728 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2729 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2730 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2731 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2732 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2733 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2734 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2735 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2736 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2737 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2738 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2739 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2740 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2741 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2742 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2743 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2744 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2745 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2746 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2747 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2748 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2749 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2752 static struct drm_driver driver = {
2753 /* Don't use MTRRs here; the Xserver or userspace app should
2754 * deal with them for Intel hardware.
2758 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2759 .release = i915_driver_release,
2760 .open = i915_driver_open,
2761 .lastclose = i915_driver_lastclose,
2762 .postclose = i915_driver_postclose,
2764 .gem_close_object = i915_gem_close_object,
2765 .gem_free_object_unlocked = i915_gem_free_object,
2767 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2768 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2769 .gem_prime_export = i915_gem_prime_export,
2770 .gem_prime_import = i915_gem_prime_import,
2772 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2773 .get_scanout_position = i915_get_crtc_scanoutpos,
2775 .dumb_create = i915_gem_dumb_create,
2776 .dumb_map_offset = i915_gem_dumb_mmap_offset,
2778 .ioctls = i915_ioctls,
2779 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2780 .fops = &i915_driver_fops,
2781 .name = DRIVER_NAME,
2782 .desc = DRIVER_DESC,
2783 .date = DRIVER_DATE,
2784 .major = DRIVER_MAJOR,
2785 .minor = DRIVER_MINOR,
2786 .patchlevel = DRIVER_PATCHLEVEL,