1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
50 int i915_panel_ignore_lid __read_mostly = 1;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
121 int i915_enable_psr __read_mostly = 0;
122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
125 unsigned int i915_preliminary_hw_support __read_mostly = 0;
126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
127 MODULE_PARM_DESC(preliminary_hw_support,
128 "Enable preliminary hardware support. (default: false)");
130 int i915_disable_power_well __read_mostly = 1;
131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
132 MODULE_PARM_DESC(disable_power_well,
133 "Disable the power well when possible (default: true)");
135 int i915_enable_ips __read_mostly = 1;
136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
139 bool i915_fastboot __read_mostly = 0;
140 module_param_named(fastboot, i915_fastboot, bool, 0600);
141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
144 bool i915_prefault_disable __read_mostly;
145 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
146 MODULE_PARM_DESC(prefault_disable,
147 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
149 static struct drm_driver driver;
150 extern int intel_agp_enabled;
152 #define INTEL_VGA_DEVICE(id, info) { \
153 .class = PCI_BASE_CLASS_DISPLAY << 16, \
154 .class_mask = 0xff0000, \
157 .subvendor = PCI_ANY_ID, \
158 .subdevice = PCI_ANY_ID, \
159 .driver_data = (unsigned long) info }
161 #define INTEL_QUANTA_VGA_DEVICE(info) { \
162 .class = PCI_BASE_CLASS_DISPLAY << 16, \
163 .class_mask = 0xff0000, \
166 .subvendor = 0x152d, \
167 .subdevice = 0x8990, \
168 .driver_data = (unsigned long) info }
171 static const struct intel_device_info intel_i830_info = {
172 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
173 .has_overlay = 1, .overlay_needs_physical = 1,
176 static const struct intel_device_info intel_845g_info = {
177 .gen = 2, .num_pipes = 1,
178 .has_overlay = 1, .overlay_needs_physical = 1,
181 static const struct intel_device_info intel_i85x_info = {
182 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
183 .cursor_needs_physical = 1,
184 .has_overlay = 1, .overlay_needs_physical = 1,
187 static const struct intel_device_info intel_i865g_info = {
188 .gen = 2, .num_pipes = 1,
189 .has_overlay = 1, .overlay_needs_physical = 1,
192 static const struct intel_device_info intel_i915g_info = {
193 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
194 .has_overlay = 1, .overlay_needs_physical = 1,
196 static const struct intel_device_info intel_i915gm_info = {
197 .gen = 3, .is_mobile = 1, .num_pipes = 2,
198 .cursor_needs_physical = 1,
199 .has_overlay = 1, .overlay_needs_physical = 1,
202 static const struct intel_device_info intel_i945g_info = {
203 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
204 .has_overlay = 1, .overlay_needs_physical = 1,
206 static const struct intel_device_info intel_i945gm_info = {
207 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
208 .has_hotplug = 1, .cursor_needs_physical = 1,
209 .has_overlay = 1, .overlay_needs_physical = 1,
213 static const struct intel_device_info intel_i965g_info = {
214 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
219 static const struct intel_device_info intel_i965gm_info = {
220 .gen = 4, .is_crestline = 1, .num_pipes = 2,
221 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
226 static const struct intel_device_info intel_g33_info = {
227 .gen = 3, .is_g33 = 1, .num_pipes = 2,
228 .need_gfx_hws = 1, .has_hotplug = 1,
232 static const struct intel_device_info intel_g45_info = {
233 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
234 .has_pipe_cxsr = 1, .has_hotplug = 1,
238 static const struct intel_device_info intel_gm45_info = {
239 .gen = 4, .is_g4x = 1, .num_pipes = 2,
240 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
241 .has_pipe_cxsr = 1, .has_hotplug = 1,
246 static const struct intel_device_info intel_pineview_info = {
247 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
248 .need_gfx_hws = 1, .has_hotplug = 1,
252 static const struct intel_device_info intel_ironlake_d_info = {
253 .gen = 5, .num_pipes = 2,
254 .need_gfx_hws = 1, .has_hotplug = 1,
258 static const struct intel_device_info intel_ironlake_m_info = {
259 .gen = 5, .is_mobile = 1, .num_pipes = 2,
260 .need_gfx_hws = 1, .has_hotplug = 1,
265 static const struct intel_device_info intel_sandybridge_d_info = {
266 .gen = 6, .num_pipes = 2,
267 .need_gfx_hws = 1, .has_hotplug = 1,
274 static const struct intel_device_info intel_sandybridge_m_info = {
275 .gen = 6, .is_mobile = 1, .num_pipes = 2,
276 .need_gfx_hws = 1, .has_hotplug = 1,
284 #define GEN7_FEATURES \
285 .gen = 7, .num_pipes = 3, \
286 .need_gfx_hws = 1, .has_hotplug = 1, \
292 static const struct intel_device_info intel_ivybridge_d_info = {
297 static const struct intel_device_info intel_ivybridge_m_info = {
304 static const struct intel_device_info intel_ivybridge_q_info = {
307 .num_pipes = 0, /* legal, last one wins */
310 static const struct intel_device_info intel_valleyview_m_info = {
315 .display_mmio_offset = VLV_DISPLAY_BASE,
316 .has_llc = 0, /* legal, last one wins */
319 static const struct intel_device_info intel_valleyview_d_info = {
323 .display_mmio_offset = VLV_DISPLAY_BASE,
324 .has_llc = 0, /* legal, last one wins */
327 static const struct intel_device_info intel_haswell_d_info = {
335 static const struct intel_device_info intel_haswell_m_info = {
345 static const struct pci_device_id pciidlist[] = { /* aka */
346 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
347 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
348 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
349 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
350 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
351 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
352 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
353 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
354 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
355 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
356 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
357 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
358 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
359 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
360 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
361 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
362 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
363 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
364 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
365 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
366 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
367 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
368 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
369 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
370 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
371 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
372 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
373 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
374 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
375 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
376 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
377 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
378 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
379 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
380 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
381 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
382 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
383 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
384 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
385 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
386 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
387 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
388 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
389 INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
390 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
391 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
392 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
393 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
394 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
395 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
396 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
397 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
398 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
399 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
400 INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
401 INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
402 INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
403 INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
404 INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
405 INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
406 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
407 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
408 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
409 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
410 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
411 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
412 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
413 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
414 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
415 INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
416 INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
417 INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
418 INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
419 INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
420 INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
421 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
422 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
423 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
424 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
425 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
426 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
427 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
428 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
429 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
430 INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
431 INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
432 INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
433 INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
434 INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
435 INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
436 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
437 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
438 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
439 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
440 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
441 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
442 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
443 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
444 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
445 INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
446 INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
447 INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
448 INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
449 INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
450 INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
451 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
452 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
453 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
454 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
455 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
456 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
460 #if defined(CONFIG_DRM_I915_KMS)
461 MODULE_DEVICE_TABLE(pci, pciidlist);
464 void intel_detect_pch(struct drm_device *dev)
466 struct drm_i915_private *dev_priv = dev->dev_private;
469 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
470 * (which really amounts to a PCH but no South Display).
472 if (INTEL_INFO(dev)->num_pipes == 0) {
473 dev_priv->pch_type = PCH_NOP;
478 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
479 * make graphics device passthrough work easy for VMM, that only
480 * need to expose ISA bridge to let driver know the real hardware
481 * underneath. This is a requirement from virtualization team.
483 * In some virtualized environments (e.g. XEN), there is irrelevant
484 * ISA bridge in the system. To work reliably, we should scan trhough
485 * all the ISA bridge devices and check for the first match, instead
486 * of only checking the first one.
488 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
490 struct pci_dev *curr = pch;
491 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
493 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
494 dev_priv->pch_id = id;
496 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
497 dev_priv->pch_type = PCH_IBX;
498 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
499 WARN_ON(!IS_GEN5(dev));
500 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
501 dev_priv->pch_type = PCH_CPT;
502 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
503 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
504 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
505 /* PantherPoint is CPT compatible */
506 dev_priv->pch_type = PCH_CPT;
507 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
508 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
509 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
510 dev_priv->pch_type = PCH_LPT;
511 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
512 WARN_ON(!IS_HASWELL(dev));
513 WARN_ON(IS_ULT(dev));
514 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
515 dev_priv->pch_type = PCH_LPT;
516 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
517 WARN_ON(!IS_HASWELL(dev));
518 WARN_ON(!IS_ULT(dev));
526 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
530 DRM_DEBUG_KMS("No PCH found?\n");
533 bool i915_semaphore_is_enabled(struct drm_device *dev)
535 if (INTEL_INFO(dev)->gen < 6)
538 if (i915_semaphores >= 0)
539 return i915_semaphores;
541 #ifdef CONFIG_INTEL_IOMMU
542 /* Enable semaphores on SNB when IO remapping is off */
543 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
550 static int i915_drm_freeze(struct drm_device *dev)
552 struct drm_i915_private *dev_priv = dev->dev_private;
553 struct drm_crtc *crtc;
555 /* ignore lid events during suspend */
556 mutex_lock(&dev_priv->modeset_restore_lock);
557 dev_priv->modeset_restore = MODESET_SUSPENDED;
558 mutex_unlock(&dev_priv->modeset_restore_lock);
560 intel_set_power_well(dev, true);
562 drm_kms_helper_poll_disable(dev);
564 pci_save_state(dev->pdev);
566 /* If KMS is active, we do the leavevt stuff here */
567 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
570 mutex_lock(&dev->struct_mutex);
571 error = i915_gem_idle(dev);
572 mutex_unlock(&dev->struct_mutex);
574 dev_err(&dev->pdev->dev,
575 "GEM idle failed, resume might fail\n");
579 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
581 drm_irq_uninstall(dev);
582 dev_priv->enable_hotplug_processing = false;
584 * Disable CRTCs directly since we want to preserve sw state
587 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
588 dev_priv->display.crtc_disable(crtc);
590 intel_modeset_suspend_hw(dev);
593 i915_save_state(dev);
595 intel_opregion_fini(dev);
598 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
604 int i915_suspend(struct drm_device *dev, pm_message_t state)
608 if (!dev || !dev->dev_private) {
609 DRM_ERROR("dev: %p\n", dev);
610 DRM_ERROR("DRM not initialized, aborting suspend.\n");
614 if (state.event == PM_EVENT_PRETHAW)
618 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
621 error = i915_drm_freeze(dev);
625 if (state.event == PM_EVENT_SUSPEND) {
626 /* Shut down the device */
627 pci_disable_device(dev->pdev);
628 pci_set_power_state(dev->pdev, PCI_D3hot);
634 void intel_console_resume(struct work_struct *work)
636 struct drm_i915_private *dev_priv =
637 container_of(work, struct drm_i915_private,
638 console_resume_work);
639 struct drm_device *dev = dev_priv->dev;
642 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
646 static void intel_resume_hotplug(struct drm_device *dev)
648 struct drm_mode_config *mode_config = &dev->mode_config;
649 struct intel_encoder *encoder;
651 mutex_lock(&mode_config->mutex);
652 DRM_DEBUG_KMS("running encoder hotplug functions\n");
654 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
655 if (encoder->hot_plug)
656 encoder->hot_plug(encoder);
658 mutex_unlock(&mode_config->mutex);
660 /* Just fire off a uevent and let userspace tell us what to do */
661 drm_helper_hpd_irq_event(dev);
664 static int __i915_drm_thaw(struct drm_device *dev)
666 struct drm_i915_private *dev_priv = dev->dev_private;
669 i915_restore_state(dev);
670 intel_opregion_setup(dev);
672 /* KMS EnterVT equivalent */
673 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
674 intel_init_pch_refclk(dev);
676 mutex_lock(&dev->struct_mutex);
678 error = i915_gem_init_hw(dev);
679 mutex_unlock(&dev->struct_mutex);
681 /* We need working interrupts for modeset enabling ... */
682 drm_irq_install(dev);
684 intel_modeset_init_hw(dev);
686 drm_modeset_lock_all(dev);
687 intel_modeset_setup_hw_state(dev, true);
688 drm_modeset_unlock_all(dev);
691 * ... but also need to make sure that hotplug processing
692 * doesn't cause havoc. Like in the driver load code we don't
693 * bother with the tiny race here where we might loose hotplug
697 dev_priv->enable_hotplug_processing = true;
698 /* Config may have changed between suspend and resume */
699 intel_resume_hotplug(dev);
702 intel_opregion_init(dev);
705 * The console lock can be pretty contented on resume due
706 * to all the printk activity. Try to keep it out of the hot
707 * path of resume if possible.
709 if (console_trylock()) {
710 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
713 schedule_work(&dev_priv->console_resume_work);
716 mutex_lock(&dev_priv->modeset_restore_lock);
717 dev_priv->modeset_restore = MODESET_DONE;
718 mutex_unlock(&dev_priv->modeset_restore_lock);
722 static int i915_drm_thaw(struct drm_device *dev)
726 intel_uncore_sanitize(dev);
728 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
729 mutex_lock(&dev->struct_mutex);
730 i915_gem_restore_gtt_mappings(dev);
731 mutex_unlock(&dev->struct_mutex);
734 __i915_drm_thaw(dev);
739 int i915_resume(struct drm_device *dev)
741 struct drm_i915_private *dev_priv = dev->dev_private;
744 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
747 if (pci_enable_device(dev->pdev))
750 pci_set_master(dev->pdev);
752 intel_uncore_sanitize(dev);
755 * Platforms with opregion should have sane BIOS, older ones (gen3 and
756 * earlier) need this since the BIOS might clear all our scratch PTEs.
758 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
759 !dev_priv->opregion.header) {
760 mutex_lock(&dev->struct_mutex);
761 i915_gem_restore_gtt_mappings(dev);
762 mutex_unlock(&dev->struct_mutex);
765 ret = __i915_drm_thaw(dev);
769 drm_kms_helper_poll_enable(dev);
774 * i915_reset - reset chip after a hang
775 * @dev: drm device to reset
777 * Reset the chip. Useful if a hang is detected. Returns zero on successful
778 * reset or otherwise an error code.
780 * Procedure is fairly simple:
781 * - reset the chip using the reset reg
782 * - re-init context state
783 * - re-init hardware status page
784 * - re-init ring buffer
785 * - re-init interrupt state
788 int i915_reset(struct drm_device *dev)
790 drm_i915_private_t *dev_priv = dev->dev_private;
797 mutex_lock(&dev->struct_mutex);
801 simulated = dev_priv->gpu_error.stop_rings != 0;
803 if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) {
804 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
807 ret = intel_gpu_reset(dev);
809 /* Also reset the gpu hangman. */
811 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
812 dev_priv->gpu_error.stop_rings = 0;
813 if (ret == -ENODEV) {
814 DRM_ERROR("Reset not implemented, but ignoring "
815 "error for simulated gpu hangs\n");
819 dev_priv->gpu_error.last_reset = get_seconds();
822 DRM_ERROR("Failed to reset chip.\n");
823 mutex_unlock(&dev->struct_mutex);
827 /* Ok, now get things going again... */
830 * Everything depends on having the GTT running, so we need to start
831 * there. Fortunately we don't need to do this unless we reset the
832 * chip at a PCI level.
834 * Next we need to restore the context, but we don't use those
837 * Ring buffer needs to be re-initialized in the KMS case, or if X
838 * was running at the time of the reset (i.e. we weren't VT
841 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
842 !dev_priv->ums.mm_suspended) {
843 struct intel_ring_buffer *ring;
846 dev_priv->ums.mm_suspended = 0;
848 i915_gem_init_swizzling(dev);
850 for_each_ring(ring, dev_priv, i)
853 i915_gem_context_init(dev);
854 if (dev_priv->mm.aliasing_ppgtt) {
855 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
857 i915_gem_cleanup_aliasing_ppgtt(dev);
861 * It would make sense to re-init all the other hw state, at
862 * least the rps/rc6/emon init done within modeset_init_hw. For
863 * some unknown reason, this blows up my ilk, so don't.
866 mutex_unlock(&dev->struct_mutex);
868 drm_irq_uninstall(dev);
869 drm_irq_install(dev);
872 mutex_unlock(&dev->struct_mutex);
878 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
880 struct intel_device_info *intel_info =
881 (struct intel_device_info *) ent->driver_data;
883 /* Only bind to function 0 of the device. Early generations
884 * used function 1 as a placeholder for multi-head. This causes
885 * us confusion instead, especially on the systems where both
886 * functions have the same PCI-ID!
888 if (PCI_FUNC(pdev->devfn))
891 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
892 * implementation for gen3 (and only gen3) that used legacy drm maps
893 * (gasp!) to share buffers between X and the client. Hence we need to
894 * keep around the fake agp stuff for gen3, even when kms is enabled. */
895 if (intel_info->gen != 3) {
896 driver.driver_features &=
897 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
898 } else if (!intel_agp_enabled) {
899 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
903 return drm_get_pci_dev(pdev, ent, &driver);
907 i915_pci_remove(struct pci_dev *pdev)
909 struct drm_device *dev = pci_get_drvdata(pdev);
914 static int i915_pm_suspend(struct device *dev)
916 struct pci_dev *pdev = to_pci_dev(dev);
917 struct drm_device *drm_dev = pci_get_drvdata(pdev);
920 if (!drm_dev || !drm_dev->dev_private) {
921 dev_err(dev, "DRM not initialized, aborting suspend.\n");
925 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
928 error = i915_drm_freeze(drm_dev);
932 pci_disable_device(pdev);
933 pci_set_power_state(pdev, PCI_D3hot);
938 static int i915_pm_resume(struct device *dev)
940 struct pci_dev *pdev = to_pci_dev(dev);
941 struct drm_device *drm_dev = pci_get_drvdata(pdev);
943 return i915_resume(drm_dev);
946 static int i915_pm_freeze(struct device *dev)
948 struct pci_dev *pdev = to_pci_dev(dev);
949 struct drm_device *drm_dev = pci_get_drvdata(pdev);
951 if (!drm_dev || !drm_dev->dev_private) {
952 dev_err(dev, "DRM not initialized, aborting suspend.\n");
956 return i915_drm_freeze(drm_dev);
959 static int i915_pm_thaw(struct device *dev)
961 struct pci_dev *pdev = to_pci_dev(dev);
962 struct drm_device *drm_dev = pci_get_drvdata(pdev);
964 return i915_drm_thaw(drm_dev);
967 static int i915_pm_poweroff(struct device *dev)
969 struct pci_dev *pdev = to_pci_dev(dev);
970 struct drm_device *drm_dev = pci_get_drvdata(pdev);
972 return i915_drm_freeze(drm_dev);
975 static const struct dev_pm_ops i915_pm_ops = {
976 .suspend = i915_pm_suspend,
977 .resume = i915_pm_resume,
978 .freeze = i915_pm_freeze,
979 .thaw = i915_pm_thaw,
980 .poweroff = i915_pm_poweroff,
981 .restore = i915_pm_resume,
984 static const struct vm_operations_struct i915_gem_vm_ops = {
985 .fault = i915_gem_fault,
986 .open = drm_gem_vm_open,
987 .close = drm_gem_vm_close,
990 static const struct file_operations i915_driver_fops = {
991 .owner = THIS_MODULE,
993 .release = drm_release,
994 .unlocked_ioctl = drm_ioctl,
995 .mmap = drm_gem_mmap,
999 .compat_ioctl = i915_compat_ioctl,
1001 .llseek = noop_llseek,
1004 static struct drm_driver driver = {
1005 /* Don't use MTRRs here; the Xserver or userspace app should
1006 * deal with them for Intel hardware.
1009 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1010 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1011 .load = i915_driver_load,
1012 .unload = i915_driver_unload,
1013 .open = i915_driver_open,
1014 .lastclose = i915_driver_lastclose,
1015 .preclose = i915_driver_preclose,
1016 .postclose = i915_driver_postclose,
1018 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1019 .suspend = i915_suspend,
1020 .resume = i915_resume,
1022 .device_is_agp = i915_driver_device_is_agp,
1023 .master_create = i915_master_create,
1024 .master_destroy = i915_master_destroy,
1025 #if defined(CONFIG_DEBUG_FS)
1026 .debugfs_init = i915_debugfs_init,
1027 .debugfs_cleanup = i915_debugfs_cleanup,
1029 .gem_init_object = i915_gem_init_object,
1030 .gem_free_object = i915_gem_free_object,
1031 .gem_vm_ops = &i915_gem_vm_ops,
1033 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1034 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1035 .gem_prime_export = i915_gem_prime_export,
1036 .gem_prime_import = i915_gem_prime_import,
1038 .dumb_create = i915_gem_dumb_create,
1039 .dumb_map_offset = i915_gem_mmap_gtt,
1040 .dumb_destroy = drm_gem_dumb_destroy,
1041 .ioctls = i915_ioctls,
1042 .fops = &i915_driver_fops,
1043 .name = DRIVER_NAME,
1044 .desc = DRIVER_DESC,
1045 .date = DRIVER_DATE,
1046 .major = DRIVER_MAJOR,
1047 .minor = DRIVER_MINOR,
1048 .patchlevel = DRIVER_PATCHLEVEL,
1051 static struct pci_driver i915_pci_driver = {
1052 .name = DRIVER_NAME,
1053 .id_table = pciidlist,
1054 .probe = i915_pci_probe,
1055 .remove = i915_pci_remove,
1056 .driver.pm = &i915_pm_ops,
1059 static int __init i915_init(void)
1061 driver.num_ioctls = i915_max_ioctl;
1064 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1065 * explicitly disabled with the module pararmeter.
1067 * Otherwise, just follow the parameter (defaulting to off).
1069 * Allow optional vga_text_mode_force boot option to override
1070 * the default behavior.
1072 #if defined(CONFIG_DRM_I915_KMS)
1073 if (i915_modeset != 0)
1074 driver.driver_features |= DRIVER_MODESET;
1076 if (i915_modeset == 1)
1077 driver.driver_features |= DRIVER_MODESET;
1079 #ifdef CONFIG_VGA_CONSOLE
1080 if (vgacon_text_force() && i915_modeset == -1)
1081 driver.driver_features &= ~DRIVER_MODESET;
1084 if (!(driver.driver_features & DRIVER_MODESET))
1085 driver.get_vblank_timestamp = NULL;
1087 return drm_pci_init(&driver, &i915_pci_driver);
1090 static void __exit i915_exit(void)
1092 drm_pci_exit(&driver, &i915_pci_driver);
1095 module_init(i915_init);
1096 module_exit(i915_exit);
1098 MODULE_AUTHOR(DRIVER_AUTHOR);
1099 MODULE_DESCRIPTION(DRIVER_DESC);
1100 MODULE_LICENSE("GPL and additional rights");