drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41 #include <acpi/video.h>
  42
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_irq.h>
  46 #include <drm/drm_probe_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_audio.h"
  51 #include "display/intel_bw.h"
  52 #include "display/intel_cdclk.h"
  53 #include "display/intel_display_types.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_fbdev.h"
  56 #include "display/intel_hotplug.h"
  57 #include "display/intel_overlay.h"
  58 #include "display/intel_pipe_crc.h"
  59 #include "display/intel_psr.h"
  60 #include "display/intel_sprite.h"
  61 #include "display/intel_vga.h"
  62
  63 #include "gem/i915_gem_context.h"
  64 #include "gem/i915_gem_ioctls.h"
  65 #include "gem/i915_gem_mman.h"
  66 #include "gt/intel_gt.h"
  67 #include "gt/intel_gt_pm.h"
  68 #include "gt/intel_rc6.h"
  69
  70 #include "i915_debugfs.h"
  71 #include "i915_drv.h"
  72 #include "i915_irq.h"
  73 #include "i915_memcpy.h"
  74 #include "i915_perf.h"
  75 #include "i915_query.h"
  76 #include "i915_suspend.h"
  77 #include "i915_switcheroo.h"
  78 #include "i915_sysfs.h"
  79 #include "i915_trace.h"
  80 #include "i915_vgpu.h"
  81 #include "intel_csr.h"
  82 #include "intel_memory_region.h"
  83 #include "intel_pm.h"
  84
  85 static struct drm_driver driver;
  86
  87 struct vlv_s0ix_state {
  88         /* GAM */
  89         u32 wr_watermark;
  90         u32 gfx_prio_ctrl;
  91         u32 arb_mode;
  92         u32 gfx_pend_tlb0;
  93         u32 gfx_pend_tlb1;
  94         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
  95         u32 media_max_req_count;
  96         u32 gfx_max_req_count;
  97         u32 render_hwsp;
  98         u32 ecochk;
  99         u32 bsd_hwsp;
 100         u32 blt_hwsp;
 101         u32 tlb_rd_addr;
 102
 103         /* MBC */
 104         u32 g3dctl;
 105         u32 gsckgctl;
 106         u32 mbctl;
 107
 108         /* GCP */
 109         u32 ucgctl1;
 110         u32 ucgctl3;
 111         u32 rcgctl1;
 112         u32 rcgctl2;
 113         u32 rstctl;
 114         u32 misccpctl;
 115
 116         /* GPM */
 117         u32 gfxpause;
 118         u32 rpdeuhwtc;
 119         u32 rpdeuc;
 120         u32 ecobus;
 121         u32 pwrdwnupctl;
 122         u32 rp_down_timeout;
 123         u32 rp_deucsw;
 124         u32 rcubmabdtmr;
 125         u32 rcedata;
 126         u32 spare2gh;
 127
 128         /* Display 1 CZ domain */
 129         u32 gt_imr;
 130         u32 gt_ier;
 131         u32 pm_imr;
 132         u32 pm_ier;
 133         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 134
 135         /* GT SA CZ domain */
 136         u32 tilectl;
 137         u32 gt_fifoctl;
 138         u32 gtlc_wake_ctrl;
 139         u32 gtlc_survive;
 140         u32 pmwgicz;
 141
 142         /* Display 2 CZ domain */
 143         u32 gu_ctl0;
 144         u32 gu_ctl1;
 145         u32 pcbr;
 146         u32 clock_gate_dis2;
 147 };
 148
 149 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 150 {
 151         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 152
 153         dev_priv->bridge_dev =
 154                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 155         if (!dev_priv->bridge_dev) {
 156                 DRM_ERROR("bridge device not found\n");
 157                 return -1;
 158         }
 159         return 0;
 160 }
 161
 162 /* Allocate space for the MCH regs if needed, return nonzero on error */
 163 static int
 164 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 165 {
 166         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 167         u32 temp_lo, temp_hi = 0;
 168         u64 mchbar_addr;
 169         int ret;
 170
 171         if (INTEL_GEN(dev_priv) >= 4)
 172                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 173         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 174         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 175
 176         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 177 #ifdef CONFIG_PNP
 178         if (mchbar_addr &&
 179             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 180                 return 0;
 181 #endif
 182
 183         /* Get some space for it */
 184         dev_priv->mch_res.name = "i915 MCHBAR";
 185         dev_priv->mch_res.flags = IORESOURCE_MEM;
 186         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 187                                      &dev_priv->mch_res,
 188                                      MCHBAR_SIZE, MCHBAR_SIZE,
 189                                      PCIBIOS_MIN_MEM,
 190                                      0, pcibios_align_resource,
 191                                      dev_priv->bridge_dev);
 192         if (ret) {
 193                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 194                 dev_priv->mch_res.start = 0;
 195                 return ret;
 196         }
 197
 198         if (INTEL_GEN(dev_priv) >= 4)
 199                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 200                                        upper_32_bits(dev_priv->mch_res.start));
 201
 202         pci_write_config_dword(dev_priv->bridge_dev, reg,
 203                                lower_32_bits(dev_priv->mch_res.start));
 204         return 0;
 205 }
 206
 207 /* Setup MCHBAR if possible, return true if we should disable it again */
 208 static void
 209 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 210 {
 211         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 212         u32 temp;
 213         bool enabled;
 214
 215         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 216                 return;
 217
 218         dev_priv->mchbar_need_disable = false;
 219
 220         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 221                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 222                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 223         } else {
 224                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 225                 enabled = temp & 1;
 226         }
 227
 228         /* If it's already enabled, don't have to do anything */
 229         if (enabled)
 230                 return;
 231
 232         if (intel_alloc_mchbar_resource(dev_priv))
 233                 return;
 234
 235         dev_priv->mchbar_need_disable = true;
 236
 237         /* Space is allocated or reserved, so enable it. */
 238         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 239                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 240                                        temp | DEVEN_MCHBAR_EN);
 241         } else {
 242                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 243                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 244         }
 245 }
 246
 247 static void
 248 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 249 {
 250         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 251
 252         if (dev_priv->mchbar_need_disable) {
 253                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 254                         u32 deven_val;
 255
 256                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 257                                               &deven_val);
 258                         deven_val &= ~DEVEN_MCHBAR_EN;
 259                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 260                                                deven_val);
 261                 } else {
 262                         u32 mchbar_val;
 263
 264                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 265                                               &mchbar_val);
 266                         mchbar_val &= ~1;
 267                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 268                                                mchbar_val);
 269                 }
 270         }
 271
 272         if (dev_priv->mch_res.start)
 273                 release_resource(&dev_priv->mch_res);
 274 }
 275
 276 static int i915_driver_modeset_probe(struct drm_i915_private *i915)
 277 {
 278         int ret;
 279
 280         if (i915_inject_probe_failure(i915))
 281                 return -ENODEV;
 282
 283         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
 284                 ret = drm_vblank_init(&i915->drm,
 285                                       INTEL_NUM_PIPES(i915));
 286                 if (ret)
 287                         goto out;
 288         }
 289
 290         intel_bios_init(i915);
 291
 292         ret = intel_vga_register(i915);
 293         if (ret)
 294                 goto out;
 295
 296         intel_register_dsm_handler();
 297
 298         ret = i915_switcheroo_register(i915);
 299         if (ret)
 300                 goto cleanup_vga_client;
 301
 302         intel_power_domains_init_hw(i915, false);
 303
 304         intel_csr_ucode_init(i915);
 305
 306         ret = intel_irq_install(i915);
 307         if (ret)
 308                 goto cleanup_csr;
 309
 310         /* Important: The output setup functions called by modeset_init need
 311          * working irqs for e.g. gmbus and dp aux transfers. */
 312         ret = intel_modeset_init(i915);
 313         if (ret)
 314                 goto cleanup_irq;
 315
 316         ret = i915_gem_init(i915);
 317         if (ret)
 318                 goto cleanup_modeset;
 319
 320         intel_overlay_setup(i915);
 321
 322         if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
 323                 return 0;
 324
 325         ret = intel_fbdev_init(&i915->drm);
 326         if (ret)
 327                 goto cleanup_gem;
 328
 329         /* Only enable hotplug handling once the fbdev is fully set up. */
 330         intel_hpd_init(i915);
 331
 332         intel_init_ipc(i915);
 333
 334         intel_psr_set_force_mode_changed(i915->psr.dp);
 335
 336         return 0;
 337
 338 cleanup_gem:
 339         i915_gem_suspend(i915);
 340         i915_gem_driver_remove(i915);
 341         i915_gem_driver_release(i915);
 342 cleanup_modeset:
 343         intel_modeset_driver_remove(i915);
 344 cleanup_irq:
 345         intel_irq_uninstall(i915);
 346 cleanup_csr:
 347         intel_csr_ucode_fini(i915);
 348         intel_power_domains_driver_remove(i915);
 349         i915_switcheroo_unregister(i915);
 350 cleanup_vga_client:
 351         intel_vga_unregister(i915);
 352 out:
 353         return ret;
 354 }
 355
 356 static void i915_driver_modeset_remove(struct drm_i915_private *i915)
 357 {
 358         intel_modeset_driver_remove(i915);
 359
 360         intel_irq_uninstall(i915);
 361
 362         intel_bios_driver_remove(i915);
 363
 364         i915_switcheroo_unregister(i915);
 365
 366         intel_vga_unregister(i915);
 367
 368         intel_csr_ucode_fini(i915);
 369 }
 370
 371 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 372 {
 373         /*
 374          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 375          * CHV x1 PHY (DP/HDMI D)
 376          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 377          */
 378         if (IS_CHERRYVIEW(dev_priv)) {
 379                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 380                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 381         } else if (IS_VALLEYVIEW(dev_priv)) {
 382                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 383         }
 384 }
 385
 386 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 387 {
 388         /*
 389          * The i915 workqueue is primarily used for batched retirement of
 390          * requests (and thus managing bo) once the task has been completed
 391          * by the GPU. i915_retire_requests() is called directly when we
 392          * need high-priority retirement, such as waiting for an explicit
 393          * bo.
 394          *
 395          * It is also used for periodic low-priority events, such as
 396          * idle-timers and recording error state.
 397          *
 398          * All tasks on the workqueue are expected to acquire the dev mutex
 399          * so there is no point in running more than one instance of the
 400          * workqueue at any time.  Use an ordered one.
 401          */
 402         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 403         if (dev_priv->wq == NULL)
 404                 goto out_err;
 405
 406         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 407         if (dev_priv->hotplug.dp_wq == NULL)
 408                 goto out_free_wq;
 409
 410         return 0;
 411
 412 out_free_wq:
 413         destroy_workqueue(dev_priv->wq);
 414 out_err:
 415         DRM_ERROR("Failed to allocate workqueues.\n");
 416
 417         return -ENOMEM;
 418 }
 419
 420 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 421 {
 422         destroy_workqueue(dev_priv->hotplug.dp_wq);
 423         destroy_workqueue(dev_priv->wq);
 424 }
 425
 426 /*
 427  * We don't keep the workarounds for pre-production hardware, so we expect our
 428  * driver to fail on these machines in one way or another. A little warning on
 429  * dmesg may help both the user and the bug triagers.
 430  *
 431  * Our policy for removing pre-production workarounds is to keep the
 432  * current gen workarounds as a guide to the bring-up of the next gen
 433  * (workarounds have a habit of persisting!). Anything older than that
 434  * should be removed along with the complications they introduce.
 435  */
 436 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 437 {
 438         bool pre = false;
 439
 440         pre |= IS_HSW_EARLY_SDV(dev_priv);
 441         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 442         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 443         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 444
 445         if (pre) {
 446                 DRM_ERROR("This is a pre-production stepping. "
 447                           "It may not be fully functional.\n");
 448                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 449         }
 450 }
 451
 452 static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
 453 {
 454         if (!IS_VALLEYVIEW(i915))
 455                 return 0;
 456
 457         /* we write all the values in the struct, so no need to zero it out */
 458         i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
 459                                        GFP_KERNEL);
 460         if (!i915->vlv_s0ix_state)
 461                 return -ENOMEM;
 462
 463         return 0;
 464 }
 465
 466 static void vlv_free_s0ix_state(struct drm_i915_private *i915)
 467 {
 468         if (!i915->vlv_s0ix_state)
 469                 return;
 470
 471         kfree(i915->vlv_s0ix_state);
 472         i915->vlv_s0ix_state = NULL;
 473 }
 474
 475 static void sanitize_gpu(struct drm_i915_private *i915)
 476 {
 477         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 478                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 479 }
 480
 481 /**
 482  * i915_driver_early_probe - setup state not requiring device access
 483  * @dev_priv: device private
 484  *
 485  * Initialize everything that is a "SW-only" state, that is state not
 486  * requiring accessing the device or exposing the driver via kernel internal
 487  * or userspace interfaces. Example steps belonging here: lock initialization,
 488  * system memory allocation, setting up device specific attributes and
 489  * function hooks not requiring accessing the device.
 490  */
 491 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 492 {
 493         int ret = 0;
 494
 495         if (i915_inject_probe_failure(dev_priv))
 496                 return -ENODEV;
 497
 498         intel_device_info_subplatform_init(dev_priv);
 499
 500         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 501         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 502
 503         spin_lock_init(&dev_priv->irq_lock);
 504         spin_lock_init(&dev_priv->gpu_error.lock);
 505         mutex_init(&dev_priv->backlight_lock);
 506
 507         mutex_init(&dev_priv->sb_lock);
 508         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 509
 510         mutex_init(&dev_priv->av_mutex);
 511         mutex_init(&dev_priv->wm.wm_mutex);
 512         mutex_init(&dev_priv->pps_mutex);
 513         mutex_init(&dev_priv->hdcp_comp_mutex);
 514
 515         i915_memcpy_init_early(dev_priv);
 516         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 517
 518         ret = i915_workqueues_init(dev_priv);
 519         if (ret < 0)
 520                 return ret;
 521
 522         ret = vlv_alloc_s0ix_state(dev_priv);
 523         if (ret < 0)
 524                 goto err_workqueues;
 525
 526         intel_wopcm_init_early(&dev_priv->wopcm);
 527
 528         intel_gt_init_early(&dev_priv->gt, dev_priv);
 529
 530         i915_gem_init_early(dev_priv);
 531
 532         /* This must be called before any calls to HAS_PCH_* */
 533         intel_detect_pch(dev_priv);
 534
 535         intel_pm_setup(dev_priv);
 536         intel_init_dpio(dev_priv);
 537         ret = intel_power_domains_init(dev_priv);
 538         if (ret < 0)
 539                 goto err_gem;
 540         intel_irq_init(dev_priv);
 541         intel_init_display_hooks(dev_priv);
 542         intel_init_clock_gating_hooks(dev_priv);
 543         intel_init_audio_hooks(dev_priv);
 544         intel_display_crc_init(dev_priv);
 545
 546         intel_detect_preproduction_hw(dev_priv);
 547
 548         return 0;
 549
 550 err_gem:
 551         i915_gem_cleanup_early(dev_priv);
 552         intel_gt_driver_late_release(&dev_priv->gt);
 553         vlv_free_s0ix_state(dev_priv);
 554 err_workqueues:
 555         i915_workqueues_cleanup(dev_priv);
 556         return ret;
 557 }
 558
 559 /**
 560  * i915_driver_late_release - cleanup the setup done in
 561  *                             i915_driver_early_probe()
 562  * @dev_priv: device private
 563  */
 564 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 565 {
 566         intel_irq_fini(dev_priv);
 567         intel_power_domains_cleanup(dev_priv);
 568         i915_gem_cleanup_early(dev_priv);
 569         intel_gt_driver_late_release(&dev_priv->gt);
 570         vlv_free_s0ix_state(dev_priv);
 571         i915_workqueues_cleanup(dev_priv);
 572
 573         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 574         mutex_destroy(&dev_priv->sb_lock);
 575 }
 576
 577 /**
 578  * i915_driver_mmio_probe - setup device MMIO
 579  * @dev_priv: device private
 580  *
 581  * Setup minimal device state necessary for MMIO accesses later in the
 582  * initialization sequence. The setup here should avoid any other device-wide
 583  * side effects or exposing the driver via kernel internal or user space
 584  * interfaces.
 585  */
 586 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 587 {
 588         int ret;
 589
 590         if (i915_inject_probe_failure(dev_priv))
 591                 return -ENODEV;
 592
 593         if (i915_get_bridge_dev(dev_priv))
 594                 return -EIO;
 595
 596         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 597         if (ret < 0)
 598                 goto err_bridge;
 599
 600         /* Try to make sure MCHBAR is enabled before poking at it */
 601         intel_setup_mchbar(dev_priv);
 602
 603         intel_device_info_init_mmio(dev_priv);
 604
 605         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
 606
 607         intel_uc_init_mmio(&dev_priv->gt.uc);
 608
 609         ret = intel_engines_init_mmio(&dev_priv->gt);
 610         if (ret)
 611                 goto err_uncore;
 612
 613         /* As early as possible, scrub existing GPU state before clobbering */
 614         sanitize_gpu(dev_priv);
 615
 616         return 0;
 617
 618 err_uncore:
 619         intel_teardown_mchbar(dev_priv);
 620         intel_uncore_fini_mmio(&dev_priv->uncore);
 621 err_bridge:
 622         pci_dev_put(dev_priv->bridge_dev);
 623
 624         return ret;
 625 }
 626
 627 /**
 628  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 629  * @dev_priv: device private
 630  */
 631 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 632 {
 633         intel_teardown_mchbar(dev_priv);
 634         intel_uncore_fini_mmio(&dev_priv->uncore);
 635         pci_dev_put(dev_priv->bridge_dev);
 636 }
 637
 638 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 639 {
 640         intel_gvt_sanitize_options(dev_priv);
 641 }
 642
 643 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
 644
 645 static const char *intel_dram_type_str(enum intel_dram_type type)
 646 {
 647         static const char * const str[] = {
 648                 DRAM_TYPE_STR(UNKNOWN),
 649                 DRAM_TYPE_STR(DDR3),
 650                 DRAM_TYPE_STR(DDR4),
 651                 DRAM_TYPE_STR(LPDDR3),
 652                 DRAM_TYPE_STR(LPDDR4),
 653         };
 654
 655         if (type >= ARRAY_SIZE(str))
 656                 type = INTEL_DRAM_UNKNOWN;
 657
 658         return str[type];
 659 }
 660
 661 #undef DRAM_TYPE_STR
 662
 663 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
 664 {
 665         return dimm->ranks * 64 / (dimm->width ?: 1);
 666 }
 667
 668 /* Returns total GB for the whole DIMM */
 669 static int skl_get_dimm_size(u16 val)
 670 {
 671         return val & SKL_DRAM_SIZE_MASK;
 672 }
 673
 674 static int skl_get_dimm_width(u16 val)
 675 {
 676         if (skl_get_dimm_size(val) == 0)
 677                 return 0;
 678
 679         switch (val & SKL_DRAM_WIDTH_MASK) {
 680         case SKL_DRAM_WIDTH_X8:
 681         case SKL_DRAM_WIDTH_X16:
 682         case SKL_DRAM_WIDTH_X32:
 683                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
 684                 return 8 << val;
 685         default:
 686                 MISSING_CASE(val);
 687                 return 0;
 688         }
 689 }
 690
 691 static int skl_get_dimm_ranks(u16 val)
 692 {
 693         if (skl_get_dimm_size(val) == 0)
 694                 return 0;
 695
 696         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
 697
 698         return val + 1;
 699 }
 700
 701 /* Returns total GB for the whole DIMM */
 702 static int cnl_get_dimm_size(u16 val)
 703 {
 704         return (val & CNL_DRAM_SIZE_MASK) / 2;
 705 }
 706
 707 static int cnl_get_dimm_width(u16 val)
 708 {
 709         if (cnl_get_dimm_size(val) == 0)
 710                 return 0;
 711
 712         switch (val & CNL_DRAM_WIDTH_MASK) {
 713         case CNL_DRAM_WIDTH_X8:
 714         case CNL_DRAM_WIDTH_X16:
 715         case CNL_DRAM_WIDTH_X32:
 716                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
 717                 return 8 << val;
 718         default:
 719                 MISSING_CASE(val);
 720                 return 0;
 721         }
 722 }
 723
 724 static int cnl_get_dimm_ranks(u16 val)
 725 {
 726         if (cnl_get_dimm_size(val) == 0)
 727                 return 0;
 728
 729         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
 730
 731         return val + 1;
 732 }
 733
 734 static bool
 735 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
 736 {
 737         /* Convert total GB to Gb per DRAM device */
 738         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
 739 }
 740
 741 static void
 742 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
 743                        struct dram_dimm_info *dimm,
 744                        int channel, char dimm_name, u16 val)
 745 {
 746         if (INTEL_GEN(dev_priv) >= 10) {
 747                 dimm->size = cnl_get_dimm_size(val);
 748                 dimm->width = cnl_get_dimm_width(val);
 749                 dimm->ranks = cnl_get_dimm_ranks(val);
 750         } else {
 751                 dimm->size = skl_get_dimm_size(val);
 752                 dimm->width = skl_get_dimm_width(val);
 753                 dimm->ranks = skl_get_dimm_ranks(val);
 754         }
 755
 756         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
 757                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
 758                       yesno(skl_is_16gb_dimm(dimm)));
 759 }
 760
 761 static int
 762 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
 763                           struct dram_channel_info *ch,
 764                           int channel, u32 val)
 765 {
 766         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
 767                                channel, 'L', val & 0xffff);
 768         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
 769                                channel, 'S', val >> 16);
 770
 771         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
 772                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
 773                 return -EINVAL;
 774         }
 775
 776         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
 777                 ch->ranks = 2;
 778         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
 779                 ch->ranks = 2;
 780         else
 781                 ch->ranks = 1;
 782
 783         ch->is_16gb_dimm =
 784                 skl_is_16gb_dimm(&ch->dimm_l) ||
 785                 skl_is_16gb_dimm(&ch->dimm_s);
 786
 787         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
 788                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
 789
 790         return 0;
 791 }
 792
 793 static bool
 794 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
 795                         const struct dram_channel_info *ch1)
 796 {
 797         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
 798                 (ch0->dimm_s.size == 0 ||
 799                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
 800 }
 801
 802 static int
 803 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 804 {
 805         struct dram_info *dram_info = &dev_priv->dram_info;
 806         struct dram_channel_info ch0 = {}, ch1 = {};
 807         u32 val;
 808         int ret;
 809
 810         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 811         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
 812         if (ret == 0)
 813                 dram_info->num_channels++;
 814
 815         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 816         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
 817         if (ret == 0)
 818                 dram_info->num_channels++;
 819
 820         if (dram_info->num_channels == 0) {
 821                 DRM_INFO("Number of memory channels is zero\n");
 822                 return -EINVAL;
 823         }
 824
 825         /*
 826          * If any of the channel is single rank channel, worst case output
 827          * will be same as if single rank memory, so consider single rank
 828          * memory.
 829          */
 830         if (ch0.ranks == 1 || ch1.ranks == 1)
 831                 dram_info->ranks = 1;
 832         else
 833                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
 834
 835         if (dram_info->ranks == 0) {
 836                 DRM_INFO("couldn't get memory rank information\n");
 837                 return -EINVAL;
 838         }
 839
 840         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 841
 842         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
 843
 844         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
 845                       yesno(dram_info->symmetric_memory));
 846         return 0;
 847 }
 848
 849 static enum intel_dram_type
 850 skl_get_dram_type(struct drm_i915_private *dev_priv)
 851 {
 852         u32 val;
 853
 854         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 855
 856         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
 857         case SKL_DRAM_DDR_TYPE_DDR3:
 858                 return INTEL_DRAM_DDR3;
 859         case SKL_DRAM_DDR_TYPE_DDR4:
 860                 return INTEL_DRAM_DDR4;
 861         case SKL_DRAM_DDR_TYPE_LPDDR3:
 862                 return INTEL_DRAM_LPDDR3;
 863         case SKL_DRAM_DDR_TYPE_LPDDR4:
 864                 return INTEL_DRAM_LPDDR4;
 865         default:
 866                 MISSING_CASE(val);
 867                 return INTEL_DRAM_UNKNOWN;
 868         }
 869 }
 870
 871 static int
 872 skl_get_dram_info(struct drm_i915_private *dev_priv)
 873 {
 874         struct dram_info *dram_info = &dev_priv->dram_info;
 875         u32 mem_freq_khz, val;
 876         int ret;
 877
 878         dram_info->type = skl_get_dram_type(dev_priv);
 879         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
 880
 881         ret = skl_dram_get_channels_info(dev_priv);
 882         if (ret)
 883                 return ret;
 884
 885         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
 886         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
 887                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 888
 889         dram_info->bandwidth_kbps = dram_info->num_channels *
 890                                                         mem_freq_khz * 8;
 891
 892         if (dram_info->bandwidth_kbps == 0) {
 893                 DRM_INFO("Couldn't get system memory bandwidth\n");
 894                 return -EINVAL;
 895         }
 896
 897         dram_info->valid = true;
 898         return 0;
 899 }
 900
 901 /* Returns Gb per DRAM device */
 902 static int bxt_get_dimm_size(u32 val)
 903 {
 904         switch (val & BXT_DRAM_SIZE_MASK) {
 905         case BXT_DRAM_SIZE_4GBIT:
 906                 return 4;
 907         case BXT_DRAM_SIZE_6GBIT:
 908                 return 6;
 909         case BXT_DRAM_SIZE_8GBIT:
 910                 return 8;
 911         case BXT_DRAM_SIZE_12GBIT:
 912                 return 12;
 913         case BXT_DRAM_SIZE_16GBIT:
 914                 return 16;
 915         default:
 916                 MISSING_CASE(val);
 917                 return 0;
 918         }
 919 }
 920
 921 static int bxt_get_dimm_width(u32 val)
 922 {
 923         if (!bxt_get_dimm_size(val))
 924                 return 0;
 925
 926         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
 927
 928         return 8 << val;
 929 }
 930
 931 static int bxt_get_dimm_ranks(u32 val)
 932 {
 933         if (!bxt_get_dimm_size(val))
 934                 return 0;
 935
 936         switch (val & BXT_DRAM_RANK_MASK) {
 937         case BXT_DRAM_RANK_SINGLE:
 938                 return 1;
 939         case BXT_DRAM_RANK_DUAL:
 940                 return 2;
 941         default:
 942                 MISSING_CASE(val);
 943                 return 0;
 944         }
 945 }
 946
 947 static enum intel_dram_type bxt_get_dimm_type(u32 val)
 948 {
 949         if (!bxt_get_dimm_size(val))
 950                 return INTEL_DRAM_UNKNOWN;
 951
 952         switch (val & BXT_DRAM_TYPE_MASK) {
 953         case BXT_DRAM_TYPE_DDR3:
 954                 return INTEL_DRAM_DDR3;
 955         case BXT_DRAM_TYPE_LPDDR3:
 956                 return INTEL_DRAM_LPDDR3;
 957         case BXT_DRAM_TYPE_DDR4:
 958                 return INTEL_DRAM_DDR4;
 959         case BXT_DRAM_TYPE_LPDDR4:
 960                 return INTEL_DRAM_LPDDR4;
 961         default:
 962                 MISSING_CASE(val);
 963                 return INTEL_DRAM_UNKNOWN;
 964         }
 965 }
 966
 967 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
 968                               u32 val)
 969 {
 970         dimm->width = bxt_get_dimm_width(val);
 971         dimm->ranks = bxt_get_dimm_ranks(val);
 972
 973         /*
 974          * Size in register is Gb per DRAM device. Convert to total
 975          * GB to match the way we report this for non-LP platforms.
 976          */
 977         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
 978 }
 979
 980 static int
 981 bxt_get_dram_info(struct drm_i915_private *dev_priv)
 982 {
 983         struct dram_info *dram_info = &dev_priv->dram_info;
 984         u32 dram_channels;
 985         u32 mem_freq_khz, val;
 986         u8 num_active_channels;
 987         int i;
 988
 989         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
 990         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
 991                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 992
 993         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
 994         num_active_channels = hweight32(dram_channels);
 995
 996         /* Each active bit represents 4-byte channel */
 997         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
 998
 999         if (dram_info->bandwidth_kbps == 0) {
1000                 DRM_INFO("Couldn't get system memory bandwidth\n");
1001                 return -EINVAL;
1002         }
1003
1004         /*
1005          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1006          */
1007         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1008                 struct dram_dimm_info dimm;
1009                 enum intel_dram_type type;
1010
1011                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1012                 if (val == 0xFFFFFFFF)
1013                         continue;
1014
1015                 dram_info->num_channels++;
1016
1017                 bxt_get_dimm_info(&dimm, val);
1018                 type = bxt_get_dimm_type(val);
1019
1020                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1021                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1022                         dram_info->type != type);
1023
1024                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1025                               i - BXT_D_CR_DRP0_DUNIT_START,
1026                               dimm.size, dimm.width, dimm.ranks,
1027                               intel_dram_type_str(type));
1028
1029                 /*
1030                  * If any of the channel is single rank channel,
1031                  * worst case output will be same as if single rank
1032                  * memory, so consider single rank memory.
1033                  */
1034                 if (dram_info->ranks == 0)
1035                         dram_info->ranks = dimm.ranks;
1036                 else if (dimm.ranks == 1)
1037                         dram_info->ranks = 1;
1038
1039                 if (type != INTEL_DRAM_UNKNOWN)
1040                         dram_info->type = type;
1041         }
1042
1043         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1044             dram_info->ranks == 0) {
1045                 DRM_INFO("couldn't get memory information\n");
1046                 return -EINVAL;
1047         }
1048
1049         dram_info->valid = true;
1050         return 0;
1051 }
1052
1053 static void
1054 intel_get_dram_info(struct drm_i915_private *dev_priv)
1055 {
1056         struct dram_info *dram_info = &dev_priv->dram_info;
1057         int ret;
1058
1059         /*
1060          * Assume 16Gb DIMMs are present until proven otherwise.
1061          * This is only used for the level 0 watermark latency
1062          * w/a which does not apply to bxt/glk.
1063          */
1064         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1065
1066         if (INTEL_GEN(dev_priv) < 9 || !HAS_DISPLAY(dev_priv))
1067                 return;
1068
1069         if (IS_GEN9_LP(dev_priv))
1070                 ret = bxt_get_dram_info(dev_priv);
1071         else
1072                 ret = skl_get_dram_info(dev_priv);
1073         if (ret)
1074                 return;
1075
1076         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1077                       dram_info->bandwidth_kbps,
1078                       dram_info->num_channels);
1079
1080         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1081                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1082 }
1083
1084 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1085 {
1086         static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1087         static const u8 sets[4] = { 1, 1, 2, 2 };
1088
1089         return EDRAM_NUM_BANKS(cap) *
1090                 ways[EDRAM_WAYS_IDX(cap)] *
1091                 sets[EDRAM_SETS_IDX(cap)];
1092 }
1093
1094 static void edram_detect(struct drm_i915_private *dev_priv)
1095 {
1096         u32 edram_cap = 0;
1097
1098         if (!(IS_HASWELL(dev_priv) ||
1099               IS_BROADWELL(dev_priv) ||
1100               INTEL_GEN(dev_priv) >= 9))
1101                 return;
1102
1103         edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1104
1105         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1106
1107         if (!(edram_cap & EDRAM_ENABLED))
1108                 return;
1109
1110         /*
1111          * The needed capability bits for size calculation are not there with
1112          * pre gen9 so return 128MB always.
1113          */
1114         if (INTEL_GEN(dev_priv) < 9)
1115                 dev_priv->edram_size_mb = 128;
1116         else
1117                 dev_priv->edram_size_mb =
1118                         gen9_edram_size_mb(dev_priv, edram_cap);
1119
1120         dev_info(dev_priv->drm.dev,
1121                  "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1122 }
1123
1124 /**
1125  * i915_driver_hw_probe - setup state requiring device access
1126  * @dev_priv: device private
1127  *
1128  * Setup state that requires accessing the device, but doesn't require
1129  * exposing the driver via kernel internal or userspace interfaces.
1130  */
1131 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1132 {
1133         struct pci_dev *pdev = dev_priv->drm.pdev;
1134         int ret;
1135
1136         if (i915_inject_probe_failure(dev_priv))
1137                 return -ENODEV;
1138
1139         intel_device_info_runtime_init(dev_priv);
1140
1141         if (HAS_PPGTT(dev_priv)) {
1142                 if (intel_vgpu_active(dev_priv) &&
1143                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1144                         i915_report_error(dev_priv,
1145                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1146                         return -ENXIO;
1147                 }
1148         }
1149
1150         if (HAS_EXECLISTS(dev_priv)) {
1151                 /*
1152                  * Older GVT emulation depends upon intercepting CSB mmio,
1153                  * which we no longer use, preferring to use the HWSP cache
1154                  * instead.
1155                  */
1156                 if (intel_vgpu_active(dev_priv) &&
1157                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1158                         i915_report_error(dev_priv,
1159                                           "old vGPU host found, support for HWSP emulation required\n");
1160                         return -ENXIO;
1161                 }
1162         }
1163
1164         intel_sanitize_options(dev_priv);
1165
1166         /* needs to be done before ggtt probe */
1167         edram_detect(dev_priv);
1168
1169         i915_perf_init(dev_priv);
1170
1171         ret = i915_ggtt_probe_hw(dev_priv);
1172         if (ret)
1173                 goto err_perf;
1174
1175         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
1176         if (ret)
1177                 goto err_ggtt;
1178
1179         ret = i915_ggtt_init_hw(dev_priv);
1180         if (ret)
1181                 goto err_ggtt;
1182
1183         ret = intel_memory_regions_hw_probe(dev_priv);
1184         if (ret)
1185                 goto err_ggtt;
1186
1187         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
1188
1189         ret = i915_ggtt_enable_hw(dev_priv);
1190         if (ret) {
1191                 DRM_ERROR("failed to enable GGTT\n");
1192                 goto err_mem_regions;
1193         }
1194
1195         pci_set_master(pdev);
1196
1197         /*
1198          * We don't have a max segment size, so set it to the max so sg's
1199          * debugging layer doesn't complain
1200          */
1201         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1202
1203         /* overlay on gen2 is broken and can't address above 1G */
1204         if (IS_GEN(dev_priv, 2)) {
1205                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1206                 if (ret) {
1207                         DRM_ERROR("failed to set DMA mask\n");
1208
1209                         goto err_mem_regions;
1210                 }
1211         }
1212
1213         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1214          * using 32bit addressing, overwriting memory if HWS is located
1215          * above 4GB.
1216          *
1217          * The documentation also mentions an issue with undefined
1218          * behaviour if any general state is accessed within a page above 4GB,
1219          * which also needs to be handled carefully.
1220          */
1221         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1222                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1223
1224                 if (ret) {
1225                         DRM_ERROR("failed to set DMA mask\n");
1226
1227                         goto err_mem_regions;
1228                 }
1229         }
1230
1231         cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1232
1233         intel_gt_init_workarounds(dev_priv);
1234
1235         /* On the 945G/GM, the chipset reports the MSI capability on the
1236          * integrated graphics even though the support isn't actually there
1237          * according to the published specs.  It doesn't appear to function
1238          * correctly in testing on 945G.
1239          * This may be a side effect of MSI having been made available for PEG
1240          * and the registers being closely associated.
1241          *
1242          * According to chipset errata, on the 965GM, MSI interrupts may
1243          * be lost or delayed, and was defeatured. MSI interrupts seem to
1244          * get lost on g4x as well, and interrupt delivery seems to stay
1245          * properly dead afterwards. So we'll just disable them for all
1246          * pre-gen5 chipsets.
1247          *
1248          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1249          * interrupts even when in MSI mode. This results in spurious
1250          * interrupt warnings if the legacy irq no. is shared with another
1251          * device. The kernel then disables that interrupt source and so
1252          * prevents the other device from working properly.
1253          */
1254         if (INTEL_GEN(dev_priv) >= 5) {
1255                 if (pci_enable_msi(pdev) < 0)
1256                         DRM_DEBUG_DRIVER("can't enable MSI");
1257         }
1258
1259         ret = intel_gvt_init(dev_priv);
1260         if (ret)
1261                 goto err_msi;
1262
1263         intel_opregion_setup(dev_priv);
1264         /*
1265          * Fill the dram structure to get the system raw bandwidth and
1266          * dram info. This will be used for memory latency calculation.
1267          */
1268         intel_get_dram_info(dev_priv);
1269
1270         intel_bw_init_hw(dev_priv);
1271
1272         return 0;
1273
1274 err_msi:
1275         if (pdev->msi_enabled)
1276                 pci_disable_msi(pdev);
1277         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
1278 err_mem_regions:
1279         intel_memory_regions_driver_release(dev_priv);
1280 err_ggtt:
1281         i915_ggtt_driver_release(dev_priv);
1282 err_perf:
1283         i915_perf_fini(dev_priv);
1284         return ret;
1285 }
1286
1287 /**
1288  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1289  * @dev_priv: device private
1290  */
1291 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1292 {
1293         struct pci_dev *pdev = dev_priv->drm.pdev;
1294
1295         i915_perf_fini(dev_priv);
1296
1297         if (pdev->msi_enabled)
1298                 pci_disable_msi(pdev);
1299
1300         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
1301 }
1302
1303 /**
1304  * i915_driver_register - register the driver with the rest of the system
1305  * @dev_priv: device private
1306  *
1307  * Perform any steps necessary to make the driver available via kernel
1308  * internal or userspace interfaces.
1309  */
1310 static void i915_driver_register(struct drm_i915_private *dev_priv)
1311 {
1312         struct drm_device *dev = &dev_priv->drm;
1313
1314         i915_gem_driver_register(dev_priv);
1315         i915_pmu_register(dev_priv);
1316
1317         /*
1318          * Notify a valid surface after modesetting,
1319          * when running inside a VM.
1320          */
1321         if (intel_vgpu_active(dev_priv))
1322                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1323
1324         /* Reveal our presence to userspace */
1325         if (drm_dev_register(dev, 0) == 0) {
1326                 i915_debugfs_register(dev_priv);
1327                 i915_setup_sysfs(dev_priv);
1328
1329                 /* Depends on sysfs having been initialized */
1330                 i915_perf_register(dev_priv);
1331         } else
1332                 DRM_ERROR("Failed to register driver for userspace access!\n");
1333
1334         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
1335                 /* Must be done after probing outputs */
1336                 intel_opregion_register(dev_priv);
1337                 acpi_video_register();
1338         }
1339
1340         intel_gt_driver_register(&dev_priv->gt);
1341
1342         intel_audio_init(dev_priv);
1343
1344         /*
1345          * Some ports require correctly set-up hpd registers for detection to
1346          * work properly (leading to ghost connected connector status), e.g. VGA
1347          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1348          * irqs are fully enabled. We do it last so that the async config
1349          * cannot run before the connectors are registered.
1350          */
1351         intel_fbdev_initial_config_async(dev);
1352
1353         /*
1354          * We need to coordinate the hotplugs with the asynchronous fbdev
1355          * configuration, for which we use the fbdev->async_cookie.
1356          */
1357         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
1358                 drm_kms_helper_poll_init(dev);
1359
1360         intel_power_domains_enable(dev_priv);
1361         intel_runtime_pm_enable(&dev_priv->runtime_pm);
1362 }
1363
1364 /**
1365  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1366  * @dev_priv: device private
1367  */
1368 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1369 {
1370         intel_runtime_pm_disable(&dev_priv->runtime_pm);
1371         intel_power_domains_disable(dev_priv);
1372
1373         intel_fbdev_unregister(dev_priv);
1374         intel_audio_deinit(dev_priv);
1375
1376         /*
1377          * After flushing the fbdev (incl. a late async config which will
1378          * have delayed queuing of a hotplug event), then flush the hotplug
1379          * events.
1380          */
1381         drm_kms_helper_poll_fini(&dev_priv->drm);
1382
1383         intel_gt_driver_unregister(&dev_priv->gt);
1384         acpi_video_unregister();
1385         intel_opregion_unregister(dev_priv);
1386
1387         i915_perf_unregister(dev_priv);
1388         i915_pmu_unregister(dev_priv);
1389
1390         i915_teardown_sysfs(dev_priv);
1391         drm_dev_unplug(&dev_priv->drm);
1392
1393         i915_gem_driver_unregister(dev_priv);
1394 }
1395
1396 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1397 {
1398         if (drm_debug_enabled(DRM_UT_DRIVER)) {
1399                 struct drm_printer p = drm_debug_printer("i915 device info:");
1400
1401                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1402                            INTEL_DEVID(dev_priv),
1403                            INTEL_REVID(dev_priv),
1404                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1405                            intel_subplatform(RUNTIME_INFO(dev_priv),
1406                                              INTEL_INFO(dev_priv)->platform),
1407                            INTEL_GEN(dev_priv));
1408
1409                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
1410                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
1411         }
1412
1413         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1414                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1415         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1416                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1417         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1418                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1419 }
1420
1421 static struct drm_i915_private *
1422 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1423 {
1424         const struct intel_device_info *match_info =
1425                 (struct intel_device_info *)ent->driver_data;
1426         struct intel_device_info *device_info;
1427         struct drm_i915_private *i915;
1428         int err;
1429
1430         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1431         if (!i915)
1432                 return ERR_PTR(-ENOMEM);
1433
1434         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1435         if (err) {
1436                 kfree(i915);
1437                 return ERR_PTR(err);
1438         }
1439
1440         i915->drm.dev_private = i915;
1441
1442         i915->drm.pdev = pdev;
1443         pci_set_drvdata(pdev, i915);
1444
1445         /* Setup the write-once "constant" device info */
1446         device_info = mkwrite_device_info(i915);
1447         memcpy(device_info, match_info, sizeof(*device_info));
1448         RUNTIME_INFO(i915)->device_id = pdev->device;
1449
1450         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1451
1452         return i915;
1453 }
1454
1455 static void i915_driver_destroy(struct drm_i915_private *i915)
1456 {
1457         struct pci_dev *pdev = i915->drm.pdev;
1458
1459         drm_dev_fini(&i915->drm);
1460         kfree(i915);
1461
1462         /* And make sure we never chase our dangling pointer from pci_dev */
1463         pci_set_drvdata(pdev, NULL);
1464 }
1465
1466 /**
1467  * i915_driver_probe - setup chip and create an initial config
1468  * @pdev: PCI device
1469  * @ent: matching PCI ID entry
1470  *
1471  * The driver probe routine has to do several things:
1472  *   - drive output discovery via intel_modeset_init()
1473  *   - initialize the memory manager
1474  *   - allocate initial config memory
1475  *   - setup the DRM framebuffer with the allocated memory
1476  */
1477 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1478 {
1479         const struct intel_device_info *match_info =
1480                 (struct intel_device_info *)ent->driver_data;
1481         struct drm_i915_private *dev_priv;
1482         int ret;
1483
1484         dev_priv = i915_driver_create(pdev, ent);
1485         if (IS_ERR(dev_priv))
1486                 return PTR_ERR(dev_priv);
1487
1488         /* Disable nuclear pageflip by default on pre-ILK */
1489         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1490                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1491
1492         /*
1493          * Check if we support fake LMEM -- for now we only unleash this for
1494          * the live selftests(test-and-exit).
1495          */
1496 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1497         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
1498                 if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live < 0 &&
1499                     i915_modparams.fake_lmem_start) {
1500                         mkwrite_device_info(dev_priv)->memory_regions =
1501                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
1502                         mkwrite_device_info(dev_priv)->is_dgfx = true;
1503                         GEM_BUG_ON(!HAS_LMEM(dev_priv));
1504                         GEM_BUG_ON(!IS_DGFX(dev_priv));
1505                 }
1506         }
1507 #endif
1508
1509         ret = pci_enable_device(pdev);
1510         if (ret)
1511                 goto out_fini;
1512
1513         ret = i915_driver_early_probe(dev_priv);
1514         if (ret < 0)
1515                 goto out_pci_disable;
1516
1517         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1518
1519         i915_detect_vgpu(dev_priv);
1520
1521         ret = i915_driver_mmio_probe(dev_priv);
1522         if (ret < 0)
1523                 goto out_runtime_pm_put;
1524
1525         ret = i915_driver_hw_probe(dev_priv);
1526         if (ret < 0)
1527                 goto out_cleanup_mmio;
1528
1529         ret = i915_driver_modeset_probe(dev_priv);
1530         if (ret < 0)
1531                 goto out_cleanup_hw;
1532
1533         i915_driver_register(dev_priv);
1534
1535         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1536
1537         i915_welcome_messages(dev_priv);
1538
1539         return 0;
1540
1541 out_cleanup_hw:
1542         i915_driver_hw_remove(dev_priv);
1543         intel_memory_regions_driver_release(dev_priv);
1544         i915_ggtt_driver_release(dev_priv);
1545 out_cleanup_mmio:
1546         i915_driver_mmio_release(dev_priv);
1547 out_runtime_pm_put:
1548         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1549         i915_driver_late_release(dev_priv);
1550 out_pci_disable:
1551         pci_disable_device(pdev);
1552 out_fini:
1553         i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
1554         i915_driver_destroy(dev_priv);
1555         return ret;
1556 }
1557
1558 void i915_driver_remove(struct drm_i915_private *i915)
1559 {
1560         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1561
1562         i915_driver_unregister(i915);
1563
1564         /*
1565          * After unregistering the device to prevent any new users, cancel
1566          * all in-flight requests so that we can quickly unbind the active
1567          * resources.
1568          */
1569         intel_gt_set_wedged(&i915->gt);
1570
1571         /* Flush any external code that still may be under the RCU lock */
1572         synchronize_rcu();
1573
1574         i915_gem_suspend(i915);
1575
1576         drm_atomic_helper_shutdown(&i915->drm);
1577
1578         intel_gvt_driver_remove(i915);
1579
1580         i915_driver_modeset_remove(i915);
1581
1582         i915_reset_error_state(i915);
1583         i915_gem_driver_remove(i915);
1584
1585         intel_power_domains_driver_remove(i915);
1586
1587         i915_driver_hw_remove(i915);
1588
1589         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1590 }
1591
1592 static void i915_driver_release(struct drm_device *dev)
1593 {
1594         struct drm_i915_private *dev_priv = to_i915(dev);
1595         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1596
1597         disable_rpm_wakeref_asserts(rpm);
1598
1599         i915_gem_driver_release(dev_priv);
1600
1601         intel_memory_regions_driver_release(dev_priv);
1602         i915_ggtt_driver_release(dev_priv);
1603
1604         i915_driver_mmio_release(dev_priv);
1605
1606         enable_rpm_wakeref_asserts(rpm);
1607         intel_runtime_pm_driver_release(rpm);
1608
1609         i915_driver_late_release(dev_priv);
1610         i915_driver_destroy(dev_priv);
1611 }
1612
1613 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1614 {
1615         struct drm_i915_private *i915 = to_i915(dev);
1616         int ret;
1617
1618         ret = i915_gem_open(i915, file);
1619         if (ret)
1620                 return ret;
1621
1622         return 0;
1623 }
1624
1625 /**
1626  * i915_driver_lastclose - clean up after all DRM clients have exited
1627  * @dev: DRM device
1628  *
1629  * Take care of cleaning up after all DRM clients have exited.  In the
1630  * mode setting case, we want to restore the kernel's initial mode (just
1631  * in case the last client left us in a bad state).
1632  *
1633  * Additionally, in the non-mode setting case, we'll tear down the GTT
1634  * and DMA structures, since the kernel won't be using them, and clea
1635  * up any GEM state.
1636  */
1637 static void i915_driver_lastclose(struct drm_device *dev)
1638 {
1639         intel_fbdev_restore_mode(dev);
1640         vga_switcheroo_process_delayed_switch();
1641 }
1642
1643 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1644 {
1645         struct drm_i915_file_private *file_priv = file->driver_priv;
1646
1647         i915_gem_context_close(file);
1648         i915_gem_release(dev, file);
1649
1650         kfree_rcu(file_priv, rcu);
1651
1652         /* Catch up with all the deferred frees from "this" client */
1653         i915_gem_flush_free_objects(to_i915(dev));
1654 }
1655
1656 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1657 {
1658         struct drm_device *dev = &dev_priv->drm;
1659         struct intel_encoder *encoder;
1660
1661         drm_modeset_lock_all(dev);
1662         for_each_intel_encoder(dev, encoder)
1663                 if (encoder->suspend)
1664                         encoder->suspend(encoder);
1665         drm_modeset_unlock_all(dev);
1666 }
1667
1668 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1669                               bool rpm_resume);
1670 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1671
1672 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1673 {
1674 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1675         if (acpi_target_system_state() < ACPI_STATE_S3)
1676                 return true;
1677 #endif
1678         return false;
1679 }
1680
1681 static int i915_drm_prepare(struct drm_device *dev)
1682 {
1683         struct drm_i915_private *i915 = to_i915(dev);
1684
1685         /*
1686          * NB intel_display_suspend() may issue new requests after we've
1687          * ostensibly marked the GPU as ready-to-sleep here. We need to
1688          * split out that work and pull it forward so that after point,
1689          * the GPU is not woken again.
1690          */
1691         i915_gem_suspend(i915);
1692
1693         return 0;
1694 }
1695
1696 static int i915_drm_suspend(struct drm_device *dev)
1697 {
1698         struct drm_i915_private *dev_priv = to_i915(dev);
1699         struct pci_dev *pdev = dev_priv->drm.pdev;
1700         pci_power_t opregion_target_state;
1701
1702         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1703
1704         /* We do a lot of poking in a lot of registers, make sure they work
1705          * properly. */
1706         intel_power_domains_disable(dev_priv);
1707
1708         drm_kms_helper_poll_disable(dev);
1709
1710         pci_save_state(pdev);
1711
1712         intel_display_suspend(dev);
1713
1714         intel_dp_mst_suspend(dev_priv);
1715
1716         intel_runtime_pm_disable_interrupts(dev_priv);
1717         intel_hpd_cancel_work(dev_priv);
1718
1719         intel_suspend_encoders(dev_priv);
1720
1721         intel_suspend_hw(dev_priv);
1722
1723         i915_gem_suspend_gtt_mappings(dev_priv);
1724
1725         i915_save_state(dev_priv);
1726
1727         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1728         intel_opregion_suspend(dev_priv, opregion_target_state);
1729
1730         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1731
1732         dev_priv->suspend_count++;
1733
1734         intel_csr_ucode_suspend(dev_priv);
1735
1736         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1737
1738         return 0;
1739 }
1740
1741 static enum i915_drm_suspend_mode
1742 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1743 {
1744         if (hibernate)
1745                 return I915_DRM_SUSPEND_HIBERNATE;
1746
1747         if (suspend_to_idle(dev_priv))
1748                 return I915_DRM_SUSPEND_IDLE;
1749
1750         return I915_DRM_SUSPEND_MEM;
1751 }
1752
1753 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1754 {
1755         struct drm_i915_private *dev_priv = to_i915(dev);
1756         struct pci_dev *pdev = dev_priv->drm.pdev;
1757         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1758         int ret = 0;
1759
1760         disable_rpm_wakeref_asserts(rpm);
1761
1762         i915_gem_suspend_late(dev_priv);
1763
1764         intel_uncore_suspend(&dev_priv->uncore);
1765
1766         intel_power_domains_suspend(dev_priv,
1767                                     get_suspend_mode(dev_priv, hibernation));
1768
1769         intel_display_power_suspend_late(dev_priv);
1770
1771         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1772                 ret = vlv_suspend_complete(dev_priv);
1773
1774         if (ret) {
1775                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1776                 intel_power_domains_resume(dev_priv);
1777
1778                 goto out;
1779         }
1780
1781         pci_disable_device(pdev);
1782         /*
1783          * During hibernation on some platforms the BIOS may try to access
1784          * the device even though it's already in D3 and hang the machine. So
1785          * leave the device in D0 on those platforms and hope the BIOS will
1786          * power down the device properly. The issue was seen on multiple old
1787          * GENs with different BIOS vendors, so having an explicit blacklist
1788          * is inpractical; apply the workaround on everything pre GEN6. The
1789          * platforms where the issue was seen:
1790          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1791          * Fujitsu FSC S7110
1792          * Acer Aspire 1830T
1793          */
1794         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1795                 pci_set_power_state(pdev, PCI_D3hot);
1796
1797 out:
1798         enable_rpm_wakeref_asserts(rpm);
1799         if (!dev_priv->uncore.user_forcewake_count)
1800                 intel_runtime_pm_driver_release(rpm);
1801
1802         return ret;
1803 }
1804
1805 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1806 {
1807         int error;
1808
1809         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1810                          state.event != PM_EVENT_FREEZE))
1811                 return -EINVAL;
1812
1813         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1814                 return 0;
1815
1816         error = i915_drm_suspend(&i915->drm);
1817         if (error)
1818                 return error;
1819
1820         return i915_drm_suspend_late(&i915->drm, false);
1821 }
1822
1823 static int i915_drm_resume(struct drm_device *dev)
1824 {
1825         struct drm_i915_private *dev_priv = to_i915(dev);
1826         int ret;
1827
1828         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1829
1830         sanitize_gpu(dev_priv);
1831
1832         ret = i915_ggtt_enable_hw(dev_priv);
1833         if (ret)
1834                 DRM_ERROR("failed to re-enable GGTT\n");
1835
1836         i915_gem_restore_gtt_mappings(dev_priv);
1837         i915_gem_restore_fences(&dev_priv->ggtt);
1838
1839         intel_csr_ucode_resume(dev_priv);
1840
1841         i915_restore_state(dev_priv);
1842         intel_pps_unlock_regs_wa(dev_priv);
1843
1844         intel_init_pch_refclk(dev_priv);
1845
1846         /*
1847          * Interrupts have to be enabled before any batches are run. If not the
1848          * GPU will hang. i915_gem_init_hw() will initiate batches to
1849          * update/restore the context.
1850          *
1851          * drm_mode_config_reset() needs AUX interrupts.
1852          *
1853          * Modeset enabling in intel_modeset_init_hw() also needs working
1854          * interrupts.
1855          */
1856         intel_runtime_pm_enable_interrupts(dev_priv);
1857
1858         drm_mode_config_reset(dev);
1859
1860         i915_gem_resume(dev_priv);
1861
1862         intel_modeset_init_hw(dev_priv);
1863         intel_init_clock_gating(dev_priv);
1864
1865         spin_lock_irq(&dev_priv->irq_lock);
1866         if (dev_priv->display.hpd_irq_setup)
1867                 dev_priv->display.hpd_irq_setup(dev_priv);
1868         spin_unlock_irq(&dev_priv->irq_lock);
1869
1870         intel_dp_mst_resume(dev_priv);
1871
1872         intel_display_resume(dev);
1873
1874         drm_kms_helper_poll_enable(dev);
1875
1876         /*
1877          * ... but also need to make sure that hotplug processing
1878          * doesn't cause havoc. Like in the driver load code we don't
1879          * bother with the tiny race here where we might lose hotplug
1880          * notifications.
1881          * */
1882         intel_hpd_init(dev_priv);
1883
1884         intel_opregion_resume(dev_priv);
1885
1886         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1887
1888         intel_power_domains_enable(dev_priv);
1889
1890         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1891
1892         return 0;
1893 }
1894
1895 static int i915_drm_resume_early(struct drm_device *dev)
1896 {
1897         struct drm_i915_private *dev_priv = to_i915(dev);
1898         struct pci_dev *pdev = dev_priv->drm.pdev;
1899         int ret;
1900
1901         /*
1902          * We have a resume ordering issue with the snd-hda driver also
1903          * requiring our device to be power up. Due to the lack of a
1904          * parent/child relationship we currently solve this with an early
1905          * resume hook.
1906          *
1907          * FIXME: This should be solved with a special hdmi sink device or
1908          * similar so that power domains can be employed.
1909          */
1910
1911         /*
1912          * Note that we need to set the power state explicitly, since we
1913          * powered off the device during freeze and the PCI core won't power
1914          * it back up for us during thaw. Powering off the device during
1915          * freeze is not a hard requirement though, and during the
1916          * suspend/resume phases the PCI core makes sure we get here with the
1917          * device powered on. So in case we change our freeze logic and keep
1918          * the device powered we can also remove the following set power state
1919          * call.
1920          */
1921         ret = pci_set_power_state(pdev, PCI_D0);
1922         if (ret) {
1923                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1924                 return ret;
1925         }
1926
1927         /*
1928          * Note that pci_enable_device() first enables any parent bridge
1929          * device and only then sets the power state for this device. The
1930          * bridge enabling is a nop though, since bridge devices are resumed
1931          * first. The order of enabling power and enabling the device is
1932          * imposed by the PCI core as described above, so here we preserve the
1933          * same order for the freeze/thaw phases.
1934          *
1935          * TODO: eventually we should remove pci_disable_device() /
1936          * pci_enable_enable_device() from suspend/resume. Due to how they
1937          * depend on the device enable refcount we can't anyway depend on them
1938          * disabling/enabling the device.
1939          */
1940         if (pci_enable_device(pdev))
1941                 return -EIO;
1942
1943         pci_set_master(pdev);
1944
1945         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1946
1947         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1948                 ret = vlv_resume_prepare(dev_priv, false);
1949         if (ret)
1950                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1951                           ret);
1952
1953         intel_uncore_resume_early(&dev_priv->uncore);
1954
1955         intel_gt_check_and_clear_faults(&dev_priv->gt);
1956
1957         intel_display_power_resume_early(dev_priv);
1958
1959         intel_power_domains_resume(dev_priv);
1960
1961         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1962
1963         return ret;
1964 }
1965
1966 int i915_resume_switcheroo(struct drm_i915_private *i915)
1967 {
1968         int ret;
1969
1970         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1971                 return 0;
1972
1973         ret = i915_drm_resume_early(&i915->drm);
1974         if (ret)
1975                 return ret;
1976
1977         return i915_drm_resume(&i915->drm);
1978 }
1979
1980 static int i915_pm_prepare(struct device *kdev)
1981 {
1982         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1983
1984         if (!i915) {
1985                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1986                 return -ENODEV;
1987         }
1988
1989         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1990                 return 0;
1991
1992         return i915_drm_prepare(&i915->drm);
1993 }
1994
1995 static int i915_pm_suspend(struct device *kdev)
1996 {
1997         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1998
1999         if (!i915) {
2000                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2001                 return -ENODEV;
2002         }
2003
2004         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2005                 return 0;
2006
2007         return i915_drm_suspend(&i915->drm);
2008 }
2009
2010 static int i915_pm_suspend_late(struct device *kdev)
2011 {
2012         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2013
2014         /*
2015          * We have a suspend ordering issue with the snd-hda driver also
2016          * requiring our device to be power up. Due to the lack of a
2017          * parent/child relationship we currently solve this with an late
2018          * suspend hook.
2019          *
2020          * FIXME: This should be solved with a special hdmi sink device or
2021          * similar so that power domains can be employed.
2022          */
2023         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2024                 return 0;
2025
2026         return i915_drm_suspend_late(&i915->drm, false);
2027 }
2028
2029 static int i915_pm_poweroff_late(struct device *kdev)
2030 {
2031         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2032
2033         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2034                 return 0;
2035
2036         return i915_drm_suspend_late(&i915->drm, true);
2037 }
2038
2039 static int i915_pm_resume_early(struct device *kdev)
2040 {
2041         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2042
2043         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2044                 return 0;
2045
2046         return i915_drm_resume_early(&i915->drm);
2047 }
2048
2049 static int i915_pm_resume(struct device *kdev)
2050 {
2051         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2052
2053         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2054                 return 0;
2055
2056         return i915_drm_resume(&i915->drm);
2057 }
2058
2059 /* freeze: before creating the hibernation_image */
2060 static int i915_pm_freeze(struct device *kdev)
2061 {
2062         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2063         int ret;
2064
2065         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2066                 ret = i915_drm_suspend(&i915->drm);
2067                 if (ret)
2068                         return ret;
2069         }
2070
2071         ret = i915_gem_freeze(i915);
2072         if (ret)
2073                 return ret;
2074
2075         return 0;
2076 }
2077
2078 static int i915_pm_freeze_late(struct device *kdev)
2079 {
2080         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2081         int ret;
2082
2083         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2084                 ret = i915_drm_suspend_late(&i915->drm, true);
2085                 if (ret)
2086                         return ret;
2087         }
2088
2089         ret = i915_gem_freeze_late(i915);
2090         if (ret)
2091                 return ret;
2092
2093         return 0;
2094 }
2095
2096 /* thaw: called after creating the hibernation image, but before turning off. */
2097 static int i915_pm_thaw_early(struct device *kdev)
2098 {
2099         return i915_pm_resume_early(kdev);
2100 }
2101
2102 static int i915_pm_thaw(struct device *kdev)
2103 {
2104         return i915_pm_resume(kdev);
2105 }
2106
2107 /* restore: called after loading the hibernation image. */
2108 static int i915_pm_restore_early(struct device *kdev)
2109 {
2110         return i915_pm_resume_early(kdev);
2111 }
2112
2113 static int i915_pm_restore(struct device *kdev)
2114 {
2115         return i915_pm_resume(kdev);
2116 }
2117
2118 /*
2119  * Save all Gunit registers that may be lost after a D3 and a subsequent
2120  * S0i[R123] transition. The list of registers needing a save/restore is
2121  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2122  * registers in the following way:
2123  * - Driver: saved/restored by the driver
2124  * - Punit : saved/restored by the Punit firmware
2125  * - No, w/o marking: no need to save/restore, since the register is R/O or
2126  *                    used internally by the HW in a way that doesn't depend
2127  *                    keeping the content across a suspend/resume.
2128  * - Debug : used for debugging
2129  *
2130  * We save/restore all registers marked with 'Driver', with the following
2131  * exceptions:
2132  * - Registers out of use, including also registers marked with 'Debug'.
2133  *   These have no effect on the driver's operation, so we don't save/restore
2134  *   them to reduce the overhead.
2135  * - Registers that are fully setup by an initialization function called from
2136  *   the resume path. For example many clock gating and RPS/RC6 registers.
2137  * - Registers that provide the right functionality with their reset defaults.
2138  *
2139  * TODO: Except for registers that based on the above 3 criteria can be safely
2140  * ignored, we save/restore all others, practically treating the HW context as
2141  * a black-box for the driver. Further investigation is needed to reduce the
2142  * saved/restored registers even further, by following the same 3 criteria.
2143  */
2144 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2145 {
2146         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2147         int i;
2148
2149         if (!s)
2150                 return;
2151
2152         /* GAM 0x4000-0x4770 */
2153         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2154         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2155         s->arb_mode             = I915_READ(ARB_MODE);
2156         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2157         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2158
2159         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2160                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2161
2162         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2163         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2164
2165         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2166         s->ecochk               = I915_READ(GAM_ECOCHK);
2167         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2168         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2169
2170         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2171
2172         /* MBC 0x9024-0x91D0, 0x8500 */
2173         s->g3dctl               = I915_READ(VLV_G3DCTL);
2174         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2175         s->mbctl                = I915_READ(GEN6_MBCTL);
2176
2177         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2178         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2179         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2180         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2181         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2182         s->rstctl               = I915_READ(GEN6_RSTCTL);
2183         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2184
2185         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2186         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2187         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2188         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2189         s->ecobus               = I915_READ(ECOBUS);
2190         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2191         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2192         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2193         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2194         s->rcedata              = I915_READ(VLV_RCEDATA);
2195         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2196
2197         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2198         s->gt_imr               = I915_READ(GTIMR);
2199         s->gt_ier               = I915_READ(GTIER);
2200         s->pm_imr               = I915_READ(GEN6_PMIMR);
2201         s->pm_ier               = I915_READ(GEN6_PMIER);
2202
2203         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2204                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2205
2206         /* GT SA CZ domain, 0x100000-0x138124 */
2207         s->tilectl              = I915_READ(TILECTL);
2208         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2209         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2210         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2211         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2212
2213         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2214         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2215         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2216         s->pcbr                 = I915_READ(VLV_PCBR);
2217         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2218
2219         /*
2220          * Not saving any of:
2221          * DFT,         0x9800-0x9EC0
2222          * SARB,        0xB000-0xB1FC
2223          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2224          * PCI CFG
2225          */
2226 }
2227
2228 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2229 {
2230         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2231         u32 val;
2232         int i;
2233
2234         if (!s)
2235                 return;
2236
2237         /* GAM 0x4000-0x4770 */
2238         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2239         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2240         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2241         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2242         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2243
2244         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2245                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2246
2247         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2248         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2249
2250         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2251         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2252         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2253         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2254
2255         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2256
2257         /* MBC 0x9024-0x91D0, 0x8500 */
2258         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2259         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2260         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2261
2262         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2263         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2264         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2265         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2266         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2267         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2268         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2269
2270         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2271         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2272         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2273         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2274         I915_WRITE(ECOBUS,              s->ecobus);
2275         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2276         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2277         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2278         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2279         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2280         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2281
2282         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2283         I915_WRITE(GTIMR,               s->gt_imr);
2284         I915_WRITE(GTIER,               s->gt_ier);
2285         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2286         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2287
2288         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2289                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2290
2291         /* GT SA CZ domain, 0x100000-0x138124 */
2292         I915_WRITE(TILECTL,                     s->tilectl);
2293         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2294         /*
2295          * Preserve the GT allow wake and GFX force clock bit, they are not
2296          * be restored, as they are used to control the s0ix suspend/resume
2297          * sequence by the caller.
2298          */
2299         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2300         val &= VLV_GTLC_ALLOWWAKEREQ;
2301         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2302         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2303
2304         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2305         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2306         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2307         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2308
2309         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2310
2311         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2312         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2313         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2314         I915_WRITE(VLV_PCBR,                    s->pcbr);
2315         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2316 }
2317
2318 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2319                                   u32 mask, u32 val)
2320 {
2321         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2322         u32 reg_value;
2323         int ret;
2324
2325         /* The HW does not like us polling for PW_STATUS frequently, so
2326          * use the sleeping loop rather than risk the busy spin within
2327          * intel_wait_for_register().
2328          *
2329          * Transitioning between RC6 states should be at most 2ms (see
2330          * valleyview_enable_rps) so use a 3ms timeout.
2331          */
2332         ret = wait_for(((reg_value =
2333                          intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2334                        == val, 3);
2335
2336         /* just trace the final value */
2337         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2338
2339         return ret;
2340 }
2341
2342 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2343 {
2344         u32 val;
2345         int err;
2346
2347         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2348         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2349         if (force_on)
2350                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2351         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2352
2353         if (!force_on)
2354                 return 0;
2355
2356         err = intel_wait_for_register(&dev_priv->uncore,
2357                                       VLV_GTLC_SURVIVABILITY_REG,
2358                                       VLV_GFX_CLK_STATUS_BIT,
2359                                       VLV_GFX_CLK_STATUS_BIT,
2360                                       20);
2361         if (err)
2362                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2363                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2364
2365         return err;
2366 }
2367
2368 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2369 {
2370         u32 mask;
2371         u32 val;
2372         int err;
2373
2374         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2375         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2376         if (allow)
2377                 val |= VLV_GTLC_ALLOWWAKEREQ;
2378         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2379         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2380
2381         mask = VLV_GTLC_ALLOWWAKEACK;
2382         val = allow ? mask : 0;
2383
2384         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2385         if (err)
2386                 DRM_ERROR("timeout disabling GT waking\n");
2387
2388         return err;
2389 }
2390
2391 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2392                                   bool wait_for_on)
2393 {
2394         u32 mask;
2395         u32 val;
2396
2397         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2398         val = wait_for_on ? mask : 0;
2399
2400         /*
2401          * RC6 transitioning can be delayed up to 2 msec (see
2402          * valleyview_enable_rps), use 3 msec for safety.
2403          *
2404          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2405          * reset and we are trying to force the machine to sleep.
2406          */
2407         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2408                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2409                                  onoff(wait_for_on));
2410 }
2411
2412 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2413 {
2414         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2415                 return;
2416
2417         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2418         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2419 }
2420
2421 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2422 {
2423         u32 mask;
2424         int err;
2425
2426         /*
2427          * Bspec defines the following GT well on flags as debug only, so
2428          * don't treat them as hard failures.
2429          */
2430         vlv_wait_for_gt_wells(dev_priv, false);
2431
2432         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2433         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2434
2435         vlv_check_no_gt_access(dev_priv);
2436
2437         err = vlv_force_gfx_clock(dev_priv, true);
2438         if (err)
2439                 goto err1;
2440
2441         err = vlv_allow_gt_wake(dev_priv, false);
2442         if (err)
2443                 goto err2;
2444
2445         vlv_save_gunit_s0ix_state(dev_priv);
2446
2447         err = vlv_force_gfx_clock(dev_priv, false);
2448         if (err)
2449                 goto err2;
2450
2451         return 0;
2452
2453 err2:
2454         /* For safety always re-enable waking and disable gfx clock forcing */
2455         vlv_allow_gt_wake(dev_priv, true);
2456 err1:
2457         vlv_force_gfx_clock(dev_priv, false);
2458
2459         return err;
2460 }
2461
2462 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2463                                 bool rpm_resume)
2464 {
2465         int err;
2466         int ret;
2467
2468         /*
2469          * If any of the steps fail just try to continue, that's the best we
2470          * can do at this point. Return the first error code (which will also
2471          * leave RPM permanently disabled).
2472          */
2473         ret = vlv_force_gfx_clock(dev_priv, true);
2474
2475         vlv_restore_gunit_s0ix_state(dev_priv);
2476
2477         err = vlv_allow_gt_wake(dev_priv, true);
2478         if (!ret)
2479                 ret = err;
2480
2481         err = vlv_force_gfx_clock(dev_priv, false);
2482         if (!ret)
2483                 ret = err;
2484
2485         vlv_check_no_gt_access(dev_priv);
2486
2487         if (rpm_resume)
2488                 intel_init_clock_gating(dev_priv);
2489
2490         return ret;
2491 }
2492
2493 static int intel_runtime_suspend(struct device *kdev)
2494 {
2495         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2496         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2497         int ret = 0;
2498
2499         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2500                 return -ENODEV;
2501
2502         DRM_DEBUG_KMS("Suspending device\n");
2503
2504         disable_rpm_wakeref_asserts(rpm);
2505
2506         /*
2507          * We are safe here against re-faults, since the fault handler takes
2508          * an RPM reference.
2509          */
2510         i915_gem_runtime_suspend(dev_priv);
2511
2512         intel_gt_runtime_suspend(&dev_priv->gt);
2513
2514         intel_runtime_pm_disable_interrupts(dev_priv);
2515
2516         intel_uncore_suspend(&dev_priv->uncore);
2517
2518         intel_display_power_suspend(dev_priv);
2519
2520         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2521                 ret = vlv_suspend_complete(dev_priv);
2522
2523         if (ret) {
2524                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2525                 intel_uncore_runtime_resume(&dev_priv->uncore);
2526
2527                 intel_runtime_pm_enable_interrupts(dev_priv);
2528
2529                 intel_gt_runtime_resume(&dev_priv->gt);
2530
2531                 i915_gem_restore_fences(&dev_priv->ggtt);
2532
2533                 enable_rpm_wakeref_asserts(rpm);
2534
2535                 return ret;
2536         }
2537
2538         enable_rpm_wakeref_asserts(rpm);
2539         intel_runtime_pm_driver_release(rpm);
2540
2541         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2542                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2543
2544         rpm->suspended = true;
2545
2546         /*
2547          * FIXME: We really should find a document that references the arguments
2548          * used below!
2549          */
2550         if (IS_BROADWELL(dev_priv)) {
2551                 /*
2552                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2553                  * being detected, and the call we do at intel_runtime_resume()
2554                  * won't be able to restore them. Since PCI_D3hot matches the
2555                  * actual specification and appears to be working, use it.
2556                  */
2557                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2558         } else {
2559                 /*
2560                  * current versions of firmware which depend on this opregion
2561                  * notification have repurposed the D1 definition to mean
2562                  * "runtime suspended" vs. what you would normally expect (D3)
2563                  * to distinguish it from notifications that might be sent via
2564                  * the suspend path.
2565                  */
2566                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2567         }
2568
2569         assert_forcewakes_inactive(&dev_priv->uncore);
2570
2571         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2572                 intel_hpd_poll_init(dev_priv);
2573
2574         DRM_DEBUG_KMS("Device suspended\n");
2575         return 0;
2576 }
2577
2578 static int intel_runtime_resume(struct device *kdev)
2579 {
2580         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2581         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2582         int ret = 0;
2583
2584         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2585                 return -ENODEV;
2586
2587         DRM_DEBUG_KMS("Resuming device\n");
2588
2589         WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
2590         disable_rpm_wakeref_asserts(rpm);
2591
2592         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2593         rpm->suspended = false;
2594         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2595                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2596
2597         intel_display_power_resume(dev_priv);
2598
2599         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2600                 ret = vlv_resume_prepare(dev_priv, true);
2601
2602         intel_uncore_runtime_resume(&dev_priv->uncore);
2603
2604         intel_runtime_pm_enable_interrupts(dev_priv);
2605
2606         /*
2607          * No point of rolling back things in case of an error, as the best
2608          * we can do is to hope that things will still work (and disable RPM).
2609          */
2610         intel_gt_runtime_resume(&dev_priv->gt);
2611         i915_gem_restore_fences(&dev_priv->ggtt);
2612
2613         /*
2614          * On VLV/CHV display interrupts are part of the display
2615          * power well, so hpd is reinitialized from there. For
2616          * everyone else do it here.
2617          */
2618         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2619                 intel_hpd_init(dev_priv);
2620
2621         intel_enable_ipc(dev_priv);
2622
2623         enable_rpm_wakeref_asserts(rpm);
2624
2625         if (ret)
2626                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2627         else
2628                 DRM_DEBUG_KMS("Device resumed\n");
2629
2630         return ret;
2631 }
2632
2633 const struct dev_pm_ops i915_pm_ops = {
2634         /*
2635          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2636          * PMSG_RESUME]
2637          */
2638         .prepare = i915_pm_prepare,
2639         .suspend = i915_pm_suspend,
2640         .suspend_late = i915_pm_suspend_late,
2641         .resume_early = i915_pm_resume_early,
2642         .resume = i915_pm_resume,
2643
2644         /*
2645          * S4 event handlers
2646          * @freeze, @freeze_late    : called (1) before creating the
2647          *                            hibernation image [PMSG_FREEZE] and
2648          *                            (2) after rebooting, before restoring
2649          *                            the image [PMSG_QUIESCE]
2650          * @thaw, @thaw_early       : called (1) after creating the hibernation
2651          *                            image, before writing it [PMSG_THAW]
2652          *                            and (2) after failing to create or
2653          *                            restore the image [PMSG_RECOVER]
2654          * @poweroff, @poweroff_late: called after writing the hibernation
2655          *                            image, before rebooting [PMSG_HIBERNATE]
2656          * @restore, @restore_early : called after rebooting and restoring the
2657          *                            hibernation image [PMSG_RESTORE]
2658          */
2659         .freeze = i915_pm_freeze,
2660         .freeze_late = i915_pm_freeze_late,
2661         .thaw_early = i915_pm_thaw_early,
2662         .thaw = i915_pm_thaw,
2663         .poweroff = i915_pm_suspend,
2664         .poweroff_late = i915_pm_poweroff_late,
2665         .restore_early = i915_pm_restore_early,
2666         .restore = i915_pm_restore,
2667
2668         /* S0ix (via runtime suspend) event handlers */
2669         .runtime_suspend = intel_runtime_suspend,
2670         .runtime_resume = intel_runtime_resume,
2671 };
2672
2673 static const struct file_operations i915_driver_fops = {
2674         .owner = THIS_MODULE,
2675         .open = drm_open,
2676         .release = drm_release,
2677         .unlocked_ioctl = drm_ioctl,
2678         .mmap = i915_gem_mmap,
2679         .poll = drm_poll,
2680         .read = drm_read,
2681         .compat_ioctl = i915_compat_ioctl,
2682         .llseek = noop_llseek,
2683 };
2684
2685 static int
2686 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2687                           struct drm_file *file)
2688 {
2689         return -ENODEV;
2690 }
2691
2692 static const struct drm_ioctl_desc i915_ioctls[] = {
2693         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2694         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2695         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2696         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2697         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2698         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2699         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2700         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2701         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2702         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2703         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2704         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2705         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2706         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2707         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2708         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2709         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2710         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2711         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2712         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2713         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2714         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2715         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2716         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2717         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2718         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2719         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2720         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2721         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2722         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2723         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2724         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2725         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
2726         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2727         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2728         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2729         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2730         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2731         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2732         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2733         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2734         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2735         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2736         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2737         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2738         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2739         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2740         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2741         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2742         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2743         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2744         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2745         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2746         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2747         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2748         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2749         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2750         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2751 };
2752
2753 static struct drm_driver driver = {
2754         /* Don't use MTRRs here; the Xserver or userspace app should
2755          * deal with them for Intel hardware.
2756          */
2757         .driver_features =
2758             DRIVER_GEM |
2759             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2760         .release = i915_driver_release,
2761         .open = i915_driver_open,
2762         .lastclose = i915_driver_lastclose,
2763         .postclose = i915_driver_postclose,
2764
2765         .gem_close_object = i915_gem_close_object,
2766         .gem_free_object_unlocked = i915_gem_free_object,
2767
2768         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2769         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2770         .gem_prime_export = i915_gem_prime_export,
2771         .gem_prime_import = i915_gem_prime_import,
2772
2773         .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2774         .get_scanout_position = i915_get_crtc_scanoutpos,
2775
2776         .dumb_create = i915_gem_dumb_create,
2777         .dumb_map_offset = i915_gem_dumb_mmap_offset,
2778
2779         .ioctls = i915_ioctls,
2780         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2781         .fops = &i915_driver_fops,
2782         .name = DRIVER_NAME,
2783         .desc = DRIVER_DESC,
2784         .date = DRIVER_DATE,
2785         .major = DRIVER_MAJOR,
2786         .minor = DRIVER_MINOR,
2787         .patchlevel = DRIVER_PATCHLEVEL,
2788 };