drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 140                 ret = PCH_SPT;
 141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 142         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 143                 ret = PCH_CNP;
 144                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 145         }
 146
 147         return ret;
 148 }
 149
 150 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 151 {
 152         struct pci_dev *pch = NULL;
 153
 154         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 155          * (which really amounts to a PCH but no South Display).
 156          */
 157         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 158                 dev_priv->pch_type = PCH_NOP;
 159                 return;
 160         }
 161
 162         /*
 163          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 164          * make graphics device passthrough work easy for VMM, that only
 165          * need to expose ISA bridge to let driver know the real hardware
 166          * underneath. This is a requirement from virtualization team.
 167          *
 168          * In some virtualized environments (e.g. XEN), there is irrelevant
 169          * ISA bridge in the system. To work reliably, we should scan trhough
 170          * all the ISA bridge devices and check for the first match, instead
 171          * of only checking the first one.
 172          */
 173         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 174                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 175                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 176                         unsigned short id_ext = pch->device &
 177                                 INTEL_PCH_DEVICE_ID_MASK_EXT;
 178
 179                         dev_priv->pch_id = id;
 180
 181                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 182                                 dev_priv->pch_type = PCH_IBX;
 183                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 184                                 WARN_ON(!IS_GEN5(dev_priv));
 185                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 186                                 dev_priv->pch_type = PCH_CPT;
 187                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 189                                         IS_IVYBRIDGE(dev_priv)));
 190                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 191                                 /* PantherPoint is CPT compatible */
 192                                 dev_priv->pch_type = PCH_CPT;
 193                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 194                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 195                                         IS_IVYBRIDGE(dev_priv)));
 196                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 197                                 dev_priv->pch_type = PCH_LPT;
 198                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 199                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 200                                         !IS_BROADWELL(dev_priv));
 201                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 202                                         IS_BDW_ULT(dev_priv));
 203                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 204                                 dev_priv->pch_type = PCH_LPT;
 205                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 206                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 207                                         !IS_BROADWELL(dev_priv));
 208                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 209                                         !IS_BDW_ULT(dev_priv));
 210                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 211                                 dev_priv->pch_type = PCH_SPT;
 212                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 213                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 214                                         !IS_KABYLAKE(dev_priv));
 215                         } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 216                                 dev_priv->pch_type = PCH_SPT;
 217                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 218                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 219                                         !IS_KABYLAKE(dev_priv));
 220                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 221                                 dev_priv->pch_type = PCH_KBP;
 222                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 223                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 224                                         !IS_KABYLAKE(dev_priv));
 225                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 226                                 dev_priv->pch_type = PCH_CNP;
 227                                 DRM_DEBUG_KMS("Found CannonPoint PCH\n");
 228                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 229                                         !IS_COFFEELAKE(dev_priv));
 230                         } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 231                                 dev_priv->pch_type = PCH_CNP;
 232                                 DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
 233                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 234                                         !IS_COFFEELAKE(dev_priv));
 235                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 236                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 237                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 238                                     pch->subsystem_vendor ==
 239                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 240                                     pch->subsystem_device ==
 241                                             PCI_SUBDEVICE_ID_QEMU)) {
 242                                 dev_priv->pch_type =
 243                                         intel_virt_detect_pch(dev_priv);
 244                         } else
 245                                 continue;
 246
 247                         break;
 248                 }
 249         }
 250         if (!pch)
 251                 DRM_DEBUG_KMS("No PCH found.\n");
 252
 253         pci_dev_put(pch);
 254 }
 255
 256 static int i915_getparam(struct drm_device *dev, void *data,
 257                          struct drm_file *file_priv)
 258 {
 259         struct drm_i915_private *dev_priv = to_i915(dev);
 260         struct pci_dev *pdev = dev_priv->drm.pdev;
 261         drm_i915_getparam_t *param = data;
 262         int value;
 263
 264         switch (param->param) {
 265         case I915_PARAM_IRQ_ACTIVE:
 266         case I915_PARAM_ALLOW_BATCHBUFFER:
 267         case I915_PARAM_LAST_DISPATCH:
 268         case I915_PARAM_HAS_EXEC_CONSTANTS:
 269                 /* Reject all old ums/dri params. */
 270                 return -ENODEV;
 271         case I915_PARAM_CHIPSET_ID:
 272                 value = pdev->device;
 273                 break;
 274         case I915_PARAM_REVISION:
 275                 value = pdev->revision;
 276                 break;
 277         case I915_PARAM_NUM_FENCES_AVAIL:
 278                 value = dev_priv->num_fence_regs;
 279                 break;
 280         case I915_PARAM_HAS_OVERLAY:
 281                 value = dev_priv->overlay ? 1 : 0;
 282                 break;
 283         case I915_PARAM_HAS_BSD:
 284                 value = !!dev_priv->engine[VCS];
 285                 break;
 286         case I915_PARAM_HAS_BLT:
 287                 value = !!dev_priv->engine[BCS];
 288                 break;
 289         case I915_PARAM_HAS_VEBOX:
 290                 value = !!dev_priv->engine[VECS];
 291                 break;
 292         case I915_PARAM_HAS_BSD2:
 293                 value = !!dev_priv->engine[VCS2];
 294                 break;
 295         case I915_PARAM_HAS_LLC:
 296                 value = HAS_LLC(dev_priv);
 297                 break;
 298         case I915_PARAM_HAS_WT:
 299                 value = HAS_WT(dev_priv);
 300                 break;
 301         case I915_PARAM_HAS_ALIASING_PPGTT:
 302                 value = USES_PPGTT(dev_priv);
 303                 break;
 304         case I915_PARAM_HAS_SEMAPHORES:
 305                 value = i915.semaphores;
 306                 break;
 307         case I915_PARAM_HAS_SECURE_BATCHES:
 308                 value = capable(CAP_SYS_ADMIN);
 309                 break;
 310         case I915_PARAM_CMD_PARSER_VERSION:
 311                 value = i915_cmd_parser_get_version(dev_priv);
 312                 break;
 313         case I915_PARAM_SUBSLICE_TOTAL:
 314                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 315                 if (!value)
 316                         return -ENODEV;
 317                 break;
 318         case I915_PARAM_EU_TOTAL:
 319                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 320                 if (!value)
 321                         return -ENODEV;
 322                 break;
 323         case I915_PARAM_HAS_GPU_RESET:
 324                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 325                 break;
 326         case I915_PARAM_HAS_RESOURCE_STREAMER:
 327                 value = HAS_RESOURCE_STREAMER(dev_priv);
 328                 break;
 329         case I915_PARAM_HAS_POOLED_EU:
 330                 value = HAS_POOLED_EU(dev_priv);
 331                 break;
 332         case I915_PARAM_MIN_EU_IN_POOL:
 333                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 334                 break;
 335         case I915_PARAM_HUC_STATUS:
 336                 intel_runtime_pm_get(dev_priv);
 337                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 338                 intel_runtime_pm_put(dev_priv);
 339                 break;
 340         case I915_PARAM_MMAP_GTT_VERSION:
 341                 /* Though we've started our numbering from 1, and so class all
 342                  * earlier versions as 0, in effect their value is undefined as
 343                  * the ioctl will report EINVAL for the unknown param!
 344                  */
 345                 value = i915_gem_mmap_gtt_version();
 346                 break;
 347         case I915_PARAM_HAS_SCHEDULER:
 348                 value = dev_priv->engine[RCS] &&
 349                         dev_priv->engine[RCS]->schedule;
 350                 break;
 351         case I915_PARAM_MMAP_VERSION:
 352                 /* Remember to bump this if the version changes! */
 353         case I915_PARAM_HAS_GEM:
 354         case I915_PARAM_HAS_PAGEFLIPPING:
 355         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 356         case I915_PARAM_HAS_RELAXED_FENCING:
 357         case I915_PARAM_HAS_COHERENT_RINGS:
 358         case I915_PARAM_HAS_RELAXED_DELTA:
 359         case I915_PARAM_HAS_GEN7_SOL_RESET:
 360         case I915_PARAM_HAS_WAIT_TIMEOUT:
 361         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 362         case I915_PARAM_HAS_PINNED_BATCHES:
 363         case I915_PARAM_HAS_EXEC_NO_RELOC:
 364         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 365         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 366         case I915_PARAM_HAS_EXEC_SOFTPIN:
 367         case I915_PARAM_HAS_EXEC_ASYNC:
 368         case I915_PARAM_HAS_EXEC_FENCE:
 369         case I915_PARAM_HAS_EXEC_CAPTURE:
 370                 /* For the time being all of these are always true;
 371                  * if some supported hardware does not have one of these
 372                  * features this value needs to be provided from
 373                  * INTEL_INFO(), a feature macro, or similar.
 374                  */
 375                 value = 1;
 376                 break;
 377         case I915_PARAM_SLICE_MASK:
 378                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 379                 if (!value)
 380                         return -ENODEV;
 381                 break;
 382         case I915_PARAM_SUBSLICE_MASK:
 383                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 384                 if (!value)
 385                         return -ENODEV;
 386                 break;
 387         default:
 388                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 389                 return -EINVAL;
 390         }
 391
 392         if (put_user(value, param->value))
 393                 return -EFAULT;
 394
 395         return 0;
 396 }
 397
 398 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 399 {
 400         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 401         if (!dev_priv->bridge_dev) {
 402                 DRM_ERROR("bridge device not found\n");
 403                 return -1;
 404         }
 405         return 0;
 406 }
 407
 408 /* Allocate space for the MCH regs if needed, return nonzero on error */
 409 static int
 410 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 411 {
 412         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 413         u32 temp_lo, temp_hi = 0;
 414         u64 mchbar_addr;
 415         int ret;
 416
 417         if (INTEL_GEN(dev_priv) >= 4)
 418                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 419         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 420         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 421
 422         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 423 #ifdef CONFIG_PNP
 424         if (mchbar_addr &&
 425             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 426                 return 0;
 427 #endif
 428
 429         /* Get some space for it */
 430         dev_priv->mch_res.name = "i915 MCHBAR";
 431         dev_priv->mch_res.flags = IORESOURCE_MEM;
 432         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 433                                      &dev_priv->mch_res,
 434                                      MCHBAR_SIZE, MCHBAR_SIZE,
 435                                      PCIBIOS_MIN_MEM,
 436                                      0, pcibios_align_resource,
 437                                      dev_priv->bridge_dev);
 438         if (ret) {
 439                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 440                 dev_priv->mch_res.start = 0;
 441                 return ret;
 442         }
 443
 444         if (INTEL_GEN(dev_priv) >= 4)
 445                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 446                                        upper_32_bits(dev_priv->mch_res.start));
 447
 448         pci_write_config_dword(dev_priv->bridge_dev, reg,
 449                                lower_32_bits(dev_priv->mch_res.start));
 450         return 0;
 451 }
 452
 453 /* Setup MCHBAR if possible, return true if we should disable it again */
 454 static void
 455 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 456 {
 457         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 458         u32 temp;
 459         bool enabled;
 460
 461         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 462                 return;
 463
 464         dev_priv->mchbar_need_disable = false;
 465
 466         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 467                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 468                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 469         } else {
 470                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 471                 enabled = temp & 1;
 472         }
 473
 474         /* If it's already enabled, don't have to do anything */
 475         if (enabled)
 476                 return;
 477
 478         if (intel_alloc_mchbar_resource(dev_priv))
 479                 return;
 480
 481         dev_priv->mchbar_need_disable = true;
 482
 483         /* Space is allocated or reserved, so enable it. */
 484         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 485                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 486                                        temp | DEVEN_MCHBAR_EN);
 487         } else {
 488                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 489                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 490         }
 491 }
 492
 493 static void
 494 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 495 {
 496         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 497
 498         if (dev_priv->mchbar_need_disable) {
 499                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 500                         u32 deven_val;
 501
 502                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 503                                               &deven_val);
 504                         deven_val &= ~DEVEN_MCHBAR_EN;
 505                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 506                                                deven_val);
 507                 } else {
 508                         u32 mchbar_val;
 509
 510                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 511                                               &mchbar_val);
 512                         mchbar_val &= ~1;
 513                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 514                                                mchbar_val);
 515                 }
 516         }
 517
 518         if (dev_priv->mch_res.start)
 519                 release_resource(&dev_priv->mch_res);
 520 }
 521
 522 /* true = enable decode, false = disable decoder */
 523 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 524 {
 525         struct drm_i915_private *dev_priv = cookie;
 526
 527         intel_modeset_vga_set_state(dev_priv, state);
 528         if (state)
 529                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 530                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 531         else
 532                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 533 }
 534
 535 static int i915_resume_switcheroo(struct drm_device *dev);
 536 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 537
 538 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 539 {
 540         struct drm_device *dev = pci_get_drvdata(pdev);
 541         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 542
 543         if (state == VGA_SWITCHEROO_ON) {
 544                 pr_info("switched on\n");
 545                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 546                 /* i915 resume handler doesn't set to D0 */
 547                 pci_set_power_state(pdev, PCI_D0);
 548                 i915_resume_switcheroo(dev);
 549                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 550         } else {
 551                 pr_info("switched off\n");
 552                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 553                 i915_suspend_switcheroo(dev, pmm);
 554                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 555         }
 556 }
 557
 558 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 559 {
 560         struct drm_device *dev = pci_get_drvdata(pdev);
 561
 562         /*
 563          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 564          * locking inversion with the driver load path. And the access here is
 565          * completely racy anyway. So don't bother with locking for now.
 566          */
 567         return dev->open_count == 0;
 568 }
 569
 570 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 571         .set_gpu_state = i915_switcheroo_set_state,
 572         .reprobe = NULL,
 573         .can_switch = i915_switcheroo_can_switch,
 574 };
 575
 576 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 577 {
 578         mutex_lock(&dev_priv->drm.struct_mutex);
 579         intel_uc_fini_hw(dev_priv);
 580         i915_gem_cleanup_engines(dev_priv);
 581         i915_gem_context_fini(dev_priv);
 582         i915_gem_cleanup_userptr(dev_priv);
 583         mutex_unlock(&dev_priv->drm.struct_mutex);
 584
 585         i915_gem_drain_freed_objects(dev_priv);
 586
 587         WARN_ON(!list_empty(&dev_priv->context_list));
 588 }
 589
 590 static int i915_load_modeset_init(struct drm_device *dev)
 591 {
 592         struct drm_i915_private *dev_priv = to_i915(dev);
 593         struct pci_dev *pdev = dev_priv->drm.pdev;
 594         int ret;
 595
 596         if (i915_inject_load_failure())
 597                 return -ENODEV;
 598
 599         intel_bios_init(dev_priv);
 600
 601         /* If we have > 1 VGA cards, then we need to arbitrate access
 602          * to the common VGA resources.
 603          *
 604          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 605          * then we do not take part in VGA arbitration and the
 606          * vga_client_register() fails with -ENODEV.
 607          */
 608         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 609         if (ret && ret != -ENODEV)
 610                 goto out;
 611
 612         intel_register_dsm_handler();
 613
 614         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 615         if (ret)
 616                 goto cleanup_vga_client;
 617
 618         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 619         intel_update_rawclk(dev_priv);
 620
 621         intel_power_domains_init_hw(dev_priv, false);
 622
 623         intel_csr_ucode_init(dev_priv);
 624
 625         ret = intel_irq_install(dev_priv);
 626         if (ret)
 627                 goto cleanup_csr;
 628
 629         intel_setup_gmbus(dev_priv);
 630
 631         /* Important: The output setup functions called by modeset_init need
 632          * working irqs for e.g. gmbus and dp aux transfers. */
 633         ret = intel_modeset_init(dev);
 634         if (ret)
 635                 goto cleanup_irq;
 636
 637         intel_uc_init_fw(dev_priv);
 638
 639         ret = i915_gem_init(dev_priv);
 640         if (ret)
 641                 goto cleanup_uc;
 642
 643         intel_modeset_gem_init(dev);
 644
 645         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 646                 return 0;
 647
 648         ret = intel_fbdev_init(dev);
 649         if (ret)
 650                 goto cleanup_gem;
 651
 652         /* Only enable hotplug handling once the fbdev is fully set up. */
 653         intel_hpd_init(dev_priv);
 654
 655         drm_kms_helper_poll_init(dev);
 656
 657         return 0;
 658
 659 cleanup_gem:
 660         if (i915_gem_suspend(dev_priv))
 661                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 662         i915_gem_fini(dev_priv);
 663 cleanup_uc:
 664         intel_uc_fini_fw(dev_priv);
 665 cleanup_irq:
 666         drm_irq_uninstall(dev);
 667         intel_teardown_gmbus(dev_priv);
 668 cleanup_csr:
 669         intel_csr_ucode_fini(dev_priv);
 670         intel_power_domains_fini(dev_priv);
 671         vga_switcheroo_unregister_client(pdev);
 672 cleanup_vga_client:
 673         vga_client_register(pdev, NULL, NULL, NULL);
 674 out:
 675         return ret;
 676 }
 677
 678 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 679 {
 680         struct apertures_struct *ap;
 681         struct pci_dev *pdev = dev_priv->drm.pdev;
 682         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 683         bool primary;
 684         int ret;
 685
 686         ap = alloc_apertures(1);
 687         if (!ap)
 688                 return -ENOMEM;
 689
 690         ap->ranges[0].base = ggtt->mappable_base;
 691         ap->ranges[0].size = ggtt->mappable_end;
 692
 693         primary =
 694                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 695
 696         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 697
 698         kfree(ap);
 699
 700         return ret;
 701 }
 702
 703 #if !defined(CONFIG_VGA_CONSOLE)
 704 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 705 {
 706         return 0;
 707 }
 708 #elif !defined(CONFIG_DUMMY_CONSOLE)
 709 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 710 {
 711         return -ENODEV;
 712 }
 713 #else
 714 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 715 {
 716         int ret = 0;
 717
 718         DRM_INFO("Replacing VGA console driver\n");
 719
 720         console_lock();
 721         if (con_is_bound(&vga_con))
 722                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 723         if (ret == 0) {
 724                 ret = do_unregister_con_driver(&vga_con);
 725
 726                 /* Ignore "already unregistered". */
 727                 if (ret == -ENODEV)
 728                         ret = 0;
 729         }
 730         console_unlock();
 731
 732         return ret;
 733 }
 734 #endif
 735
 736 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 737 {
 738         /*
 739          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 740          * CHV x1 PHY (DP/HDMI D)
 741          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 742          */
 743         if (IS_CHERRYVIEW(dev_priv)) {
 744                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 745                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 746         } else if (IS_VALLEYVIEW(dev_priv)) {
 747                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 748         }
 749 }
 750
 751 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 752 {
 753         /*
 754          * The i915 workqueue is primarily used for batched retirement of
 755          * requests (and thus managing bo) once the task has been completed
 756          * by the GPU. i915_gem_retire_requests() is called directly when we
 757          * need high-priority retirement, such as waiting for an explicit
 758          * bo.
 759          *
 760          * It is also used for periodic low-priority events, such as
 761          * idle-timers and recording error state.
 762          *
 763          * All tasks on the workqueue are expected to acquire the dev mutex
 764          * so there is no point in running more than one instance of the
 765          * workqueue at any time.  Use an ordered one.
 766          */
 767         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 768         if (dev_priv->wq == NULL)
 769                 goto out_err;
 770
 771         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 772         if (dev_priv->hotplug.dp_wq == NULL)
 773                 goto out_free_wq;
 774
 775         return 0;
 776
 777 out_free_wq:
 778         destroy_workqueue(dev_priv->wq);
 779 out_err:
 780         DRM_ERROR("Failed to allocate workqueues.\n");
 781
 782         return -ENOMEM;
 783 }
 784
 785 static void i915_engines_cleanup(struct drm_i915_private *i915)
 786 {
 787         struct intel_engine_cs *engine;
 788         enum intel_engine_id id;
 789
 790         for_each_engine(engine, i915, id)
 791                 kfree(engine);
 792 }
 793
 794 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 795 {
 796         destroy_workqueue(dev_priv->hotplug.dp_wq);
 797         destroy_workqueue(dev_priv->wq);
 798 }
 799
 800 /*
 801  * We don't keep the workarounds for pre-production hardware, so we expect our
 802  * driver to fail on these machines in one way or another. A little warning on
 803  * dmesg may help both the user and the bug triagers.
 804  */
 805 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 806 {
 807         bool pre = false;
 808
 809         pre |= IS_HSW_EARLY_SDV(dev_priv);
 810         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 811         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 812
 813         if (pre) {
 814                 DRM_ERROR("This is a pre-production stepping. "
 815                           "It may not be fully functional.\n");
 816                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 817         }
 818 }
 819
 820 /**
 821  * i915_driver_init_early - setup state not requiring device access
 822  * @dev_priv: device private
 823  *
 824  * Initialize everything that is a "SW-only" state, that is state not
 825  * requiring accessing the device or exposing the driver via kernel internal
 826  * or userspace interfaces. Example steps belonging here: lock initialization,
 827  * system memory allocation, setting up device specific attributes and
 828  * function hooks not requiring accessing the device.
 829  */
 830 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 831                                   const struct pci_device_id *ent)
 832 {
 833         const struct intel_device_info *match_info =
 834                 (struct intel_device_info *)ent->driver_data;
 835         struct intel_device_info *device_info;
 836         int ret = 0;
 837
 838         if (i915_inject_load_failure())
 839                 return -ENODEV;
 840
 841         /* Setup the write-once "constant" device info */
 842         device_info = mkwrite_device_info(dev_priv);
 843         memcpy(device_info, match_info, sizeof(*device_info));
 844         device_info->device_id = dev_priv->drm.pdev->device;
 845
 846         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 847         device_info->gen_mask = BIT(device_info->gen - 1);
 848
 849         spin_lock_init(&dev_priv->irq_lock);
 850         spin_lock_init(&dev_priv->gpu_error.lock);
 851         mutex_init(&dev_priv->backlight_lock);
 852         spin_lock_init(&dev_priv->uncore.lock);
 853
 854         spin_lock_init(&dev_priv->mm.object_stat_lock);
 855         spin_lock_init(&dev_priv->mmio_flip_lock);
 856         mutex_init(&dev_priv->sb_lock);
 857         mutex_init(&dev_priv->modeset_restore_lock);
 858         mutex_init(&dev_priv->av_mutex);
 859         mutex_init(&dev_priv->wm.wm_mutex);
 860         mutex_init(&dev_priv->pps_mutex);
 861
 862         intel_uc_init_early(dev_priv);
 863         i915_memcpy_init_early(dev_priv);
 864
 865         ret = i915_workqueues_init(dev_priv);
 866         if (ret < 0)
 867                 goto err_engines;
 868
 869         /* This must be called before any calls to HAS_PCH_* */
 870         intel_detect_pch(dev_priv);
 871
 872         intel_pm_setup(dev_priv);
 873         intel_init_dpio(dev_priv);
 874         intel_power_domains_init(dev_priv);
 875         intel_irq_init(dev_priv);
 876         intel_hangcheck_init(dev_priv);
 877         intel_init_display_hooks(dev_priv);
 878         intel_init_clock_gating_hooks(dev_priv);
 879         intel_init_audio_hooks(dev_priv);
 880         ret = i915_gem_load_init(dev_priv);
 881         if (ret < 0)
 882                 goto err_irq;
 883
 884         intel_display_crc_init(dev_priv);
 885
 886         intel_device_info_dump(dev_priv);
 887
 888         intel_detect_preproduction_hw(dev_priv);
 889
 890         i915_perf_init(dev_priv);
 891
 892         return 0;
 893
 894 err_irq:
 895         intel_irq_fini(dev_priv);
 896         i915_workqueues_cleanup(dev_priv);
 897 err_engines:
 898         i915_engines_cleanup(dev_priv);
 899         return ret;
 900 }
 901
 902 /**
 903  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 904  * @dev_priv: device private
 905  */
 906 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 907 {
 908         i915_perf_fini(dev_priv);
 909         i915_gem_load_cleanup(dev_priv);
 910         intel_irq_fini(dev_priv);
 911         i915_workqueues_cleanup(dev_priv);
 912         i915_engines_cleanup(dev_priv);
 913 }
 914
 915 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 916 {
 917         struct pci_dev *pdev = dev_priv->drm.pdev;
 918         int mmio_bar;
 919         int mmio_size;
 920
 921         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 922         /*
 923          * Before gen4, the registers and the GTT are behind different BARs.
 924          * However, from gen4 onwards, the registers and the GTT are shared
 925          * in the same BAR, so we want to restrict this ioremap from
 926          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 927          * the register BAR remains the same size for all the earlier
 928          * generations up to Ironlake.
 929          */
 930         if (INTEL_GEN(dev_priv) < 5)
 931                 mmio_size = 512 * 1024;
 932         else
 933                 mmio_size = 2 * 1024 * 1024;
 934         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 935         if (dev_priv->regs == NULL) {
 936                 DRM_ERROR("failed to map registers\n");
 937
 938                 return -EIO;
 939         }
 940
 941         /* Try to make sure MCHBAR is enabled before poking at it */
 942         intel_setup_mchbar(dev_priv);
 943
 944         return 0;
 945 }
 946
 947 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 948 {
 949         struct pci_dev *pdev = dev_priv->drm.pdev;
 950
 951         intel_teardown_mchbar(dev_priv);
 952         pci_iounmap(pdev, dev_priv->regs);
 953 }
 954
 955 /**
 956  * i915_driver_init_mmio - setup device MMIO
 957  * @dev_priv: device private
 958  *
 959  * Setup minimal device state necessary for MMIO accesses later in the
 960  * initialization sequence. The setup here should avoid any other device-wide
 961  * side effects or exposing the driver via kernel internal or user space
 962  * interfaces.
 963  */
 964 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 965 {
 966         int ret;
 967
 968         if (i915_inject_load_failure())
 969                 return -ENODEV;
 970
 971         if (i915_get_bridge_dev(dev_priv))
 972                 return -EIO;
 973
 974         ret = i915_mmio_setup(dev_priv);
 975         if (ret < 0)
 976                 goto err_bridge;
 977
 978         intel_uncore_init(dev_priv);
 979
 980         ret = intel_engines_init_mmio(dev_priv);
 981         if (ret)
 982                 goto err_uncore;
 983
 984         i915_gem_init_mmio(dev_priv);
 985
 986         return 0;
 987
 988 err_uncore:
 989         intel_uncore_fini(dev_priv);
 990 err_bridge:
 991         pci_dev_put(dev_priv->bridge_dev);
 992
 993         return ret;
 994 }
 995
 996 /**
 997  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 998  * @dev_priv: device private
 999  */
1000 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1001 {
1002         intel_uncore_fini(dev_priv);
1003         i915_mmio_cleanup(dev_priv);
1004         pci_dev_put(dev_priv->bridge_dev);
1005 }
1006
1007 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1008 {
1009         i915.enable_execlists =
1010                 intel_sanitize_enable_execlists(dev_priv,
1011                                                 i915.enable_execlists);
1012
1013         /*
1014          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1015          * user's requested state against the hardware/driver capabilities.  We
1016          * do this now so that we can print out any log messages once rather
1017          * than every time we check intel_enable_ppgtt().
1018          */
1019         i915.enable_ppgtt =
1020                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1021         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1022
1023         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1024         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1025
1026         intel_uc_sanitize_options(dev_priv);
1027
1028         intel_gvt_sanitize_options(dev_priv);
1029 }
1030
1031 /**
1032  * i915_driver_init_hw - setup state requiring device access
1033  * @dev_priv: device private
1034  *
1035  * Setup state that requires accessing the device, but doesn't require
1036  * exposing the driver via kernel internal or userspace interfaces.
1037  */
1038 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1039 {
1040         struct pci_dev *pdev = dev_priv->drm.pdev;
1041         int ret;
1042
1043         if (i915_inject_load_failure())
1044                 return -ENODEV;
1045
1046         intel_device_info_runtime_init(dev_priv);
1047
1048         intel_sanitize_options(dev_priv);
1049
1050         ret = i915_ggtt_probe_hw(dev_priv);
1051         if (ret)
1052                 return ret;
1053
1054         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1055          * otherwise the vga fbdev driver falls over. */
1056         ret = i915_kick_out_firmware_fb(dev_priv);
1057         if (ret) {
1058                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1059                 goto out_ggtt;
1060         }
1061
1062         ret = i915_kick_out_vgacon(dev_priv);
1063         if (ret) {
1064                 DRM_ERROR("failed to remove conflicting VGA console\n");
1065                 goto out_ggtt;
1066         }
1067
1068         ret = i915_ggtt_init_hw(dev_priv);
1069         if (ret)
1070                 return ret;
1071
1072         ret = i915_ggtt_enable_hw(dev_priv);
1073         if (ret) {
1074                 DRM_ERROR("failed to enable GGTT\n");
1075                 goto out_ggtt;
1076         }
1077
1078         pci_set_master(pdev);
1079
1080         /* overlay on gen2 is broken and can't address above 1G */
1081         if (IS_GEN2(dev_priv)) {
1082                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1083                 if (ret) {
1084                         DRM_ERROR("failed to set DMA mask\n");
1085
1086                         goto out_ggtt;
1087                 }
1088         }
1089
1090         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1091          * using 32bit addressing, overwriting memory if HWS is located
1092          * above 4GB.
1093          *
1094          * The documentation also mentions an issue with undefined
1095          * behaviour if any general state is accessed within a page above 4GB,
1096          * which also needs to be handled carefully.
1097          */
1098         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1099                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1100
1101                 if (ret) {
1102                         DRM_ERROR("failed to set DMA mask\n");
1103
1104                         goto out_ggtt;
1105                 }
1106         }
1107
1108         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1109                            PM_QOS_DEFAULT_VALUE);
1110
1111         intel_uncore_sanitize(dev_priv);
1112
1113         intel_opregion_setup(dev_priv);
1114
1115         i915_gem_load_init_fences(dev_priv);
1116
1117         /* On the 945G/GM, the chipset reports the MSI capability on the
1118          * integrated graphics even though the support isn't actually there
1119          * according to the published specs.  It doesn't appear to function
1120          * correctly in testing on 945G.
1121          * This may be a side effect of MSI having been made available for PEG
1122          * and the registers being closely associated.
1123          *
1124          * According to chipset errata, on the 965GM, MSI interrupts may
1125          * be lost or delayed, but we use them anyways to avoid
1126          * stuck interrupts on some machines.
1127          */
1128         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1129                 if (pci_enable_msi(pdev) < 0)
1130                         DRM_DEBUG_DRIVER("can't enable MSI");
1131         }
1132
1133         ret = intel_gvt_init(dev_priv);
1134         if (ret)
1135                 goto out_ggtt;
1136
1137         return 0;
1138
1139 out_ggtt:
1140         i915_ggtt_cleanup_hw(dev_priv);
1141
1142         return ret;
1143 }
1144
1145 /**
1146  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1147  * @dev_priv: device private
1148  */
1149 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1150 {
1151         struct pci_dev *pdev = dev_priv->drm.pdev;
1152
1153         if (pdev->msi_enabled)
1154                 pci_disable_msi(pdev);
1155
1156         pm_qos_remove_request(&dev_priv->pm_qos);
1157         i915_ggtt_cleanup_hw(dev_priv);
1158 }
1159
1160 /**
1161  * i915_driver_register - register the driver with the rest of the system
1162  * @dev_priv: device private
1163  *
1164  * Perform any steps necessary to make the driver available via kernel
1165  * internal or userspace interfaces.
1166  */
1167 static void i915_driver_register(struct drm_i915_private *dev_priv)
1168 {
1169         struct drm_device *dev = &dev_priv->drm;
1170
1171         i915_gem_shrinker_init(dev_priv);
1172
1173         /*
1174          * Notify a valid surface after modesetting,
1175          * when running inside a VM.
1176          */
1177         if (intel_vgpu_active(dev_priv))
1178                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1179
1180         /* Reveal our presence to userspace */
1181         if (drm_dev_register(dev, 0) == 0) {
1182                 i915_debugfs_register(dev_priv);
1183                 i915_guc_log_register(dev_priv);
1184                 i915_setup_sysfs(dev_priv);
1185
1186                 /* Depends on sysfs having been initialized */
1187                 i915_perf_register(dev_priv);
1188         } else
1189                 DRM_ERROR("Failed to register driver for userspace access!\n");
1190
1191         if (INTEL_INFO(dev_priv)->num_pipes) {
1192                 /* Must be done after probing outputs */
1193                 intel_opregion_register(dev_priv);
1194                 acpi_video_register();
1195         }
1196
1197         if (IS_GEN5(dev_priv))
1198                 intel_gpu_ips_init(dev_priv);
1199
1200         intel_audio_init(dev_priv);
1201
1202         /*
1203          * Some ports require correctly set-up hpd registers for detection to
1204          * work properly (leading to ghost connected connector status), e.g. VGA
1205          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1206          * irqs are fully enabled. We do it last so that the async config
1207          * cannot run before the connectors are registered.
1208          */
1209         intel_fbdev_initial_config_async(dev);
1210 }
1211
1212 /**
1213  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1214  * @dev_priv: device private
1215  */
1216 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1217 {
1218         intel_audio_deinit(dev_priv);
1219
1220         intel_gpu_ips_teardown();
1221         acpi_video_unregister();
1222         intel_opregion_unregister(dev_priv);
1223
1224         i915_perf_unregister(dev_priv);
1225
1226         i915_teardown_sysfs(dev_priv);
1227         i915_guc_log_unregister(dev_priv);
1228         drm_dev_unregister(&dev_priv->drm);
1229
1230         i915_gem_shrinker_cleanup(dev_priv);
1231 }
1232
1233 /**
1234  * i915_driver_load - setup chip and create an initial config
1235  * @pdev: PCI device
1236  * @ent: matching PCI ID entry
1237  *
1238  * The driver load routine has to do several things:
1239  *   - drive output discovery via intel_modeset_init()
1240  *   - initialize the memory manager
1241  *   - allocate initial config memory
1242  *   - setup the DRM framebuffer with the allocated memory
1243  */
1244 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1245 {
1246         const struct intel_device_info *match_info =
1247                 (struct intel_device_info *)ent->driver_data;
1248         struct drm_i915_private *dev_priv;
1249         int ret;
1250
1251         /* Enable nuclear pageflip on ILK+ */
1252         if (!i915.nuclear_pageflip && match_info->gen < 5)
1253                 driver.driver_features &= ~DRIVER_ATOMIC;
1254
1255         ret = -ENOMEM;
1256         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1257         if (dev_priv)
1258                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1259         if (ret) {
1260                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1261                 goto out_free;
1262         }
1263
1264         dev_priv->drm.pdev = pdev;
1265         dev_priv->drm.dev_private = dev_priv;
1266
1267         ret = pci_enable_device(pdev);
1268         if (ret)
1269                 goto out_fini;
1270
1271         pci_set_drvdata(pdev, &dev_priv->drm);
1272         /*
1273          * Disable the system suspend direct complete optimization, which can
1274          * leave the device suspended skipping the driver's suspend handlers
1275          * if the device was already runtime suspended. This is needed due to
1276          * the difference in our runtime and system suspend sequence and
1277          * becaue the HDA driver may require us to enable the audio power
1278          * domain during system suspend.
1279          */
1280         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1281
1282         ret = i915_driver_init_early(dev_priv, ent);
1283         if (ret < 0)
1284                 goto out_pci_disable;
1285
1286         intel_runtime_pm_get(dev_priv);
1287
1288         ret = i915_driver_init_mmio(dev_priv);
1289         if (ret < 0)
1290                 goto out_runtime_pm_put;
1291
1292         ret = i915_driver_init_hw(dev_priv);
1293         if (ret < 0)
1294                 goto out_cleanup_mmio;
1295
1296         /*
1297          * TODO: move the vblank init and parts of modeset init steps into one
1298          * of the i915_driver_init_/i915_driver_register functions according
1299          * to the role/effect of the given init step.
1300          */
1301         if (INTEL_INFO(dev_priv)->num_pipes) {
1302                 ret = drm_vblank_init(&dev_priv->drm,
1303                                       INTEL_INFO(dev_priv)->num_pipes);
1304                 if (ret)
1305                         goto out_cleanup_hw;
1306         }
1307
1308         ret = i915_load_modeset_init(&dev_priv->drm);
1309         if (ret < 0)
1310                 goto out_cleanup_vblank;
1311
1312         i915_driver_register(dev_priv);
1313
1314         intel_runtime_pm_enable(dev_priv);
1315
1316         dev_priv->ipc_enabled = false;
1317
1318         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1319                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1320         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1321                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1322
1323         intel_runtime_pm_put(dev_priv);
1324
1325         return 0;
1326
1327 out_cleanup_vblank:
1328         drm_vblank_cleanup(&dev_priv->drm);
1329 out_cleanup_hw:
1330         i915_driver_cleanup_hw(dev_priv);
1331 out_cleanup_mmio:
1332         i915_driver_cleanup_mmio(dev_priv);
1333 out_runtime_pm_put:
1334         intel_runtime_pm_put(dev_priv);
1335         i915_driver_cleanup_early(dev_priv);
1336 out_pci_disable:
1337         pci_disable_device(pdev);
1338 out_fini:
1339         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1340         drm_dev_fini(&dev_priv->drm);
1341 out_free:
1342         kfree(dev_priv);
1343         return ret;
1344 }
1345
1346 void i915_driver_unload(struct drm_device *dev)
1347 {
1348         struct drm_i915_private *dev_priv = to_i915(dev);
1349         struct pci_dev *pdev = dev_priv->drm.pdev;
1350
1351         intel_fbdev_fini(dev);
1352
1353         if (i915_gem_suspend(dev_priv))
1354                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1355
1356         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1357
1358         drm_atomic_helper_shutdown(dev);
1359
1360         intel_gvt_cleanup(dev_priv);
1361
1362         i915_driver_unregister(dev_priv);
1363
1364         drm_vblank_cleanup(dev);
1365
1366         intel_modeset_cleanup(dev);
1367
1368         /*
1369          * free the memory space allocated for the child device
1370          * config parsed from VBT
1371          */
1372         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1373                 kfree(dev_priv->vbt.child_dev);
1374                 dev_priv->vbt.child_dev = NULL;
1375                 dev_priv->vbt.child_dev_num = 0;
1376         }
1377         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1378         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1379         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1380         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1381
1382         vga_switcheroo_unregister_client(pdev);
1383         vga_client_register(pdev, NULL, NULL, NULL);
1384
1385         intel_csr_ucode_fini(dev_priv);
1386
1387         /* Free error state after interrupts are fully disabled. */
1388         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1389         i915_reset_error_state(dev_priv);
1390
1391         /* Flush any outstanding unpin_work. */
1392         drain_workqueue(dev_priv->wq);
1393
1394         i915_gem_fini(dev_priv);
1395         intel_uc_fini_fw(dev_priv);
1396         intel_fbc_cleanup_cfb(dev_priv);
1397
1398         intel_power_domains_fini(dev_priv);
1399
1400         i915_driver_cleanup_hw(dev_priv);
1401         i915_driver_cleanup_mmio(dev_priv);
1402
1403         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1404 }
1405
1406 static void i915_driver_release(struct drm_device *dev)
1407 {
1408         struct drm_i915_private *dev_priv = to_i915(dev);
1409
1410         i915_driver_cleanup_early(dev_priv);
1411         drm_dev_fini(&dev_priv->drm);
1412
1413         kfree(dev_priv);
1414 }
1415
1416 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1417 {
1418         int ret;
1419
1420         ret = i915_gem_open(dev, file);
1421         if (ret)
1422                 return ret;
1423
1424         return 0;
1425 }
1426
1427 /**
1428  * i915_driver_lastclose - clean up after all DRM clients have exited
1429  * @dev: DRM device
1430  *
1431  * Take care of cleaning up after all DRM clients have exited.  In the
1432  * mode setting case, we want to restore the kernel's initial mode (just
1433  * in case the last client left us in a bad state).
1434  *
1435  * Additionally, in the non-mode setting case, we'll tear down the GTT
1436  * and DMA structures, since the kernel won't be using them, and clea
1437  * up any GEM state.
1438  */
1439 static void i915_driver_lastclose(struct drm_device *dev)
1440 {
1441         intel_fbdev_restore_mode(dev);
1442         vga_switcheroo_process_delayed_switch();
1443 }
1444
1445 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1446 {
1447         struct drm_i915_file_private *file_priv = file->driver_priv;
1448
1449         mutex_lock(&dev->struct_mutex);
1450         i915_gem_context_close(dev, file);
1451         i915_gem_release(dev, file);
1452         mutex_unlock(&dev->struct_mutex);
1453
1454         kfree(file_priv);
1455 }
1456
1457 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1458 {
1459         struct drm_device *dev = &dev_priv->drm;
1460         struct intel_encoder *encoder;
1461
1462         drm_modeset_lock_all(dev);
1463         for_each_intel_encoder(dev, encoder)
1464                 if (encoder->suspend)
1465                         encoder->suspend(encoder);
1466         drm_modeset_unlock_all(dev);
1467 }
1468
1469 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1470                               bool rpm_resume);
1471 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1472
1473 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1474 {
1475 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1476         if (acpi_target_system_state() < ACPI_STATE_S3)
1477                 return true;
1478 #endif
1479         return false;
1480 }
1481
1482 static int i915_drm_suspend(struct drm_device *dev)
1483 {
1484         struct drm_i915_private *dev_priv = to_i915(dev);
1485         struct pci_dev *pdev = dev_priv->drm.pdev;
1486         pci_power_t opregion_target_state;
1487         int error;
1488
1489         /* ignore lid events during suspend */
1490         mutex_lock(&dev_priv->modeset_restore_lock);
1491         dev_priv->modeset_restore = MODESET_SUSPENDED;
1492         mutex_unlock(&dev_priv->modeset_restore_lock);
1493
1494         disable_rpm_wakeref_asserts(dev_priv);
1495
1496         /* We do a lot of poking in a lot of registers, make sure they work
1497          * properly. */
1498         intel_display_set_init_power(dev_priv, true);
1499
1500         drm_kms_helper_poll_disable(dev);
1501
1502         pci_save_state(pdev);
1503
1504         error = i915_gem_suspend(dev_priv);
1505         if (error) {
1506                 dev_err(&pdev->dev,
1507                         "GEM idle failed, resume might fail\n");
1508                 goto out;
1509         }
1510
1511         intel_display_suspend(dev);
1512
1513         intel_dp_mst_suspend(dev);
1514
1515         intel_runtime_pm_disable_interrupts(dev_priv);
1516         intel_hpd_cancel_work(dev_priv);
1517
1518         intel_suspend_encoders(dev_priv);
1519
1520         intel_suspend_hw(dev_priv);
1521
1522         i915_gem_suspend_gtt_mappings(dev_priv);
1523
1524         i915_save_state(dev_priv);
1525
1526         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1527         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1528
1529         intel_uncore_suspend(dev_priv);
1530         intel_opregion_unregister(dev_priv);
1531
1532         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1533
1534         dev_priv->suspend_count++;
1535
1536         intel_csr_ucode_suspend(dev_priv);
1537
1538 out:
1539         enable_rpm_wakeref_asserts(dev_priv);
1540
1541         return error;
1542 }
1543
1544 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1545 {
1546         struct drm_i915_private *dev_priv = to_i915(dev);
1547         struct pci_dev *pdev = dev_priv->drm.pdev;
1548         bool fw_csr;
1549         int ret;
1550
1551         disable_rpm_wakeref_asserts(dev_priv);
1552
1553         intel_display_set_init_power(dev_priv, false);
1554
1555         fw_csr = !IS_GEN9_LP(dev_priv) &&
1556                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1557         /*
1558          * In case of firmware assisted context save/restore don't manually
1559          * deinit the power domains. This also means the CSR/DMC firmware will
1560          * stay active, it will power down any HW resources as required and
1561          * also enable deeper system power states that would be blocked if the
1562          * firmware was inactive.
1563          */
1564         if (!fw_csr)
1565                 intel_power_domains_suspend(dev_priv);
1566
1567         ret = 0;
1568         if (IS_GEN9_LP(dev_priv))
1569                 bxt_enable_dc9(dev_priv);
1570         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1571                 hsw_enable_pc8(dev_priv);
1572         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1573                 ret = vlv_suspend_complete(dev_priv);
1574
1575         if (ret) {
1576                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1577                 if (!fw_csr)
1578                         intel_power_domains_init_hw(dev_priv, true);
1579
1580                 goto out;
1581         }
1582
1583         pci_disable_device(pdev);
1584         /*
1585          * During hibernation on some platforms the BIOS may try to access
1586          * the device even though it's already in D3 and hang the machine. So
1587          * leave the device in D0 on those platforms and hope the BIOS will
1588          * power down the device properly. The issue was seen on multiple old
1589          * GENs with different BIOS vendors, so having an explicit blacklist
1590          * is inpractical; apply the workaround on everything pre GEN6. The
1591          * platforms where the issue was seen:
1592          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1593          * Fujitsu FSC S7110
1594          * Acer Aspire 1830T
1595          */
1596         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1597                 pci_set_power_state(pdev, PCI_D3hot);
1598
1599         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1600
1601 out:
1602         enable_rpm_wakeref_asserts(dev_priv);
1603
1604         return ret;
1605 }
1606
1607 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1608 {
1609         int error;
1610
1611         if (!dev) {
1612                 DRM_ERROR("dev: %p\n", dev);
1613                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1614                 return -ENODEV;
1615         }
1616
1617         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1618                          state.event != PM_EVENT_FREEZE))
1619                 return -EINVAL;
1620
1621         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1622                 return 0;
1623
1624         error = i915_drm_suspend(dev);
1625         if (error)
1626                 return error;
1627
1628         return i915_drm_suspend_late(dev, false);
1629 }
1630
1631 static int i915_drm_resume(struct drm_device *dev)
1632 {
1633         struct drm_i915_private *dev_priv = to_i915(dev);
1634         int ret;
1635
1636         disable_rpm_wakeref_asserts(dev_priv);
1637         intel_sanitize_gt_powersave(dev_priv);
1638
1639         ret = i915_ggtt_enable_hw(dev_priv);
1640         if (ret)
1641                 DRM_ERROR("failed to re-enable GGTT\n");
1642
1643         intel_csr_ucode_resume(dev_priv);
1644
1645         i915_gem_resume(dev_priv);
1646
1647         i915_restore_state(dev_priv);
1648         intel_pps_unlock_regs_wa(dev_priv);
1649         intel_opregion_setup(dev_priv);
1650
1651         intel_init_pch_refclk(dev_priv);
1652
1653         /*
1654          * Interrupts have to be enabled before any batches are run. If not the
1655          * GPU will hang. i915_gem_init_hw() will initiate batches to
1656          * update/restore the context.
1657          *
1658          * drm_mode_config_reset() needs AUX interrupts.
1659          *
1660          * Modeset enabling in intel_modeset_init_hw() also needs working
1661          * interrupts.
1662          */
1663         intel_runtime_pm_enable_interrupts(dev_priv);
1664
1665         drm_mode_config_reset(dev);
1666
1667         mutex_lock(&dev->struct_mutex);
1668         if (i915_gem_init_hw(dev_priv)) {
1669                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1670                 i915_gem_set_wedged(dev_priv);
1671         }
1672         mutex_unlock(&dev->struct_mutex);
1673
1674         intel_guc_resume(dev_priv);
1675
1676         intel_modeset_init_hw(dev);
1677
1678         spin_lock_irq(&dev_priv->irq_lock);
1679         if (dev_priv->display.hpd_irq_setup)
1680                 dev_priv->display.hpd_irq_setup(dev_priv);
1681         spin_unlock_irq(&dev_priv->irq_lock);
1682
1683         intel_dp_mst_resume(dev);
1684
1685         intel_display_resume(dev);
1686
1687         drm_kms_helper_poll_enable(dev);
1688
1689         /*
1690          * ... but also need to make sure that hotplug processing
1691          * doesn't cause havoc. Like in the driver load code we don't
1692          * bother with the tiny race here where we might loose hotplug
1693          * notifications.
1694          * */
1695         intel_hpd_init(dev_priv);
1696
1697         intel_opregion_register(dev_priv);
1698
1699         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1700
1701         mutex_lock(&dev_priv->modeset_restore_lock);
1702         dev_priv->modeset_restore = MODESET_DONE;
1703         mutex_unlock(&dev_priv->modeset_restore_lock);
1704
1705         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1706
1707         intel_autoenable_gt_powersave(dev_priv);
1708
1709         enable_rpm_wakeref_asserts(dev_priv);
1710
1711         return 0;
1712 }
1713
1714 static int i915_drm_resume_early(struct drm_device *dev)
1715 {
1716         struct drm_i915_private *dev_priv = to_i915(dev);
1717         struct pci_dev *pdev = dev_priv->drm.pdev;
1718         int ret;
1719
1720         /*
1721          * We have a resume ordering issue with the snd-hda driver also
1722          * requiring our device to be power up. Due to the lack of a
1723          * parent/child relationship we currently solve this with an early
1724          * resume hook.
1725          *
1726          * FIXME: This should be solved with a special hdmi sink device or
1727          * similar so that power domains can be employed.
1728          */
1729
1730         /*
1731          * Note that we need to set the power state explicitly, since we
1732          * powered off the device during freeze and the PCI core won't power
1733          * it back up for us during thaw. Powering off the device during
1734          * freeze is not a hard requirement though, and during the
1735          * suspend/resume phases the PCI core makes sure we get here with the
1736          * device powered on. So in case we change our freeze logic and keep
1737          * the device powered we can also remove the following set power state
1738          * call.
1739          */
1740         ret = pci_set_power_state(pdev, PCI_D0);
1741         if (ret) {
1742                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1743                 goto out;
1744         }
1745
1746         /*
1747          * Note that pci_enable_device() first enables any parent bridge
1748          * device and only then sets the power state for this device. The
1749          * bridge enabling is a nop though, since bridge devices are resumed
1750          * first. The order of enabling power and enabling the device is
1751          * imposed by the PCI core as described above, so here we preserve the
1752          * same order for the freeze/thaw phases.
1753          *
1754          * TODO: eventually we should remove pci_disable_device() /
1755          * pci_enable_enable_device() from suspend/resume. Due to how they
1756          * depend on the device enable refcount we can't anyway depend on them
1757          * disabling/enabling the device.
1758          */
1759         if (pci_enable_device(pdev)) {
1760                 ret = -EIO;
1761                 goto out;
1762         }
1763
1764         pci_set_master(pdev);
1765
1766         disable_rpm_wakeref_asserts(dev_priv);
1767
1768         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1769                 ret = vlv_resume_prepare(dev_priv, false);
1770         if (ret)
1771                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1772                           ret);
1773
1774         intel_uncore_resume_early(dev_priv);
1775
1776         if (IS_GEN9_LP(dev_priv)) {
1777                 if (!dev_priv->suspended_to_idle)
1778                         gen9_sanitize_dc_state(dev_priv);
1779                 bxt_disable_dc9(dev_priv);
1780         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1781                 hsw_disable_pc8(dev_priv);
1782         }
1783
1784         intel_uncore_sanitize(dev_priv);
1785
1786         if (IS_GEN9_LP(dev_priv) ||
1787             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1788                 intel_power_domains_init_hw(dev_priv, true);
1789
1790         i915_gem_sanitize(dev_priv);
1791
1792         enable_rpm_wakeref_asserts(dev_priv);
1793
1794 out:
1795         dev_priv->suspended_to_idle = false;
1796
1797         return ret;
1798 }
1799
1800 static int i915_resume_switcheroo(struct drm_device *dev)
1801 {
1802         int ret;
1803
1804         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1805                 return 0;
1806
1807         ret = i915_drm_resume_early(dev);
1808         if (ret)
1809                 return ret;
1810
1811         return i915_drm_resume(dev);
1812 }
1813
1814 /**
1815  * i915_reset - reset chip after a hang
1816  * @dev_priv: device private to reset
1817  *
1818  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1819  * on failure.
1820  *
1821  * Caller must hold the struct_mutex.
1822  *
1823  * Procedure is fairly simple:
1824  *   - reset the chip using the reset reg
1825  *   - re-init context state
1826  *   - re-init hardware status page
1827  *   - re-init ring buffer
1828  *   - re-init interrupt state
1829  *   - re-init display
1830  */
1831 void i915_reset(struct drm_i915_private *dev_priv)
1832 {
1833         struct i915_gpu_error *error = &dev_priv->gpu_error;
1834         int ret;
1835
1836         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1837         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1838
1839         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1840                 return;
1841
1842         /* Clear any previous failed attempts at recovery. Time to try again. */
1843         if (!i915_gem_unset_wedged(dev_priv))
1844                 goto wakeup;
1845
1846         error->reset_count++;
1847
1848         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1849         disable_irq(dev_priv->drm.irq);
1850         ret = i915_gem_reset_prepare(dev_priv);
1851         if (ret) {
1852                 DRM_ERROR("GPU recovery failed\n");
1853                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1854                 goto error;
1855         }
1856
1857         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1858         if (ret) {
1859                 if (ret != -ENODEV)
1860                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1861                 else
1862                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1863                 goto error;
1864         }
1865
1866         i915_gem_reset(dev_priv);
1867         intel_overlay_reset(dev_priv);
1868
1869         /* Ok, now get things going again... */
1870
1871         /*
1872          * Everything depends on having the GTT running, so we need to start
1873          * there.  Fortunately we don't need to do this unless we reset the
1874          * chip at a PCI level.
1875          *
1876          * Next we need to restore the context, but we don't use those
1877          * yet either...
1878          *
1879          * Ring buffer needs to be re-initialized in the KMS case, or if X
1880          * was running at the time of the reset (i.e. we weren't VT
1881          * switched away).
1882          */
1883         ret = i915_gem_init_hw(dev_priv);
1884         if (ret) {
1885                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1886                 goto error;
1887         }
1888
1889         i915_queue_hangcheck(dev_priv);
1890
1891 finish:
1892         i915_gem_reset_finish(dev_priv);
1893         enable_irq(dev_priv->drm.irq);
1894
1895 wakeup:
1896         clear_bit(I915_RESET_HANDOFF, &error->flags);
1897         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1898         return;
1899
1900 error:
1901         i915_gem_set_wedged(dev_priv);
1902         goto finish;
1903 }
1904
1905 static int i915_pm_suspend(struct device *kdev)
1906 {
1907         struct pci_dev *pdev = to_pci_dev(kdev);
1908         struct drm_device *dev = pci_get_drvdata(pdev);
1909
1910         if (!dev) {
1911                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1912                 return -ENODEV;
1913         }
1914
1915         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1916                 return 0;
1917
1918         return i915_drm_suspend(dev);
1919 }
1920
1921 static int i915_pm_suspend_late(struct device *kdev)
1922 {
1923         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1924
1925         /*
1926          * We have a suspend ordering issue with the snd-hda driver also
1927          * requiring our device to be power up. Due to the lack of a
1928          * parent/child relationship we currently solve this with an late
1929          * suspend hook.
1930          *
1931          * FIXME: This should be solved with a special hdmi sink device or
1932          * similar so that power domains can be employed.
1933          */
1934         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1935                 return 0;
1936
1937         return i915_drm_suspend_late(dev, false);
1938 }
1939
1940 static int i915_pm_poweroff_late(struct device *kdev)
1941 {
1942         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1943
1944         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1945                 return 0;
1946
1947         return i915_drm_suspend_late(dev, true);
1948 }
1949
1950 static int i915_pm_resume_early(struct device *kdev)
1951 {
1952         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1953
1954         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1955                 return 0;
1956
1957         return i915_drm_resume_early(dev);
1958 }
1959
1960 static int i915_pm_resume(struct device *kdev)
1961 {
1962         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1963
1964         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1965                 return 0;
1966
1967         return i915_drm_resume(dev);
1968 }
1969
1970 /* freeze: before creating the hibernation_image */
1971 static int i915_pm_freeze(struct device *kdev)
1972 {
1973         int ret;
1974
1975         ret = i915_pm_suspend(kdev);
1976         if (ret)
1977                 return ret;
1978
1979         ret = i915_gem_freeze(kdev_to_i915(kdev));
1980         if (ret)
1981                 return ret;
1982
1983         return 0;
1984 }
1985
1986 static int i915_pm_freeze_late(struct device *kdev)
1987 {
1988         int ret;
1989
1990         ret = i915_pm_suspend_late(kdev);
1991         if (ret)
1992                 return ret;
1993
1994         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1995         if (ret)
1996                 return ret;
1997
1998         return 0;
1999 }
2000
2001 /* thaw: called after creating the hibernation image, but before turning off. */
2002 static int i915_pm_thaw_early(struct device *kdev)
2003 {
2004         return i915_pm_resume_early(kdev);
2005 }
2006
2007 static int i915_pm_thaw(struct device *kdev)
2008 {
2009         return i915_pm_resume(kdev);
2010 }
2011
2012 /* restore: called after loading the hibernation image. */
2013 static int i915_pm_restore_early(struct device *kdev)
2014 {
2015         return i915_pm_resume_early(kdev);
2016 }
2017
2018 static int i915_pm_restore(struct device *kdev)
2019 {
2020         return i915_pm_resume(kdev);
2021 }
2022
2023 /*
2024  * Save all Gunit registers that may be lost after a D3 and a subsequent
2025  * S0i[R123] transition. The list of registers needing a save/restore is
2026  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2027  * registers in the following way:
2028  * - Driver: saved/restored by the driver
2029  * - Punit : saved/restored by the Punit firmware
2030  * - No, w/o marking: no need to save/restore, since the register is R/O or
2031  *                    used internally by the HW in a way that doesn't depend
2032  *                    keeping the content across a suspend/resume.
2033  * - Debug : used for debugging
2034  *
2035  * We save/restore all registers marked with 'Driver', with the following
2036  * exceptions:
2037  * - Registers out of use, including also registers marked with 'Debug'.
2038  *   These have no effect on the driver's operation, so we don't save/restore
2039  *   them to reduce the overhead.
2040  * - Registers that are fully setup by an initialization function called from
2041  *   the resume path. For example many clock gating and RPS/RC6 registers.
2042  * - Registers that provide the right functionality with their reset defaults.
2043  *
2044  * TODO: Except for registers that based on the above 3 criteria can be safely
2045  * ignored, we save/restore all others, practically treating the HW context as
2046  * a black-box for the driver. Further investigation is needed to reduce the
2047  * saved/restored registers even further, by following the same 3 criteria.
2048  */
2049 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2050 {
2051         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2052         int i;
2053
2054         /* GAM 0x4000-0x4770 */
2055         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2056         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2057         s->arb_mode             = I915_READ(ARB_MODE);
2058         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2059         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2060
2061         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2062                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2063
2064         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2065         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2066
2067         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2068         s->ecochk               = I915_READ(GAM_ECOCHK);
2069         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2070         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2071
2072         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2073
2074         /* MBC 0x9024-0x91D0, 0x8500 */
2075         s->g3dctl               = I915_READ(VLV_G3DCTL);
2076         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2077         s->mbctl                = I915_READ(GEN6_MBCTL);
2078
2079         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2080         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2081         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2082         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2083         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2084         s->rstctl               = I915_READ(GEN6_RSTCTL);
2085         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2086
2087         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2088         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2089         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2090         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2091         s->ecobus               = I915_READ(ECOBUS);
2092         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2093         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2094         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2095         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2096         s->rcedata              = I915_READ(VLV_RCEDATA);
2097         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2098
2099         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2100         s->gt_imr               = I915_READ(GTIMR);
2101         s->gt_ier               = I915_READ(GTIER);
2102         s->pm_imr               = I915_READ(GEN6_PMIMR);
2103         s->pm_ier               = I915_READ(GEN6_PMIER);
2104
2105         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2106                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2107
2108         /* GT SA CZ domain, 0x100000-0x138124 */
2109         s->tilectl              = I915_READ(TILECTL);
2110         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2111         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2112         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2113         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2114
2115         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2116         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2117         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2118         s->pcbr                 = I915_READ(VLV_PCBR);
2119         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2120
2121         /*
2122          * Not saving any of:
2123          * DFT,         0x9800-0x9EC0
2124          * SARB,        0xB000-0xB1FC
2125          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2126          * PCI CFG
2127          */
2128 }
2129
2130 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2131 {
2132         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2133         u32 val;
2134         int i;
2135
2136         /* GAM 0x4000-0x4770 */
2137         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2138         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2139         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2140         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2141         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2142
2143         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2144                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2145
2146         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2147         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2148
2149         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2150         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2151         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2152         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2153
2154         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2155
2156         /* MBC 0x9024-0x91D0, 0x8500 */
2157         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2158         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2159         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2160
2161         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2162         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2163         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2164         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2165         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2166         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2167         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2168
2169         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2170         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2171         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2172         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2173         I915_WRITE(ECOBUS,              s->ecobus);
2174         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2175         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2176         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2177         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2178         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2179         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2180
2181         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2182         I915_WRITE(GTIMR,               s->gt_imr);
2183         I915_WRITE(GTIER,               s->gt_ier);
2184         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2185         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2186
2187         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2188                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2189
2190         /* GT SA CZ domain, 0x100000-0x138124 */
2191         I915_WRITE(TILECTL,                     s->tilectl);
2192         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2193         /*
2194          * Preserve the GT allow wake and GFX force clock bit, they are not
2195          * be restored, as they are used to control the s0ix suspend/resume
2196          * sequence by the caller.
2197          */
2198         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2199         val &= VLV_GTLC_ALLOWWAKEREQ;
2200         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2201         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2202
2203         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2204         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2205         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2206         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2207
2208         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2209
2210         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2211         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2212         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2213         I915_WRITE(VLV_PCBR,                    s->pcbr);
2214         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2215 }
2216
2217 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2218                                   u32 mask, u32 val)
2219 {
2220         /* The HW does not like us polling for PW_STATUS frequently, so
2221          * use the sleeping loop rather than risk the busy spin within
2222          * intel_wait_for_register().
2223          *
2224          * Transitioning between RC6 states should be at most 2ms (see
2225          * valleyview_enable_rps) so use a 3ms timeout.
2226          */
2227         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2228                         3);
2229 }
2230
2231 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2232 {
2233         u32 val;
2234         int err;
2235
2236         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2237         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2238         if (force_on)
2239                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2240         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2241
2242         if (!force_on)
2243                 return 0;
2244
2245         err = intel_wait_for_register(dev_priv,
2246                                       VLV_GTLC_SURVIVABILITY_REG,
2247                                       VLV_GFX_CLK_STATUS_BIT,
2248                                       VLV_GFX_CLK_STATUS_BIT,
2249                                       20);
2250         if (err)
2251                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2252                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2253
2254         return err;
2255 }
2256
2257 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2258 {
2259         u32 mask;
2260         u32 val;
2261         int err;
2262
2263         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2264         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2265         if (allow)
2266                 val |= VLV_GTLC_ALLOWWAKEREQ;
2267         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2268         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2269
2270         mask = VLV_GTLC_ALLOWWAKEACK;
2271         val = allow ? mask : 0;
2272
2273         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2274         if (err)
2275                 DRM_ERROR("timeout disabling GT waking\n");
2276
2277         return err;
2278 }
2279
2280 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2281                                   bool wait_for_on)
2282 {
2283         u32 mask;
2284         u32 val;
2285
2286         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2287         val = wait_for_on ? mask : 0;
2288
2289         /*
2290          * RC6 transitioning can be delayed up to 2 msec (see
2291          * valleyview_enable_rps), use 3 msec for safety.
2292          */
2293         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2294                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2295                           onoff(wait_for_on));
2296 }
2297
2298 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2299 {
2300         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2301                 return;
2302
2303         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2304         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2305 }
2306
2307 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2308 {
2309         u32 mask;
2310         int err;
2311
2312         /*
2313          * Bspec defines the following GT well on flags as debug only, so
2314          * don't treat them as hard failures.
2315          */
2316         vlv_wait_for_gt_wells(dev_priv, false);
2317
2318         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2319         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2320
2321         vlv_check_no_gt_access(dev_priv);
2322
2323         err = vlv_force_gfx_clock(dev_priv, true);
2324         if (err)
2325                 goto err1;
2326
2327         err = vlv_allow_gt_wake(dev_priv, false);
2328         if (err)
2329                 goto err2;
2330
2331         if (!IS_CHERRYVIEW(dev_priv))
2332                 vlv_save_gunit_s0ix_state(dev_priv);
2333
2334         err = vlv_force_gfx_clock(dev_priv, false);
2335         if (err)
2336                 goto err2;
2337
2338         return 0;
2339
2340 err2:
2341         /* For safety always re-enable waking and disable gfx clock forcing */
2342         vlv_allow_gt_wake(dev_priv, true);
2343 err1:
2344         vlv_force_gfx_clock(dev_priv, false);
2345
2346         return err;
2347 }
2348
2349 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2350                                 bool rpm_resume)
2351 {
2352         int err;
2353         int ret;
2354
2355         /*
2356          * If any of the steps fail just try to continue, that's the best we
2357          * can do at this point. Return the first error code (which will also
2358          * leave RPM permanently disabled).
2359          */
2360         ret = vlv_force_gfx_clock(dev_priv, true);
2361
2362         if (!IS_CHERRYVIEW(dev_priv))
2363                 vlv_restore_gunit_s0ix_state(dev_priv);
2364
2365         err = vlv_allow_gt_wake(dev_priv, true);
2366         if (!ret)
2367                 ret = err;
2368
2369         err = vlv_force_gfx_clock(dev_priv, false);
2370         if (!ret)
2371                 ret = err;
2372
2373         vlv_check_no_gt_access(dev_priv);
2374
2375         if (rpm_resume)
2376                 intel_init_clock_gating(dev_priv);
2377
2378         return ret;
2379 }
2380
2381 static int intel_runtime_suspend(struct device *kdev)
2382 {
2383         struct pci_dev *pdev = to_pci_dev(kdev);
2384         struct drm_device *dev = pci_get_drvdata(pdev);
2385         struct drm_i915_private *dev_priv = to_i915(dev);
2386         int ret;
2387
2388         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2389                 return -ENODEV;
2390
2391         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2392                 return -ENODEV;
2393
2394         DRM_DEBUG_KMS("Suspending device\n");
2395
2396         disable_rpm_wakeref_asserts(dev_priv);
2397
2398         /*
2399          * We are safe here against re-faults, since the fault handler takes
2400          * an RPM reference.
2401          */
2402         i915_gem_runtime_suspend(dev_priv);
2403
2404         intel_guc_suspend(dev_priv);
2405
2406         intel_runtime_pm_disable_interrupts(dev_priv);
2407
2408         ret = 0;
2409         if (IS_GEN9_LP(dev_priv)) {
2410                 bxt_display_core_uninit(dev_priv);
2411                 bxt_enable_dc9(dev_priv);
2412         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2413                 hsw_enable_pc8(dev_priv);
2414         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2415                 ret = vlv_suspend_complete(dev_priv);
2416         }
2417
2418         if (ret) {
2419                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2420                 intel_runtime_pm_enable_interrupts(dev_priv);
2421
2422                 enable_rpm_wakeref_asserts(dev_priv);
2423
2424                 return ret;
2425         }
2426
2427         intel_uncore_suspend(dev_priv);
2428
2429         enable_rpm_wakeref_asserts(dev_priv);
2430         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2431
2432         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2433                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2434
2435         dev_priv->pm.suspended = true;
2436
2437         /*
2438          * FIXME: We really should find a document that references the arguments
2439          * used below!
2440          */
2441         if (IS_BROADWELL(dev_priv)) {
2442                 /*
2443                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2444                  * being detected, and the call we do at intel_runtime_resume()
2445                  * won't be able to restore them. Since PCI_D3hot matches the
2446                  * actual specification and appears to be working, use it.
2447                  */
2448                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2449         } else {
2450                 /*
2451                  * current versions of firmware which depend on this opregion
2452                  * notification have repurposed the D1 definition to mean
2453                  * "runtime suspended" vs. what you would normally expect (D3)
2454                  * to distinguish it from notifications that might be sent via
2455                  * the suspend path.
2456                  */
2457                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2458         }
2459
2460         assert_forcewakes_inactive(dev_priv);
2461
2462         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2463                 intel_hpd_poll_init(dev_priv);
2464
2465         DRM_DEBUG_KMS("Device suspended\n");
2466         return 0;
2467 }
2468
2469 static int intel_runtime_resume(struct device *kdev)
2470 {
2471         struct pci_dev *pdev = to_pci_dev(kdev);
2472         struct drm_device *dev = pci_get_drvdata(pdev);
2473         struct drm_i915_private *dev_priv = to_i915(dev);
2474         int ret = 0;
2475
2476         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2477                 return -ENODEV;
2478
2479         DRM_DEBUG_KMS("Resuming device\n");
2480
2481         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2482         disable_rpm_wakeref_asserts(dev_priv);
2483
2484         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2485         dev_priv->pm.suspended = false;
2486         if (intel_uncore_unclaimed_mmio(dev_priv))
2487                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2488
2489         intel_guc_resume(dev_priv);
2490
2491         if (IS_GEN9_LP(dev_priv)) {
2492                 bxt_disable_dc9(dev_priv);
2493                 bxt_display_core_init(dev_priv, true);
2494                 if (dev_priv->csr.dmc_payload &&
2495                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2496                         gen9_enable_dc5(dev_priv);
2497         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2498                 hsw_disable_pc8(dev_priv);
2499         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2500                 ret = vlv_resume_prepare(dev_priv, true);
2501         }
2502
2503         /*
2504          * No point of rolling back things in case of an error, as the best
2505          * we can do is to hope that things will still work (and disable RPM).
2506          */
2507         i915_gem_init_swizzling(dev_priv);
2508         i915_gem_restore_fences(dev_priv);
2509
2510         intel_runtime_pm_enable_interrupts(dev_priv);
2511
2512         /*
2513          * On VLV/CHV display interrupts are part of the display
2514          * power well, so hpd is reinitialized from there. For
2515          * everyone else do it here.
2516          */
2517         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2518                 intel_hpd_init(dev_priv);
2519
2520         enable_rpm_wakeref_asserts(dev_priv);
2521
2522         if (ret)
2523                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2524         else
2525                 DRM_DEBUG_KMS("Device resumed\n");
2526
2527         return ret;
2528 }
2529
2530 const struct dev_pm_ops i915_pm_ops = {
2531         /*
2532          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2533          * PMSG_RESUME]
2534          */
2535         .suspend = i915_pm_suspend,
2536         .suspend_late = i915_pm_suspend_late,
2537         .resume_early = i915_pm_resume_early,
2538         .resume = i915_pm_resume,
2539
2540         /*
2541          * S4 event handlers
2542          * @freeze, @freeze_late    : called (1) before creating the
2543          *                            hibernation image [PMSG_FREEZE] and
2544          *                            (2) after rebooting, before restoring
2545          *                            the image [PMSG_QUIESCE]
2546          * @thaw, @thaw_early       : called (1) after creating the hibernation
2547          *                            image, before writing it [PMSG_THAW]
2548          *                            and (2) after failing to create or
2549          *                            restore the image [PMSG_RECOVER]
2550          * @poweroff, @poweroff_late: called after writing the hibernation
2551          *                            image, before rebooting [PMSG_HIBERNATE]
2552          * @restore, @restore_early : called after rebooting and restoring the
2553          *                            hibernation image [PMSG_RESTORE]
2554          */
2555         .freeze = i915_pm_freeze,
2556         .freeze_late = i915_pm_freeze_late,
2557         .thaw_early = i915_pm_thaw_early,
2558         .thaw = i915_pm_thaw,
2559         .poweroff = i915_pm_suspend,
2560         .poweroff_late = i915_pm_poweroff_late,
2561         .restore_early = i915_pm_restore_early,
2562         .restore = i915_pm_restore,
2563
2564         /* S0ix (via runtime suspend) event handlers */
2565         .runtime_suspend = intel_runtime_suspend,
2566         .runtime_resume = intel_runtime_resume,
2567 };
2568
2569 static const struct vm_operations_struct i915_gem_vm_ops = {
2570         .fault = i915_gem_fault,
2571         .open = drm_gem_vm_open,
2572         .close = drm_gem_vm_close,
2573 };
2574
2575 static const struct file_operations i915_driver_fops = {
2576         .owner = THIS_MODULE,
2577         .open = drm_open,
2578         .release = drm_release,
2579         .unlocked_ioctl = drm_ioctl,
2580         .mmap = drm_gem_mmap,
2581         .poll = drm_poll,
2582         .read = drm_read,
2583         .compat_ioctl = i915_compat_ioctl,
2584         .llseek = noop_llseek,
2585 };
2586
2587 static int
2588 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2589                           struct drm_file *file)
2590 {
2591         return -ENODEV;
2592 }
2593
2594 static const struct drm_ioctl_desc i915_ioctls[] = {
2595         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2596         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2597         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2598         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2599         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2600         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2601         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2602         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2603         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2604         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2605         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2606         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2607         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2608         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2609         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2610         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2611         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2612         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2613         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2614         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2615         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2616         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2617         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2618         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2619         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2620         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2621         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2622         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2623         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2624         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2625         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2626         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2627         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2628         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2629         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2630         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2631         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2632         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2633         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2634         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2635         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2636         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2637         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2638         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2639         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2640         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2641         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2642         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2643         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2644         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2645         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2646         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2647         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2648 };
2649
2650 static struct drm_driver driver = {
2651         /* Don't use MTRRs here; the Xserver or userspace app should
2652          * deal with them for Intel hardware.
2653          */
2654         .driver_features =
2655             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2656             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2657         .release = i915_driver_release,
2658         .open = i915_driver_open,
2659         .lastclose = i915_driver_lastclose,
2660         .postclose = i915_driver_postclose,
2661         .set_busid = drm_pci_set_busid,
2662
2663         .gem_close_object = i915_gem_close_object,
2664         .gem_free_object_unlocked = i915_gem_free_object,
2665         .gem_vm_ops = &i915_gem_vm_ops,
2666
2667         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2668         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2669         .gem_prime_export = i915_gem_prime_export,
2670         .gem_prime_import = i915_gem_prime_import,
2671
2672         .dumb_create = i915_gem_dumb_create,
2673         .dumb_map_offset = i915_gem_mmap_gtt,
2674         .dumb_destroy = drm_gem_dumb_destroy,
2675         .ioctls = i915_ioctls,
2676         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2677         .fops = &i915_driver_fops,
2678         .name = DRIVER_NAME,
2679         .desc = DRIVER_DESC,
2680         .date = DRIVER_DATE,
2681         .major = DRIVER_MAJOR,
2682         .minor = DRIVER_MINOR,
2683         .patchlevel = DRIVER_PATCHLEVEL,
2684 };
2685
2686 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2687 #include "selftests/mock_drm.c"
2688 #endif