drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .num_pipes = 3,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .is_valleyview = 1,
 354         .display_mmio_offset = VLV_DISPLAY_BASE,
 355         GEN_CHV_PIPEOFFSETS,
 356         CURSOR_OFFSETS,
 357 };
 358
 359 static const struct intel_device_info intel_skylake_info = {
 360         .is_preliminary = 1,
 361         .is_skylake = 1,
 362         .gen = 9, .num_pipes = 3,
 363         .need_gfx_hws = 1, .has_hotplug = 1,
 364         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 365         .has_llc = 1,
 366         .has_ddi = 1,
 367         .has_fbc = 1,
 368         GEN_DEFAULT_PIPEOFFSETS,
 369         IVB_CURSOR_OFFSETS,
 370 };
 371
 372 /*
 373  * Make sure any device matches here are from most specific to most
 374  * general.  For example, since the Quanta match is based on the subsystem
 375  * and subvendor IDs, we need it to come before the more general IVB
 376  * PCI ID matches, otherwise we'll use the wrong info struct above.
 377  */
 378 #define INTEL_PCI_IDS \
 379         INTEL_I830_IDS(&intel_i830_info),       \
 380         INTEL_I845G_IDS(&intel_845g_info),      \
 381         INTEL_I85X_IDS(&intel_i85x_info),       \
 382         INTEL_I865G_IDS(&intel_i865g_info),     \
 383         INTEL_I915G_IDS(&intel_i915g_info),     \
 384         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 385         INTEL_I945G_IDS(&intel_i945g_info),     \
 386         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 387         INTEL_I965G_IDS(&intel_i965g_info),     \
 388         INTEL_G33_IDS(&intel_g33_info),         \
 389         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 390         INTEL_GM45_IDS(&intel_gm45_info),       \
 391         INTEL_G45_IDS(&intel_g45_info),         \
 392         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 393         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 394         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 395         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 396         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 397         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 398         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 399         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 400         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 401         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 402         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 403         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 404         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 405         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 406         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 407         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 408         INTEL_CHV_IDS(&intel_cherryview_info),  \
 409         INTEL_SKL_IDS(&intel_skylake_info)
 410
 411 static const struct pci_device_id pciidlist[] = {               /* aka */
 412         INTEL_PCI_IDS,
 413         {0, 0, 0}
 414 };
 415
 416 #if defined(CONFIG_DRM_I915_KMS)
 417 MODULE_DEVICE_TABLE(pci, pciidlist);
 418 #endif
 419
 420 void intel_detect_pch(struct drm_device *dev)
 421 {
 422         struct drm_i915_private *dev_priv = dev->dev_private;
 423         struct pci_dev *pch = NULL;
 424
 425         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 426          * (which really amounts to a PCH but no South Display).
 427          */
 428         if (INTEL_INFO(dev)->num_pipes == 0) {
 429                 dev_priv->pch_type = PCH_NOP;
 430                 return;
 431         }
 432
 433         /*
 434          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 435          * make graphics device passthrough work easy for VMM, that only
 436          * need to expose ISA bridge to let driver know the real hardware
 437          * underneath. This is a requirement from virtualization team.
 438          *
 439          * In some virtualized environments (e.g. XEN), there is irrelevant
 440          * ISA bridge in the system. To work reliably, we should scan trhough
 441          * all the ISA bridge devices and check for the first match, instead
 442          * of only checking the first one.
 443          */
 444         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 445                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 446                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 447                         dev_priv->pch_id = id;
 448
 449                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 450                                 dev_priv->pch_type = PCH_IBX;
 451                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 452                                 WARN_ON(!IS_GEN5(dev));
 453                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 454                                 dev_priv->pch_type = PCH_CPT;
 455                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 456                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 457                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 458                                 /* PantherPoint is CPT compatible */
 459                                 dev_priv->pch_type = PCH_CPT;
 460                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 461                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 462                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 463                                 dev_priv->pch_type = PCH_LPT;
 464                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 465                                 WARN_ON(!IS_HASWELL(dev));
 466                                 WARN_ON(IS_HSW_ULT(dev));
 467                         } else if (IS_BROADWELL(dev)) {
 468                                 dev_priv->pch_type = PCH_LPT;
 469                                 dev_priv->pch_id =
 470                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 471                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 472                                               "LynxPoint LP PCH\n");
 473                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 474                                 dev_priv->pch_type = PCH_LPT;
 475                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 476                                 WARN_ON(!IS_HASWELL(dev));
 477                                 WARN_ON(!IS_HSW_ULT(dev));
 478                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 479                                 dev_priv->pch_type = PCH_SPT;
 480                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 481                                 WARN_ON(!IS_SKYLAKE(dev));
 482                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 483                                 dev_priv->pch_type = PCH_SPT;
 484                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 485                                 WARN_ON(!IS_SKYLAKE(dev));
 486                         } else
 487                                 continue;
 488
 489                         break;
 490                 }
 491         }
 492         if (!pch)
 493                 DRM_DEBUG_KMS("No PCH found.\n");
 494
 495         pci_dev_put(pch);
 496 }
 497
 498 bool i915_semaphore_is_enabled(struct drm_device *dev)
 499 {
 500         if (INTEL_INFO(dev)->gen < 6)
 501                 return false;
 502
 503         if (i915.semaphores >= 0)
 504                 return i915.semaphores;
 505
 506         /* TODO: make semaphores and Execlists play nicely together */
 507         if (i915.enable_execlists)
 508                 return false;
 509
 510         /* Until we get further testing... */
 511         if (IS_GEN8(dev))
 512                 return false;
 513
 514 #ifdef CONFIG_INTEL_IOMMU
 515         /* Enable semaphores on SNB when IO remapping is off */
 516         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 517                 return false;
 518 #endif
 519
 520         return true;
 521 }
 522
 523 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 524 {
 525         spin_lock_irq(&dev_priv->irq_lock);
 526
 527         dev_priv->long_hpd_port_mask = 0;
 528         dev_priv->short_hpd_port_mask = 0;
 529         dev_priv->hpd_event_bits = 0;
 530
 531         spin_unlock_irq(&dev_priv->irq_lock);
 532
 533         cancel_work_sync(&dev_priv->dig_port_work);
 534         cancel_work_sync(&dev_priv->hotplug_work);
 535         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 536 }
 537
 538 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 539 {
 540         struct drm_device *dev = dev_priv->dev;
 541         struct drm_encoder *encoder;
 542
 543         drm_modeset_lock_all(dev);
 544         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 545                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 546
 547                 if (intel_encoder->suspend)
 548                         intel_encoder->suspend(intel_encoder);
 549         }
 550         drm_modeset_unlock_all(dev);
 551 }
 552
 553 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 554 static int intel_resume_prepare(struct drm_i915_private *dev_priv,
 555                                 bool rpm_resume);
 556
 557 static int i915_drm_freeze(struct drm_device *dev)
 558 {
 559         struct drm_i915_private *dev_priv = dev->dev_private;
 560         struct drm_crtc *crtc;
 561         pci_power_t opregion_target_state;
 562
 563         /* ignore lid events during suspend */
 564         mutex_lock(&dev_priv->modeset_restore_lock);
 565         dev_priv->modeset_restore = MODESET_SUSPENDED;
 566         mutex_unlock(&dev_priv->modeset_restore_lock);
 567
 568         /* We do a lot of poking in a lot of registers, make sure they work
 569          * properly. */
 570         intel_display_set_init_power(dev_priv, true);
 571
 572         drm_kms_helper_poll_disable(dev);
 573
 574         pci_save_state(dev->pdev);
 575
 576         /* If KMS is active, we do the leavevt stuff here */
 577         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 578                 int error;
 579
 580                 error = i915_gem_suspend(dev);
 581                 if (error) {
 582                         dev_err(&dev->pdev->dev,
 583                                 "GEM idle failed, resume might fail\n");
 584                         return error;
 585                 }
 586
 587                 /*
 588                  * Disable CRTCs directly since we want to preserve sw state
 589                  * for _thaw. Also, power gate the CRTC power wells.
 590                  */
 591                 drm_modeset_lock_all(dev);
 592                 for_each_crtc(dev, crtc)
 593                         intel_crtc_control(crtc, false);
 594                 drm_modeset_unlock_all(dev);
 595
 596                 intel_dp_mst_suspend(dev);
 597
 598                 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 599
 600                 intel_runtime_pm_disable_interrupts(dev_priv);
 601                 intel_hpd_cancel_work(dev_priv);
 602
 603                 intel_suspend_encoders(dev_priv);
 604
 605                 intel_suspend_gt_powersave(dev);
 606
 607                 intel_suspend_hw(dev);
 608         }
 609
 610         i915_gem_suspend_gtt_mappings(dev);
 611
 612         i915_save_state(dev);
 613
 614         opregion_target_state = PCI_D3cold;
 615 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 616         if (acpi_target_system_state() < ACPI_STATE_S3)
 617                 opregion_target_state = PCI_D1;
 618 #endif
 619         intel_opregion_notify_adapter(dev, opregion_target_state);
 620
 621         intel_uncore_forcewake_reset(dev, false);
 622         intel_opregion_fini(dev);
 623
 624         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 625
 626         dev_priv->suspend_count++;
 627
 628         intel_display_set_init_power(dev_priv, false);
 629
 630         return 0;
 631 }
 632
 633 static int i915_drm_suspend_late(struct drm_device *drm_dev)
 634 {
 635         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 636         int ret;
 637
 638         ret = intel_suspend_complete(dev_priv);
 639
 640         if (ret) {
 641                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 642
 643                 return ret;
 644         }
 645
 646         pci_disable_device(drm_dev->pdev);
 647         pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 648
 649         return 0;
 650 }
 651
 652 int i915_suspend(struct drm_device *dev, pm_message_t state)
 653 {
 654         int error;
 655
 656         if (!dev || !dev->dev_private) {
 657                 DRM_ERROR("dev: %p\n", dev);
 658                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 659                 return -ENODEV;
 660         }
 661
 662         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 663                          state.event != PM_EVENT_FREEZE))
 664                 return -EINVAL;
 665
 666         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 667                 return 0;
 668
 669         error = i915_drm_freeze(dev);
 670         if (error)
 671                 return error;
 672
 673         return i915_drm_suspend_late(dev);
 674 }
 675
 676 static int i915_drm_thaw_early(struct drm_device *dev)
 677 {
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         int ret;
 680
 681         ret = intel_resume_prepare(dev_priv, false);
 682         if (ret)
 683                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 684
 685         intel_uncore_early_sanitize(dev, true);
 686         intel_uncore_sanitize(dev);
 687         intel_power_domains_init_hw(dev_priv);
 688
 689         return ret;
 690 }
 691
 692 static int __i915_drm_thaw(struct drm_device *dev)
 693 {
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695
 696         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 697                 mutex_lock(&dev->struct_mutex);
 698                 i915_gem_restore_gtt_mappings(dev);
 699                 mutex_unlock(&dev->struct_mutex);
 700         }
 701
 702         i915_restore_state(dev);
 703         intel_opregion_setup(dev);
 704
 705         /* KMS EnterVT equivalent */
 706         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 707                 intel_init_pch_refclk(dev);
 708                 drm_mode_config_reset(dev);
 709
 710                 mutex_lock(&dev->struct_mutex);
 711                 if (i915_gem_init_hw(dev)) {
 712                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 713                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 714                 }
 715                 mutex_unlock(&dev->struct_mutex);
 716
 717                 /* We need working interrupts for modeset enabling ... */
 718                 intel_runtime_pm_enable_interrupts(dev_priv);
 719
 720                 intel_modeset_init_hw(dev);
 721
 722                 {
 723                         spin_lock_irq(&dev_priv->irq_lock);
 724                         if (dev_priv->display.hpd_irq_setup)
 725                                 dev_priv->display.hpd_irq_setup(dev);
 726                         spin_unlock_irq(&dev_priv->irq_lock);
 727                 }
 728
 729                 intel_dp_mst_resume(dev);
 730                 drm_modeset_lock_all(dev);
 731                 intel_modeset_setup_hw_state(dev, true);
 732                 drm_modeset_unlock_all(dev);
 733
 734                 /*
 735                  * ... but also need to make sure that hotplug processing
 736                  * doesn't cause havoc. Like in the driver load code we don't
 737                  * bother with the tiny race here where we might loose hotplug
 738                  * notifications.
 739                  * */
 740                 intel_hpd_init(dev_priv);
 741                 /* Config may have changed between suspend and resume */
 742                 drm_helper_hpd_irq_event(dev);
 743         }
 744
 745         intel_opregion_init(dev);
 746
 747         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 748
 749         mutex_lock(&dev_priv->modeset_restore_lock);
 750         dev_priv->modeset_restore = MODESET_DONE;
 751         mutex_unlock(&dev_priv->modeset_restore_lock);
 752
 753         intel_opregion_notify_adapter(dev, PCI_D0);
 754
 755         return 0;
 756 }
 757
 758 static int i915_drm_thaw(struct drm_device *dev)
 759 {
 760         return __i915_drm_thaw(dev);
 761 }
 762
 763 static int i915_resume_early(struct drm_device *dev)
 764 {
 765         /*
 766          * We have a resume ordering issue with the snd-hda driver also
 767          * requiring our device to be power up. Due to the lack of a
 768          * parent/child relationship we currently solve this with an early
 769          * resume hook.
 770          *
 771          * FIXME: This should be solved with a special hdmi sink device or
 772          * similar so that power domains can be employed.
 773          */
 774         if (pci_enable_device(dev->pdev))
 775                 return -EIO;
 776
 777         pci_set_master(dev->pdev);
 778
 779         return i915_drm_thaw_early(dev);
 780 }
 781
 782 static int i915_drm_resume(struct drm_device *dev)
 783 {
 784         int ret;
 785
 786         ret = __i915_drm_thaw(dev);
 787         if (ret)
 788                 return ret;
 789
 790         drm_kms_helper_poll_enable(dev);
 791         return 0;
 792 }
 793
 794 static int i915_resume_legacy(struct drm_device *dev)
 795 {
 796         int ret;
 797
 798         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 799                 return 0;
 800
 801         ret = i915_resume_early(dev);
 802         if (ret)
 803                 return ret;
 804
 805         return i915_drm_resume(dev);
 806 }
 807
 808 int i915_resume(struct drm_device *dev)
 809 {
 810         return i915_resume_legacy(dev);
 811 }
 812
 813 /**
 814  * i915_reset - reset chip after a hang
 815  * @dev: drm device to reset
 816  *
 817  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 818  * reset or otherwise an error code.
 819  *
 820  * Procedure is fairly simple:
 821  *   - reset the chip using the reset reg
 822  *   - re-init context state
 823  *   - re-init hardware status page
 824  *   - re-init ring buffer
 825  *   - re-init interrupt state
 826  *   - re-init display
 827  */
 828 int i915_reset(struct drm_device *dev)
 829 {
 830         struct drm_i915_private *dev_priv = dev->dev_private;
 831         bool simulated;
 832         int ret;
 833
 834         if (!i915.reset)
 835                 return 0;
 836
 837         mutex_lock(&dev->struct_mutex);
 838
 839         i915_gem_reset(dev);
 840
 841         simulated = dev_priv->gpu_error.stop_rings != 0;
 842
 843         ret = intel_gpu_reset(dev);
 844
 845         /* Also reset the gpu hangman. */
 846         if (simulated) {
 847                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 848                 dev_priv->gpu_error.stop_rings = 0;
 849                 if (ret == -ENODEV) {
 850                         DRM_INFO("Reset not implemented, but ignoring "
 851                                  "error for simulated gpu hangs\n");
 852                         ret = 0;
 853                 }
 854         }
 855
 856         if (i915_stop_ring_allow_warn(dev_priv))
 857                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 858
 859         if (ret) {
 860                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 861                 mutex_unlock(&dev->struct_mutex);
 862                 return ret;
 863         }
 864
 865         /* Ok, now get things going again... */
 866
 867         /*
 868          * Everything depends on having the GTT running, so we need to start
 869          * there.  Fortunately we don't need to do this unless we reset the
 870          * chip at a PCI level.
 871          *
 872          * Next we need to restore the context, but we don't use those
 873          * yet either...
 874          *
 875          * Ring buffer needs to be re-initialized in the KMS case, or if X
 876          * was running at the time of the reset (i.e. we weren't VT
 877          * switched away).
 878          */
 879         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 880                         !dev_priv->ums.mm_suspended) {
 881                 dev_priv->ums.mm_suspended = 0;
 882
 883                 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 884                 dev_priv->gpu_error.reload_in_reset = true;
 885
 886                 ret = i915_gem_init_hw(dev);
 887
 888                 dev_priv->gpu_error.reload_in_reset = false;
 889
 890                 mutex_unlock(&dev->struct_mutex);
 891                 if (ret) {
 892                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 893                         return ret;
 894                 }
 895
 896                 /*
 897                  * FIXME: This races pretty badly against concurrent holders of
 898                  * ring interrupts. This is possible since we've started to drop
 899                  * dev->struct_mutex in select places when waiting for the gpu.
 900                  */
 901
 902                 /*
 903                  * rps/rc6 re-init is necessary to restore state lost after the
 904                  * reset and the re-install of gt irqs. Skip for ironlake per
 905                  * previous concerns that it doesn't respond well to some forms
 906                  * of re-init after reset.
 907                  */
 908                 if (INTEL_INFO(dev)->gen > 5)
 909                         intel_reset_gt_powersave(dev);
 910         } else {
 911                 mutex_unlock(&dev->struct_mutex);
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 918 {
 919         struct intel_device_info *intel_info =
 920                 (struct intel_device_info *) ent->driver_data;
 921
 922         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 923                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 924                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 925                 return -ENODEV;
 926         }
 927
 928         /* Only bind to function 0 of the device. Early generations
 929          * used function 1 as a placeholder for multi-head. This causes
 930          * us confusion instead, especially on the systems where both
 931          * functions have the same PCI-ID!
 932          */
 933         if (PCI_FUNC(pdev->devfn))
 934                 return -ENODEV;
 935
 936         driver.driver_features &= ~(DRIVER_USE_AGP);
 937
 938         return drm_get_pci_dev(pdev, ent, &driver);
 939 }
 940
 941 static void
 942 i915_pci_remove(struct pci_dev *pdev)
 943 {
 944         struct drm_device *dev = pci_get_drvdata(pdev);
 945
 946         drm_put_dev(dev);
 947 }
 948
 949 static int i915_pm_suspend(struct device *dev)
 950 {
 951         struct pci_dev *pdev = to_pci_dev(dev);
 952         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 953
 954         if (!drm_dev || !drm_dev->dev_private) {
 955                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 956                 return -ENODEV;
 957         }
 958
 959         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 960                 return 0;
 961
 962         return i915_drm_freeze(drm_dev);
 963 }
 964
 965 static int i915_pm_suspend_late(struct device *dev)
 966 {
 967         struct pci_dev *pdev = to_pci_dev(dev);
 968         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 969
 970         /*
 971          * We have a suspedn ordering issue with the snd-hda driver also
 972          * requiring our device to be power up. Due to the lack of a
 973          * parent/child relationship we currently solve this with an late
 974          * suspend hook.
 975          *
 976          * FIXME: This should be solved with a special hdmi sink device or
 977          * similar so that power domains can be employed.
 978          */
 979         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 980                 return 0;
 981
 982         return i915_drm_suspend_late(drm_dev);
 983 }
 984
 985 static int i915_pm_resume_early(struct device *dev)
 986 {
 987         struct pci_dev *pdev = to_pci_dev(dev);
 988         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 989
 990         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 991                 return 0;
 992
 993         return i915_resume_early(drm_dev);
 994 }
 995
 996 static int i915_pm_resume(struct device *dev)
 997 {
 998         struct pci_dev *pdev = to_pci_dev(dev);
 999         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1000
1001         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1002                 return 0;
1003
1004         return i915_drm_resume(drm_dev);
1005 }
1006
1007 static int i915_pm_freeze(struct device *dev)
1008 {
1009         struct pci_dev *pdev = to_pci_dev(dev);
1010         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1011
1012         if (!drm_dev || !drm_dev->dev_private) {
1013                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1014                 return -ENODEV;
1015         }
1016
1017         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1018                 return 0;
1019
1020         return i915_drm_freeze(drm_dev);
1021 }
1022
1023 static int i915_pm_freeze_late(struct device *dev)
1024 {
1025         struct pci_dev *pdev = to_pci_dev(dev);
1026         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1027         struct drm_i915_private *dev_priv = drm_dev->dev_private;
1028
1029         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1030                 return 0;
1031
1032         return intel_suspend_complete(dev_priv);
1033 }
1034
1035 static int i915_pm_thaw_early(struct device *dev)
1036 {
1037         struct pci_dev *pdev = to_pci_dev(dev);
1038         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1039
1040         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1041                 return 0;
1042
1043         return i915_drm_thaw_early(drm_dev);
1044 }
1045
1046 static int i915_pm_thaw(struct device *dev)
1047 {
1048         struct pci_dev *pdev = to_pci_dev(dev);
1049         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1050
1051         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1052                 return 0;
1053
1054         return i915_drm_thaw(drm_dev);
1055 }
1056
1057 static int i915_pm_poweroff(struct device *dev)
1058 {
1059         struct pci_dev *pdev = to_pci_dev(dev);
1060         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1061
1062         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1063                 return 0;
1064
1065         return i915_drm_freeze(drm_dev);
1066 }
1067
1068 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1069 {
1070         hsw_enable_pc8(dev_priv);
1071
1072         return 0;
1073 }
1074
1075 static int snb_resume_prepare(struct drm_i915_private *dev_priv,
1076                                 bool rpm_resume)
1077 {
1078         struct drm_device *dev = dev_priv->dev;
1079
1080         if (rpm_resume)
1081                 intel_init_pch_refclk(dev);
1082
1083         return 0;
1084 }
1085
1086 static int hsw_resume_prepare(struct drm_i915_private *dev_priv,
1087                                 bool rpm_resume)
1088 {
1089         hsw_disable_pc8(dev_priv);
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * Save all Gunit registers that may be lost after a D3 and a subsequent
1096  * S0i[R123] transition. The list of registers needing a save/restore is
1097  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1098  * registers in the following way:
1099  * - Driver: saved/restored by the driver
1100  * - Punit : saved/restored by the Punit firmware
1101  * - No, w/o marking: no need to save/restore, since the register is R/O or
1102  *                    used internally by the HW in a way that doesn't depend
1103  *                    keeping the content across a suspend/resume.
1104  * - Debug : used for debugging
1105  *
1106  * We save/restore all registers marked with 'Driver', with the following
1107  * exceptions:
1108  * - Registers out of use, including also registers marked with 'Debug'.
1109  *   These have no effect on the driver's operation, so we don't save/restore
1110  *   them to reduce the overhead.
1111  * - Registers that are fully setup by an initialization function called from
1112  *   the resume path. For example many clock gating and RPS/RC6 registers.
1113  * - Registers that provide the right functionality with their reset defaults.
1114  *
1115  * TODO: Except for registers that based on the above 3 criteria can be safely
1116  * ignored, we save/restore all others, practically treating the HW context as
1117  * a black-box for the driver. Further investigation is needed to reduce the
1118  * saved/restored registers even further, by following the same 3 criteria.
1119  */
1120 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1121 {
1122         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1123         int i;
1124
1125         /* GAM 0x4000-0x4770 */
1126         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1127         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1128         s->arb_mode             = I915_READ(ARB_MODE);
1129         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1130         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1131
1132         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1133                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1134
1135         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1136         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1137
1138         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1139         s->ecochk               = I915_READ(GAM_ECOCHK);
1140         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1141         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1142
1143         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1144
1145         /* MBC 0x9024-0x91D0, 0x8500 */
1146         s->g3dctl               = I915_READ(VLV_G3DCTL);
1147         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1148         s->mbctl                = I915_READ(GEN6_MBCTL);
1149
1150         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1151         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1152         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1153         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1154         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1155         s->rstctl               = I915_READ(GEN6_RSTCTL);
1156         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1157
1158         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1159         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1160         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1161         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1162         s->ecobus               = I915_READ(ECOBUS);
1163         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1164         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1165         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1166         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1167         s->rcedata              = I915_READ(VLV_RCEDATA);
1168         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1169
1170         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1171         s->gt_imr               = I915_READ(GTIMR);
1172         s->gt_ier               = I915_READ(GTIER);
1173         s->pm_imr               = I915_READ(GEN6_PMIMR);
1174         s->pm_ier               = I915_READ(GEN6_PMIER);
1175
1176         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1177                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1178
1179         /* GT SA CZ domain, 0x100000-0x138124 */
1180         s->tilectl              = I915_READ(TILECTL);
1181         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1182         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1183         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1184         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1185
1186         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1187         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1188         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1189         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1190
1191         /*
1192          * Not saving any of:
1193          * DFT,         0x9800-0x9EC0
1194          * SARB,        0xB000-0xB1FC
1195          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1196          * PCI CFG
1197          */
1198 }
1199
1200 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1201 {
1202         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1203         u32 val;
1204         int i;
1205
1206         /* GAM 0x4000-0x4770 */
1207         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1208         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1209         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1210         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1211         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1212
1213         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1214                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1215
1216         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1217         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1218
1219         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1220         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1221         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1222         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1223
1224         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1225
1226         /* MBC 0x9024-0x91D0, 0x8500 */
1227         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1228         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1229         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1230
1231         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1232         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1233         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1234         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1235         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1236         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1237         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1238
1239         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1240         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1241         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1242         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1243         I915_WRITE(ECOBUS,              s->ecobus);
1244         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1245         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1246         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1247         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1248         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1249         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1250
1251         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1252         I915_WRITE(GTIMR,               s->gt_imr);
1253         I915_WRITE(GTIER,               s->gt_ier);
1254         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1255         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1256
1257         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1258                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1259
1260         /* GT SA CZ domain, 0x100000-0x138124 */
1261         I915_WRITE(TILECTL,                     s->tilectl);
1262         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1263         /*
1264          * Preserve the GT allow wake and GFX force clock bit, they are not
1265          * be restored, as they are used to control the s0ix suspend/resume
1266          * sequence by the caller.
1267          */
1268         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1269         val &= VLV_GTLC_ALLOWWAKEREQ;
1270         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1271         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1272
1273         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1274         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1275         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1276         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1277
1278         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1279
1280         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1281         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1282         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1283         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1284 }
1285
1286 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1287 {
1288         u32 val;
1289         int err;
1290
1291         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1292         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1293
1294 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1295         /* Wait for a previous force-off to settle */
1296         if (force_on) {
1297                 err = wait_for(!COND, 20);
1298                 if (err) {
1299                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1300                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1301                         return err;
1302                 }
1303         }
1304
1305         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1306         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1307         if (force_on)
1308                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1309         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1310
1311         if (!force_on)
1312                 return 0;
1313
1314         err = wait_for(COND, 20);
1315         if (err)
1316                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1317                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1318
1319         return err;
1320 #undef COND
1321 }
1322
1323 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1324 {
1325         u32 val;
1326         int err = 0;
1327
1328         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1329         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1330         if (allow)
1331                 val |= VLV_GTLC_ALLOWWAKEREQ;
1332         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1333         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1334
1335 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1336               allow)
1337         err = wait_for(COND, 1);
1338         if (err)
1339                 DRM_ERROR("timeout disabling GT waking\n");
1340         return err;
1341 #undef COND
1342 }
1343
1344 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1345                                  bool wait_for_on)
1346 {
1347         u32 mask;
1348         u32 val;
1349         int err;
1350
1351         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1352         val = wait_for_on ? mask : 0;
1353 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1354         if (COND)
1355                 return 0;
1356
1357         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1358                         wait_for_on ? "on" : "off",
1359                         I915_READ(VLV_GTLC_PW_STATUS));
1360
1361         /*
1362          * RC6 transitioning can be delayed up to 2 msec (see
1363          * valleyview_enable_rps), use 3 msec for safety.
1364          */
1365         err = wait_for(COND, 3);
1366         if (err)
1367                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1368                           wait_for_on ? "on" : "off");
1369
1370         return err;
1371 #undef COND
1372 }
1373
1374 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1375 {
1376         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1377                 return;
1378
1379         DRM_ERROR("GT register access while GT waking disabled\n");
1380         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1381 }
1382
1383 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1384 {
1385         u32 mask;
1386         int err;
1387
1388         /*
1389          * Bspec defines the following GT well on flags as debug only, so
1390          * don't treat them as hard failures.
1391          */
1392         (void)vlv_wait_for_gt_wells(dev_priv, false);
1393
1394         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1395         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1396
1397         vlv_check_no_gt_access(dev_priv);
1398
1399         err = vlv_force_gfx_clock(dev_priv, true);
1400         if (err)
1401                 goto err1;
1402
1403         err = vlv_allow_gt_wake(dev_priv, false);
1404         if (err)
1405                 goto err2;
1406         vlv_save_gunit_s0ix_state(dev_priv);
1407
1408         err = vlv_force_gfx_clock(dev_priv, false);
1409         if (err)
1410                 goto err2;
1411
1412         return 0;
1413
1414 err2:
1415         /* For safety always re-enable waking and disable gfx clock forcing */
1416         vlv_allow_gt_wake(dev_priv, true);
1417 err1:
1418         vlv_force_gfx_clock(dev_priv, false);
1419
1420         return err;
1421 }
1422
1423 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1424                                 bool rpm_resume)
1425 {
1426         struct drm_device *dev = dev_priv->dev;
1427         int err;
1428         int ret;
1429
1430         /*
1431          * If any of the steps fail just try to continue, that's the best we
1432          * can do at this point. Return the first error code (which will also
1433          * leave RPM permanently disabled).
1434          */
1435         ret = vlv_force_gfx_clock(dev_priv, true);
1436
1437         vlv_restore_gunit_s0ix_state(dev_priv);
1438
1439         err = vlv_allow_gt_wake(dev_priv, true);
1440         if (!ret)
1441                 ret = err;
1442
1443         err = vlv_force_gfx_clock(dev_priv, false);
1444         if (!ret)
1445                 ret = err;
1446
1447         vlv_check_no_gt_access(dev_priv);
1448
1449         if (rpm_resume) {
1450                 intel_init_clock_gating(dev);
1451                 i915_gem_restore_fences(dev);
1452         }
1453
1454         return ret;
1455 }
1456
1457 static int intel_runtime_suspend(struct device *device)
1458 {
1459         struct pci_dev *pdev = to_pci_dev(device);
1460         struct drm_device *dev = pci_get_drvdata(pdev);
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         int ret;
1463
1464         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1465                 return -ENODEV;
1466
1467         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1468                 return -ENODEV;
1469
1470         assert_force_wake_inactive(dev_priv);
1471
1472         DRM_DEBUG_KMS("Suspending device\n");
1473
1474         /*
1475          * We could deadlock here in case another thread holding struct_mutex
1476          * calls RPM suspend concurrently, since the RPM suspend will wait
1477          * first for this RPM suspend to finish. In this case the concurrent
1478          * RPM resume will be followed by its RPM suspend counterpart. Still
1479          * for consistency return -EAGAIN, which will reschedule this suspend.
1480          */
1481         if (!mutex_trylock(&dev->struct_mutex)) {
1482                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1483                 /*
1484                  * Bump the expiration timestamp, otherwise the suspend won't
1485                  * be rescheduled.
1486                  */
1487                 pm_runtime_mark_last_busy(device);
1488
1489                 return -EAGAIN;
1490         }
1491         /*
1492          * We are safe here against re-faults, since the fault handler takes
1493          * an RPM reference.
1494          */
1495         i915_gem_release_all_mmaps(dev_priv);
1496         mutex_unlock(&dev->struct_mutex);
1497
1498         /*
1499          * rps.work can't be rearmed here, since we get here only after making
1500          * sure the GPU is idle and the RPS freq is set to the minimum. See
1501          * intel_mark_idle().
1502          */
1503         cancel_work_sync(&dev_priv->rps.work);
1504         intel_runtime_pm_disable_interrupts(dev_priv);
1505
1506         ret = intel_suspend_complete(dev_priv);
1507         if (ret) {
1508                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1509                 intel_runtime_pm_enable_interrupts(dev_priv);
1510
1511                 return ret;
1512         }
1513
1514         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1515         dev_priv->pm.suspended = true;
1516
1517         /*
1518          * FIXME: We really should find a document that references the arguments
1519          * used below!
1520          */
1521         if (IS_HASWELL(dev)) {
1522                 /*
1523                  * current versions of firmware which depend on this opregion
1524                  * notification have repurposed the D1 definition to mean
1525                  * "runtime suspended" vs. what you would normally expect (D3)
1526                  * to distinguish it from notifications that might be sent via
1527                  * the suspend path.
1528                  */
1529                 intel_opregion_notify_adapter(dev, PCI_D1);
1530         } else {
1531                 /*
1532                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1533                  * being detected, and the call we do at intel_runtime_resume()
1534                  * won't be able to restore them. Since PCI_D3hot matches the
1535                  * actual specification and appears to be working, use it. Let's
1536                  * assume the other non-Haswell platforms will stay the same as
1537                  * Broadwell.
1538                  */
1539                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1540         }
1541
1542         DRM_DEBUG_KMS("Device suspended\n");
1543         return 0;
1544 }
1545
1546 static int intel_runtime_resume(struct device *device)
1547 {
1548         struct pci_dev *pdev = to_pci_dev(device);
1549         struct drm_device *dev = pci_get_drvdata(pdev);
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int ret;
1552
1553         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1554                 return -ENODEV;
1555
1556         DRM_DEBUG_KMS("Resuming device\n");
1557
1558         intel_opregion_notify_adapter(dev, PCI_D0);
1559         dev_priv->pm.suspended = false;
1560
1561         ret = intel_resume_prepare(dev_priv, true);
1562         /*
1563          * No point of rolling back things in case of an error, as the best
1564          * we can do is to hope that things will still work (and disable RPM).
1565          */
1566         i915_gem_init_swizzling(dev);
1567         gen6_update_ring_freq(dev);
1568
1569         intel_runtime_pm_enable_interrupts(dev_priv);
1570         intel_reset_gt_powersave(dev);
1571
1572         if (ret)
1573                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1574         else
1575                 DRM_DEBUG_KMS("Device resumed\n");
1576
1577         return ret;
1578 }
1579
1580 /*
1581  * This function implements common functionality of runtime and system
1582  * suspend sequence.
1583  */
1584 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1585 {
1586         struct drm_device *dev = dev_priv->dev;
1587         int ret;
1588
1589         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1590                 ret = hsw_suspend_complete(dev_priv);
1591         else if (IS_VALLEYVIEW(dev))
1592                 ret = vlv_suspend_complete(dev_priv);
1593         else
1594                 ret = 0;
1595
1596         return ret;
1597 }
1598
1599 /*
1600  * This function implements common functionality of runtime and system
1601  * resume sequence. Variable rpm_resume used for implementing different
1602  * code paths.
1603  */
1604 static int intel_resume_prepare(struct drm_i915_private *dev_priv,
1605                                 bool rpm_resume)
1606 {
1607         struct drm_device *dev = dev_priv->dev;
1608         int ret;
1609
1610         if (IS_GEN6(dev))
1611                 ret = snb_resume_prepare(dev_priv, rpm_resume);
1612         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1613                 ret = hsw_resume_prepare(dev_priv, rpm_resume);
1614         else if (IS_VALLEYVIEW(dev))
1615                 ret = vlv_resume_prepare(dev_priv, rpm_resume);
1616         else
1617                 ret = 0;
1618
1619         return ret;
1620 }
1621
1622 static const struct dev_pm_ops i915_pm_ops = {
1623         .suspend = i915_pm_suspend,
1624         .suspend_late = i915_pm_suspend_late,
1625         .resume_early = i915_pm_resume_early,
1626         .resume = i915_pm_resume,
1627         .freeze = i915_pm_freeze,
1628         .freeze_late = i915_pm_freeze_late,
1629         .thaw_early = i915_pm_thaw_early,
1630         .thaw = i915_pm_thaw,
1631         .poweroff = i915_pm_poweroff,
1632         .restore_early = i915_pm_resume_early,
1633         .restore = i915_pm_resume,
1634         .runtime_suspend = intel_runtime_suspend,
1635         .runtime_resume = intel_runtime_resume,
1636 };
1637
1638 static const struct vm_operations_struct i915_gem_vm_ops = {
1639         .fault = i915_gem_fault,
1640         .open = drm_gem_vm_open,
1641         .close = drm_gem_vm_close,
1642 };
1643
1644 static const struct file_operations i915_driver_fops = {
1645         .owner = THIS_MODULE,
1646         .open = drm_open,
1647         .release = drm_release,
1648         .unlocked_ioctl = drm_ioctl,
1649         .mmap = drm_gem_mmap,
1650         .poll = drm_poll,
1651         .read = drm_read,
1652 #ifdef CONFIG_COMPAT
1653         .compat_ioctl = i915_compat_ioctl,
1654 #endif
1655         .llseek = noop_llseek,
1656 };
1657
1658 static struct drm_driver driver = {
1659         /* Don't use MTRRs here; the Xserver or userspace app should
1660          * deal with them for Intel hardware.
1661          */
1662         .driver_features =
1663             DRIVER_USE_AGP |
1664             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1665             DRIVER_RENDER,
1666         .load = i915_driver_load,
1667         .unload = i915_driver_unload,
1668         .open = i915_driver_open,
1669         .lastclose = i915_driver_lastclose,
1670         .preclose = i915_driver_preclose,
1671         .postclose = i915_driver_postclose,
1672         .set_busid = drm_pci_set_busid,
1673
1674         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1675         .suspend = i915_suspend,
1676         .resume = i915_resume_legacy,
1677
1678         .device_is_agp = i915_driver_device_is_agp,
1679         .master_create = i915_master_create,
1680         .master_destroy = i915_master_destroy,
1681 #if defined(CONFIG_DEBUG_FS)
1682         .debugfs_init = i915_debugfs_init,
1683         .debugfs_cleanup = i915_debugfs_cleanup,
1684 #endif
1685         .gem_free_object = i915_gem_free_object,
1686         .gem_vm_ops = &i915_gem_vm_ops,
1687
1688         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1689         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1690         .gem_prime_export = i915_gem_prime_export,
1691         .gem_prime_import = i915_gem_prime_import,
1692
1693         .dumb_create = i915_gem_dumb_create,
1694         .dumb_map_offset = i915_gem_mmap_gtt,
1695         .dumb_destroy = drm_gem_dumb_destroy,
1696         .ioctls = i915_ioctls,
1697         .fops = &i915_driver_fops,
1698         .name = DRIVER_NAME,
1699         .desc = DRIVER_DESC,
1700         .date = DRIVER_DATE,
1701         .major = DRIVER_MAJOR,
1702         .minor = DRIVER_MINOR,
1703         .patchlevel = DRIVER_PATCHLEVEL,
1704 };
1705
1706 static struct pci_driver i915_pci_driver = {
1707         .name = DRIVER_NAME,
1708         .id_table = pciidlist,
1709         .probe = i915_pci_probe,
1710         .remove = i915_pci_remove,
1711         .driver.pm = &i915_pm_ops,
1712 };
1713
1714 static int __init i915_init(void)
1715 {
1716         driver.num_ioctls = i915_max_ioctl;
1717
1718         /*
1719          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1720          * explicitly disabled with the module pararmeter.
1721          *
1722          * Otherwise, just follow the parameter (defaulting to off).
1723          *
1724          * Allow optional vga_text_mode_force boot option to override
1725          * the default behavior.
1726          */
1727 #if defined(CONFIG_DRM_I915_KMS)
1728         if (i915.modeset != 0)
1729                 driver.driver_features |= DRIVER_MODESET;
1730 #endif
1731         if (i915.modeset == 1)
1732                 driver.driver_features |= DRIVER_MODESET;
1733
1734 #ifdef CONFIG_VGA_CONSOLE
1735         if (vgacon_text_force() && i915.modeset == -1)
1736                 driver.driver_features &= ~DRIVER_MODESET;
1737 #endif
1738
1739         if (!(driver.driver_features & DRIVER_MODESET)) {
1740                 driver.get_vblank_timestamp = NULL;
1741 #ifndef CONFIG_DRM_I915_UMS
1742                 /* Silently fail loading to not upset userspace. */
1743                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1744                 return 0;
1745 #endif
1746         }
1747
1748         return drm_pci_init(&driver, &i915_pci_driver);
1749 }
1750
1751 static void __exit i915_exit(void)
1752 {
1753 #ifndef CONFIG_DRM_I915_UMS
1754         if (!(driver.driver_features & DRIVER_MODESET))
1755                 return; /* Never loaded a driver. */
1756 #endif
1757
1758         drm_pci_exit(&driver, &i915_pci_driver);
1759 }
1760
1761 module_init(i915_init);
1762 module_exit(i915_exit);
1763
1764 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1765 MODULE_AUTHOR("Intel Corporation");
1766
1767 MODULE_DESCRIPTION(DRIVER_DESC);
1768 MODULE_LICENSE("GPL and additional rights");