drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include "drm_crtc_helper.h"
  41
  42 static int i915_modeset __read_mostly = -1;
  43 module_param_named(modeset, i915_modeset, int, 0400);
  44 MODULE_PARM_DESC(modeset,
  45                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  46                 "1=on, -1=force vga console preference [default])");
  47
  48 unsigned int i915_fbpercrtc __always_unused = 0;
  49 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  50
  51 int i915_panel_ignore_lid __read_mostly = 0;
  52 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  53 MODULE_PARM_DESC(panel_ignore_lid,
  54                 "Override lid status (0=autodetect [default], 1=lid open, "
  55                 "-1=lid closed)");
  56
  57 unsigned int i915_powersave __read_mostly = 1;
  58 module_param_named(powersave, i915_powersave, int, 0600);
  59 MODULE_PARM_DESC(powersave,
  60                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  61
  62 int i915_semaphores __read_mostly = -1;
  63 module_param_named(semaphores, i915_semaphores, int, 0600);
  64 MODULE_PARM_DESC(semaphores,
  65                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  66
  67 int i915_enable_rc6 __read_mostly = -1;
  68 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  69 MODULE_PARM_DESC(i915_enable_rc6,
  70                 "Enable power-saving render C-state 6. "
  71                 "Different stages can be selected via bitmask values "
  72                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  73                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  74                 "default: -1 (use per-chip default)");
  75
  76 int i915_enable_fbc __read_mostly = -1;
  77 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  78 MODULE_PARM_DESC(i915_enable_fbc,
  79                 "Enable frame buffer compression for power savings "
  80                 "(default: -1 (use per-chip default))");
  81
  82 unsigned int i915_lvds_downclock __read_mostly = 0;
  83 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  84 MODULE_PARM_DESC(lvds_downclock,
  85                 "Use panel (LVDS/eDP) downclocking for power savings "
  86                 "(default: false)");
  87
  88 int i915_lvds_channel_mode __read_mostly;
  89 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  90 MODULE_PARM_DESC(lvds_channel_mode,
  91                  "Specify LVDS channel mode "
  92                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  93
  94 int i915_panel_use_ssc __read_mostly = -1;
  95 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  96 MODULE_PARM_DESC(lvds_use_ssc,
  97                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  98                 "(default: auto from VBT)");
  99
 100 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 101 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 102 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 103                 "Override/Ignore selection of SDVO panel mode in the VBT "
 104                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 105
 106 static bool i915_try_reset __read_mostly = true;
 107 module_param_named(reset, i915_try_reset, bool, 0600);
 108 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 109
 110 bool i915_enable_hangcheck __read_mostly = true;
 111 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 112 MODULE_PARM_DESC(enable_hangcheck,
 113                 "Periodically check GPU activity for detecting hangs. "
 114                 "WARNING: Disabling this can cause system wide hangs. "
 115                 "(default: true)");
 116
 117 int i915_enable_ppgtt __read_mostly = -1;
 118 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 119 MODULE_PARM_DESC(i915_enable_ppgtt,
 120                 "Enable PPGTT (default: true)");
 121
 122 static struct drm_driver driver;
 123 extern int intel_agp_enabled;
 124
 125 #define INTEL_VGA_DEVICE(id, info) {            \
 126         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 127         .class_mask = 0xff0000,                 \
 128         .vendor = 0x8086,                       \
 129         .device = id,                           \
 130         .subvendor = PCI_ANY_ID,                \
 131         .subdevice = PCI_ANY_ID,                \
 132         .driver_data = (unsigned long) info }
 133
 134 static const struct intel_device_info intel_i830_info = {
 135         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_845g_info = {
 140         .gen = 2,
 141         .has_overlay = 1, .overlay_needs_physical = 1,
 142 };
 143
 144 static const struct intel_device_info intel_i85x_info = {
 145         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 146         .cursor_needs_physical = 1,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i865g_info = {
 151         .gen = 2,
 152         .has_overlay = 1, .overlay_needs_physical = 1,
 153 };
 154
 155 static const struct intel_device_info intel_i915g_info = {
 156         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 157         .has_overlay = 1, .overlay_needs_physical = 1,
 158 };
 159 static const struct intel_device_info intel_i915gm_info = {
 160         .gen = 3, .is_mobile = 1,
 161         .cursor_needs_physical = 1,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163         .supports_tv = 1,
 164 };
 165 static const struct intel_device_info intel_i945g_info = {
 166         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168 };
 169 static const struct intel_device_info intel_i945gm_info = {
 170         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 171         .has_hotplug = 1, .cursor_needs_physical = 1,
 172         .has_overlay = 1, .overlay_needs_physical = 1,
 173         .supports_tv = 1,
 174 };
 175
 176 static const struct intel_device_info intel_i965g_info = {
 177         .gen = 4, .is_broadwater = 1,
 178         .has_hotplug = 1,
 179         .has_overlay = 1,
 180 };
 181
 182 static const struct intel_device_info intel_i965gm_info = {
 183         .gen = 4, .is_crestline = 1,
 184         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 185         .has_overlay = 1,
 186         .supports_tv = 1,
 187 };
 188
 189 static const struct intel_device_info intel_g33_info = {
 190         .gen = 3, .is_g33 = 1,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .has_overlay = 1,
 193 };
 194
 195 static const struct intel_device_info intel_g45_info = {
 196         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 197         .has_pipe_cxsr = 1, .has_hotplug = 1,
 198         .has_bsd_ring = 1,
 199 };
 200
 201 static const struct intel_device_info intel_gm45_info = {
 202         .gen = 4, .is_g4x = 1,
 203         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 204         .has_pipe_cxsr = 1, .has_hotplug = 1,
 205         .supports_tv = 1,
 206         .has_bsd_ring = 1,
 207 };
 208
 209 static const struct intel_device_info intel_pineview_info = {
 210         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 211         .need_gfx_hws = 1, .has_hotplug = 1,
 212         .has_overlay = 1,
 213 };
 214
 215 static const struct intel_device_info intel_ironlake_d_info = {
 216         .gen = 5,
 217         .need_gfx_hws = 1, .has_hotplug = 1,
 218         .has_bsd_ring = 1,
 219         .has_pch_split = 1,
 220 };
 221
 222 static const struct intel_device_info intel_ironlake_m_info = {
 223         .gen = 5, .is_mobile = 1,
 224         .need_gfx_hws = 1, .has_hotplug = 1,
 225         .has_fbc = 1,
 226         .has_bsd_ring = 1,
 227         .has_pch_split = 1,
 228 };
 229
 230 static const struct intel_device_info intel_sandybridge_d_info = {
 231         .gen = 6,
 232         .need_gfx_hws = 1, .has_hotplug = 1,
 233         .has_bsd_ring = 1,
 234         .has_blt_ring = 1,
 235         .has_llc = 1,
 236         .has_pch_split = 1,
 237         .has_force_wake = 1,
 238 };
 239
 240 static const struct intel_device_info intel_sandybridge_m_info = {
 241         .gen = 6, .is_mobile = 1,
 242         .need_gfx_hws = 1, .has_hotplug = 1,
 243         .has_fbc = 1,
 244         .has_bsd_ring = 1,
 245         .has_blt_ring = 1,
 246         .has_llc = 1,
 247         .has_pch_split = 1,
 248         .has_force_wake = 1,
 249 };
 250
 251 static const struct intel_device_info intel_ivybridge_d_info = {
 252         .is_ivybridge = 1, .gen = 7,
 253         .need_gfx_hws = 1, .has_hotplug = 1,
 254         .has_bsd_ring = 1,
 255         .has_blt_ring = 1,
 256         .has_llc = 1,
 257         .has_pch_split = 1,
 258         .has_force_wake = 1,
 259 };
 260
 261 static const struct intel_device_info intel_ivybridge_m_info = {
 262         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 263         .need_gfx_hws = 1, .has_hotplug = 1,
 264         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 265         .has_bsd_ring = 1,
 266         .has_blt_ring = 1,
 267         .has_llc = 1,
 268         .has_pch_split = 1,
 269         .has_force_wake = 1,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_m_info = {
 273         .gen = 7, .is_mobile = 1,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 0,
 276         .has_bsd_ring = 1,
 277         .has_blt_ring = 1,
 278         .is_valleyview = 1,
 279 };
 280
 281 static const struct intel_device_info intel_valleyview_d_info = {
 282         .gen = 7,
 283         .need_gfx_hws = 1, .has_hotplug = 1,
 284         .has_fbc = 0,
 285         .has_bsd_ring = 1,
 286         .has_blt_ring = 1,
 287         .is_valleyview = 1,
 288 };
 289
 290 static const struct intel_device_info intel_haswell_d_info = {
 291         .is_haswell = 1, .gen = 7,
 292         .need_gfx_hws = 1, .has_hotplug = 1,
 293         .has_bsd_ring = 1,
 294         .has_blt_ring = 1,
 295         .has_llc = 1,
 296         .has_pch_split = 1,
 297         .has_force_wake = 1,
 298 };
 299
 300 static const struct intel_device_info intel_haswell_m_info = {
 301         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .has_bsd_ring = 1,
 304         .has_blt_ring = 1,
 305         .has_llc = 1,
 306         .has_pch_split = 1,
 307         .has_force_wake = 1,
 308 };
 309
 310 static const struct pci_device_id pciidlist[] = {               /* aka */
 311         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 312         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 313         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 314         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 315         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 316         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 317         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 318         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 319         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 320         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 321         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 322         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 323         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 324         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 325         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 326         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 327         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 328         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 329         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 330         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 331         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 332         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 333         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 334         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 335         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 336         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 337         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 338         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 339         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 340         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 341         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 342         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 343         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 344         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 345         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 346         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 347         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 348         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 349         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 350         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 351         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 352         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 353         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 354         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 355         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 356         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 357         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 358         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 359         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 360         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 361         INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
 362         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 363         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 364         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 365         {0, 0, 0}
 366 };
 367
 368 #if defined(CONFIG_DRM_I915_KMS)
 369 MODULE_DEVICE_TABLE(pci, pciidlist);
 370 #endif
 371
 372 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 373 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 374 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 375 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 376 #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
 377
 378 void intel_detect_pch(struct drm_device *dev)
 379 {
 380         struct drm_i915_private *dev_priv = dev->dev_private;
 381         struct pci_dev *pch;
 382
 383         /*
 384          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 385          * make graphics device passthrough work easy for VMM, that only
 386          * need to expose ISA bridge to let driver know the real hardware
 387          * underneath. This is a requirement from virtualization team.
 388          */
 389         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 390         if (pch) {
 391                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 392                         int id;
 393                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 394
 395                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 396                                 dev_priv->pch_type = PCH_IBX;
 397                                 dev_priv->num_pch_pll = 2;
 398                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 399                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 400                                 dev_priv->pch_type = PCH_CPT;
 401                                 dev_priv->num_pch_pll = 2;
 402                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 403                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 404                                 /* PantherPoint is CPT compatible */
 405                                 dev_priv->pch_type = PCH_CPT;
 406                                 dev_priv->num_pch_pll = 2;
 407                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 408                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 409                                 dev_priv->pch_type = PCH_LPT;
 410                                 dev_priv->num_pch_pll = 0;
 411                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 412                         }
 413                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 414                 }
 415                 pci_dev_put(pch);
 416         }
 417 }
 418
 419 bool i915_semaphore_is_enabled(struct drm_device *dev)
 420 {
 421         if (INTEL_INFO(dev)->gen < 6)
 422                 return 0;
 423
 424         if (i915_semaphores >= 0)
 425                 return i915_semaphores;
 426
 427 #ifdef CONFIG_INTEL_IOMMU
 428         /* Enable semaphores on SNB when IO remapping is off */
 429         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 430                 return false;
 431 #endif
 432
 433         return 1;
 434 }
 435
 436 static int i915_drm_freeze(struct drm_device *dev)
 437 {
 438         struct drm_i915_private *dev_priv = dev->dev_private;
 439
 440         drm_kms_helper_poll_disable(dev);
 441
 442         pci_save_state(dev->pdev);
 443
 444         /* If KMS is active, we do the leavevt stuff here */
 445         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 446                 int error = i915_gem_idle(dev);
 447                 if (error) {
 448                         dev_err(&dev->pdev->dev,
 449                                 "GEM idle failed, resume might fail\n");
 450                         return error;
 451                 }
 452                 drm_irq_uninstall(dev);
 453         }
 454
 455         i915_save_state(dev);
 456
 457         intel_opregion_fini(dev);
 458
 459         /* Modeset on resume, not lid events */
 460         dev_priv->modeset_on_lid = 0;
 461
 462         console_lock();
 463         intel_fbdev_set_suspend(dev, 1);
 464         console_unlock();
 465
 466         return 0;
 467 }
 468
 469 int i915_suspend(struct drm_device *dev, pm_message_t state)
 470 {
 471         int error;
 472
 473         if (!dev || !dev->dev_private) {
 474                 DRM_ERROR("dev: %p\n", dev);
 475                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 476                 return -ENODEV;
 477         }
 478
 479         if (state.event == PM_EVENT_PRETHAW)
 480                 return 0;
 481
 482
 483         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 484                 return 0;
 485
 486         error = i915_drm_freeze(dev);
 487         if (error)
 488                 return error;
 489
 490         if (state.event == PM_EVENT_SUSPEND) {
 491                 /* Shut down the device */
 492                 pci_disable_device(dev->pdev);
 493                 pci_set_power_state(dev->pdev, PCI_D3hot);
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int i915_drm_thaw(struct drm_device *dev)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         int error = 0;
 503
 504         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 505                 mutex_lock(&dev->struct_mutex);
 506                 i915_gem_restore_gtt_mappings(dev);
 507                 mutex_unlock(&dev->struct_mutex);
 508         }
 509
 510         i915_restore_state(dev);
 511         intel_opregion_setup(dev);
 512
 513         /* KMS EnterVT equivalent */
 514         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 515                 if (HAS_PCH_SPLIT(dev))
 516                         ironlake_init_pch_refclk(dev);
 517
 518                 mutex_lock(&dev->struct_mutex);
 519                 dev_priv->mm.suspended = 0;
 520
 521                 error = i915_gem_init_hw(dev);
 522                 mutex_unlock(&dev->struct_mutex);
 523
 524                 intel_modeset_init_hw(dev);
 525                 drm_mode_config_reset(dev);
 526                 drm_irq_install(dev);
 527
 528                 /* Resume the modeset for every activated CRTC */
 529                 mutex_lock(&dev->mode_config.mutex);
 530                 drm_helper_resume_force_mode(dev);
 531                 mutex_unlock(&dev->mode_config.mutex);
 532         }
 533
 534         intel_opregion_init(dev);
 535
 536         dev_priv->modeset_on_lid = 0;
 537
 538         console_lock();
 539         intel_fbdev_set_suspend(dev, 0);
 540         console_unlock();
 541         return error;
 542 }
 543
 544 int i915_resume(struct drm_device *dev)
 545 {
 546         int ret;
 547
 548         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 549                 return 0;
 550
 551         if (pci_enable_device(dev->pdev))
 552                 return -EIO;
 553
 554         pci_set_master(dev->pdev);
 555
 556         ret = i915_drm_thaw(dev);
 557         if (ret)
 558                 return ret;
 559
 560         drm_kms_helper_poll_enable(dev);
 561         return 0;
 562 }
 563
 564 static int i8xx_do_reset(struct drm_device *dev)
 565 {
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567
 568         if (IS_I85X(dev))
 569                 return -ENODEV;
 570
 571         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 572         POSTING_READ(D_STATE);
 573
 574         if (IS_I830(dev) || IS_845G(dev)) {
 575                 I915_WRITE(DEBUG_RESET_I830,
 576                            DEBUG_RESET_DISPLAY |
 577                            DEBUG_RESET_RENDER |
 578                            DEBUG_RESET_FULL);
 579                 POSTING_READ(DEBUG_RESET_I830);
 580                 msleep(1);
 581
 582                 I915_WRITE(DEBUG_RESET_I830, 0);
 583                 POSTING_READ(DEBUG_RESET_I830);
 584         }
 585
 586         msleep(1);
 587
 588         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 589         POSTING_READ(D_STATE);
 590
 591         return 0;
 592 }
 593
 594 static int i965_reset_complete(struct drm_device *dev)
 595 {
 596         u8 gdrst;
 597         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 598         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 599 }
 600
 601 static int i965_do_reset(struct drm_device *dev)
 602 {
 603         int ret;
 604         u8 gdrst;
 605
 606         /*
 607          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 608          * well as the reset bit (GR/bit 0).  Setting the GR bit
 609          * triggers the reset; when done, the hardware will clear it.
 610          */
 611         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 612         pci_write_config_byte(dev->pdev, I965_GDRST,
 613                               gdrst | GRDOM_RENDER |
 614                               GRDOM_RESET_ENABLE);
 615         ret =  wait_for(i965_reset_complete(dev), 500);
 616         if (ret)
 617                 return ret;
 618
 619         /* We can't reset render&media without also resetting display ... */
 620         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 621         pci_write_config_byte(dev->pdev, I965_GDRST,
 622                               gdrst | GRDOM_MEDIA |
 623                               GRDOM_RESET_ENABLE);
 624
 625         return wait_for(i965_reset_complete(dev), 500);
 626 }
 627
 628 static int ironlake_do_reset(struct drm_device *dev)
 629 {
 630         struct drm_i915_private *dev_priv = dev->dev_private;
 631         u32 gdrst;
 632         int ret;
 633
 634         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 635         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 636                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 637         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 638         if (ret)
 639                 return ret;
 640
 641         /* We can't reset render&media without also resetting display ... */
 642         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 643         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 644                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 645         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 646 }
 647
 648 static int gen6_do_reset(struct drm_device *dev)
 649 {
 650         struct drm_i915_private *dev_priv = dev->dev_private;
 651         int     ret;
 652         unsigned long irqflags;
 653
 654         /* Hold gt_lock across reset to prevent any register access
 655          * with forcewake not set correctly
 656          */
 657         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 658
 659         /* Reset the chip */
 660
 661         /* GEN6_GDRST is not in the gt power well, no need to check
 662          * for fifo space for the write or forcewake the chip for
 663          * the read
 664          */
 665         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 666
 667         /* Spin waiting for the device to ack the reset request */
 668         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 669
 670         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 671         if (dev_priv->forcewake_count)
 672                 dev_priv->gt.force_wake_get(dev_priv);
 673         else
 674                 dev_priv->gt.force_wake_put(dev_priv);
 675
 676         /* Restore fifo count */
 677         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 678
 679         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 680         return ret;
 681 }
 682
 683 int intel_gpu_reset(struct drm_device *dev)
 684 {
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686         int ret = -ENODEV;
 687
 688         switch (INTEL_INFO(dev)->gen) {
 689         case 7:
 690         case 6:
 691                 ret = gen6_do_reset(dev);
 692                 break;
 693         case 5:
 694                 ret = ironlake_do_reset(dev);
 695                 break;
 696         case 4:
 697                 ret = i965_do_reset(dev);
 698                 break;
 699         case 2:
 700                 ret = i8xx_do_reset(dev);
 701                 break;
 702         }
 703
 704         /* Also reset the gpu hangman. */
 705         if (dev_priv->stop_rings) {
 706                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 707                 dev_priv->stop_rings = 0;
 708                 if (ret == -ENODEV) {
 709                         DRM_ERROR("Reset not implemented, but ignoring "
 710                                   "error for simulated gpu hangs\n");
 711                         ret = 0;
 712                 }
 713         }
 714
 715         return ret;
 716 }
 717
 718 /**
 719  * i915_reset - reset chip after a hang
 720  * @dev: drm device to reset
 721  *
 722  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 723  * reset or otherwise an error code.
 724  *
 725  * Procedure is fairly simple:
 726  *   - reset the chip using the reset reg
 727  *   - re-init context state
 728  *   - re-init hardware status page
 729  *   - re-init ring buffer
 730  *   - re-init interrupt state
 731  *   - re-init display
 732  */
 733 int i915_reset(struct drm_device *dev)
 734 {
 735         drm_i915_private_t *dev_priv = dev->dev_private;
 736         int ret;
 737
 738         if (!i915_try_reset)
 739                 return 0;
 740
 741         if (!mutex_trylock(&dev->struct_mutex))
 742                 return -EBUSY;
 743
 744         i915_gem_reset(dev);
 745
 746         ret = -ENODEV;
 747         if (get_seconds() - dev_priv->last_gpu_reset < 5)
 748                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 749         else
 750                 ret = intel_gpu_reset(dev);
 751
 752         dev_priv->last_gpu_reset = get_seconds();
 753         if (ret) {
 754                 DRM_ERROR("Failed to reset chip.\n");
 755                 mutex_unlock(&dev->struct_mutex);
 756                 return ret;
 757         }
 758
 759         /* Ok, now get things going again... */
 760
 761         /*
 762          * Everything depends on having the GTT running, so we need to start
 763          * there.  Fortunately we don't need to do this unless we reset the
 764          * chip at a PCI level.
 765          *
 766          * Next we need to restore the context, but we don't use those
 767          * yet either...
 768          *
 769          * Ring buffer needs to be re-initialized in the KMS case, or if X
 770          * was running at the time of the reset (i.e. we weren't VT
 771          * switched away).
 772          */
 773         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 774                         !dev_priv->mm.suspended) {
 775                 struct intel_ring_buffer *ring;
 776                 int i;
 777
 778                 dev_priv->mm.suspended = 0;
 779
 780                 i915_gem_init_swizzling(dev);
 781
 782                 for_each_ring(ring, dev_priv, i)
 783                         ring->init(ring);
 784
 785                 i915_gem_context_init(dev);
 786                 i915_gem_init_ppgtt(dev);
 787
 788                 /*
 789                  * It would make sense to re-init all the other hw state, at
 790                  * least the rps/rc6/emon init done within modeset_init_hw. For
 791                  * some unknown reason, this blows up my ilk, so don't.
 792                  */
 793
 794                 mutex_unlock(&dev->struct_mutex);
 795
 796                 drm_irq_uninstall(dev);
 797                 drm_irq_install(dev);
 798         } else {
 799                 mutex_unlock(&dev->struct_mutex);
 800         }
 801
 802         return 0;
 803 }
 804
 805 static int __devinit
 806 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 807 {
 808         struct intel_device_info *intel_info =
 809                 (struct intel_device_info *) ent->driver_data;
 810
 811         /* Only bind to function 0 of the device. Early generations
 812          * used function 1 as a placeholder for multi-head. This causes
 813          * us confusion instead, especially on the systems where both
 814          * functions have the same PCI-ID!
 815          */
 816         if (PCI_FUNC(pdev->devfn))
 817                 return -ENODEV;
 818
 819         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 820          * implementation for gen3 (and only gen3) that used legacy drm maps
 821          * (gasp!) to share buffers between X and the client. Hence we need to
 822          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 823         if (intel_info->gen != 3) {
 824                 driver.driver_features &=
 825                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 826         } else if (!intel_agp_enabled) {
 827                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 828                 return -ENODEV;
 829         }
 830
 831         return drm_get_pci_dev(pdev, ent, &driver);
 832 }
 833
 834 static void
 835 i915_pci_remove(struct pci_dev *pdev)
 836 {
 837         struct drm_device *dev = pci_get_drvdata(pdev);
 838
 839         drm_put_dev(dev);
 840 }
 841
 842 static int i915_pm_suspend(struct device *dev)
 843 {
 844         struct pci_dev *pdev = to_pci_dev(dev);
 845         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 846         int error;
 847
 848         if (!drm_dev || !drm_dev->dev_private) {
 849                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 850                 return -ENODEV;
 851         }
 852
 853         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 854                 return 0;
 855
 856         error = i915_drm_freeze(drm_dev);
 857         if (error)
 858                 return error;
 859
 860         pci_disable_device(pdev);
 861         pci_set_power_state(pdev, PCI_D3hot);
 862
 863         return 0;
 864 }
 865
 866 static int i915_pm_resume(struct device *dev)
 867 {
 868         struct pci_dev *pdev = to_pci_dev(dev);
 869         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 870
 871         return i915_resume(drm_dev);
 872 }
 873
 874 static int i915_pm_freeze(struct device *dev)
 875 {
 876         struct pci_dev *pdev = to_pci_dev(dev);
 877         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 878
 879         if (!drm_dev || !drm_dev->dev_private) {
 880                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 881                 return -ENODEV;
 882         }
 883
 884         return i915_drm_freeze(drm_dev);
 885 }
 886
 887 static int i915_pm_thaw(struct device *dev)
 888 {
 889         struct pci_dev *pdev = to_pci_dev(dev);
 890         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 891
 892         return i915_drm_thaw(drm_dev);
 893 }
 894
 895 static int i915_pm_poweroff(struct device *dev)
 896 {
 897         struct pci_dev *pdev = to_pci_dev(dev);
 898         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 899
 900         return i915_drm_freeze(drm_dev);
 901 }
 902
 903 static const struct dev_pm_ops i915_pm_ops = {
 904         .suspend = i915_pm_suspend,
 905         .resume = i915_pm_resume,
 906         .freeze = i915_pm_freeze,
 907         .thaw = i915_pm_thaw,
 908         .poweroff = i915_pm_poweroff,
 909         .restore = i915_pm_resume,
 910 };
 911
 912 static const struct vm_operations_struct i915_gem_vm_ops = {
 913         .fault = i915_gem_fault,
 914         .open = drm_gem_vm_open,
 915         .close = drm_gem_vm_close,
 916 };
 917
 918 static const struct file_operations i915_driver_fops = {
 919         .owner = THIS_MODULE,
 920         .open = drm_open,
 921         .release = drm_release,
 922         .unlocked_ioctl = drm_ioctl,
 923         .mmap = drm_gem_mmap,
 924         .poll = drm_poll,
 925         .fasync = drm_fasync,
 926         .read = drm_read,
 927 #ifdef CONFIG_COMPAT
 928         .compat_ioctl = i915_compat_ioctl,
 929 #endif
 930         .llseek = noop_llseek,
 931 };
 932
 933 static struct drm_driver driver = {
 934         /* Don't use MTRRs here; the Xserver or userspace app should
 935          * deal with them for Intel hardware.
 936          */
 937         .driver_features =
 938             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 939             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
 940         .load = i915_driver_load,
 941         .unload = i915_driver_unload,
 942         .open = i915_driver_open,
 943         .lastclose = i915_driver_lastclose,
 944         .preclose = i915_driver_preclose,
 945         .postclose = i915_driver_postclose,
 946
 947         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 948         .suspend = i915_suspend,
 949         .resume = i915_resume,
 950
 951         .device_is_agp = i915_driver_device_is_agp,
 952         .reclaim_buffers = drm_core_reclaim_buffers,
 953         .master_create = i915_master_create,
 954         .master_destroy = i915_master_destroy,
 955 #if defined(CONFIG_DEBUG_FS)
 956         .debugfs_init = i915_debugfs_init,
 957         .debugfs_cleanup = i915_debugfs_cleanup,
 958 #endif
 959         .gem_init_object = i915_gem_init_object,
 960         .gem_free_object = i915_gem_free_object,
 961         .gem_vm_ops = &i915_gem_vm_ops,
 962
 963         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 964         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 965         .gem_prime_export = i915_gem_prime_export,
 966         .gem_prime_import = i915_gem_prime_import,
 967
 968         .dumb_create = i915_gem_dumb_create,
 969         .dumb_map_offset = i915_gem_mmap_gtt,
 970         .dumb_destroy = i915_gem_dumb_destroy,
 971         .ioctls = i915_ioctls,
 972         .fops = &i915_driver_fops,
 973         .name = DRIVER_NAME,
 974         .desc = DRIVER_DESC,
 975         .date = DRIVER_DATE,
 976         .major = DRIVER_MAJOR,
 977         .minor = DRIVER_MINOR,
 978         .patchlevel = DRIVER_PATCHLEVEL,
 979 };
 980
 981 static struct pci_driver i915_pci_driver = {
 982         .name = DRIVER_NAME,
 983         .id_table = pciidlist,
 984         .probe = i915_pci_probe,
 985         .remove = i915_pci_remove,
 986         .driver.pm = &i915_pm_ops,
 987 };
 988
 989 static int __init i915_init(void)
 990 {
 991         driver.num_ioctls = i915_max_ioctl;
 992
 993         /*
 994          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 995          * explicitly disabled with the module pararmeter.
 996          *
 997          * Otherwise, just follow the parameter (defaulting to off).
 998          *
 999          * Allow optional vga_text_mode_force boot option to override
1000          * the default behavior.
1001          */
1002 #if defined(CONFIG_DRM_I915_KMS)
1003         if (i915_modeset != 0)
1004                 driver.driver_features |= DRIVER_MODESET;
1005 #endif
1006         if (i915_modeset == 1)
1007                 driver.driver_features |= DRIVER_MODESET;
1008
1009 #ifdef CONFIG_VGA_CONSOLE
1010         if (vgacon_text_force() && i915_modeset == -1)
1011                 driver.driver_features &= ~DRIVER_MODESET;
1012 #endif
1013
1014         if (!(driver.driver_features & DRIVER_MODESET))
1015                 driver.get_vblank_timestamp = NULL;
1016
1017         return drm_pci_init(&driver, &i915_pci_driver);
1018 }
1019
1020 static void __exit i915_exit(void)
1021 {
1022         drm_pci_exit(&driver, &i915_pci_driver);
1023 }
1024
1025 module_init(i915_init);
1026 module_exit(i915_exit);
1027
1028 MODULE_AUTHOR(DRIVER_AUTHOR);
1029 MODULE_DESCRIPTION(DRIVER_DESC);
1030 MODULE_LICENSE("GPL and additional rights");
1031
1032 /* We give fast paths for the really cool registers */
1033 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1034         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1035          ((reg) < 0x40000) &&            \
1036          ((reg) != FORCEWAKE))
1037
1038 static bool IS_DISPLAYREG(u32 reg)
1039 {
1040         /*
1041          * This should make it easier to transition modules over to the
1042          * new register block scheme, since we can do it incrementally.
1043          */
1044         if (reg >= 0x180000)
1045                 return false;
1046
1047         if (reg >= RENDER_RING_BASE &&
1048             reg < RENDER_RING_BASE + 0xff)
1049                 return false;
1050         if (reg >= GEN6_BSD_RING_BASE &&
1051             reg < GEN6_BSD_RING_BASE + 0xff)
1052                 return false;
1053         if (reg >= BLT_RING_BASE &&
1054             reg < BLT_RING_BASE + 0xff)
1055                 return false;
1056
1057         if (reg == PGTBL_ER)
1058                 return false;
1059
1060         if (reg >= IPEIR_I965 &&
1061             reg < HWSTAM)
1062                 return false;
1063
1064         if (reg == MI_MODE)
1065                 return false;
1066
1067         if (reg == GFX_MODE_GEN7)
1068                 return false;
1069
1070         if (reg == RENDER_HWS_PGA_GEN7 ||
1071             reg == BSD_HWS_PGA_GEN7 ||
1072             reg == BLT_HWS_PGA_GEN7)
1073                 return false;
1074
1075         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1076             reg == GEN6_BSD_RNCID)
1077                 return false;
1078
1079         if (reg == GEN6_BLITTER_ECOSKPD)
1080                 return false;
1081
1082         if (reg >= 0x4000c &&
1083             reg <= 0x4002c)
1084                 return false;
1085
1086         if (reg >= 0x4f000 &&
1087             reg <= 0x4f08f)
1088                 return false;
1089
1090         if (reg >= 0x4f100 &&
1091             reg <= 0x4f11f)
1092                 return false;
1093
1094         if (reg >= VLV_MASTER_IER &&
1095             reg <= GEN6_PMIER)
1096                 return false;
1097
1098         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1099             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1100                 return false;
1101
1102         if (reg >= VLV_IIR_RW &&
1103             reg <= VLV_ISR)
1104                 return false;
1105
1106         if (reg == FORCEWAKE_VLV ||
1107             reg == FORCEWAKE_ACK_VLV)
1108                 return false;
1109
1110         if (reg == GEN6_GDRST)
1111                 return false;
1112
1113         return true;
1114 }
1115
1116 #define __i915_read(x, y) \
1117 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1118         u##x val = 0; \
1119         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1120                 unsigned long irqflags; \
1121                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1122                 if (dev_priv->forcewake_count == 0) \
1123                         dev_priv->gt.force_wake_get(dev_priv); \
1124                 val = read##y(dev_priv->regs + reg); \
1125                 if (dev_priv->forcewake_count == 0) \
1126                         dev_priv->gt.force_wake_put(dev_priv); \
1127                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1128         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1129                 val = read##y(dev_priv->regs + reg + 0x180000);         \
1130         } else { \
1131                 val = read##y(dev_priv->regs + reg); \
1132         } \
1133         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1134         return val; \
1135 }
1136
1137 __i915_read(8, b)
1138 __i915_read(16, w)
1139 __i915_read(32, l)
1140 __i915_read(64, q)
1141 #undef __i915_read
1142
1143 #define __i915_write(x, y) \
1144 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1145         u32 __fifo_ret = 0; \
1146         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1147         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1148                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1149         } \
1150         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1151                 write##y(val, dev_priv->regs + reg + 0x180000);         \
1152         } else {                                                        \
1153                 write##y(val, dev_priv->regs + reg);                    \
1154         }                                                               \
1155         if (unlikely(__fifo_ret)) { \
1156                 gen6_gt_check_fifodbg(dev_priv); \
1157         } \
1158 }
1159 __i915_write(8, b)
1160 __i915_write(16, w)
1161 __i915_write(32, l)
1162 __i915_write(64, q)
1163 #undef __i915_write