1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include "drm_crtc_helper.h"
40 static int i915_modeset = -1;
41 module_param_named(modeset, i915_modeset, int, 0400);
43 unsigned int i915_fbpercrtc = 0;
44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
46 unsigned int i915_powersave = 1;
47 module_param_named(powersave, i915_powersave, int, 0600);
49 unsigned int i915_lvds_downclock = 0;
50 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
52 unsigned int i915_panel_use_ssc = 1;
53 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
55 int i915_vbt_sdvo_panel_type = -1;
56 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
58 static bool i915_try_reset = true;
59 module_param_named(reset, i915_try_reset, bool, 0600);
61 static struct drm_driver driver;
62 extern int intel_agp_enabled;
64 #define INTEL_VGA_DEVICE(id, info) { \
65 .class = PCI_CLASS_DISPLAY_VGA << 8, \
66 .class_mask = 0xff0000, \
69 .subvendor = PCI_ANY_ID, \
70 .subdevice = PCI_ANY_ID, \
71 .driver_data = (unsigned long) info }
73 static const struct intel_device_info intel_i830_info = {
74 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
75 .has_overlay = 1, .overlay_needs_physical = 1,
78 static const struct intel_device_info intel_845g_info = {
80 .has_overlay = 1, .overlay_needs_physical = 1,
83 static const struct intel_device_info intel_i85x_info = {
84 .gen = 2, .is_i85x = 1, .is_mobile = 1,
85 .cursor_needs_physical = 1,
86 .has_overlay = 1, .overlay_needs_physical = 1,
89 static const struct intel_device_info intel_i865g_info = {
91 .has_overlay = 1, .overlay_needs_physical = 1,
94 static const struct intel_device_info intel_i915g_info = {
95 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
96 .has_overlay = 1, .overlay_needs_physical = 1,
98 static const struct intel_device_info intel_i915gm_info = {
99 .gen = 3, .is_mobile = 1,
100 .cursor_needs_physical = 1,
101 .has_overlay = 1, .overlay_needs_physical = 1,
104 static const struct intel_device_info intel_i945g_info = {
105 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
106 .has_overlay = 1, .overlay_needs_physical = 1,
108 static const struct intel_device_info intel_i945gm_info = {
109 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
110 .has_hotplug = 1, .cursor_needs_physical = 1,
111 .has_overlay = 1, .overlay_needs_physical = 1,
115 static const struct intel_device_info intel_i965g_info = {
116 .gen = 4, .is_broadwater = 1,
121 static const struct intel_device_info intel_i965gm_info = {
122 .gen = 4, .is_crestline = 1,
123 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
128 static const struct intel_device_info intel_g33_info = {
129 .gen = 3, .is_g33 = 1,
130 .need_gfx_hws = 1, .has_hotplug = 1,
134 static const struct intel_device_info intel_g45_info = {
135 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
136 .has_pipe_cxsr = 1, .has_hotplug = 1,
140 static const struct intel_device_info intel_gm45_info = {
141 .gen = 4, .is_g4x = 1,
142 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
143 .has_pipe_cxsr = 1, .has_hotplug = 1,
148 static const struct intel_device_info intel_pineview_info = {
149 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
150 .need_gfx_hws = 1, .has_hotplug = 1,
154 static const struct intel_device_info intel_ironlake_d_info = {
156 .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
160 static const struct intel_device_info intel_ironlake_m_info = {
161 .gen = 5, .is_mobile = 1,
162 .need_gfx_hws = 1, .has_hotplug = 1,
163 .has_fbc = 0, /* disabled due to buggy hardware */
167 static const struct intel_device_info intel_sandybridge_d_info = {
169 .need_gfx_hws = 1, .has_hotplug = 1,
174 static const struct intel_device_info intel_sandybridge_m_info = {
175 .gen = 6, .is_mobile = 1,
176 .need_gfx_hws = 1, .has_hotplug = 1,
182 static const struct pci_device_id pciidlist[] = { /* aka */
183 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
184 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
185 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
186 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
187 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
188 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
189 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
190 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
191 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
192 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
193 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
194 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
195 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
196 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
197 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
198 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
199 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
200 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
201 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
202 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
203 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
204 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
205 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
206 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
207 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
208 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
209 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
210 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
211 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
212 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
213 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
214 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
215 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
216 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
217 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
218 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
219 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
220 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
224 #if defined(CONFIG_DRM_I915_KMS)
225 MODULE_DEVICE_TABLE(pci, pciidlist);
228 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
229 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
231 void intel_detect_pch (struct drm_device *dev)
233 struct drm_i915_private *dev_priv = dev->dev_private;
237 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
238 * make graphics device passthrough work easy for VMM, that only
239 * need to expose ISA bridge to let driver know the real hardware
240 * underneath. This is a requirement from virtualization team.
242 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
244 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
246 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
248 if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
249 dev_priv->pch_type = PCH_CPT;
250 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
257 void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
262 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
265 I915_WRITE_NOTRACE(FORCEWAKE, 1);
266 POSTING_READ(FORCEWAKE);
269 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
273 void __gen6_force_wake_put(struct drm_i915_private *dev_priv)
275 I915_WRITE_NOTRACE(FORCEWAKE, 0);
276 POSTING_READ(FORCEWAKE);
279 static int i915_drm_freeze(struct drm_device *dev)
281 struct drm_i915_private *dev_priv = dev->dev_private;
283 drm_kms_helper_poll_disable(dev);
285 pci_save_state(dev->pdev);
287 /* If KMS is active, we do the leavevt stuff here */
288 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
289 int error = i915_gem_idle(dev);
291 dev_err(&dev->pdev->dev,
292 "GEM idle failed, resume might fail\n");
295 drm_irq_uninstall(dev);
298 i915_save_state(dev);
300 intel_opregion_fini(dev);
302 /* Modeset on resume, not lid events */
303 dev_priv->modeset_on_lid = 0;
308 int i915_suspend(struct drm_device *dev, pm_message_t state)
312 if (!dev || !dev->dev_private) {
313 DRM_ERROR("dev: %p\n", dev);
314 DRM_ERROR("DRM not initialized, aborting suspend.\n");
318 if (state.event == PM_EVENT_PRETHAW)
322 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
325 error = i915_drm_freeze(dev);
329 if (state.event == PM_EVENT_SUSPEND) {
330 /* Shut down the device */
331 pci_disable_device(dev->pdev);
332 pci_set_power_state(dev->pdev, PCI_D3hot);
338 static int i915_drm_thaw(struct drm_device *dev)
340 struct drm_i915_private *dev_priv = dev->dev_private;
343 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
344 mutex_lock(&dev->struct_mutex);
345 i915_gem_restore_gtt_mappings(dev);
346 mutex_unlock(&dev->struct_mutex);
349 i915_restore_state(dev);
350 intel_opregion_setup(dev);
352 /* KMS EnterVT equivalent */
353 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
354 mutex_lock(&dev->struct_mutex);
355 dev_priv->mm.suspended = 0;
357 error = i915_gem_init_ringbuffer(dev);
358 mutex_unlock(&dev->struct_mutex);
360 drm_mode_config_reset(dev);
361 drm_irq_install(dev);
363 /* Resume the modeset for every activated CRTC */
364 drm_helper_resume_force_mode(dev);
366 if (dev_priv->renderctx && dev_priv->pwrctx)
367 ironlake_enable_rc6(dev);
370 intel_opregion_init(dev);
372 dev_priv->modeset_on_lid = 0;
377 int i915_resume(struct drm_device *dev)
381 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
384 if (pci_enable_device(dev->pdev))
387 pci_set_master(dev->pdev);
389 ret = i915_drm_thaw(dev);
393 drm_kms_helper_poll_enable(dev);
397 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
399 struct drm_i915_private *dev_priv = dev->dev_private;
404 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
405 POSTING_READ(D_STATE);
407 if (IS_I830(dev) || IS_845G(dev)) {
408 I915_WRITE(DEBUG_RESET_I830,
409 DEBUG_RESET_DISPLAY |
412 POSTING_READ(DEBUG_RESET_I830);
415 I915_WRITE(DEBUG_RESET_I830, 0);
416 POSTING_READ(DEBUG_RESET_I830);
421 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
422 POSTING_READ(D_STATE);
427 static int i965_reset_complete(struct drm_device *dev)
430 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
434 static int i965_do_reset(struct drm_device *dev, u8 flags)
439 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
440 * well as the reset bit (GR/bit 0). Setting the GR bit
441 * triggers the reset; when done, the hardware will clear it.
443 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
444 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
446 return wait_for(i965_reset_complete(dev), 500);
449 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
453 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
454 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
457 static int gen6_do_reset(struct drm_device *dev, u8 flags)
459 struct drm_i915_private *dev_priv = dev->dev_private;
461 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
462 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
466 * i965_reset - reset chip after a hang
467 * @dev: drm device to reset
468 * @flags: reset domains
470 * Reset the chip. Useful if a hang is detected. Returns zero on successful
471 * reset or otherwise an error code.
473 * Procedure is fairly simple:
474 * - reset the chip using the reset reg
475 * - re-init context state
476 * - re-init hardware status page
477 * - re-init ring buffer
478 * - re-init interrupt state
481 int i915_reset(struct drm_device *dev, u8 flags)
483 drm_i915_private_t *dev_priv = dev->dev_private;
485 * We really should only reset the display subsystem if we actually
488 bool need_display = true;
494 if (!mutex_trylock(&dev->struct_mutex))
500 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
501 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
502 } else switch (INTEL_INFO(dev)->gen) {
504 ret = gen6_do_reset(dev, flags);
507 ret = ironlake_do_reset(dev, flags);
510 ret = i965_do_reset(dev, flags);
513 ret = i8xx_do_reset(dev, flags);
516 dev_priv->last_gpu_reset = get_seconds();
518 DRM_ERROR("Failed to reset chip.\n");
519 mutex_unlock(&dev->struct_mutex);
523 /* Ok, now get things going again... */
526 * Everything depends on having the GTT running, so we need to start
527 * there. Fortunately we don't need to do this unless we reset the
528 * chip at a PCI level.
530 * Next we need to restore the context, but we don't use those
533 * Ring buffer needs to be re-initialized in the KMS case, or if X
534 * was running at the time of the reset (i.e. we weren't VT
537 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
538 !dev_priv->mm.suspended) {
539 dev_priv->mm.suspended = 0;
541 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
543 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
545 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
547 mutex_unlock(&dev->struct_mutex);
548 drm_irq_uninstall(dev);
549 drm_mode_config_reset(dev);
550 drm_irq_install(dev);
551 mutex_lock(&dev->struct_mutex);
554 mutex_unlock(&dev->struct_mutex);
557 * Perform a full modeset as on later generations, e.g. Ironlake, we may
558 * need to retrain the display link and cannot just restore the register
562 mutex_lock(&dev->mode_config.mutex);
563 drm_helper_resume_force_mode(dev);
564 mutex_unlock(&dev->mode_config.mutex);
572 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
574 return drm_get_pci_dev(pdev, ent, &driver);
578 i915_pci_remove(struct pci_dev *pdev)
580 struct drm_device *dev = pci_get_drvdata(pdev);
585 static int i915_pm_suspend(struct device *dev)
587 struct pci_dev *pdev = to_pci_dev(dev);
588 struct drm_device *drm_dev = pci_get_drvdata(pdev);
591 if (!drm_dev || !drm_dev->dev_private) {
592 dev_err(dev, "DRM not initialized, aborting suspend.\n");
596 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
599 error = i915_drm_freeze(drm_dev);
603 pci_disable_device(pdev);
604 pci_set_power_state(pdev, PCI_D3hot);
609 static int i915_pm_resume(struct device *dev)
611 struct pci_dev *pdev = to_pci_dev(dev);
612 struct drm_device *drm_dev = pci_get_drvdata(pdev);
614 return i915_resume(drm_dev);
617 static int i915_pm_freeze(struct device *dev)
619 struct pci_dev *pdev = to_pci_dev(dev);
620 struct drm_device *drm_dev = pci_get_drvdata(pdev);
622 if (!drm_dev || !drm_dev->dev_private) {
623 dev_err(dev, "DRM not initialized, aborting suspend.\n");
627 return i915_drm_freeze(drm_dev);
630 static int i915_pm_thaw(struct device *dev)
632 struct pci_dev *pdev = to_pci_dev(dev);
633 struct drm_device *drm_dev = pci_get_drvdata(pdev);
635 return i915_drm_thaw(drm_dev);
638 static int i915_pm_poweroff(struct device *dev)
640 struct pci_dev *pdev = to_pci_dev(dev);
641 struct drm_device *drm_dev = pci_get_drvdata(pdev);
643 return i915_drm_freeze(drm_dev);
646 static const struct dev_pm_ops i915_pm_ops = {
647 .suspend = i915_pm_suspend,
648 .resume = i915_pm_resume,
649 .freeze = i915_pm_freeze,
650 .thaw = i915_pm_thaw,
651 .poweroff = i915_pm_poweroff,
652 .restore = i915_pm_resume,
655 static struct vm_operations_struct i915_gem_vm_ops = {
656 .fault = i915_gem_fault,
657 .open = drm_gem_vm_open,
658 .close = drm_gem_vm_close,
661 static struct drm_driver driver = {
662 /* don't use mtrr's here, the Xserver or user space app should
663 * deal with them for intel hardware.
666 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
667 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
668 .load = i915_driver_load,
669 .unload = i915_driver_unload,
670 .open = i915_driver_open,
671 .lastclose = i915_driver_lastclose,
672 .preclose = i915_driver_preclose,
673 .postclose = i915_driver_postclose,
675 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
676 .suspend = i915_suspend,
677 .resume = i915_resume,
679 .device_is_agp = i915_driver_device_is_agp,
680 .enable_vblank = i915_enable_vblank,
681 .disable_vblank = i915_disable_vblank,
682 .get_vblank_timestamp = i915_get_vblank_timestamp,
683 .get_scanout_position = i915_get_crtc_scanoutpos,
684 .irq_preinstall = i915_driver_irq_preinstall,
685 .irq_postinstall = i915_driver_irq_postinstall,
686 .irq_uninstall = i915_driver_irq_uninstall,
687 .irq_handler = i915_driver_irq_handler,
688 .reclaim_buffers = drm_core_reclaim_buffers,
689 .master_create = i915_master_create,
690 .master_destroy = i915_master_destroy,
691 #if defined(CONFIG_DEBUG_FS)
692 .debugfs_init = i915_debugfs_init,
693 .debugfs_cleanup = i915_debugfs_cleanup,
695 .gem_init_object = i915_gem_init_object,
696 .gem_free_object = i915_gem_free_object,
697 .gem_vm_ops = &i915_gem_vm_ops,
698 .ioctls = i915_ioctls,
700 .owner = THIS_MODULE,
702 .release = drm_release,
703 .unlocked_ioctl = drm_ioctl,
704 .mmap = drm_gem_mmap,
706 .fasync = drm_fasync,
709 .compat_ioctl = i915_compat_ioctl,
711 .llseek = noop_llseek,
716 .id_table = pciidlist,
717 .probe = i915_pci_probe,
718 .remove = i915_pci_remove,
719 .driver.pm = &i915_pm_ops,
725 .major = DRIVER_MAJOR,
726 .minor = DRIVER_MINOR,
727 .patchlevel = DRIVER_PATCHLEVEL,
730 static int __init i915_init(void)
732 if (!intel_agp_enabled) {
733 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
737 driver.num_ioctls = i915_max_ioctl;
740 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
741 * explicitly disabled with the module pararmeter.
743 * Otherwise, just follow the parameter (defaulting to off).
745 * Allow optional vga_text_mode_force boot option to override
746 * the default behavior.
748 #if defined(CONFIG_DRM_I915_KMS)
749 if (i915_modeset != 0)
750 driver.driver_features |= DRIVER_MODESET;
752 if (i915_modeset == 1)
753 driver.driver_features |= DRIVER_MODESET;
755 #ifdef CONFIG_VGA_CONSOLE
756 if (vgacon_text_force() && i915_modeset == -1)
757 driver.driver_features &= ~DRIVER_MODESET;
760 if (!(driver.driver_features & DRIVER_MODESET))
761 driver.get_vblank_timestamp = NULL;
763 return drm_init(&driver);
766 static void __exit i915_exit(void)
771 module_init(i915_init);
772 module_exit(i915_exit);
774 MODULE_AUTHOR(DRIVER_AUTHOR);
775 MODULE_DESCRIPTION(DRIVER_DESC);
776 MODULE_LICENSE("GPL and additional rights");