drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41 #include <acpi/video.h>
  42
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_irq.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_audio.h"
  50 #include "display/intel_bw.h"
  51 #include "display/intel_cdclk.h"
  52 #include "display/intel_csr.h"
  53 #include "display/intel_display_debugfs.h"
  54 #include "display/intel_display_types.h"
  55 #include "display/intel_dp.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pipe_crc.h"
  60 #include "display/intel_psr.h"
  61 #include "display/intel_sprite.h"
  62 #include "display/intel_vga.h"
  63
  64 #include "gem/i915_gem_context.h"
  65 #include "gem/i915_gem_ioctls.h"
  66 #include "gem/i915_gem_mman.h"
  67 #include "gt/intel_gt.h"
  68 #include "gt/intel_gt_pm.h"
  69 #include "gt/intel_rc6.h"
  70
  71 #include "i915_debugfs.h"
  72 #include "i915_drv.h"
  73 #include "i915_ioc32.h"
  74 #include "i915_irq.h"
  75 #include "i915_memcpy.h"
  76 #include "i915_perf.h"
  77 #include "i915_query.h"
  78 #include "i915_suspend.h"
  79 #include "i915_switcheroo.h"
  80 #include "i915_sysfs.h"
  81 #include "i915_trace.h"
  82 #include "i915_vgpu.h"
  83 #include "intel_dram.h"
  84 #include "intel_gvt.h"
  85 #include "intel_memory_region.h"
  86 #include "intel_pm.h"
  87 #include "vlv_suspend.h"
  88
  89 static struct drm_driver driver;
  90
  91 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  92 {
  93         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
  94
  95         dev_priv->bridge_dev =
  96                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  97         if (!dev_priv->bridge_dev) {
  98                 drm_err(&dev_priv->drm, "bridge device not found\n");
  99                 return -1;
 100         }
 101         return 0;
 102 }
 103
 104 /* Allocate space for the MCH regs if needed, return nonzero on error */
 105 static int
 106 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 107 {
 108         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 109         u32 temp_lo, temp_hi = 0;
 110         u64 mchbar_addr;
 111         int ret;
 112
 113         if (INTEL_GEN(dev_priv) >= 4)
 114                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 115         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 116         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 117
 118         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 119 #ifdef CONFIG_PNP
 120         if (mchbar_addr &&
 121             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 122                 return 0;
 123 #endif
 124
 125         /* Get some space for it */
 126         dev_priv->mch_res.name = "i915 MCHBAR";
 127         dev_priv->mch_res.flags = IORESOURCE_MEM;
 128         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 129                                      &dev_priv->mch_res,
 130                                      MCHBAR_SIZE, MCHBAR_SIZE,
 131                                      PCIBIOS_MIN_MEM,
 132                                      0, pcibios_align_resource,
 133                                      dev_priv->bridge_dev);
 134         if (ret) {
 135                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 136                 dev_priv->mch_res.start = 0;
 137                 return ret;
 138         }
 139
 140         if (INTEL_GEN(dev_priv) >= 4)
 141                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 142                                        upper_32_bits(dev_priv->mch_res.start));
 143
 144         pci_write_config_dword(dev_priv->bridge_dev, reg,
 145                                lower_32_bits(dev_priv->mch_res.start));
 146         return 0;
 147 }
 148
 149 /* Setup MCHBAR if possible, return true if we should disable it again */
 150 static void
 151 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 152 {
 153         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 154         u32 temp;
 155         bool enabled;
 156
 157         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 158                 return;
 159
 160         dev_priv->mchbar_need_disable = false;
 161
 162         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 163                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 164                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 165         } else {
 166                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 167                 enabled = temp & 1;
 168         }
 169
 170         /* If it's already enabled, don't have to do anything */
 171         if (enabled)
 172                 return;
 173
 174         if (intel_alloc_mchbar_resource(dev_priv))
 175                 return;
 176
 177         dev_priv->mchbar_need_disable = true;
 178
 179         /* Space is allocated or reserved, so enable it. */
 180         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 181                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 182                                        temp | DEVEN_MCHBAR_EN);
 183         } else {
 184                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 185                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 186         }
 187 }
 188
 189 static void
 190 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 191 {
 192         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 193
 194         if (dev_priv->mchbar_need_disable) {
 195                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 196                         u32 deven_val;
 197
 198                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 199                                               &deven_val);
 200                         deven_val &= ~DEVEN_MCHBAR_EN;
 201                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 202                                                deven_val);
 203                 } else {
 204                         u32 mchbar_val;
 205
 206                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 207                                               &mchbar_val);
 208                         mchbar_val &= ~1;
 209                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 210                                                mchbar_val);
 211                 }
 212         }
 213
 214         if (dev_priv->mch_res.start)
 215                 release_resource(&dev_priv->mch_res);
 216 }
 217
 218 /* part #1: call before irq install */
 219 static int i915_driver_modeset_probe_noirq(struct drm_i915_private *i915)
 220 {
 221         int ret;
 222
 223         if (i915_inject_probe_failure(i915))
 224                 return -ENODEV;
 225
 226         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
 227                 ret = drm_vblank_init(&i915->drm,
 228                                       INTEL_NUM_PIPES(i915));
 229                 if (ret)
 230                         goto out;
 231         }
 232
 233         intel_bios_init(i915);
 234
 235         ret = intel_vga_register(i915);
 236         if (ret)
 237                 goto out;
 238
 239         intel_power_domains_init_hw(i915, false);
 240
 241         intel_csr_ucode_init(i915);
 242
 243         ret = intel_modeset_init_noirq(i915);
 244         if (ret)
 245                 goto cleanup_vga_client;
 246
 247         return 0;
 248
 249 cleanup_vga_client:
 250         intel_vga_unregister(i915);
 251 out:
 252         return ret;
 253 }
 254
 255 /* part #2: call after irq install */
 256 static int i915_driver_modeset_probe(struct drm_i915_private *i915)
 257 {
 258         int ret;
 259
 260         /* Important: The output setup functions called by modeset_init need
 261          * working irqs for e.g. gmbus and dp aux transfers. */
 262         ret = intel_modeset_init(i915);
 263         if (ret)
 264                 goto out;
 265
 266         ret = i915_gem_init(i915);
 267         if (ret)
 268                 goto cleanup_modeset;
 269
 270         intel_overlay_setup(i915);
 271
 272         if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
 273                 return 0;
 274
 275         ret = intel_fbdev_init(&i915->drm);
 276         if (ret)
 277                 goto cleanup_gem;
 278
 279         /* Only enable hotplug handling once the fbdev is fully set up. */
 280         intel_hpd_init(i915);
 281
 282         intel_init_ipc(i915);
 283
 284         intel_psr_set_force_mode_changed(i915->psr.dp);
 285
 286         return 0;
 287
 288 cleanup_gem:
 289         i915_gem_suspend(i915);
 290         i915_gem_driver_remove(i915);
 291         i915_gem_driver_release(i915);
 292 cleanup_modeset:
 293         /* FIXME */
 294         intel_modeset_driver_remove(i915);
 295         intel_irq_uninstall(i915);
 296         intel_modeset_driver_remove_noirq(i915);
 297 out:
 298         return ret;
 299 }
 300
 301 /* part #1: call before irq uninstall */
 302 static void i915_driver_modeset_remove(struct drm_i915_private *i915)
 303 {
 304         intel_modeset_driver_remove(i915);
 305 }
 306
 307 /* part #2: call after irq uninstall */
 308 static void i915_driver_modeset_remove_noirq(struct drm_i915_private *i915)
 309 {
 310         intel_modeset_driver_remove_noirq(i915);
 311
 312         intel_bios_driver_remove(i915);
 313
 314         intel_vga_unregister(i915);
 315
 316         intel_csr_ucode_fini(i915);
 317 }
 318
 319 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 320 {
 321         /*
 322          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 323          * CHV x1 PHY (DP/HDMI D)
 324          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 325          */
 326         if (IS_CHERRYVIEW(dev_priv)) {
 327                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 328                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 329         } else if (IS_VALLEYVIEW(dev_priv)) {
 330                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 331         }
 332 }
 333
 334 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 335 {
 336         /*
 337          * The i915 workqueue is primarily used for batched retirement of
 338          * requests (and thus managing bo) once the task has been completed
 339          * by the GPU. i915_retire_requests() is called directly when we
 340          * need high-priority retirement, such as waiting for an explicit
 341          * bo.
 342          *
 343          * It is also used for periodic low-priority events, such as
 344          * idle-timers and recording error state.
 345          *
 346          * All tasks on the workqueue are expected to acquire the dev mutex
 347          * so there is no point in running more than one instance of the
 348          * workqueue at any time.  Use an ordered one.
 349          */
 350         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 351         if (dev_priv->wq == NULL)
 352                 goto out_err;
 353
 354         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 355         if (dev_priv->hotplug.dp_wq == NULL)
 356                 goto out_free_wq;
 357
 358         return 0;
 359
 360 out_free_wq:
 361         destroy_workqueue(dev_priv->wq);
 362 out_err:
 363         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 364
 365         return -ENOMEM;
 366 }
 367
 368 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 369 {
 370         destroy_workqueue(dev_priv->hotplug.dp_wq);
 371         destroy_workqueue(dev_priv->wq);
 372 }
 373
 374 /*
 375  * We don't keep the workarounds for pre-production hardware, so we expect our
 376  * driver to fail on these machines in one way or another. A little warning on
 377  * dmesg may help both the user and the bug triagers.
 378  *
 379  * Our policy for removing pre-production workarounds is to keep the
 380  * current gen workarounds as a guide to the bring-up of the next gen
 381  * (workarounds have a habit of persisting!). Anything older than that
 382  * should be removed along with the complications they introduce.
 383  */
 384 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 385 {
 386         bool pre = false;
 387
 388         pre |= IS_HSW_EARLY_SDV(dev_priv);
 389         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 390         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 391         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 392         pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
 393
 394         if (pre) {
 395                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 396                           "It may not be fully functional.\n");
 397                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 398         }
 399 }
 400
 401 static void sanitize_gpu(struct drm_i915_private *i915)
 402 {
 403         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 404                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 405 }
 406
 407 /**
 408  * i915_driver_early_probe - setup state not requiring device access
 409  * @dev_priv: device private
 410  *
 411  * Initialize everything that is a "SW-only" state, that is state not
 412  * requiring accessing the device or exposing the driver via kernel internal
 413  * or userspace interfaces. Example steps belonging here: lock initialization,
 414  * system memory allocation, setting up device specific attributes and
 415  * function hooks not requiring accessing the device.
 416  */
 417 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 418 {
 419         int ret = 0;
 420
 421         if (i915_inject_probe_failure(dev_priv))
 422                 return -ENODEV;
 423
 424         intel_device_info_subplatform_init(dev_priv);
 425
 426         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 427         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 428
 429         spin_lock_init(&dev_priv->irq_lock);
 430         spin_lock_init(&dev_priv->gpu_error.lock);
 431         mutex_init(&dev_priv->backlight_lock);
 432
 433         mutex_init(&dev_priv->sb_lock);
 434         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 435
 436         mutex_init(&dev_priv->av_mutex);
 437         mutex_init(&dev_priv->wm.wm_mutex);
 438         mutex_init(&dev_priv->pps_mutex);
 439         mutex_init(&dev_priv->hdcp_comp_mutex);
 440
 441         i915_memcpy_init_early(dev_priv);
 442         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 443
 444         ret = i915_workqueues_init(dev_priv);
 445         if (ret < 0)
 446                 return ret;
 447
 448         ret = vlv_suspend_init(dev_priv);
 449         if (ret < 0)
 450                 goto err_workqueues;
 451
 452         intel_wopcm_init_early(&dev_priv->wopcm);
 453
 454         intel_gt_init_early(&dev_priv->gt, dev_priv);
 455
 456         i915_gem_init_early(dev_priv);
 457
 458         /* This must be called before any calls to HAS_PCH_* */
 459         intel_detect_pch(dev_priv);
 460
 461         intel_pm_setup(dev_priv);
 462         intel_init_dpio(dev_priv);
 463         ret = intel_power_domains_init(dev_priv);
 464         if (ret < 0)
 465                 goto err_gem;
 466         intel_irq_init(dev_priv);
 467         intel_init_display_hooks(dev_priv);
 468         intel_init_clock_gating_hooks(dev_priv);
 469         intel_init_audio_hooks(dev_priv);
 470
 471         intel_detect_preproduction_hw(dev_priv);
 472
 473         return 0;
 474
 475 err_gem:
 476         i915_gem_cleanup_early(dev_priv);
 477         intel_gt_driver_late_release(&dev_priv->gt);
 478         vlv_suspend_cleanup(dev_priv);
 479 err_workqueues:
 480         i915_workqueues_cleanup(dev_priv);
 481         return ret;
 482 }
 483
 484 /**
 485  * i915_driver_late_release - cleanup the setup done in
 486  *                             i915_driver_early_probe()
 487  * @dev_priv: device private
 488  */
 489 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 490 {
 491         intel_irq_fini(dev_priv);
 492         intel_power_domains_cleanup(dev_priv);
 493         i915_gem_cleanup_early(dev_priv);
 494         intel_gt_driver_late_release(&dev_priv->gt);
 495         vlv_suspend_cleanup(dev_priv);
 496         i915_workqueues_cleanup(dev_priv);
 497
 498         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 499         mutex_destroy(&dev_priv->sb_lock);
 500 }
 501
 502 /**
 503  * i915_driver_mmio_probe - setup device MMIO
 504  * @dev_priv: device private
 505  *
 506  * Setup minimal device state necessary for MMIO accesses later in the
 507  * initialization sequence. The setup here should avoid any other device-wide
 508  * side effects or exposing the driver via kernel internal or user space
 509  * interfaces.
 510  */
 511 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 512 {
 513         int ret;
 514
 515         if (i915_inject_probe_failure(dev_priv))
 516                 return -ENODEV;
 517
 518         if (i915_get_bridge_dev(dev_priv))
 519                 return -EIO;
 520
 521         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 522         if (ret < 0)
 523                 goto err_bridge;
 524
 525         /* Try to make sure MCHBAR is enabled before poking at it */
 526         intel_setup_mchbar(dev_priv);
 527
 528         intel_device_info_init_mmio(dev_priv);
 529
 530         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
 531
 532         intel_uc_init_mmio(&dev_priv->gt.uc);
 533
 534         ret = intel_engines_init_mmio(&dev_priv->gt);
 535         if (ret)
 536                 goto err_uncore;
 537
 538         /* As early as possible, scrub existing GPU state before clobbering */
 539         sanitize_gpu(dev_priv);
 540
 541         return 0;
 542
 543 err_uncore:
 544         intel_teardown_mchbar(dev_priv);
 545         intel_uncore_fini_mmio(&dev_priv->uncore);
 546 err_bridge:
 547         pci_dev_put(dev_priv->bridge_dev);
 548
 549         return ret;
 550 }
 551
 552 /**
 553  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 554  * @dev_priv: device private
 555  */
 556 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 557 {
 558         intel_teardown_mchbar(dev_priv);
 559         intel_uncore_fini_mmio(&dev_priv->uncore);
 560         pci_dev_put(dev_priv->bridge_dev);
 561 }
 562
 563 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 564 {
 565         intel_gvt_sanitize_options(dev_priv);
 566 }
 567
 568 /**
 569  * i915_driver_hw_probe - setup state requiring device access
 570  * @dev_priv: device private
 571  *
 572  * Setup state that requires accessing the device, but doesn't require
 573  * exposing the driver via kernel internal or userspace interfaces.
 574  */
 575 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 576 {
 577         struct pci_dev *pdev = dev_priv->drm.pdev;
 578         int ret;
 579
 580         if (i915_inject_probe_failure(dev_priv))
 581                 return -ENODEV;
 582
 583         intel_device_info_runtime_init(dev_priv);
 584
 585         if (HAS_PPGTT(dev_priv)) {
 586                 if (intel_vgpu_active(dev_priv) &&
 587                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 588                         i915_report_error(dev_priv,
 589                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 590                         return -ENXIO;
 591                 }
 592         }
 593
 594         if (HAS_EXECLISTS(dev_priv)) {
 595                 /*
 596                  * Older GVT emulation depends upon intercepting CSB mmio,
 597                  * which we no longer use, preferring to use the HWSP cache
 598                  * instead.
 599                  */
 600                 if (intel_vgpu_active(dev_priv) &&
 601                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 602                         i915_report_error(dev_priv,
 603                                           "old vGPU host found, support for HWSP emulation required\n");
 604                         return -ENXIO;
 605                 }
 606         }
 607
 608         intel_sanitize_options(dev_priv);
 609
 610         /* needs to be done before ggtt probe */
 611         intel_dram_edram_detect(dev_priv);
 612
 613         i915_perf_init(dev_priv);
 614
 615         ret = i915_ggtt_probe_hw(dev_priv);
 616         if (ret)
 617                 goto err_perf;
 618
 619         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
 620         if (ret)
 621                 goto err_ggtt;
 622
 623         ret = i915_ggtt_init_hw(dev_priv);
 624         if (ret)
 625                 goto err_ggtt;
 626
 627         ret = intel_memory_regions_hw_probe(dev_priv);
 628         if (ret)
 629                 goto err_ggtt;
 630
 631         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 632
 633         ret = i915_ggtt_enable_hw(dev_priv);
 634         if (ret) {
 635                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 636                 goto err_mem_regions;
 637         }
 638
 639         pci_set_master(pdev);
 640
 641         /*
 642          * We don't have a max segment size, so set it to the max so sg's
 643          * debugging layer doesn't complain
 644          */
 645         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
 646
 647         /* overlay on gen2 is broken and can't address above 1G */
 648         if (IS_GEN(dev_priv, 2)) {
 649                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
 650                 if (ret) {
 651                         drm_err(&dev_priv->drm, "failed to set DMA mask\n");
 652
 653                         goto err_mem_regions;
 654                 }
 655         }
 656
 657         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 658          * using 32bit addressing, overwriting memory if HWS is located
 659          * above 4GB.
 660          *
 661          * The documentation also mentions an issue with undefined
 662          * behaviour if any general state is accessed within a page above 4GB,
 663          * which also needs to be handled carefully.
 664          */
 665         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
 666                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 667
 668                 if (ret) {
 669                         drm_err(&dev_priv->drm, "failed to set DMA mask\n");
 670
 671                         goto err_mem_regions;
 672                 }
 673         }
 674
 675         cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 676
 677         intel_gt_init_workarounds(dev_priv);
 678
 679         /* On the 945G/GM, the chipset reports the MSI capability on the
 680          * integrated graphics even though the support isn't actually there
 681          * according to the published specs.  It doesn't appear to function
 682          * correctly in testing on 945G.
 683          * This may be a side effect of MSI having been made available for PEG
 684          * and the registers being closely associated.
 685          *
 686          * According to chipset errata, on the 965GM, MSI interrupts may
 687          * be lost or delayed, and was defeatured. MSI interrupts seem to
 688          * get lost on g4x as well, and interrupt delivery seems to stay
 689          * properly dead afterwards. So we'll just disable them for all
 690          * pre-gen5 chipsets.
 691          *
 692          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 693          * interrupts even when in MSI mode. This results in spurious
 694          * interrupt warnings if the legacy irq no. is shared with another
 695          * device. The kernel then disables that interrupt source and so
 696          * prevents the other device from working properly.
 697          */
 698         if (INTEL_GEN(dev_priv) >= 5) {
 699                 if (pci_enable_msi(pdev) < 0)
 700                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 701         }
 702
 703         ret = intel_gvt_init(dev_priv);
 704         if (ret)
 705                 goto err_msi;
 706
 707         intel_opregion_setup(dev_priv);
 708         /*
 709          * Fill the dram structure to get the system raw bandwidth and
 710          * dram info. This will be used for memory latency calculation.
 711          */
 712         intel_dram_detect(dev_priv);
 713
 714         intel_bw_init_hw(dev_priv);
 715
 716         return 0;
 717
 718 err_msi:
 719         if (pdev->msi_enabled)
 720                 pci_disable_msi(pdev);
 721         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 722 err_mem_regions:
 723         intel_memory_regions_driver_release(dev_priv);
 724 err_ggtt:
 725         i915_ggtt_driver_release(dev_priv);
 726 err_perf:
 727         i915_perf_fini(dev_priv);
 728         return ret;
 729 }
 730
 731 /**
 732  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 733  * @dev_priv: device private
 734  */
 735 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 736 {
 737         struct pci_dev *pdev = dev_priv->drm.pdev;
 738
 739         i915_perf_fini(dev_priv);
 740
 741         if (pdev->msi_enabled)
 742                 pci_disable_msi(pdev);
 743
 744         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 745 }
 746
 747 /**
 748  * i915_driver_register - register the driver with the rest of the system
 749  * @dev_priv: device private
 750  *
 751  * Perform any steps necessary to make the driver available via kernel
 752  * internal or userspace interfaces.
 753  */
 754 static void i915_driver_register(struct drm_i915_private *dev_priv)
 755 {
 756         struct drm_device *dev = &dev_priv->drm;
 757
 758         i915_gem_driver_register(dev_priv);
 759         i915_pmu_register(dev_priv);
 760
 761         intel_vgpu_register(dev_priv);
 762
 763         /* Reveal our presence to userspace */
 764         if (drm_dev_register(dev, 0) == 0) {
 765                 i915_debugfs_register(dev_priv);
 766                 intel_display_debugfs_register(dev_priv);
 767                 i915_setup_sysfs(dev_priv);
 768
 769                 /* Depends on sysfs having been initialized */
 770                 i915_perf_register(dev_priv);
 771         } else
 772                 drm_err(&dev_priv->drm,
 773                         "Failed to register driver for userspace access!\n");
 774
 775         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
 776                 /* Must be done after probing outputs */
 777                 intel_opregion_register(dev_priv);
 778                 acpi_video_register();
 779         }
 780
 781         intel_gt_driver_register(&dev_priv->gt);
 782
 783         intel_audio_init(dev_priv);
 784
 785         /*
 786          * Some ports require correctly set-up hpd registers for detection to
 787          * work properly (leading to ghost connected connector status), e.g. VGA
 788          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 789          * irqs are fully enabled. We do it last so that the async config
 790          * cannot run before the connectors are registered.
 791          */
 792         intel_fbdev_initial_config_async(dev);
 793
 794         /*
 795          * We need to coordinate the hotplugs with the asynchronous fbdev
 796          * configuration, for which we use the fbdev->async_cookie.
 797          */
 798         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
 799                 drm_kms_helper_poll_init(dev);
 800
 801         intel_power_domains_enable(dev_priv);
 802         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 803
 804         intel_register_dsm_handler();
 805
 806         if (i915_switcheroo_register(dev_priv))
 807                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 808 }
 809
 810 /**
 811  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 812  * @dev_priv: device private
 813  */
 814 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 815 {
 816         i915_switcheroo_unregister(dev_priv);
 817
 818         intel_unregister_dsm_handler();
 819
 820         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 821         intel_power_domains_disable(dev_priv);
 822
 823         intel_fbdev_unregister(dev_priv);
 824         intel_audio_deinit(dev_priv);
 825
 826         /*
 827          * After flushing the fbdev (incl. a late async config which will
 828          * have delayed queuing of a hotplug event), then flush the hotplug
 829          * events.
 830          */
 831         drm_kms_helper_poll_fini(&dev_priv->drm);
 832
 833         intel_gt_driver_unregister(&dev_priv->gt);
 834         acpi_video_unregister();
 835         intel_opregion_unregister(dev_priv);
 836
 837         i915_perf_unregister(dev_priv);
 838         i915_pmu_unregister(dev_priv);
 839
 840         i915_teardown_sysfs(dev_priv);
 841         drm_dev_unplug(&dev_priv->drm);
 842
 843         i915_gem_driver_unregister(dev_priv);
 844 }
 845
 846 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 847 {
 848         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 849                 struct drm_printer p = drm_debug_printer("i915 device info:");
 850
 851                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 852                            INTEL_DEVID(dev_priv),
 853                            INTEL_REVID(dev_priv),
 854                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 855                            intel_subplatform(RUNTIME_INFO(dev_priv),
 856                                              INTEL_INFO(dev_priv)->platform),
 857                            INTEL_GEN(dev_priv));
 858
 859                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 860                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 861         }
 862
 863         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 864                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 865         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 866                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 867         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 868                 drm_info(&dev_priv->drm,
 869                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 870 }
 871
 872 static struct drm_i915_private *
 873 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 874 {
 875         const struct intel_device_info *match_info =
 876                 (struct intel_device_info *)ent->driver_data;
 877         struct intel_device_info *device_info;
 878         struct drm_i915_private *i915;
 879         int err;
 880
 881         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
 882         if (!i915)
 883                 return ERR_PTR(-ENOMEM);
 884
 885         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
 886         if (err) {
 887                 kfree(i915);
 888                 return ERR_PTR(err);
 889         }
 890
 891         i915->drm.pdev = pdev;
 892         pci_set_drvdata(pdev, i915);
 893
 894         /* Setup the write-once "constant" device info */
 895         device_info = mkwrite_device_info(i915);
 896         memcpy(device_info, match_info, sizeof(*device_info));
 897         RUNTIME_INFO(i915)->device_id = pdev->device;
 898
 899         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 900
 901         return i915;
 902 }
 903
 904 static void i915_driver_destroy(struct drm_i915_private *i915)
 905 {
 906         struct pci_dev *pdev = i915->drm.pdev;
 907
 908         drm_dev_fini(&i915->drm);
 909         kfree(i915);
 910
 911         /* And make sure we never chase our dangling pointer from pci_dev */
 912         pci_set_drvdata(pdev, NULL);
 913 }
 914
 915 /**
 916  * i915_driver_probe - setup chip and create an initial config
 917  * @pdev: PCI device
 918  * @ent: matching PCI ID entry
 919  *
 920  * The driver probe routine has to do several things:
 921  *   - drive output discovery via intel_modeset_init()
 922  *   - initialize the memory manager
 923  *   - allocate initial config memory
 924  *   - setup the DRM framebuffer with the allocated memory
 925  */
 926 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 927 {
 928         const struct intel_device_info *match_info =
 929                 (struct intel_device_info *)ent->driver_data;
 930         struct drm_i915_private *i915;
 931         int ret;
 932
 933         i915 = i915_driver_create(pdev, ent);
 934         if (IS_ERR(i915))
 935                 return PTR_ERR(i915);
 936
 937         /* Disable nuclear pageflip by default on pre-ILK */
 938         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
 939                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 940
 941         /*
 942          * Check if we support fake LMEM -- for now we only unleash this for
 943          * the live selftests(test-and-exit).
 944          */
 945 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 946         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 947                 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
 948                     i915_modparams.fake_lmem_start) {
 949                         mkwrite_device_info(i915)->memory_regions =
 950                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
 951                         mkwrite_device_info(i915)->is_dgfx = true;
 952                         GEM_BUG_ON(!HAS_LMEM(i915));
 953                         GEM_BUG_ON(!IS_DGFX(i915));
 954                 }
 955         }
 956 #endif
 957
 958         ret = pci_enable_device(pdev);
 959         if (ret)
 960                 goto out_fini;
 961
 962         ret = i915_driver_early_probe(i915);
 963         if (ret < 0)
 964                 goto out_pci_disable;
 965
 966         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 967
 968         intel_vgpu_detect(i915);
 969
 970         ret = i915_driver_mmio_probe(i915);
 971         if (ret < 0)
 972                 goto out_runtime_pm_put;
 973
 974         ret = i915_driver_hw_probe(i915);
 975         if (ret < 0)
 976                 goto out_cleanup_mmio;
 977
 978         ret = i915_driver_modeset_probe_noirq(i915);
 979         if (ret < 0)
 980                 goto out_cleanup_hw;
 981
 982         ret = intel_irq_install(i915);
 983         if (ret)
 984                 goto out_cleanup_modeset;
 985
 986         ret = i915_driver_modeset_probe(i915);
 987         if (ret < 0)
 988                 goto out_cleanup_irq;
 989
 990         i915_driver_register(i915);
 991
 992         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 993
 994         i915_welcome_messages(i915);
 995
 996         return 0;
 997
 998 out_cleanup_irq:
 999         intel_irq_uninstall(i915);
1000 out_cleanup_modeset:
1001         /* FIXME */
1002 out_cleanup_hw:
1003         i915_driver_hw_remove(i915);
1004         intel_memory_regions_driver_release(i915);
1005         i915_ggtt_driver_release(i915);
1006 out_cleanup_mmio:
1007         i915_driver_mmio_release(i915);
1008 out_runtime_pm_put:
1009         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1010         i915_driver_late_release(i915);
1011 out_pci_disable:
1012         pci_disable_device(pdev);
1013 out_fini:
1014         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
1015         i915_driver_destroy(i915);
1016         return ret;
1017 }
1018
1019 void i915_driver_remove(struct drm_i915_private *i915)
1020 {
1021         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1022
1023         i915_driver_unregister(i915);
1024
1025         /* Flush any external code that still may be under the RCU lock */
1026         synchronize_rcu();
1027
1028         i915_gem_suspend(i915);
1029
1030         drm_atomic_helper_shutdown(&i915->drm);
1031
1032         intel_gvt_driver_remove(i915);
1033
1034         i915_driver_modeset_remove(i915);
1035
1036         intel_irq_uninstall(i915);
1037
1038         i915_driver_modeset_remove_noirq(i915);
1039
1040         i915_reset_error_state(i915);
1041         i915_gem_driver_remove(i915);
1042
1043         intel_power_domains_driver_remove(i915);
1044
1045         i915_driver_hw_remove(i915);
1046
1047         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1048 }
1049
1050 static void i915_driver_release(struct drm_device *dev)
1051 {
1052         struct drm_i915_private *dev_priv = to_i915(dev);
1053         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1054
1055         disable_rpm_wakeref_asserts(rpm);
1056
1057         i915_gem_driver_release(dev_priv);
1058
1059         intel_memory_regions_driver_release(dev_priv);
1060         i915_ggtt_driver_release(dev_priv);
1061
1062         i915_driver_mmio_release(dev_priv);
1063
1064         enable_rpm_wakeref_asserts(rpm);
1065         intel_runtime_pm_driver_release(rpm);
1066
1067         i915_driver_late_release(dev_priv);
1068         i915_driver_destroy(dev_priv);
1069 }
1070
1071 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1072 {
1073         struct drm_i915_private *i915 = to_i915(dev);
1074         int ret;
1075
1076         ret = i915_gem_open(i915, file);
1077         if (ret)
1078                 return ret;
1079
1080         return 0;
1081 }
1082
1083 /**
1084  * i915_driver_lastclose - clean up after all DRM clients have exited
1085  * @dev: DRM device
1086  *
1087  * Take care of cleaning up after all DRM clients have exited.  In the
1088  * mode setting case, we want to restore the kernel's initial mode (just
1089  * in case the last client left us in a bad state).
1090  *
1091  * Additionally, in the non-mode setting case, we'll tear down the GTT
1092  * and DMA structures, since the kernel won't be using them, and clea
1093  * up any GEM state.
1094  */
1095 static void i915_driver_lastclose(struct drm_device *dev)
1096 {
1097         intel_fbdev_restore_mode(dev);
1098         vga_switcheroo_process_delayed_switch();
1099 }
1100
1101 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1102 {
1103         struct drm_i915_file_private *file_priv = file->driver_priv;
1104
1105         i915_gem_context_close(file);
1106         i915_gem_release(dev, file);
1107
1108         kfree_rcu(file_priv, rcu);
1109
1110         /* Catch up with all the deferred frees from "this" client */
1111         i915_gem_flush_free_objects(to_i915(dev));
1112 }
1113
1114 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1115 {
1116         struct drm_device *dev = &dev_priv->drm;
1117         struct intel_encoder *encoder;
1118
1119         drm_modeset_lock_all(dev);
1120         for_each_intel_encoder(dev, encoder)
1121                 if (encoder->suspend)
1122                         encoder->suspend(encoder);
1123         drm_modeset_unlock_all(dev);
1124 }
1125
1126 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1127 {
1128 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1129         if (acpi_target_system_state() < ACPI_STATE_S3)
1130                 return true;
1131 #endif
1132         return false;
1133 }
1134
1135 static int i915_drm_prepare(struct drm_device *dev)
1136 {
1137         struct drm_i915_private *i915 = to_i915(dev);
1138
1139         /*
1140          * NB intel_display_suspend() may issue new requests after we've
1141          * ostensibly marked the GPU as ready-to-sleep here. We need to
1142          * split out that work and pull it forward so that after point,
1143          * the GPU is not woken again.
1144          */
1145         i915_gem_suspend(i915);
1146
1147         return 0;
1148 }
1149
1150 static int i915_drm_suspend(struct drm_device *dev)
1151 {
1152         struct drm_i915_private *dev_priv = to_i915(dev);
1153         struct pci_dev *pdev = dev_priv->drm.pdev;
1154         pci_power_t opregion_target_state;
1155
1156         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1157
1158         /* We do a lot of poking in a lot of registers, make sure they work
1159          * properly. */
1160         intel_power_domains_disable(dev_priv);
1161
1162         drm_kms_helper_poll_disable(dev);
1163
1164         pci_save_state(pdev);
1165
1166         intel_display_suspend(dev);
1167
1168         intel_dp_mst_suspend(dev_priv);
1169
1170         intel_runtime_pm_disable_interrupts(dev_priv);
1171         intel_hpd_cancel_work(dev_priv);
1172
1173         intel_suspend_encoders(dev_priv);
1174
1175         intel_suspend_hw(dev_priv);
1176
1177         i915_ggtt_suspend(&dev_priv->ggtt);
1178
1179         i915_save_state(dev_priv);
1180
1181         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1182         intel_opregion_suspend(dev_priv, opregion_target_state);
1183
1184         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1185
1186         dev_priv->suspend_count++;
1187
1188         intel_csr_ucode_suspend(dev_priv);
1189
1190         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1191
1192         return 0;
1193 }
1194
1195 static enum i915_drm_suspend_mode
1196 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1197 {
1198         if (hibernate)
1199                 return I915_DRM_SUSPEND_HIBERNATE;
1200
1201         if (suspend_to_idle(dev_priv))
1202                 return I915_DRM_SUSPEND_IDLE;
1203
1204         return I915_DRM_SUSPEND_MEM;
1205 }
1206
1207 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1208 {
1209         struct drm_i915_private *dev_priv = to_i915(dev);
1210         struct pci_dev *pdev = dev_priv->drm.pdev;
1211         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1212         int ret;
1213
1214         disable_rpm_wakeref_asserts(rpm);
1215
1216         i915_gem_suspend_late(dev_priv);
1217
1218         intel_uncore_suspend(&dev_priv->uncore);
1219
1220         intel_power_domains_suspend(dev_priv,
1221                                     get_suspend_mode(dev_priv, hibernation));
1222
1223         intel_display_power_suspend_late(dev_priv);
1224
1225         ret = vlv_suspend_complete(dev_priv);
1226         if (ret) {
1227                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1228                 intel_power_domains_resume(dev_priv);
1229
1230                 goto out;
1231         }
1232
1233         pci_disable_device(pdev);
1234         /*
1235          * During hibernation on some platforms the BIOS may try to access
1236          * the device even though it's already in D3 and hang the machine. So
1237          * leave the device in D0 on those platforms and hope the BIOS will
1238          * power down the device properly. The issue was seen on multiple old
1239          * GENs with different BIOS vendors, so having an explicit blacklist
1240          * is inpractical; apply the workaround on everything pre GEN6. The
1241          * platforms where the issue was seen:
1242          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1243          * Fujitsu FSC S7110
1244          * Acer Aspire 1830T
1245          */
1246         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1247                 pci_set_power_state(pdev, PCI_D3hot);
1248
1249 out:
1250         enable_rpm_wakeref_asserts(rpm);
1251         if (!dev_priv->uncore.user_forcewake_count)
1252                 intel_runtime_pm_driver_release(rpm);
1253
1254         return ret;
1255 }
1256
1257 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1258 {
1259         int error;
1260
1261         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1262                              state.event != PM_EVENT_FREEZE))
1263                 return -EINVAL;
1264
1265         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1266                 return 0;
1267
1268         error = i915_drm_suspend(&i915->drm);
1269         if (error)
1270                 return error;
1271
1272         return i915_drm_suspend_late(&i915->drm, false);
1273 }
1274
1275 static int i915_drm_resume(struct drm_device *dev)
1276 {
1277         struct drm_i915_private *dev_priv = to_i915(dev);
1278         int ret;
1279
1280         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1281
1282         sanitize_gpu(dev_priv);
1283
1284         ret = i915_ggtt_enable_hw(dev_priv);
1285         if (ret)
1286                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1287
1288         i915_ggtt_resume(&dev_priv->ggtt);
1289
1290         intel_csr_ucode_resume(dev_priv);
1291
1292         i915_restore_state(dev_priv);
1293         intel_pps_unlock_regs_wa(dev_priv);
1294
1295         intel_init_pch_refclk(dev_priv);
1296
1297         /*
1298          * Interrupts have to be enabled before any batches are run. If not the
1299          * GPU will hang. i915_gem_init_hw() will initiate batches to
1300          * update/restore the context.
1301          *
1302          * drm_mode_config_reset() needs AUX interrupts.
1303          *
1304          * Modeset enabling in intel_modeset_init_hw() also needs working
1305          * interrupts.
1306          */
1307         intel_runtime_pm_enable_interrupts(dev_priv);
1308
1309         drm_mode_config_reset(dev);
1310
1311         i915_gem_resume(dev_priv);
1312
1313         intel_modeset_init_hw(dev_priv);
1314         intel_init_clock_gating(dev_priv);
1315
1316         spin_lock_irq(&dev_priv->irq_lock);
1317         if (dev_priv->display.hpd_irq_setup)
1318                 dev_priv->display.hpd_irq_setup(dev_priv);
1319         spin_unlock_irq(&dev_priv->irq_lock);
1320
1321         intel_dp_mst_resume(dev_priv);
1322
1323         intel_display_resume(dev);
1324
1325         drm_kms_helper_poll_enable(dev);
1326
1327         /*
1328          * ... but also need to make sure that hotplug processing
1329          * doesn't cause havoc. Like in the driver load code we don't
1330          * bother with the tiny race here where we might lose hotplug
1331          * notifications.
1332          * */
1333         intel_hpd_init(dev_priv);
1334
1335         intel_opregion_resume(dev_priv);
1336
1337         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1338
1339         intel_power_domains_enable(dev_priv);
1340
1341         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1342
1343         return 0;
1344 }
1345
1346 static int i915_drm_resume_early(struct drm_device *dev)
1347 {
1348         struct drm_i915_private *dev_priv = to_i915(dev);
1349         struct pci_dev *pdev = dev_priv->drm.pdev;
1350         int ret;
1351
1352         /*
1353          * We have a resume ordering issue with the snd-hda driver also
1354          * requiring our device to be power up. Due to the lack of a
1355          * parent/child relationship we currently solve this with an early
1356          * resume hook.
1357          *
1358          * FIXME: This should be solved with a special hdmi sink device or
1359          * similar so that power domains can be employed.
1360          */
1361
1362         /*
1363          * Note that we need to set the power state explicitly, since we
1364          * powered off the device during freeze and the PCI core won't power
1365          * it back up for us during thaw. Powering off the device during
1366          * freeze is not a hard requirement though, and during the
1367          * suspend/resume phases the PCI core makes sure we get here with the
1368          * device powered on. So in case we change our freeze logic and keep
1369          * the device powered we can also remove the following set power state
1370          * call.
1371          */
1372         ret = pci_set_power_state(pdev, PCI_D0);
1373         if (ret) {
1374                 drm_err(&dev_priv->drm,
1375                         "failed to set PCI D0 power state (%d)\n", ret);
1376                 return ret;
1377         }
1378
1379         /*
1380          * Note that pci_enable_device() first enables any parent bridge
1381          * device and only then sets the power state for this device. The
1382          * bridge enabling is a nop though, since bridge devices are resumed
1383          * first. The order of enabling power and enabling the device is
1384          * imposed by the PCI core as described above, so here we preserve the
1385          * same order for the freeze/thaw phases.
1386          *
1387          * TODO: eventually we should remove pci_disable_device() /
1388          * pci_enable_enable_device() from suspend/resume. Due to how they
1389          * depend on the device enable refcount we can't anyway depend on them
1390          * disabling/enabling the device.
1391          */
1392         if (pci_enable_device(pdev))
1393                 return -EIO;
1394
1395         pci_set_master(pdev);
1396
1397         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1398
1399         ret = vlv_resume_prepare(dev_priv, false);
1400         if (ret)
1401                 drm_err(&dev_priv->drm,
1402                         "Resume prepare failed: %d, continuing anyway\n", ret);
1403
1404         intel_uncore_resume_early(&dev_priv->uncore);
1405
1406         intel_gt_check_and_clear_faults(&dev_priv->gt);
1407
1408         intel_display_power_resume_early(dev_priv);
1409
1410         intel_power_domains_resume(dev_priv);
1411
1412         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1413
1414         return ret;
1415 }
1416
1417 int i915_resume_switcheroo(struct drm_i915_private *i915)
1418 {
1419         int ret;
1420
1421         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1422                 return 0;
1423
1424         ret = i915_drm_resume_early(&i915->drm);
1425         if (ret)
1426                 return ret;
1427
1428         return i915_drm_resume(&i915->drm);
1429 }
1430
1431 static int i915_pm_prepare(struct device *kdev)
1432 {
1433         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1434
1435         if (!i915) {
1436                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1437                 return -ENODEV;
1438         }
1439
1440         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1441                 return 0;
1442
1443         return i915_drm_prepare(&i915->drm);
1444 }
1445
1446 static int i915_pm_suspend(struct device *kdev)
1447 {
1448         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1449
1450         if (!i915) {
1451                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1452                 return -ENODEV;
1453         }
1454
1455         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1456                 return 0;
1457
1458         return i915_drm_suspend(&i915->drm);
1459 }
1460
1461 static int i915_pm_suspend_late(struct device *kdev)
1462 {
1463         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1464
1465         /*
1466          * We have a suspend ordering issue with the snd-hda driver also
1467          * requiring our device to be power up. Due to the lack of a
1468          * parent/child relationship we currently solve this with an late
1469          * suspend hook.
1470          *
1471          * FIXME: This should be solved with a special hdmi sink device or
1472          * similar so that power domains can be employed.
1473          */
1474         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1475                 return 0;
1476
1477         return i915_drm_suspend_late(&i915->drm, false);
1478 }
1479
1480 static int i915_pm_poweroff_late(struct device *kdev)
1481 {
1482         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1483
1484         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1485                 return 0;
1486
1487         return i915_drm_suspend_late(&i915->drm, true);
1488 }
1489
1490 static int i915_pm_resume_early(struct device *kdev)
1491 {
1492         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1493
1494         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1495                 return 0;
1496
1497         return i915_drm_resume_early(&i915->drm);
1498 }
1499
1500 static int i915_pm_resume(struct device *kdev)
1501 {
1502         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1503
1504         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1505                 return 0;
1506
1507         return i915_drm_resume(&i915->drm);
1508 }
1509
1510 /* freeze: before creating the hibernation_image */
1511 static int i915_pm_freeze(struct device *kdev)
1512 {
1513         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1514         int ret;
1515
1516         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1517                 ret = i915_drm_suspend(&i915->drm);
1518                 if (ret)
1519                         return ret;
1520         }
1521
1522         ret = i915_gem_freeze(i915);
1523         if (ret)
1524                 return ret;
1525
1526         return 0;
1527 }
1528
1529 static int i915_pm_freeze_late(struct device *kdev)
1530 {
1531         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1532         int ret;
1533
1534         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1535                 ret = i915_drm_suspend_late(&i915->drm, true);
1536                 if (ret)
1537                         return ret;
1538         }
1539
1540         ret = i915_gem_freeze_late(i915);
1541         if (ret)
1542                 return ret;
1543
1544         return 0;
1545 }
1546
1547 /* thaw: called after creating the hibernation image, but before turning off. */
1548 static int i915_pm_thaw_early(struct device *kdev)
1549 {
1550         return i915_pm_resume_early(kdev);
1551 }
1552
1553 static int i915_pm_thaw(struct device *kdev)
1554 {
1555         return i915_pm_resume(kdev);
1556 }
1557
1558 /* restore: called after loading the hibernation image. */
1559 static int i915_pm_restore_early(struct device *kdev)
1560 {
1561         return i915_pm_resume_early(kdev);
1562 }
1563
1564 static int i915_pm_restore(struct device *kdev)
1565 {
1566         return i915_pm_resume(kdev);
1567 }
1568
1569 static int intel_runtime_suspend(struct device *kdev)
1570 {
1571         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1572         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1573         int ret;
1574
1575         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1576                 return -ENODEV;
1577
1578         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1579
1580         disable_rpm_wakeref_asserts(rpm);
1581
1582         /*
1583          * We are safe here against re-faults, since the fault handler takes
1584          * an RPM reference.
1585          */
1586         i915_gem_runtime_suspend(dev_priv);
1587
1588         intel_gt_runtime_suspend(&dev_priv->gt);
1589
1590         intel_runtime_pm_disable_interrupts(dev_priv);
1591
1592         intel_uncore_suspend(&dev_priv->uncore);
1593
1594         intel_display_power_suspend(dev_priv);
1595
1596         ret = vlv_suspend_complete(dev_priv);
1597         if (ret) {
1598                 drm_err(&dev_priv->drm,
1599                         "Runtime suspend failed, disabling it (%d)\n", ret);
1600                 intel_uncore_runtime_resume(&dev_priv->uncore);
1601
1602                 intel_runtime_pm_enable_interrupts(dev_priv);
1603
1604                 intel_gt_runtime_resume(&dev_priv->gt);
1605
1606                 enable_rpm_wakeref_asserts(rpm);
1607
1608                 return ret;
1609         }
1610
1611         enable_rpm_wakeref_asserts(rpm);
1612         intel_runtime_pm_driver_release(rpm);
1613
1614         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1615                 drm_err(&dev_priv->drm,
1616                         "Unclaimed access detected prior to suspending\n");
1617
1618         rpm->suspended = true;
1619
1620         /*
1621          * FIXME: We really should find a document that references the arguments
1622          * used below!
1623          */
1624         if (IS_BROADWELL(dev_priv)) {
1625                 /*
1626                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1627                  * being detected, and the call we do at intel_runtime_resume()
1628                  * won't be able to restore them. Since PCI_D3hot matches the
1629                  * actual specification and appears to be working, use it.
1630                  */
1631                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1632         } else {
1633                 /*
1634                  * current versions of firmware which depend on this opregion
1635                  * notification have repurposed the D1 definition to mean
1636                  * "runtime suspended" vs. what you would normally expect (D3)
1637                  * to distinguish it from notifications that might be sent via
1638                  * the suspend path.
1639                  */
1640                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1641         }
1642
1643         assert_forcewakes_inactive(&dev_priv->uncore);
1644
1645         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1646                 intel_hpd_poll_init(dev_priv);
1647
1648         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1649         return 0;
1650 }
1651
1652 static int intel_runtime_resume(struct device *kdev)
1653 {
1654         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1655         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1656         int ret;
1657
1658         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1659                 return -ENODEV;
1660
1661         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1662
1663         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1664         disable_rpm_wakeref_asserts(rpm);
1665
1666         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1667         rpm->suspended = false;
1668         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1669                 drm_dbg(&dev_priv->drm,
1670                         "Unclaimed access during suspend, bios?\n");
1671
1672         intel_display_power_resume(dev_priv);
1673
1674         ret = vlv_resume_prepare(dev_priv, true);
1675
1676         intel_uncore_runtime_resume(&dev_priv->uncore);
1677
1678         intel_runtime_pm_enable_interrupts(dev_priv);
1679
1680         /*
1681          * No point of rolling back things in case of an error, as the best
1682          * we can do is to hope that things will still work (and disable RPM).
1683          */
1684         intel_gt_runtime_resume(&dev_priv->gt);
1685
1686         /*
1687          * On VLV/CHV display interrupts are part of the display
1688          * power well, so hpd is reinitialized from there. For
1689          * everyone else do it here.
1690          */
1691         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1692                 intel_hpd_init(dev_priv);
1693
1694         intel_enable_ipc(dev_priv);
1695
1696         enable_rpm_wakeref_asserts(rpm);
1697
1698         if (ret)
1699                 drm_err(&dev_priv->drm,
1700                         "Runtime resume failed, disabling it (%d)\n", ret);
1701         else
1702                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1703
1704         return ret;
1705 }
1706
1707 const struct dev_pm_ops i915_pm_ops = {
1708         /*
1709          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1710          * PMSG_RESUME]
1711          */
1712         .prepare = i915_pm_prepare,
1713         .suspend = i915_pm_suspend,
1714         .suspend_late = i915_pm_suspend_late,
1715         .resume_early = i915_pm_resume_early,
1716         .resume = i915_pm_resume,
1717
1718         /*
1719          * S4 event handlers
1720          * @freeze, @freeze_late    : called (1) before creating the
1721          *                            hibernation image [PMSG_FREEZE] and
1722          *                            (2) after rebooting, before restoring
1723          *                            the image [PMSG_QUIESCE]
1724          * @thaw, @thaw_early       : called (1) after creating the hibernation
1725          *                            image, before writing it [PMSG_THAW]
1726          *                            and (2) after failing to create or
1727          *                            restore the image [PMSG_RECOVER]
1728          * @poweroff, @poweroff_late: called after writing the hibernation
1729          *                            image, before rebooting [PMSG_HIBERNATE]
1730          * @restore, @restore_early : called after rebooting and restoring the
1731          *                            hibernation image [PMSG_RESTORE]
1732          */
1733         .freeze = i915_pm_freeze,
1734         .freeze_late = i915_pm_freeze_late,
1735         .thaw_early = i915_pm_thaw_early,
1736         .thaw = i915_pm_thaw,
1737         .poweroff = i915_pm_suspend,
1738         .poweroff_late = i915_pm_poweroff_late,
1739         .restore_early = i915_pm_restore_early,
1740         .restore = i915_pm_restore,
1741
1742         /* S0ix (via runtime suspend) event handlers */
1743         .runtime_suspend = intel_runtime_suspend,
1744         .runtime_resume = intel_runtime_resume,
1745 };
1746
1747 static const struct file_operations i915_driver_fops = {
1748         .owner = THIS_MODULE,
1749         .open = drm_open,
1750         .release = drm_release_noglobal,
1751         .unlocked_ioctl = drm_ioctl,
1752         .mmap = i915_gem_mmap,
1753         .poll = drm_poll,
1754         .read = drm_read,
1755         .compat_ioctl = i915_ioc32_compat_ioctl,
1756         .llseek = noop_llseek,
1757 };
1758
1759 static int
1760 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1761                           struct drm_file *file)
1762 {
1763         return -ENODEV;
1764 }
1765
1766 static const struct drm_ioctl_desc i915_ioctls[] = {
1767         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1768         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1769         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1770         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1771         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1772         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1773         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1774         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1775         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1776         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1777         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1778         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1779         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1780         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1781         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1782         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1783         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1784         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1785         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
1786         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1787         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1788         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1789         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1790         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1791         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1792         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1793         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1794         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1795         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1796         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1797         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1798         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1799         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1800         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1801         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1802         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1803         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1804         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1805         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1806         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1807         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1808         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1809         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1810         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1811         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1812         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1813         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1814         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1815         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1816         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1817         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1818         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1819         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1820         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1821         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1822         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1823         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1824         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1825 };
1826
1827 static struct drm_driver driver = {
1828         /* Don't use MTRRs here; the Xserver or userspace app should
1829          * deal with them for Intel hardware.
1830          */
1831         .driver_features =
1832             DRIVER_GEM |
1833             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
1834         .release = i915_driver_release,
1835         .open = i915_driver_open,
1836         .lastclose = i915_driver_lastclose,
1837         .postclose = i915_driver_postclose,
1838
1839         .gem_close_object = i915_gem_close_object,
1840         .gem_free_object_unlocked = i915_gem_free_object,
1841
1842         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1843         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1844         .gem_prime_export = i915_gem_prime_export,
1845         .gem_prime_import = i915_gem_prime_import,
1846
1847         .dumb_create = i915_gem_dumb_create,
1848         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1849
1850         .ioctls = i915_ioctls,
1851         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1852         .fops = &i915_driver_fops,
1853         .name = DRIVER_NAME,
1854         .desc = DRIVER_DESC,
1855         .date = DRIVER_DATE,
1856         .major = DRIVER_MAJOR,
1857         .minor = DRIVER_MINOR,
1858         .patchlevel = DRIVER_PATCHLEVEL,
1859 };