drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915_modparams.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915_modparams.inject_load_failure &&
 110                i915_load_fail_count == i915_modparams.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 139                         dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 140                 else
 141                         dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 142                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 143         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 144                 ret = PCH_SPT;
 145                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 146         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 147                 ret = PCH_CNP;
 148                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 149         }
 150
 151         return ret;
 152 }
 153
 154 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 155 {
 156         struct pci_dev *pch = NULL;
 157
 158         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 159          * (which really amounts to a PCH but no South Display).
 160          */
 161         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 162                 dev_priv->pch_type = PCH_NOP;
 163                 return;
 164         }
 165
 166         /*
 167          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 168          * make graphics device passthrough work easy for VMM, that only
 169          * need to expose ISA bridge to let driver know the real hardware
 170          * underneath. This is a requirement from virtualization team.
 171          *
 172          * In some virtualized environments (e.g. XEN), there is irrelevant
 173          * ISA bridge in the system. To work reliably, we should scan trhough
 174          * all the ISA bridge devices and check for the first match, instead
 175          * of only checking the first one.
 176          */
 177         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 178                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 179                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 180
 181                         dev_priv->pch_id = id;
 182
 183                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 184                                 dev_priv->pch_type = PCH_IBX;
 185                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 186                                 WARN_ON(!IS_GEN5(dev_priv));
 187                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_CPT;
 189                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 190                                 WARN_ON(!IS_GEN6(dev_priv) &&
 191                                         !IS_IVYBRIDGE(dev_priv));
 192                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 193                                 /* PantherPoint is CPT compatible */
 194                                 dev_priv->pch_type = PCH_CPT;
 195                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 196                                 WARN_ON(!IS_GEN6(dev_priv) &&
 197                                         !IS_IVYBRIDGE(dev_priv));
 198                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 199                                 dev_priv->pch_type = PCH_LPT;
 200                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 201                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 202                                         !IS_BROADWELL(dev_priv));
 203                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 204                                         IS_BDW_ULT(dev_priv));
 205                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 206                                 dev_priv->pch_type = PCH_LPT;
 207                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 208                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 209                                         !IS_BROADWELL(dev_priv));
 210                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 211                                         !IS_BDW_ULT(dev_priv));
 212                         } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
 213                                 /* WildcatPoint is LPT compatible */
 214                                 dev_priv->pch_type = PCH_LPT;
 215                                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 216                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 217                                         !IS_BROADWELL(dev_priv));
 218                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 219                                         IS_BDW_ULT(dev_priv));
 220                         } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
 221                                 /* WildcatPoint is LPT compatible */
 222                                 dev_priv->pch_type = PCH_LPT;
 223                                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 224                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 225                                         !IS_BROADWELL(dev_priv));
 226                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 227                                         !IS_BDW_ULT(dev_priv));
 228                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 229                                 dev_priv->pch_type = PCH_SPT;
 230                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 231                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 232                                         !IS_KABYLAKE(dev_priv));
 233                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 234                                 dev_priv->pch_type = PCH_SPT;
 235                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 236                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 237                                         !IS_KABYLAKE(dev_priv));
 238                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 239                                 dev_priv->pch_type = PCH_KBP;
 240                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 241                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 242                                         !IS_KABYLAKE(dev_priv) &&
 243                                         !IS_COFFEELAKE(dev_priv));
 244                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 245                                 dev_priv->pch_type = PCH_CNP;
 246                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 247                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 248                                         !IS_COFFEELAKE(dev_priv));
 249                         } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 250                                 dev_priv->pch_type = PCH_CNP;
 251                                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 252                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 253                                         !IS_COFFEELAKE(dev_priv));
 254                         } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 255                                    id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 256                                    (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 257                                     pch->subsystem_vendor ==
 258                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 259                                     pch->subsystem_device ==
 260                                             PCI_SUBDEVICE_ID_QEMU)) {
 261                                 dev_priv->pch_type =
 262                                         intel_virt_detect_pch(dev_priv);
 263                         } else
 264                                 continue;
 265
 266                         break;
 267                 }
 268         }
 269         if (!pch)
 270                 DRM_DEBUG_KMS("No PCH found.\n");
 271
 272         pci_dev_put(pch);
 273 }
 274
 275 static int i915_getparam(struct drm_device *dev, void *data,
 276                          struct drm_file *file_priv)
 277 {
 278         struct drm_i915_private *dev_priv = to_i915(dev);
 279         struct pci_dev *pdev = dev_priv->drm.pdev;
 280         drm_i915_getparam_t *param = data;
 281         int value;
 282
 283         switch (param->param) {
 284         case I915_PARAM_IRQ_ACTIVE:
 285         case I915_PARAM_ALLOW_BATCHBUFFER:
 286         case I915_PARAM_LAST_DISPATCH:
 287         case I915_PARAM_HAS_EXEC_CONSTANTS:
 288                 /* Reject all old ums/dri params. */
 289                 return -ENODEV;
 290         case I915_PARAM_CHIPSET_ID:
 291                 value = pdev->device;
 292                 break;
 293         case I915_PARAM_REVISION:
 294                 value = pdev->revision;
 295                 break;
 296         case I915_PARAM_NUM_FENCES_AVAIL:
 297                 value = dev_priv->num_fence_regs;
 298                 break;
 299         case I915_PARAM_HAS_OVERLAY:
 300                 value = dev_priv->overlay ? 1 : 0;
 301                 break;
 302         case I915_PARAM_HAS_BSD:
 303                 value = !!dev_priv->engine[VCS];
 304                 break;
 305         case I915_PARAM_HAS_BLT:
 306                 value = !!dev_priv->engine[BCS];
 307                 break;
 308         case I915_PARAM_HAS_VEBOX:
 309                 value = !!dev_priv->engine[VECS];
 310                 break;
 311         case I915_PARAM_HAS_BSD2:
 312                 value = !!dev_priv->engine[VCS2];
 313                 break;
 314         case I915_PARAM_HAS_LLC:
 315                 value = HAS_LLC(dev_priv);
 316                 break;
 317         case I915_PARAM_HAS_WT:
 318                 value = HAS_WT(dev_priv);
 319                 break;
 320         case I915_PARAM_HAS_ALIASING_PPGTT:
 321                 value = USES_PPGTT(dev_priv);
 322                 break;
 323         case I915_PARAM_HAS_SEMAPHORES:
 324                 value = i915_modparams.semaphores;
 325                 break;
 326         case I915_PARAM_HAS_SECURE_BATCHES:
 327                 value = capable(CAP_SYS_ADMIN);
 328                 break;
 329         case I915_PARAM_CMD_PARSER_VERSION:
 330                 value = i915_cmd_parser_get_version(dev_priv);
 331                 break;
 332         case I915_PARAM_SUBSLICE_TOTAL:
 333                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 334                 if (!value)
 335                         return -ENODEV;
 336                 break;
 337         case I915_PARAM_EU_TOTAL:
 338                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 339                 if (!value)
 340                         return -ENODEV;
 341                 break;
 342         case I915_PARAM_HAS_GPU_RESET:
 343                 value = i915_modparams.enable_hangcheck &&
 344                         intel_has_gpu_reset(dev_priv);
 345                 if (value && intel_has_reset_engine(dev_priv))
 346                         value = 2;
 347                 break;
 348         case I915_PARAM_HAS_RESOURCE_STREAMER:
 349                 value = HAS_RESOURCE_STREAMER(dev_priv);
 350                 break;
 351         case I915_PARAM_HAS_POOLED_EU:
 352                 value = HAS_POOLED_EU(dev_priv);
 353                 break;
 354         case I915_PARAM_MIN_EU_IN_POOL:
 355                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 356                 break;
 357         case I915_PARAM_HUC_STATUS:
 358                 intel_runtime_pm_get(dev_priv);
 359                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 360                 intel_runtime_pm_put(dev_priv);
 361                 break;
 362         case I915_PARAM_MMAP_GTT_VERSION:
 363                 /* Though we've started our numbering from 1, and so class all
 364                  * earlier versions as 0, in effect their value is undefined as
 365                  * the ioctl will report EINVAL for the unknown param!
 366                  */
 367                 value = i915_gem_mmap_gtt_version();
 368                 break;
 369         case I915_PARAM_HAS_SCHEDULER:
 370                 value = 0;
 371                 if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
 372                         value |= I915_SCHEDULER_CAP_ENABLED;
 373                         value |= I915_SCHEDULER_CAP_PRIORITY;
 374
 375                         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 376                             i915_modparams.enable_execlists)
 377                                 value |= I915_SCHEDULER_CAP_PREEMPTION;
 378                 }
 379                 break;
 380
 381         case I915_PARAM_MMAP_VERSION:
 382                 /* Remember to bump this if the version changes! */
 383         case I915_PARAM_HAS_GEM:
 384         case I915_PARAM_HAS_PAGEFLIPPING:
 385         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 386         case I915_PARAM_HAS_RELAXED_FENCING:
 387         case I915_PARAM_HAS_COHERENT_RINGS:
 388         case I915_PARAM_HAS_RELAXED_DELTA:
 389         case I915_PARAM_HAS_GEN7_SOL_RESET:
 390         case I915_PARAM_HAS_WAIT_TIMEOUT:
 391         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 392         case I915_PARAM_HAS_PINNED_BATCHES:
 393         case I915_PARAM_HAS_EXEC_NO_RELOC:
 394         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 395         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 396         case I915_PARAM_HAS_EXEC_SOFTPIN:
 397         case I915_PARAM_HAS_EXEC_ASYNC:
 398         case I915_PARAM_HAS_EXEC_FENCE:
 399         case I915_PARAM_HAS_EXEC_CAPTURE:
 400         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 401         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 402                 /* For the time being all of these are always true;
 403                  * if some supported hardware does not have one of these
 404                  * features this value needs to be provided from
 405                  * INTEL_INFO(), a feature macro, or similar.
 406                  */
 407                 value = 1;
 408                 break;
 409         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 410                 value = intel_engines_has_context_isolation(dev_priv);
 411                 break;
 412         case I915_PARAM_SLICE_MASK:
 413                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 414                 if (!value)
 415                         return -ENODEV;
 416                 break;
 417         case I915_PARAM_SUBSLICE_MASK:
 418                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 419                 if (!value)
 420                         return -ENODEV;
 421                 break;
 422         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 423                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 424                 break;
 425         default:
 426                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 427                 return -EINVAL;
 428         }
 429
 430         if (put_user(value, param->value))
 431                 return -EFAULT;
 432
 433         return 0;
 434 }
 435
 436 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 437 {
 438         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 439         if (!dev_priv->bridge_dev) {
 440                 DRM_ERROR("bridge device not found\n");
 441                 return -1;
 442         }
 443         return 0;
 444 }
 445
 446 /* Allocate space for the MCH regs if needed, return nonzero on error */
 447 static int
 448 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 449 {
 450         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 451         u32 temp_lo, temp_hi = 0;
 452         u64 mchbar_addr;
 453         int ret;
 454
 455         if (INTEL_GEN(dev_priv) >= 4)
 456                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 457         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 458         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 459
 460         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 461 #ifdef CONFIG_PNP
 462         if (mchbar_addr &&
 463             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 464                 return 0;
 465 #endif
 466
 467         /* Get some space for it */
 468         dev_priv->mch_res.name = "i915 MCHBAR";
 469         dev_priv->mch_res.flags = IORESOURCE_MEM;
 470         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 471                                      &dev_priv->mch_res,
 472                                      MCHBAR_SIZE, MCHBAR_SIZE,
 473                                      PCIBIOS_MIN_MEM,
 474                                      0, pcibios_align_resource,
 475                                      dev_priv->bridge_dev);
 476         if (ret) {
 477                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 478                 dev_priv->mch_res.start = 0;
 479                 return ret;
 480         }
 481
 482         if (INTEL_GEN(dev_priv) >= 4)
 483                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 484                                        upper_32_bits(dev_priv->mch_res.start));
 485
 486         pci_write_config_dword(dev_priv->bridge_dev, reg,
 487                                lower_32_bits(dev_priv->mch_res.start));
 488         return 0;
 489 }
 490
 491 /* Setup MCHBAR if possible, return true if we should disable it again */
 492 static void
 493 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 494 {
 495         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 496         u32 temp;
 497         bool enabled;
 498
 499         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 500                 return;
 501
 502         dev_priv->mchbar_need_disable = false;
 503
 504         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 505                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 506                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 507         } else {
 508                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 509                 enabled = temp & 1;
 510         }
 511
 512         /* If it's already enabled, don't have to do anything */
 513         if (enabled)
 514                 return;
 515
 516         if (intel_alloc_mchbar_resource(dev_priv))
 517                 return;
 518
 519         dev_priv->mchbar_need_disable = true;
 520
 521         /* Space is allocated or reserved, so enable it. */
 522         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 523                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 524                                        temp | DEVEN_MCHBAR_EN);
 525         } else {
 526                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 527                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 528         }
 529 }
 530
 531 static void
 532 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 533 {
 534         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 535
 536         if (dev_priv->mchbar_need_disable) {
 537                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 538                         u32 deven_val;
 539
 540                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 541                                               &deven_val);
 542                         deven_val &= ~DEVEN_MCHBAR_EN;
 543                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 544                                                deven_val);
 545                 } else {
 546                         u32 mchbar_val;
 547
 548                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 549                                               &mchbar_val);
 550                         mchbar_val &= ~1;
 551                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 552                                                mchbar_val);
 553                 }
 554         }
 555
 556         if (dev_priv->mch_res.start)
 557                 release_resource(&dev_priv->mch_res);
 558 }
 559
 560 /* true = enable decode, false = disable decoder */
 561 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 562 {
 563         struct drm_i915_private *dev_priv = cookie;
 564
 565         intel_modeset_vga_set_state(dev_priv, state);
 566         if (state)
 567                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 568                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 569         else
 570                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 571 }
 572
 573 static int i915_resume_switcheroo(struct drm_device *dev);
 574 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 575
 576 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 577 {
 578         struct drm_device *dev = pci_get_drvdata(pdev);
 579         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 580
 581         if (state == VGA_SWITCHEROO_ON) {
 582                 pr_info("switched on\n");
 583                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 584                 /* i915 resume handler doesn't set to D0 */
 585                 pci_set_power_state(pdev, PCI_D0);
 586                 i915_resume_switcheroo(dev);
 587                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 588         } else {
 589                 pr_info("switched off\n");
 590                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 591                 i915_suspend_switcheroo(dev, pmm);
 592                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 593         }
 594 }
 595
 596 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 597 {
 598         struct drm_device *dev = pci_get_drvdata(pdev);
 599
 600         /*
 601          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 602          * locking inversion with the driver load path. And the access here is
 603          * completely racy anyway. So don't bother with locking for now.
 604          */
 605         return dev->open_count == 0;
 606 }
 607
 608 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 609         .set_gpu_state = i915_switcheroo_set_state,
 610         .reprobe = NULL,
 611         .can_switch = i915_switcheroo_can_switch,
 612 };
 613
 614 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 615 {
 616         /* Flush any outstanding unpin_work. */
 617         i915_gem_drain_workqueue(dev_priv);
 618
 619         mutex_lock(&dev_priv->drm.struct_mutex);
 620         intel_uc_fini_hw(dev_priv);
 621         i915_gem_cleanup_engines(dev_priv);
 622         i915_gem_contexts_fini(dev_priv);
 623         mutex_unlock(&dev_priv->drm.struct_mutex);
 624
 625         i915_gem_cleanup_userptr(dev_priv);
 626
 627         i915_gem_drain_freed_objects(dev_priv);
 628
 629         WARN_ON(!list_empty(&dev_priv->contexts.list));
 630 }
 631
 632 static int i915_load_modeset_init(struct drm_device *dev)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(dev);
 635         struct pci_dev *pdev = dev_priv->drm.pdev;
 636         int ret;
 637
 638         if (i915_inject_load_failure())
 639                 return -ENODEV;
 640
 641         intel_bios_init(dev_priv);
 642
 643         /* If we have > 1 VGA cards, then we need to arbitrate access
 644          * to the common VGA resources.
 645          *
 646          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 647          * then we do not take part in VGA arbitration and the
 648          * vga_client_register() fails with -ENODEV.
 649          */
 650         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 651         if (ret && ret != -ENODEV)
 652                 goto out;
 653
 654         intel_register_dsm_handler();
 655
 656         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 657         if (ret)
 658                 goto cleanup_vga_client;
 659
 660         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 661         intel_update_rawclk(dev_priv);
 662
 663         intel_power_domains_init_hw(dev_priv, false);
 664
 665         intel_csr_ucode_init(dev_priv);
 666
 667         ret = intel_irq_install(dev_priv);
 668         if (ret)
 669                 goto cleanup_csr;
 670
 671         intel_setup_gmbus(dev_priv);
 672
 673         /* Important: The output setup functions called by modeset_init need
 674          * working irqs for e.g. gmbus and dp aux transfers. */
 675         ret = intel_modeset_init(dev);
 676         if (ret)
 677                 goto cleanup_irq;
 678
 679         intel_uc_init_fw(dev_priv);
 680
 681         ret = i915_gem_init(dev_priv);
 682         if (ret)
 683                 goto cleanup_uc;
 684
 685         intel_setup_overlay(dev_priv);
 686
 687         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 688                 return 0;
 689
 690         ret = intel_fbdev_init(dev);
 691         if (ret)
 692                 goto cleanup_gem;
 693
 694         /* Only enable hotplug handling once the fbdev is fully set up. */
 695         intel_hpd_init(dev_priv);
 696
 697         drm_kms_helper_poll_init(dev);
 698
 699         return 0;
 700
 701 cleanup_gem:
 702         if (i915_gem_suspend(dev_priv))
 703                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 704         i915_gem_fini(dev_priv);
 705 cleanup_uc:
 706         intel_uc_fini_fw(dev_priv);
 707 cleanup_irq:
 708         drm_irq_uninstall(dev);
 709         intel_teardown_gmbus(dev_priv);
 710 cleanup_csr:
 711         intel_csr_ucode_fini(dev_priv);
 712         intel_power_domains_fini(dev_priv);
 713         vga_switcheroo_unregister_client(pdev);
 714 cleanup_vga_client:
 715         vga_client_register(pdev, NULL, NULL, NULL);
 716 out:
 717         return ret;
 718 }
 719
 720 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 721 {
 722         struct apertures_struct *ap;
 723         struct pci_dev *pdev = dev_priv->drm.pdev;
 724         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 725         bool primary;
 726         int ret;
 727
 728         ap = alloc_apertures(1);
 729         if (!ap)
 730                 return -ENOMEM;
 731
 732         ap->ranges[0].base = ggtt->mappable_base;
 733         ap->ranges[0].size = ggtt->mappable_end;
 734
 735         primary =
 736                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 737
 738         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 739
 740         kfree(ap);
 741
 742         return ret;
 743 }
 744
 745 #if !defined(CONFIG_VGA_CONSOLE)
 746 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 747 {
 748         return 0;
 749 }
 750 #elif !defined(CONFIG_DUMMY_CONSOLE)
 751 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 752 {
 753         return -ENODEV;
 754 }
 755 #else
 756 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 757 {
 758         int ret = 0;
 759
 760         DRM_INFO("Replacing VGA console driver\n");
 761
 762         console_lock();
 763         if (con_is_bound(&vga_con))
 764                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 765         if (ret == 0) {
 766                 ret = do_unregister_con_driver(&vga_con);
 767
 768                 /* Ignore "already unregistered". */
 769                 if (ret == -ENODEV)
 770                         ret = 0;
 771         }
 772         console_unlock();
 773
 774         return ret;
 775 }
 776 #endif
 777
 778 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 779 {
 780         /*
 781          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 782          * CHV x1 PHY (DP/HDMI D)
 783          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 784          */
 785         if (IS_CHERRYVIEW(dev_priv)) {
 786                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 787                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 788         } else if (IS_VALLEYVIEW(dev_priv)) {
 789                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 790         }
 791 }
 792
 793 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 794 {
 795         /*
 796          * The i915 workqueue is primarily used for batched retirement of
 797          * requests (and thus managing bo) once the task has been completed
 798          * by the GPU. i915_gem_retire_requests() is called directly when we
 799          * need high-priority retirement, such as waiting for an explicit
 800          * bo.
 801          *
 802          * It is also used for periodic low-priority events, such as
 803          * idle-timers and recording error state.
 804          *
 805          * All tasks on the workqueue are expected to acquire the dev mutex
 806          * so there is no point in running more than one instance of the
 807          * workqueue at any time.  Use an ordered one.
 808          */
 809         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 810         if (dev_priv->wq == NULL)
 811                 goto out_err;
 812
 813         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 814         if (dev_priv->hotplug.dp_wq == NULL)
 815                 goto out_free_wq;
 816
 817         return 0;
 818
 819 out_free_wq:
 820         destroy_workqueue(dev_priv->wq);
 821 out_err:
 822         DRM_ERROR("Failed to allocate workqueues.\n");
 823
 824         return -ENOMEM;
 825 }
 826
 827 static void i915_engines_cleanup(struct drm_i915_private *i915)
 828 {
 829         struct intel_engine_cs *engine;
 830         enum intel_engine_id id;
 831
 832         for_each_engine(engine, i915, id)
 833                 kfree(engine);
 834 }
 835
 836 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 837 {
 838         destroy_workqueue(dev_priv->hotplug.dp_wq);
 839         destroy_workqueue(dev_priv->wq);
 840 }
 841
 842 /*
 843  * We don't keep the workarounds for pre-production hardware, so we expect our
 844  * driver to fail on these machines in one way or another. A little warning on
 845  * dmesg may help both the user and the bug triagers.
 846  *
 847  * Our policy for removing pre-production workarounds is to keep the
 848  * current gen workarounds as a guide to the bring-up of the next gen
 849  * (workarounds have a habit of persisting!). Anything older than that
 850  * should be removed along with the complications they introduce.
 851  */
 852 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 853 {
 854         bool pre = false;
 855
 856         pre |= IS_HSW_EARLY_SDV(dev_priv);
 857         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 858         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 859
 860         if (pre) {
 861                 DRM_ERROR("This is a pre-production stepping. "
 862                           "It may not be fully functional.\n");
 863                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 864         }
 865 }
 866
 867 /**
 868  * i915_driver_init_early - setup state not requiring device access
 869  * @dev_priv: device private
 870  *
 871  * Initialize everything that is a "SW-only" state, that is state not
 872  * requiring accessing the device or exposing the driver via kernel internal
 873  * or userspace interfaces. Example steps belonging here: lock initialization,
 874  * system memory allocation, setting up device specific attributes and
 875  * function hooks not requiring accessing the device.
 876  */
 877 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 878                                   const struct pci_device_id *ent)
 879 {
 880         const struct intel_device_info *match_info =
 881                 (struct intel_device_info *)ent->driver_data;
 882         struct intel_device_info *device_info;
 883         int ret = 0;
 884
 885         if (i915_inject_load_failure())
 886                 return -ENODEV;
 887
 888         /* Setup the write-once "constant" device info */
 889         device_info = mkwrite_device_info(dev_priv);
 890         memcpy(device_info, match_info, sizeof(*device_info));
 891         device_info->device_id = dev_priv->drm.pdev->device;
 892
 893         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 894                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 895         device_info->platform_mask = BIT(device_info->platform);
 896
 897         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 898         device_info->gen_mask = BIT(device_info->gen - 1);
 899
 900         spin_lock_init(&dev_priv->irq_lock);
 901         spin_lock_init(&dev_priv->gpu_error.lock);
 902         mutex_init(&dev_priv->backlight_lock);
 903         spin_lock_init(&dev_priv->uncore.lock);
 904
 905         mutex_init(&dev_priv->sb_lock);
 906         mutex_init(&dev_priv->modeset_restore_lock);
 907         mutex_init(&dev_priv->av_mutex);
 908         mutex_init(&dev_priv->wm.wm_mutex);
 909         mutex_init(&dev_priv->pps_mutex);
 910
 911         intel_uc_init_early(dev_priv);
 912         i915_memcpy_init_early(dev_priv);
 913
 914         ret = i915_workqueues_init(dev_priv);
 915         if (ret < 0)
 916                 goto err_engines;
 917
 918         /* This must be called before any calls to HAS_PCH_* */
 919         intel_detect_pch(dev_priv);
 920
 921         intel_pm_setup(dev_priv);
 922         intel_init_dpio(dev_priv);
 923         intel_power_domains_init(dev_priv);
 924         intel_irq_init(dev_priv);
 925         intel_hangcheck_init(dev_priv);
 926         intel_init_display_hooks(dev_priv);
 927         intel_init_clock_gating_hooks(dev_priv);
 928         intel_init_audio_hooks(dev_priv);
 929         ret = i915_gem_load_init(dev_priv);
 930         if (ret < 0)
 931                 goto err_irq;
 932
 933         intel_display_crc_init(dev_priv);
 934
 935         intel_device_info_dump(dev_priv);
 936
 937         intel_detect_preproduction_hw(dev_priv);
 938
 939         i915_perf_init(dev_priv);
 940
 941         return 0;
 942
 943 err_irq:
 944         intel_irq_fini(dev_priv);
 945         i915_workqueues_cleanup(dev_priv);
 946 err_engines:
 947         i915_engines_cleanup(dev_priv);
 948         return ret;
 949 }
 950
 951 /**
 952  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 953  * @dev_priv: device private
 954  */
 955 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 956 {
 957         i915_perf_fini(dev_priv);
 958         i915_gem_load_cleanup(dev_priv);
 959         intel_irq_fini(dev_priv);
 960         i915_workqueues_cleanup(dev_priv);
 961         i915_engines_cleanup(dev_priv);
 962 }
 963
 964 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 965 {
 966         struct pci_dev *pdev = dev_priv->drm.pdev;
 967         int mmio_bar;
 968         int mmio_size;
 969
 970         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 971         /*
 972          * Before gen4, the registers and the GTT are behind different BARs.
 973          * However, from gen4 onwards, the registers and the GTT are shared
 974          * in the same BAR, so we want to restrict this ioremap from
 975          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 976          * the register BAR remains the same size for all the earlier
 977          * generations up to Ironlake.
 978          */
 979         if (INTEL_GEN(dev_priv) < 5)
 980                 mmio_size = 512 * 1024;
 981         else
 982                 mmio_size = 2 * 1024 * 1024;
 983         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 984         if (dev_priv->regs == NULL) {
 985                 DRM_ERROR("failed to map registers\n");
 986
 987                 return -EIO;
 988         }
 989
 990         /* Try to make sure MCHBAR is enabled before poking at it */
 991         intel_setup_mchbar(dev_priv);
 992
 993         return 0;
 994 }
 995
 996 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 997 {
 998         struct pci_dev *pdev = dev_priv->drm.pdev;
 999
1000         intel_teardown_mchbar(dev_priv);
1001         pci_iounmap(pdev, dev_priv->regs);
1002 }
1003
1004 /**
1005  * i915_driver_init_mmio - setup device MMIO
1006  * @dev_priv: device private
1007  *
1008  * Setup minimal device state necessary for MMIO accesses later in the
1009  * initialization sequence. The setup here should avoid any other device-wide
1010  * side effects or exposing the driver via kernel internal or user space
1011  * interfaces.
1012  */
1013 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1014 {
1015         int ret;
1016
1017         if (i915_inject_load_failure())
1018                 return -ENODEV;
1019
1020         if (i915_get_bridge_dev(dev_priv))
1021                 return -EIO;
1022
1023         ret = i915_mmio_setup(dev_priv);
1024         if (ret < 0)
1025                 goto err_bridge;
1026
1027         intel_uncore_init(dev_priv);
1028
1029         intel_uc_init_mmio(dev_priv);
1030
1031         ret = intel_engines_init_mmio(dev_priv);
1032         if (ret)
1033                 goto err_uncore;
1034
1035         i915_gem_init_mmio(dev_priv);
1036
1037         return 0;
1038
1039 err_uncore:
1040         intel_uncore_fini(dev_priv);
1041 err_bridge:
1042         pci_dev_put(dev_priv->bridge_dev);
1043
1044         return ret;
1045 }
1046
1047 /**
1048  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1049  * @dev_priv: device private
1050  */
1051 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1052 {
1053         intel_uncore_fini(dev_priv);
1054         i915_mmio_cleanup(dev_priv);
1055         pci_dev_put(dev_priv->bridge_dev);
1056 }
1057
1058 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1059 {
1060         i915_modparams.enable_execlists =
1061                 intel_sanitize_enable_execlists(dev_priv,
1062                                                 i915_modparams.enable_execlists);
1063
1064         /*
1065          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1066          * user's requested state against the hardware/driver capabilities.  We
1067          * do this now so that we can print out any log messages once rather
1068          * than every time we check intel_enable_ppgtt().
1069          */
1070         i915_modparams.enable_ppgtt =
1071                 intel_sanitize_enable_ppgtt(dev_priv,
1072                                             i915_modparams.enable_ppgtt);
1073         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1074
1075         i915_modparams.semaphores =
1076                 intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
1077         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
1078                          yesno(i915_modparams.semaphores));
1079
1080         intel_uc_sanitize_options(dev_priv);
1081
1082         intel_gvt_sanitize_options(dev_priv);
1083 }
1084
1085 /**
1086  * i915_driver_init_hw - setup state requiring device access
1087  * @dev_priv: device private
1088  *
1089  * Setup state that requires accessing the device, but doesn't require
1090  * exposing the driver via kernel internal or userspace interfaces.
1091  */
1092 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1093 {
1094         struct pci_dev *pdev = dev_priv->drm.pdev;
1095         int ret;
1096
1097         if (i915_inject_load_failure())
1098                 return -ENODEV;
1099
1100         intel_device_info_runtime_init(dev_priv);
1101
1102         intel_sanitize_options(dev_priv);
1103
1104         ret = i915_ggtt_probe_hw(dev_priv);
1105         if (ret)
1106                 return ret;
1107
1108         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1109          * otherwise the vga fbdev driver falls over. */
1110         ret = i915_kick_out_firmware_fb(dev_priv);
1111         if (ret) {
1112                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1113                 goto out_ggtt;
1114         }
1115
1116         ret = i915_kick_out_vgacon(dev_priv);
1117         if (ret) {
1118                 DRM_ERROR("failed to remove conflicting VGA console\n");
1119                 goto out_ggtt;
1120         }
1121
1122         ret = i915_ggtt_init_hw(dev_priv);
1123         if (ret)
1124                 return ret;
1125
1126         ret = i915_ggtt_enable_hw(dev_priv);
1127         if (ret) {
1128                 DRM_ERROR("failed to enable GGTT\n");
1129                 goto out_ggtt;
1130         }
1131
1132         pci_set_master(pdev);
1133
1134         /* overlay on gen2 is broken and can't address above 1G */
1135         if (IS_GEN2(dev_priv)) {
1136                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1137                 if (ret) {
1138                         DRM_ERROR("failed to set DMA mask\n");
1139
1140                         goto out_ggtt;
1141                 }
1142         }
1143
1144         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1145          * using 32bit addressing, overwriting memory if HWS is located
1146          * above 4GB.
1147          *
1148          * The documentation also mentions an issue with undefined
1149          * behaviour if any general state is accessed within a page above 4GB,
1150          * which also needs to be handled carefully.
1151          */
1152         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1153                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1154
1155                 if (ret) {
1156                         DRM_ERROR("failed to set DMA mask\n");
1157
1158                         goto out_ggtt;
1159                 }
1160         }
1161
1162         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1163                            PM_QOS_DEFAULT_VALUE);
1164
1165         intel_uncore_sanitize(dev_priv);
1166
1167         intel_opregion_setup(dev_priv);
1168
1169         i915_gem_load_init_fences(dev_priv);
1170
1171         /* On the 945G/GM, the chipset reports the MSI capability on the
1172          * integrated graphics even though the support isn't actually there
1173          * according to the published specs.  It doesn't appear to function
1174          * correctly in testing on 945G.
1175          * This may be a side effect of MSI having been made available for PEG
1176          * and the registers being closely associated.
1177          *
1178          * According to chipset errata, on the 965GM, MSI interrupts may
1179          * be lost or delayed, and was defeatured. MSI interrupts seem to
1180          * get lost on g4x as well, and interrupt delivery seems to stay
1181          * properly dead afterwards. So we'll just disable them for all
1182          * pre-gen5 chipsets.
1183          */
1184         if (INTEL_GEN(dev_priv) >= 5) {
1185                 if (pci_enable_msi(pdev) < 0)
1186                         DRM_DEBUG_DRIVER("can't enable MSI");
1187         }
1188
1189         ret = intel_gvt_init(dev_priv);
1190         if (ret)
1191                 goto out_ggtt;
1192
1193         return 0;
1194
1195 out_ggtt:
1196         i915_ggtt_cleanup_hw(dev_priv);
1197
1198         return ret;
1199 }
1200
1201 /**
1202  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1203  * @dev_priv: device private
1204  */
1205 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1206 {
1207         struct pci_dev *pdev = dev_priv->drm.pdev;
1208
1209         if (pdev->msi_enabled)
1210                 pci_disable_msi(pdev);
1211
1212         pm_qos_remove_request(&dev_priv->pm_qos);
1213         i915_ggtt_cleanup_hw(dev_priv);
1214 }
1215
1216 /**
1217  * i915_driver_register - register the driver with the rest of the system
1218  * @dev_priv: device private
1219  *
1220  * Perform any steps necessary to make the driver available via kernel
1221  * internal or userspace interfaces.
1222  */
1223 static void i915_driver_register(struct drm_i915_private *dev_priv)
1224 {
1225         struct drm_device *dev = &dev_priv->drm;
1226
1227         i915_gem_shrinker_init(dev_priv);
1228
1229         /*
1230          * Notify a valid surface after modesetting,
1231          * when running inside a VM.
1232          */
1233         if (intel_vgpu_active(dev_priv))
1234                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1235
1236         /* Reveal our presence to userspace */
1237         if (drm_dev_register(dev, 0) == 0) {
1238                 i915_debugfs_register(dev_priv);
1239                 i915_guc_log_register(dev_priv);
1240                 i915_setup_sysfs(dev_priv);
1241
1242                 /* Depends on sysfs having been initialized */
1243                 i915_perf_register(dev_priv);
1244         } else
1245                 DRM_ERROR("Failed to register driver for userspace access!\n");
1246
1247         if (INTEL_INFO(dev_priv)->num_pipes) {
1248                 /* Must be done after probing outputs */
1249                 intel_opregion_register(dev_priv);
1250                 acpi_video_register();
1251         }
1252
1253         if (IS_GEN5(dev_priv))
1254                 intel_gpu_ips_init(dev_priv);
1255
1256         intel_audio_init(dev_priv);
1257
1258         /*
1259          * Some ports require correctly set-up hpd registers for detection to
1260          * work properly (leading to ghost connected connector status), e.g. VGA
1261          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1262          * irqs are fully enabled. We do it last so that the async config
1263          * cannot run before the connectors are registered.
1264          */
1265         intel_fbdev_initial_config_async(dev);
1266 }
1267
1268 /**
1269  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1270  * @dev_priv: device private
1271  */
1272 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1273 {
1274         intel_fbdev_unregister(dev_priv);
1275         intel_audio_deinit(dev_priv);
1276
1277         intel_gpu_ips_teardown();
1278         acpi_video_unregister();
1279         intel_opregion_unregister(dev_priv);
1280
1281         i915_perf_unregister(dev_priv);
1282
1283         i915_teardown_sysfs(dev_priv);
1284         i915_guc_log_unregister(dev_priv);
1285         drm_dev_unregister(&dev_priv->drm);
1286
1287         i915_gem_shrinker_cleanup(dev_priv);
1288 }
1289
1290 /**
1291  * i915_driver_load - setup chip and create an initial config
1292  * @pdev: PCI device
1293  * @ent: matching PCI ID entry
1294  *
1295  * The driver load routine has to do several things:
1296  *   - drive output discovery via intel_modeset_init()
1297  *   - initialize the memory manager
1298  *   - allocate initial config memory
1299  *   - setup the DRM framebuffer with the allocated memory
1300  */
1301 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1302 {
1303         const struct intel_device_info *match_info =
1304                 (struct intel_device_info *)ent->driver_data;
1305         struct drm_i915_private *dev_priv;
1306         int ret;
1307
1308         /* Enable nuclear pageflip on ILK+ */
1309         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1310                 driver.driver_features &= ~DRIVER_ATOMIC;
1311
1312         ret = -ENOMEM;
1313         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1314         if (dev_priv)
1315                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1316         if (ret) {
1317                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1318                 goto out_free;
1319         }
1320
1321         dev_priv->drm.pdev = pdev;
1322         dev_priv->drm.dev_private = dev_priv;
1323
1324         ret = pci_enable_device(pdev);
1325         if (ret)
1326                 goto out_fini;
1327
1328         pci_set_drvdata(pdev, &dev_priv->drm);
1329         /*
1330          * Disable the system suspend direct complete optimization, which can
1331          * leave the device suspended skipping the driver's suspend handlers
1332          * if the device was already runtime suspended. This is needed due to
1333          * the difference in our runtime and system suspend sequence and
1334          * becaue the HDA driver may require us to enable the audio power
1335          * domain during system suspend.
1336          */
1337         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1338
1339         ret = i915_driver_init_early(dev_priv, ent);
1340         if (ret < 0)
1341                 goto out_pci_disable;
1342
1343         intel_runtime_pm_get(dev_priv);
1344
1345         ret = i915_driver_init_mmio(dev_priv);
1346         if (ret < 0)
1347                 goto out_runtime_pm_put;
1348
1349         ret = i915_driver_init_hw(dev_priv);
1350         if (ret < 0)
1351                 goto out_cleanup_mmio;
1352
1353         /*
1354          * TODO: move the vblank init and parts of modeset init steps into one
1355          * of the i915_driver_init_/i915_driver_register functions according
1356          * to the role/effect of the given init step.
1357          */
1358         if (INTEL_INFO(dev_priv)->num_pipes) {
1359                 ret = drm_vblank_init(&dev_priv->drm,
1360                                       INTEL_INFO(dev_priv)->num_pipes);
1361                 if (ret)
1362                         goto out_cleanup_hw;
1363         }
1364
1365         ret = i915_load_modeset_init(&dev_priv->drm);
1366         if (ret < 0)
1367                 goto out_cleanup_hw;
1368
1369         i915_driver_register(dev_priv);
1370
1371         intel_runtime_pm_enable(dev_priv);
1372
1373         intel_init_ipc(dev_priv);
1374
1375         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1376                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1377         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1378                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1379
1380         intel_runtime_pm_put(dev_priv);
1381
1382         return 0;
1383
1384 out_cleanup_hw:
1385         i915_driver_cleanup_hw(dev_priv);
1386 out_cleanup_mmio:
1387         i915_driver_cleanup_mmio(dev_priv);
1388 out_runtime_pm_put:
1389         intel_runtime_pm_put(dev_priv);
1390         i915_driver_cleanup_early(dev_priv);
1391 out_pci_disable:
1392         pci_disable_device(pdev);
1393 out_fini:
1394         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1395         drm_dev_fini(&dev_priv->drm);
1396 out_free:
1397         kfree(dev_priv);
1398         return ret;
1399 }
1400
1401 void i915_driver_unload(struct drm_device *dev)
1402 {
1403         struct drm_i915_private *dev_priv = to_i915(dev);
1404         struct pci_dev *pdev = dev_priv->drm.pdev;
1405
1406         i915_driver_unregister(dev_priv);
1407
1408         if (i915_gem_suspend(dev_priv))
1409                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1410
1411         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1412
1413         drm_atomic_helper_shutdown(dev);
1414
1415         intel_gvt_cleanup(dev_priv);
1416
1417         intel_modeset_cleanup(dev);
1418
1419         /*
1420          * free the memory space allocated for the child device
1421          * config parsed from VBT
1422          */
1423         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1424                 kfree(dev_priv->vbt.child_dev);
1425                 dev_priv->vbt.child_dev = NULL;
1426                 dev_priv->vbt.child_dev_num = 0;
1427         }
1428         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1429         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1430         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1431         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1432
1433         vga_switcheroo_unregister_client(pdev);
1434         vga_client_register(pdev, NULL, NULL, NULL);
1435
1436         intel_csr_ucode_fini(dev_priv);
1437
1438         /* Free error state after interrupts are fully disabled. */
1439         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1440         i915_reset_error_state(dev_priv);
1441
1442         i915_gem_fini(dev_priv);
1443         intel_uc_fini_fw(dev_priv);
1444         intel_fbc_cleanup_cfb(dev_priv);
1445
1446         intel_power_domains_fini(dev_priv);
1447
1448         i915_driver_cleanup_hw(dev_priv);
1449         i915_driver_cleanup_mmio(dev_priv);
1450
1451         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1452 }
1453
1454 static void i915_driver_release(struct drm_device *dev)
1455 {
1456         struct drm_i915_private *dev_priv = to_i915(dev);
1457
1458         i915_driver_cleanup_early(dev_priv);
1459         drm_dev_fini(&dev_priv->drm);
1460
1461         kfree(dev_priv);
1462 }
1463
1464 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1465 {
1466         struct drm_i915_private *i915 = to_i915(dev);
1467         int ret;
1468
1469         ret = i915_gem_open(i915, file);
1470         if (ret)
1471                 return ret;
1472
1473         return 0;
1474 }
1475
1476 /**
1477  * i915_driver_lastclose - clean up after all DRM clients have exited
1478  * @dev: DRM device
1479  *
1480  * Take care of cleaning up after all DRM clients have exited.  In the
1481  * mode setting case, we want to restore the kernel's initial mode (just
1482  * in case the last client left us in a bad state).
1483  *
1484  * Additionally, in the non-mode setting case, we'll tear down the GTT
1485  * and DMA structures, since the kernel won't be using them, and clea
1486  * up any GEM state.
1487  */
1488 static void i915_driver_lastclose(struct drm_device *dev)
1489 {
1490         intel_fbdev_restore_mode(dev);
1491         vga_switcheroo_process_delayed_switch();
1492 }
1493
1494 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1495 {
1496         struct drm_i915_file_private *file_priv = file->driver_priv;
1497
1498         mutex_lock(&dev->struct_mutex);
1499         i915_gem_context_close(file);
1500         i915_gem_release(dev, file);
1501         mutex_unlock(&dev->struct_mutex);
1502
1503         kfree(file_priv);
1504 }
1505
1506 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1507 {
1508         struct drm_device *dev = &dev_priv->drm;
1509         struct intel_encoder *encoder;
1510
1511         drm_modeset_lock_all(dev);
1512         for_each_intel_encoder(dev, encoder)
1513                 if (encoder->suspend)
1514                         encoder->suspend(encoder);
1515         drm_modeset_unlock_all(dev);
1516 }
1517
1518 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1519                               bool rpm_resume);
1520 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1521
1522 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1523 {
1524 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1525         if (acpi_target_system_state() < ACPI_STATE_S3)
1526                 return true;
1527 #endif
1528         return false;
1529 }
1530
1531 static int i915_drm_suspend(struct drm_device *dev)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(dev);
1534         struct pci_dev *pdev = dev_priv->drm.pdev;
1535         pci_power_t opregion_target_state;
1536         int error;
1537
1538         /* ignore lid events during suspend */
1539         mutex_lock(&dev_priv->modeset_restore_lock);
1540         dev_priv->modeset_restore = MODESET_SUSPENDED;
1541         mutex_unlock(&dev_priv->modeset_restore_lock);
1542
1543         disable_rpm_wakeref_asserts(dev_priv);
1544
1545         /* We do a lot of poking in a lot of registers, make sure they work
1546          * properly. */
1547         intel_display_set_init_power(dev_priv, true);
1548
1549         drm_kms_helper_poll_disable(dev);
1550
1551         pci_save_state(pdev);
1552
1553         error = i915_gem_suspend(dev_priv);
1554         if (error) {
1555                 dev_err(&pdev->dev,
1556                         "GEM idle failed, resume might fail\n");
1557                 goto out;
1558         }
1559
1560         intel_display_suspend(dev);
1561
1562         intel_dp_mst_suspend(dev);
1563
1564         intel_runtime_pm_disable_interrupts(dev_priv);
1565         intel_hpd_cancel_work(dev_priv);
1566
1567         intel_suspend_encoders(dev_priv);
1568
1569         intel_suspend_hw(dev_priv);
1570
1571         i915_gem_suspend_gtt_mappings(dev_priv);
1572
1573         i915_save_state(dev_priv);
1574
1575         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1576         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1577
1578         intel_uncore_suspend(dev_priv);
1579         intel_opregion_unregister(dev_priv);
1580
1581         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1582
1583         dev_priv->suspend_count++;
1584
1585         intel_csr_ucode_suspend(dev_priv);
1586
1587 out:
1588         enable_rpm_wakeref_asserts(dev_priv);
1589
1590         return error;
1591 }
1592
1593 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1594 {
1595         struct drm_i915_private *dev_priv = to_i915(dev);
1596         struct pci_dev *pdev = dev_priv->drm.pdev;
1597         bool fw_csr;
1598         int ret;
1599
1600         disable_rpm_wakeref_asserts(dev_priv);
1601
1602         intel_display_set_init_power(dev_priv, false);
1603
1604         fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1605                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1606         /*
1607          * In case of firmware assisted context save/restore don't manually
1608          * deinit the power domains. This also means the CSR/DMC firmware will
1609          * stay active, it will power down any HW resources as required and
1610          * also enable deeper system power states that would be blocked if the
1611          * firmware was inactive.
1612          */
1613         if (!fw_csr)
1614                 intel_power_domains_suspend(dev_priv);
1615
1616         ret = 0;
1617         if (IS_GEN9_LP(dev_priv))
1618                 bxt_enable_dc9(dev_priv);
1619         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1620                 hsw_enable_pc8(dev_priv);
1621         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1622                 ret = vlv_suspend_complete(dev_priv);
1623
1624         if (ret) {
1625                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1626                 if (!fw_csr)
1627                         intel_power_domains_init_hw(dev_priv, true);
1628
1629                 goto out;
1630         }
1631
1632         pci_disable_device(pdev);
1633         /*
1634          * During hibernation on some platforms the BIOS may try to access
1635          * the device even though it's already in D3 and hang the machine. So
1636          * leave the device in D0 on those platforms and hope the BIOS will
1637          * power down the device properly. The issue was seen on multiple old
1638          * GENs with different BIOS vendors, so having an explicit blacklist
1639          * is inpractical; apply the workaround on everything pre GEN6. The
1640          * platforms where the issue was seen:
1641          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1642          * Fujitsu FSC S7110
1643          * Acer Aspire 1830T
1644          */
1645         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1646                 pci_set_power_state(pdev, PCI_D3hot);
1647
1648         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1649
1650 out:
1651         enable_rpm_wakeref_asserts(dev_priv);
1652
1653         return ret;
1654 }
1655
1656 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1657 {
1658         int error;
1659
1660         if (!dev) {
1661                 DRM_ERROR("dev: %p\n", dev);
1662                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1663                 return -ENODEV;
1664         }
1665
1666         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1667                          state.event != PM_EVENT_FREEZE))
1668                 return -EINVAL;
1669
1670         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1671                 return 0;
1672
1673         error = i915_drm_suspend(dev);
1674         if (error)
1675                 return error;
1676
1677         return i915_drm_suspend_late(dev, false);
1678 }
1679
1680 static int i915_drm_resume(struct drm_device *dev)
1681 {
1682         struct drm_i915_private *dev_priv = to_i915(dev);
1683         int ret;
1684
1685         disable_rpm_wakeref_asserts(dev_priv);
1686         intel_sanitize_gt_powersave(dev_priv);
1687
1688         ret = i915_ggtt_enable_hw(dev_priv);
1689         if (ret)
1690                 DRM_ERROR("failed to re-enable GGTT\n");
1691
1692         intel_csr_ucode_resume(dev_priv);
1693
1694         i915_restore_state(dev_priv);
1695         intel_pps_unlock_regs_wa(dev_priv);
1696         intel_opregion_setup(dev_priv);
1697
1698         intel_init_pch_refclk(dev_priv);
1699
1700         /*
1701          * Interrupts have to be enabled before any batches are run. If not the
1702          * GPU will hang. i915_gem_init_hw() will initiate batches to
1703          * update/restore the context.
1704          *
1705          * drm_mode_config_reset() needs AUX interrupts.
1706          *
1707          * Modeset enabling in intel_modeset_init_hw() also needs working
1708          * interrupts.
1709          */
1710         intel_runtime_pm_enable_interrupts(dev_priv);
1711
1712         drm_mode_config_reset(dev);
1713
1714         i915_gem_resume(dev_priv);
1715
1716         intel_modeset_init_hw(dev);
1717
1718         spin_lock_irq(&dev_priv->irq_lock);
1719         if (dev_priv->display.hpd_irq_setup)
1720                 dev_priv->display.hpd_irq_setup(dev_priv);
1721         spin_unlock_irq(&dev_priv->irq_lock);
1722
1723         intel_dp_mst_resume(dev);
1724
1725         intel_display_resume(dev);
1726
1727         drm_kms_helper_poll_enable(dev);
1728
1729         /*
1730          * ... but also need to make sure that hotplug processing
1731          * doesn't cause havoc. Like in the driver load code we don't
1732          * bother with the tiny race here where we might loose hotplug
1733          * notifications.
1734          * */
1735         intel_hpd_init(dev_priv);
1736
1737         intel_opregion_register(dev_priv);
1738
1739         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1740
1741         mutex_lock(&dev_priv->modeset_restore_lock);
1742         dev_priv->modeset_restore = MODESET_DONE;
1743         mutex_unlock(&dev_priv->modeset_restore_lock);
1744
1745         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1746
1747         enable_rpm_wakeref_asserts(dev_priv);
1748
1749         return 0;
1750 }
1751
1752 static int i915_drm_resume_early(struct drm_device *dev)
1753 {
1754         struct drm_i915_private *dev_priv = to_i915(dev);
1755         struct pci_dev *pdev = dev_priv->drm.pdev;
1756         int ret;
1757
1758         /*
1759          * We have a resume ordering issue with the snd-hda driver also
1760          * requiring our device to be power up. Due to the lack of a
1761          * parent/child relationship we currently solve this with an early
1762          * resume hook.
1763          *
1764          * FIXME: This should be solved with a special hdmi sink device or
1765          * similar so that power domains can be employed.
1766          */
1767
1768         /*
1769          * Note that we need to set the power state explicitly, since we
1770          * powered off the device during freeze and the PCI core won't power
1771          * it back up for us during thaw. Powering off the device during
1772          * freeze is not a hard requirement though, and during the
1773          * suspend/resume phases the PCI core makes sure we get here with the
1774          * device powered on. So in case we change our freeze logic and keep
1775          * the device powered we can also remove the following set power state
1776          * call.
1777          */
1778         ret = pci_set_power_state(pdev, PCI_D0);
1779         if (ret) {
1780                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1781                 goto out;
1782         }
1783
1784         /*
1785          * Note that pci_enable_device() first enables any parent bridge
1786          * device and only then sets the power state for this device. The
1787          * bridge enabling is a nop though, since bridge devices are resumed
1788          * first. The order of enabling power and enabling the device is
1789          * imposed by the PCI core as described above, so here we preserve the
1790          * same order for the freeze/thaw phases.
1791          *
1792          * TODO: eventually we should remove pci_disable_device() /
1793          * pci_enable_enable_device() from suspend/resume. Due to how they
1794          * depend on the device enable refcount we can't anyway depend on them
1795          * disabling/enabling the device.
1796          */
1797         if (pci_enable_device(pdev)) {
1798                 ret = -EIO;
1799                 goto out;
1800         }
1801
1802         pci_set_master(pdev);
1803
1804         disable_rpm_wakeref_asserts(dev_priv);
1805
1806         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1807                 ret = vlv_resume_prepare(dev_priv, false);
1808         if (ret)
1809                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1810                           ret);
1811
1812         intel_uncore_resume_early(dev_priv);
1813
1814         if (IS_GEN9_LP(dev_priv)) {
1815                 if (!dev_priv->suspended_to_idle)
1816                         gen9_sanitize_dc_state(dev_priv);
1817                 bxt_disable_dc9(dev_priv);
1818         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1819                 hsw_disable_pc8(dev_priv);
1820         }
1821
1822         intel_uncore_sanitize(dev_priv);
1823
1824         if (IS_GEN9_LP(dev_priv) ||
1825             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1826                 intel_power_domains_init_hw(dev_priv, true);
1827
1828         i915_gem_sanitize(dev_priv);
1829
1830         enable_rpm_wakeref_asserts(dev_priv);
1831
1832 out:
1833         dev_priv->suspended_to_idle = false;
1834
1835         return ret;
1836 }
1837
1838 static int i915_resume_switcheroo(struct drm_device *dev)
1839 {
1840         int ret;
1841
1842         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1843                 return 0;
1844
1845         ret = i915_drm_resume_early(dev);
1846         if (ret)
1847                 return ret;
1848
1849         return i915_drm_resume(dev);
1850 }
1851
1852 /**
1853  * i915_reset - reset chip after a hang
1854  * @i915: #drm_i915_private to reset
1855  * @flags: Instructions
1856  *
1857  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1858  * on failure.
1859  *
1860  * Caller must hold the struct_mutex.
1861  *
1862  * Procedure is fairly simple:
1863  *   - reset the chip using the reset reg
1864  *   - re-init context state
1865  *   - re-init hardware status page
1866  *   - re-init ring buffer
1867  *   - re-init interrupt state
1868  *   - re-init display
1869  */
1870 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1871 {
1872         struct i915_gpu_error *error = &i915->gpu_error;
1873         int ret;
1874
1875         lockdep_assert_held(&i915->drm.struct_mutex);
1876         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1877
1878         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1879                 return;
1880
1881         /* Clear any previous failed attempts at recovery. Time to try again. */
1882         if (!i915_gem_unset_wedged(i915))
1883                 goto wakeup;
1884
1885         if (!(flags & I915_RESET_QUIET))
1886                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1887         error->reset_count++;
1888
1889         disable_irq(i915->drm.irq);
1890         ret = i915_gem_reset_prepare(i915);
1891         if (ret) {
1892                 DRM_ERROR("GPU recovery failed\n");
1893                 intel_gpu_reset(i915, ALL_ENGINES);
1894                 goto error;
1895         }
1896
1897         ret = intel_gpu_reset(i915, ALL_ENGINES);
1898         if (ret) {
1899                 if (ret != -ENODEV)
1900                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1901                 else
1902                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1903                 goto error;
1904         }
1905
1906         i915_gem_reset(i915);
1907         intel_overlay_reset(i915);
1908
1909         /* Ok, now get things going again... */
1910
1911         /*
1912          * Everything depends on having the GTT running, so we need to start
1913          * there.
1914          */
1915         ret = i915_ggtt_enable_hw(i915);
1916         if (ret) {
1917                 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1918                 goto error;
1919         }
1920
1921         /*
1922          * Next we need to restore the context, but we don't use those
1923          * yet either...
1924          *
1925          * Ring buffer needs to be re-initialized in the KMS case, or if X
1926          * was running at the time of the reset (i.e. we weren't VT
1927          * switched away).
1928          */
1929         ret = i915_gem_init_hw(i915);
1930         if (ret) {
1931                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1932                 goto error;
1933         }
1934
1935         i915_queue_hangcheck(i915);
1936
1937 finish:
1938         i915_gem_reset_finish(i915);
1939         enable_irq(i915->drm.irq);
1940
1941 wakeup:
1942         clear_bit(I915_RESET_HANDOFF, &error->flags);
1943         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1944         return;
1945
1946 error:
1947         i915_gem_set_wedged(i915);
1948         i915_gem_retire_requests(i915);
1949         goto finish;
1950 }
1951
1952 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
1953                                         struct intel_engine_cs *engine)
1954 {
1955         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
1956 }
1957
1958 /**
1959  * i915_reset_engine - reset GPU engine to recover from a hang
1960  * @engine: engine to reset
1961  * @flags: options
1962  *
1963  * Reset a specific GPU engine. Useful if a hang is detected.
1964  * Returns zero on successful reset or otherwise an error code.
1965  *
1966  * Procedure is:
1967  *  - identifies the request that caused the hang and it is dropped
1968  *  - reset engine (which will force the engine to idle)
1969  *  - re-init/configure engine
1970  */
1971 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
1972 {
1973         struct i915_gpu_error *error = &engine->i915->gpu_error;
1974         struct drm_i915_gem_request *active_request;
1975         int ret;
1976
1977         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1978
1979         if (!(flags & I915_RESET_QUIET)) {
1980                 dev_notice(engine->i915->drm.dev,
1981                            "Resetting %s after gpu hang\n", engine->name);
1982         }
1983         error->reset_engine_count[engine->id]++;
1984
1985         active_request = i915_gem_reset_prepare_engine(engine);
1986         if (IS_ERR(active_request)) {
1987                 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1988                 ret = PTR_ERR(active_request);
1989                 goto out;
1990         }
1991
1992         if (!engine->i915->guc.execbuf_client)
1993                 ret = intel_gt_reset_engine(engine->i915, engine);
1994         else
1995                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
1996         if (ret) {
1997                 /* If we fail here, we expect to fallback to a global reset */
1998                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
1999                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2000                                  engine->name, ret);
2001                 goto out;
2002         }
2003
2004         /*
2005          * The request that caused the hang is stuck on elsp, we know the
2006          * active request and can drop it, adjust head to skip the offending
2007          * request to resume executing remaining requests in the queue.
2008          */
2009         i915_gem_reset_engine(engine, active_request);
2010
2011         /*
2012          * The engine and its registers (and workarounds in case of render)
2013          * have been reset to their default values. Follow the init_ring
2014          * process to program RING_MODE, HWSP and re-enable submission.
2015          */
2016         ret = engine->init_hw(engine);
2017         if (ret)
2018                 goto out;
2019
2020 out:
2021         i915_gem_reset_finish_engine(engine);
2022         return ret;
2023 }
2024
2025 static int i915_pm_suspend(struct device *kdev)
2026 {
2027         struct pci_dev *pdev = to_pci_dev(kdev);
2028         struct drm_device *dev = pci_get_drvdata(pdev);
2029
2030         if (!dev) {
2031                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2032                 return -ENODEV;
2033         }
2034
2035         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2036                 return 0;
2037
2038         return i915_drm_suspend(dev);
2039 }
2040
2041 static int i915_pm_suspend_late(struct device *kdev)
2042 {
2043         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2044
2045         /*
2046          * We have a suspend ordering issue with the snd-hda driver also
2047          * requiring our device to be power up. Due to the lack of a
2048          * parent/child relationship we currently solve this with an late
2049          * suspend hook.
2050          *
2051          * FIXME: This should be solved with a special hdmi sink device or
2052          * similar so that power domains can be employed.
2053          */
2054         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2055                 return 0;
2056
2057         return i915_drm_suspend_late(dev, false);
2058 }
2059
2060 static int i915_pm_poweroff_late(struct device *kdev)
2061 {
2062         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2063
2064         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2065                 return 0;
2066
2067         return i915_drm_suspend_late(dev, true);
2068 }
2069
2070 static int i915_pm_resume_early(struct device *kdev)
2071 {
2072         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2073
2074         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2075                 return 0;
2076
2077         return i915_drm_resume_early(dev);
2078 }
2079
2080 static int i915_pm_resume(struct device *kdev)
2081 {
2082         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2083
2084         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2085                 return 0;
2086
2087         return i915_drm_resume(dev);
2088 }
2089
2090 /* freeze: before creating the hibernation_image */
2091 static int i915_pm_freeze(struct device *kdev)
2092 {
2093         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2094         int ret;
2095
2096         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2097                 ret = i915_drm_suspend(dev);
2098                 if (ret)
2099                         return ret;
2100         }
2101
2102         ret = i915_gem_freeze(kdev_to_i915(kdev));
2103         if (ret)
2104                 return ret;
2105
2106         return 0;
2107 }
2108
2109 static int i915_pm_freeze_late(struct device *kdev)
2110 {
2111         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2112         int ret;
2113
2114         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2115                 ret = i915_drm_suspend_late(dev, true);
2116                 if (ret)
2117                         return ret;
2118         }
2119
2120         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2121         if (ret)
2122                 return ret;
2123
2124         return 0;
2125 }
2126
2127 /* thaw: called after creating the hibernation image, but before turning off. */
2128 static int i915_pm_thaw_early(struct device *kdev)
2129 {
2130         return i915_pm_resume_early(kdev);
2131 }
2132
2133 static int i915_pm_thaw(struct device *kdev)
2134 {
2135         return i915_pm_resume(kdev);
2136 }
2137
2138 /* restore: called after loading the hibernation image. */
2139 static int i915_pm_restore_early(struct device *kdev)
2140 {
2141         return i915_pm_resume_early(kdev);
2142 }
2143
2144 static int i915_pm_restore(struct device *kdev)
2145 {
2146         return i915_pm_resume(kdev);
2147 }
2148
2149 /*
2150  * Save all Gunit registers that may be lost after a D3 and a subsequent
2151  * S0i[R123] transition. The list of registers needing a save/restore is
2152  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2153  * registers in the following way:
2154  * - Driver: saved/restored by the driver
2155  * - Punit : saved/restored by the Punit firmware
2156  * - No, w/o marking: no need to save/restore, since the register is R/O or
2157  *                    used internally by the HW in a way that doesn't depend
2158  *                    keeping the content across a suspend/resume.
2159  * - Debug : used for debugging
2160  *
2161  * We save/restore all registers marked with 'Driver', with the following
2162  * exceptions:
2163  * - Registers out of use, including also registers marked with 'Debug'.
2164  *   These have no effect on the driver's operation, so we don't save/restore
2165  *   them to reduce the overhead.
2166  * - Registers that are fully setup by an initialization function called from
2167  *   the resume path. For example many clock gating and RPS/RC6 registers.
2168  * - Registers that provide the right functionality with their reset defaults.
2169  *
2170  * TODO: Except for registers that based on the above 3 criteria can be safely
2171  * ignored, we save/restore all others, practically treating the HW context as
2172  * a black-box for the driver. Further investigation is needed to reduce the
2173  * saved/restored registers even further, by following the same 3 criteria.
2174  */
2175 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2176 {
2177         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2178         int i;
2179
2180         /* GAM 0x4000-0x4770 */
2181         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2182         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2183         s->arb_mode             = I915_READ(ARB_MODE);
2184         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2185         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2186
2187         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2188                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2189
2190         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2191         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2192
2193         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2194         s->ecochk               = I915_READ(GAM_ECOCHK);
2195         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2196         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2197
2198         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2199
2200         /* MBC 0x9024-0x91D0, 0x8500 */
2201         s->g3dctl               = I915_READ(VLV_G3DCTL);
2202         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2203         s->mbctl                = I915_READ(GEN6_MBCTL);
2204
2205         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2206         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2207         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2208         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2209         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2210         s->rstctl               = I915_READ(GEN6_RSTCTL);
2211         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2212
2213         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2214         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2215         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2216         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2217         s->ecobus               = I915_READ(ECOBUS);
2218         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2219         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2220         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2221         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2222         s->rcedata              = I915_READ(VLV_RCEDATA);
2223         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2224
2225         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2226         s->gt_imr               = I915_READ(GTIMR);
2227         s->gt_ier               = I915_READ(GTIER);
2228         s->pm_imr               = I915_READ(GEN6_PMIMR);
2229         s->pm_ier               = I915_READ(GEN6_PMIER);
2230
2231         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2232                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2233
2234         /* GT SA CZ domain, 0x100000-0x138124 */
2235         s->tilectl              = I915_READ(TILECTL);
2236         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2237         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2238         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2239         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2240
2241         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2242         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2243         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2244         s->pcbr                 = I915_READ(VLV_PCBR);
2245         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2246
2247         /*
2248          * Not saving any of:
2249          * DFT,         0x9800-0x9EC0
2250          * SARB,        0xB000-0xB1FC
2251          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2252          * PCI CFG
2253          */
2254 }
2255
2256 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2257 {
2258         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2259         u32 val;
2260         int i;
2261
2262         /* GAM 0x4000-0x4770 */
2263         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2264         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2265         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2266         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2267         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2268
2269         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2270                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2271
2272         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2273         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2274
2275         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2276         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2277         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2278         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2279
2280         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2281
2282         /* MBC 0x9024-0x91D0, 0x8500 */
2283         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2284         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2285         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2286
2287         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2288         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2289         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2290         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2291         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2292         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2293         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2294
2295         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2296         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2297         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2298         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2299         I915_WRITE(ECOBUS,              s->ecobus);
2300         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2301         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2302         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2303         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2304         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2305         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2306
2307         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2308         I915_WRITE(GTIMR,               s->gt_imr);
2309         I915_WRITE(GTIER,               s->gt_ier);
2310         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2311         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2312
2313         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2314                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2315
2316         /* GT SA CZ domain, 0x100000-0x138124 */
2317         I915_WRITE(TILECTL,                     s->tilectl);
2318         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2319         /*
2320          * Preserve the GT allow wake and GFX force clock bit, they are not
2321          * be restored, as they are used to control the s0ix suspend/resume
2322          * sequence by the caller.
2323          */
2324         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2325         val &= VLV_GTLC_ALLOWWAKEREQ;
2326         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2327         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2328
2329         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2330         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2331         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2332         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2333
2334         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2335
2336         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2337         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2338         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2339         I915_WRITE(VLV_PCBR,                    s->pcbr);
2340         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2341 }
2342
2343 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2344                                   u32 mask, u32 val)
2345 {
2346         /* The HW does not like us polling for PW_STATUS frequently, so
2347          * use the sleeping loop rather than risk the busy spin within
2348          * intel_wait_for_register().
2349          *
2350          * Transitioning between RC6 states should be at most 2ms (see
2351          * valleyview_enable_rps) so use a 3ms timeout.
2352          */
2353         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2354                         3);
2355 }
2356
2357 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2358 {
2359         u32 val;
2360         int err;
2361
2362         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2363         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2364         if (force_on)
2365                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2366         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2367
2368         if (!force_on)
2369                 return 0;
2370
2371         err = intel_wait_for_register(dev_priv,
2372                                       VLV_GTLC_SURVIVABILITY_REG,
2373                                       VLV_GFX_CLK_STATUS_BIT,
2374                                       VLV_GFX_CLK_STATUS_BIT,
2375                                       20);
2376         if (err)
2377                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2378                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2379
2380         return err;
2381 }
2382
2383 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2384 {
2385         u32 mask;
2386         u32 val;
2387         int err;
2388
2389         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2390         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2391         if (allow)
2392                 val |= VLV_GTLC_ALLOWWAKEREQ;
2393         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2394         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2395
2396         mask = VLV_GTLC_ALLOWWAKEACK;
2397         val = allow ? mask : 0;
2398
2399         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2400         if (err)
2401                 DRM_ERROR("timeout disabling GT waking\n");
2402
2403         return err;
2404 }
2405
2406 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2407                                   bool wait_for_on)
2408 {
2409         u32 mask;
2410         u32 val;
2411
2412         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2413         val = wait_for_on ? mask : 0;
2414
2415         /*
2416          * RC6 transitioning can be delayed up to 2 msec (see
2417          * valleyview_enable_rps), use 3 msec for safety.
2418          */
2419         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2420                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2421                           onoff(wait_for_on));
2422 }
2423
2424 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2425 {
2426         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2427                 return;
2428
2429         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2430         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2431 }
2432
2433 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2434 {
2435         u32 mask;
2436         int err;
2437
2438         /*
2439          * Bspec defines the following GT well on flags as debug only, so
2440          * don't treat them as hard failures.
2441          */
2442         vlv_wait_for_gt_wells(dev_priv, false);
2443
2444         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2445         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2446
2447         vlv_check_no_gt_access(dev_priv);
2448
2449         err = vlv_force_gfx_clock(dev_priv, true);
2450         if (err)
2451                 goto err1;
2452
2453         err = vlv_allow_gt_wake(dev_priv, false);
2454         if (err)
2455                 goto err2;
2456
2457         if (!IS_CHERRYVIEW(dev_priv))
2458                 vlv_save_gunit_s0ix_state(dev_priv);
2459
2460         err = vlv_force_gfx_clock(dev_priv, false);
2461         if (err)
2462                 goto err2;
2463
2464         return 0;
2465
2466 err2:
2467         /* For safety always re-enable waking and disable gfx clock forcing */
2468         vlv_allow_gt_wake(dev_priv, true);
2469 err1:
2470         vlv_force_gfx_clock(dev_priv, false);
2471
2472         return err;
2473 }
2474
2475 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2476                                 bool rpm_resume)
2477 {
2478         int err;
2479         int ret;
2480
2481         /*
2482          * If any of the steps fail just try to continue, that's the best we
2483          * can do at this point. Return the first error code (which will also
2484          * leave RPM permanently disabled).
2485          */
2486         ret = vlv_force_gfx_clock(dev_priv, true);
2487
2488         if (!IS_CHERRYVIEW(dev_priv))
2489                 vlv_restore_gunit_s0ix_state(dev_priv);
2490
2491         err = vlv_allow_gt_wake(dev_priv, true);
2492         if (!ret)
2493                 ret = err;
2494
2495         err = vlv_force_gfx_clock(dev_priv, false);
2496         if (!ret)
2497                 ret = err;
2498
2499         vlv_check_no_gt_access(dev_priv);
2500
2501         if (rpm_resume)
2502                 intel_init_clock_gating(dev_priv);
2503
2504         return ret;
2505 }
2506
2507 static int intel_runtime_suspend(struct device *kdev)
2508 {
2509         struct pci_dev *pdev = to_pci_dev(kdev);
2510         struct drm_device *dev = pci_get_drvdata(pdev);
2511         struct drm_i915_private *dev_priv = to_i915(dev);
2512         int ret;
2513
2514         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled())))
2515                 return -ENODEV;
2516
2517         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2518                 return -ENODEV;
2519
2520         DRM_DEBUG_KMS("Suspending device\n");
2521
2522         disable_rpm_wakeref_asserts(dev_priv);
2523
2524         /*
2525          * We are safe here against re-faults, since the fault handler takes
2526          * an RPM reference.
2527          */
2528         i915_gem_runtime_suspend(dev_priv);
2529
2530         intel_guc_suspend(dev_priv);
2531
2532         intel_runtime_pm_disable_interrupts(dev_priv);
2533
2534         intel_uncore_suspend(dev_priv);
2535
2536         ret = 0;
2537         if (IS_GEN9_LP(dev_priv)) {
2538                 bxt_display_core_uninit(dev_priv);
2539                 bxt_enable_dc9(dev_priv);
2540         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2541                 hsw_enable_pc8(dev_priv);
2542         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2543                 ret = vlv_suspend_complete(dev_priv);
2544         }
2545
2546         if (ret) {
2547                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2548                 intel_uncore_runtime_resume(dev_priv);
2549
2550                 intel_runtime_pm_enable_interrupts(dev_priv);
2551
2552                 enable_rpm_wakeref_asserts(dev_priv);
2553
2554                 return ret;
2555         }
2556
2557         enable_rpm_wakeref_asserts(dev_priv);
2558         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2559
2560         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2561                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2562
2563         dev_priv->runtime_pm.suspended = true;
2564
2565         /*
2566          * FIXME: We really should find a document that references the arguments
2567          * used below!
2568          */
2569         if (IS_BROADWELL(dev_priv)) {
2570                 /*
2571                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2572                  * being detected, and the call we do at intel_runtime_resume()
2573                  * won't be able to restore them. Since PCI_D3hot matches the
2574                  * actual specification and appears to be working, use it.
2575                  */
2576                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2577         } else {
2578                 /*
2579                  * current versions of firmware which depend on this opregion
2580                  * notification have repurposed the D1 definition to mean
2581                  * "runtime suspended" vs. what you would normally expect (D3)
2582                  * to distinguish it from notifications that might be sent via
2583                  * the suspend path.
2584                  */
2585                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2586         }
2587
2588         assert_forcewakes_inactive(dev_priv);
2589
2590         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2591                 intel_hpd_poll_init(dev_priv);
2592
2593         DRM_DEBUG_KMS("Device suspended\n");
2594         return 0;
2595 }
2596
2597 static int intel_runtime_resume(struct device *kdev)
2598 {
2599         struct pci_dev *pdev = to_pci_dev(kdev);
2600         struct drm_device *dev = pci_get_drvdata(pdev);
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         int ret = 0;
2603
2604         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2605                 return -ENODEV;
2606
2607         DRM_DEBUG_KMS("Resuming device\n");
2608
2609         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2610         disable_rpm_wakeref_asserts(dev_priv);
2611
2612         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2613         dev_priv->runtime_pm.suspended = false;
2614         if (intel_uncore_unclaimed_mmio(dev_priv))
2615                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2616
2617         intel_guc_resume(dev_priv);
2618
2619         if (IS_GEN9_LP(dev_priv)) {
2620                 bxt_disable_dc9(dev_priv);
2621                 bxt_display_core_init(dev_priv, true);
2622                 if (dev_priv->csr.dmc_payload &&
2623                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2624                         gen9_enable_dc5(dev_priv);
2625         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2626                 hsw_disable_pc8(dev_priv);
2627         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2628                 ret = vlv_resume_prepare(dev_priv, true);
2629         }
2630
2631         intel_uncore_runtime_resume(dev_priv);
2632
2633         /*
2634          * No point of rolling back things in case of an error, as the best
2635          * we can do is to hope that things will still work (and disable RPM).
2636          */
2637         i915_gem_init_swizzling(dev_priv);
2638         i915_gem_restore_fences(dev_priv);
2639
2640         intel_runtime_pm_enable_interrupts(dev_priv);
2641
2642         /*
2643          * On VLV/CHV display interrupts are part of the display
2644          * power well, so hpd is reinitialized from there. For
2645          * everyone else do it here.
2646          */
2647         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2648                 intel_hpd_init(dev_priv);
2649
2650         intel_enable_ipc(dev_priv);
2651
2652         enable_rpm_wakeref_asserts(dev_priv);
2653
2654         if (ret)
2655                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2656         else
2657                 DRM_DEBUG_KMS("Device resumed\n");
2658
2659         return ret;
2660 }
2661
2662 const struct dev_pm_ops i915_pm_ops = {
2663         /*
2664          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2665          * PMSG_RESUME]
2666          */
2667         .suspend = i915_pm_suspend,
2668         .suspend_late = i915_pm_suspend_late,
2669         .resume_early = i915_pm_resume_early,
2670         .resume = i915_pm_resume,
2671
2672         /*
2673          * S4 event handlers
2674          * @freeze, @freeze_late    : called (1) before creating the
2675          *                            hibernation image [PMSG_FREEZE] and
2676          *                            (2) after rebooting, before restoring
2677          *                            the image [PMSG_QUIESCE]
2678          * @thaw, @thaw_early       : called (1) after creating the hibernation
2679          *                            image, before writing it [PMSG_THAW]
2680          *                            and (2) after failing to create or
2681          *                            restore the image [PMSG_RECOVER]
2682          * @poweroff, @poweroff_late: called after writing the hibernation
2683          *                            image, before rebooting [PMSG_HIBERNATE]
2684          * @restore, @restore_early : called after rebooting and restoring the
2685          *                            hibernation image [PMSG_RESTORE]
2686          */
2687         .freeze = i915_pm_freeze,
2688         .freeze_late = i915_pm_freeze_late,
2689         .thaw_early = i915_pm_thaw_early,
2690         .thaw = i915_pm_thaw,
2691         .poweroff = i915_pm_suspend,
2692         .poweroff_late = i915_pm_poweroff_late,
2693         .restore_early = i915_pm_restore_early,
2694         .restore = i915_pm_restore,
2695
2696         /* S0ix (via runtime suspend) event handlers */
2697         .runtime_suspend = intel_runtime_suspend,
2698         .runtime_resume = intel_runtime_resume,
2699 };
2700
2701 static const struct vm_operations_struct i915_gem_vm_ops = {
2702         .fault = i915_gem_fault,
2703         .open = drm_gem_vm_open,
2704         .close = drm_gem_vm_close,
2705 };
2706
2707 static const struct file_operations i915_driver_fops = {
2708         .owner = THIS_MODULE,
2709         .open = drm_open,
2710         .release = drm_release,
2711         .unlocked_ioctl = drm_ioctl,
2712         .mmap = drm_gem_mmap,
2713         .poll = drm_poll,
2714         .read = drm_read,
2715         .compat_ioctl = i915_compat_ioctl,
2716         .llseek = noop_llseek,
2717 };
2718
2719 static int
2720 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2721                           struct drm_file *file)
2722 {
2723         return -ENODEV;
2724 }
2725
2726 static const struct drm_ioctl_desc i915_ioctls[] = {
2727         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2728         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2729         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2730         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2731         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2732         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2733         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2734         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2735         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2736         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2737         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2738         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2739         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2740         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2741         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2742         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2743         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2744         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2745         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2746         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2747         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2748         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2749         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2750         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2751         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2752         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2753         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2754         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2755         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2756         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2757         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2758         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2759         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2760         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2761         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2762         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2763         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2764         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2765         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2766         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2767         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2768         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2769         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2770         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2771         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2772         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2773         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2774         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2775         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2776         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2777         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2778         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2779         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2780         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2781         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2782 };
2783
2784 static struct drm_driver driver = {
2785         /* Don't use MTRRs here; the Xserver or userspace app should
2786          * deal with them for Intel hardware.
2787          */
2788         .driver_features =
2789             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2790             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2791         .release = i915_driver_release,
2792         .open = i915_driver_open,
2793         .lastclose = i915_driver_lastclose,
2794         .postclose = i915_driver_postclose,
2795
2796         .gem_close_object = i915_gem_close_object,
2797         .gem_free_object_unlocked = i915_gem_free_object,
2798         .gem_vm_ops = &i915_gem_vm_ops,
2799
2800         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2801         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2802         .gem_prime_export = i915_gem_prime_export,
2803         .gem_prime_import = i915_gem_prime_import,
2804
2805         .dumb_create = i915_gem_dumb_create,
2806         .dumb_map_offset = i915_gem_mmap_gtt,
2807         .ioctls = i915_ioctls,
2808         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2809         .fops = &i915_driver_fops,
2810         .name = DRIVER_NAME,
2811         .desc = DRIVER_DESC,
2812         .date = DRIVER_DATE,
2813         .major = DRIVER_MAJOR,
2814         .minor = DRIVER_MINOR,
2815         .patchlevel = DRIVER_PATCHLEVEL,
2816 };
2817
2818 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2819 #include "selftests/mock_drm.c"
2820 #endif