1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
52 #include "i915_query.h"
53 #include "i915_vgpu.h"
54 #include "intel_drv.h"
57 static struct drm_driver driver;
59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
60 static unsigned int i915_load_fail_count;
62 bool __i915_inject_load_failure(const char *func, int line)
64 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
67 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
68 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
69 i915_modparams.inject_load_failure, func, line);
77 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
78 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
79 "providing the dmesg log by booting with drm.debug=0xf"
82 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
85 static bool shown_bug_once;
86 struct device *kdev = dev_priv->drm.dev;
87 bool is_error = level[1] <= KERN_ERR[1];
88 bool is_debug = level[1] == KERN_DEBUG[1];
92 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
100 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
101 __builtin_return_address(0), &vaf);
103 if (is_error && !shown_bug_once) {
104 dev_notice(kdev, "%s", FDO_BUG_MSG);
105 shown_bug_once = true;
111 static bool i915_error_injected(struct drm_i915_private *dev_priv)
113 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
114 return i915_modparams.inject_load_failure &&
115 i915_load_fail_count == i915_modparams.inject_load_failure;
121 #define i915_load_error(dev_priv, fmt, ...) \
122 __i915_printk(dev_priv, \
123 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
126 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
127 static enum intel_pch
128 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
131 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
132 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
133 WARN_ON(!IS_GEN5(dev_priv));
135 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
136 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
137 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
139 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
140 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
141 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
142 /* PantherPoint is CPT compatible */
144 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
145 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
146 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
147 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
149 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
150 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
151 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
152 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
154 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
155 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
156 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
157 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
158 /* WildcatPoint is LPT compatible */
160 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
161 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
162 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
163 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
164 /* WildcatPoint is LPT compatible */
166 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
167 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
168 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
170 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
171 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
172 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
174 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
175 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
176 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
177 !IS_COFFEELAKE(dev_priv));
179 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
180 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
181 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
183 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
184 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
185 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
187 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
188 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
189 WARN_ON(!IS_ICELAKE(dev_priv));
196 static bool intel_is_virt_pch(unsigned short id,
197 unsigned short svendor, unsigned short sdevice)
199 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
200 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
201 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
202 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
203 sdevice == PCI_SUBDEVICE_ID_QEMU));
206 static unsigned short
207 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
209 unsigned short id = 0;
212 * In a virtualized passthrough environment we can be in a
213 * setup where the ISA bridge is not able to be passed through.
214 * In this case, a south bridge can be emulated and we have to
215 * make an educated guess as to which PCH is really there.
218 if (IS_GEN5(dev_priv))
219 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
220 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
221 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
222 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
223 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
224 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
225 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
226 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
227 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
228 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
229 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
232 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
234 DRM_DEBUG_KMS("Assuming no PCH\n");
239 static void intel_detect_pch(struct drm_i915_private *dev_priv)
241 struct pci_dev *pch = NULL;
243 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
244 * (which really amounts to a PCH but no South Display).
246 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
247 dev_priv->pch_type = PCH_NOP;
252 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
253 * make graphics device passthrough work easy for VMM, that only
254 * need to expose ISA bridge to let driver know the real hardware
255 * underneath. This is a requirement from virtualization team.
257 * In some virtualized environments (e.g. XEN), there is irrelevant
258 * ISA bridge in the system. To work reliably, we should scan trhough
259 * all the ISA bridge devices and check for the first match, instead
260 * of only checking the first one.
262 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
264 enum intel_pch pch_type;
266 if (pch->vendor != PCI_VENDOR_ID_INTEL)
269 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
271 pch_type = intel_pch_type(dev_priv, id);
272 if (pch_type != PCH_NONE) {
273 dev_priv->pch_type = pch_type;
274 dev_priv->pch_id = id;
276 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
277 pch->subsystem_device)) {
278 id = intel_virt_detect_pch(dev_priv);
280 pch_type = intel_pch_type(dev_priv, id);
281 if (WARN_ON(pch_type == PCH_NONE))
286 dev_priv->pch_type = pch_type;
287 dev_priv->pch_id = id;
292 DRM_DEBUG_KMS("No PCH found.\n");
297 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
298 struct drm_file *file_priv)
300 struct drm_i915_private *dev_priv = to_i915(dev);
301 struct pci_dev *pdev = dev_priv->drm.pdev;
302 drm_i915_getparam_t *param = data;
305 switch (param->param) {
306 case I915_PARAM_IRQ_ACTIVE:
307 case I915_PARAM_ALLOW_BATCHBUFFER:
308 case I915_PARAM_LAST_DISPATCH:
309 case I915_PARAM_HAS_EXEC_CONSTANTS:
310 /* Reject all old ums/dri params. */
312 case I915_PARAM_CHIPSET_ID:
313 value = pdev->device;
315 case I915_PARAM_REVISION:
316 value = pdev->revision;
318 case I915_PARAM_NUM_FENCES_AVAIL:
319 value = dev_priv->num_fence_regs;
321 case I915_PARAM_HAS_OVERLAY:
322 value = dev_priv->overlay ? 1 : 0;
324 case I915_PARAM_HAS_BSD:
325 value = !!dev_priv->engine[VCS];
327 case I915_PARAM_HAS_BLT:
328 value = !!dev_priv->engine[BCS];
330 case I915_PARAM_HAS_VEBOX:
331 value = !!dev_priv->engine[VECS];
333 case I915_PARAM_HAS_BSD2:
334 value = !!dev_priv->engine[VCS2];
336 case I915_PARAM_HAS_LLC:
337 value = HAS_LLC(dev_priv);
339 case I915_PARAM_HAS_WT:
340 value = HAS_WT(dev_priv);
342 case I915_PARAM_HAS_ALIASING_PPGTT:
343 value = USES_PPGTT(dev_priv);
345 case I915_PARAM_HAS_SEMAPHORES:
346 value = HAS_LEGACY_SEMAPHORES(dev_priv);
348 case I915_PARAM_HAS_SECURE_BATCHES:
349 value = capable(CAP_SYS_ADMIN);
351 case I915_PARAM_CMD_PARSER_VERSION:
352 value = i915_cmd_parser_get_version(dev_priv);
354 case I915_PARAM_SUBSLICE_TOTAL:
355 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
359 case I915_PARAM_EU_TOTAL:
360 value = INTEL_INFO(dev_priv)->sseu.eu_total;
364 case I915_PARAM_HAS_GPU_RESET:
365 value = i915_modparams.enable_hangcheck &&
366 intel_has_gpu_reset(dev_priv);
367 if (value && intel_has_reset_engine(dev_priv))
370 case I915_PARAM_HAS_RESOURCE_STREAMER:
371 value = HAS_RESOURCE_STREAMER(dev_priv);
373 case I915_PARAM_HAS_POOLED_EU:
374 value = HAS_POOLED_EU(dev_priv);
376 case I915_PARAM_MIN_EU_IN_POOL:
377 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
379 case I915_PARAM_HUC_STATUS:
380 intel_runtime_pm_get(dev_priv);
381 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
382 intel_runtime_pm_put(dev_priv);
384 case I915_PARAM_MMAP_GTT_VERSION:
385 /* Though we've started our numbering from 1, and so class all
386 * earlier versions as 0, in effect their value is undefined as
387 * the ioctl will report EINVAL for the unknown param!
389 value = i915_gem_mmap_gtt_version();
391 case I915_PARAM_HAS_SCHEDULER:
392 value = dev_priv->caps.scheduler;
395 case I915_PARAM_MMAP_VERSION:
396 /* Remember to bump this if the version changes! */
397 case I915_PARAM_HAS_GEM:
398 case I915_PARAM_HAS_PAGEFLIPPING:
399 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
400 case I915_PARAM_HAS_RELAXED_FENCING:
401 case I915_PARAM_HAS_COHERENT_RINGS:
402 case I915_PARAM_HAS_RELAXED_DELTA:
403 case I915_PARAM_HAS_GEN7_SOL_RESET:
404 case I915_PARAM_HAS_WAIT_TIMEOUT:
405 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
406 case I915_PARAM_HAS_PINNED_BATCHES:
407 case I915_PARAM_HAS_EXEC_NO_RELOC:
408 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
409 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
410 case I915_PARAM_HAS_EXEC_SOFTPIN:
411 case I915_PARAM_HAS_EXEC_ASYNC:
412 case I915_PARAM_HAS_EXEC_FENCE:
413 case I915_PARAM_HAS_EXEC_CAPTURE:
414 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
415 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
416 /* For the time being all of these are always true;
417 * if some supported hardware does not have one of these
418 * features this value needs to be provided from
419 * INTEL_INFO(), a feature macro, or similar.
423 case I915_PARAM_HAS_CONTEXT_ISOLATION:
424 value = intel_engines_has_context_isolation(dev_priv);
426 case I915_PARAM_SLICE_MASK:
427 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
431 case I915_PARAM_SUBSLICE_MASK:
432 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
436 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
437 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
440 DRM_DEBUG("Unknown parameter %d\n", param->param);
444 if (put_user(value, param->value))
450 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
452 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
454 dev_priv->bridge_dev =
455 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
456 if (!dev_priv->bridge_dev) {
457 DRM_ERROR("bridge device not found\n");
463 /* Allocate space for the MCH regs if needed, return nonzero on error */
465 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
467 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
468 u32 temp_lo, temp_hi = 0;
472 if (INTEL_GEN(dev_priv) >= 4)
473 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
474 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
475 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
477 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
480 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
484 /* Get some space for it */
485 dev_priv->mch_res.name = "i915 MCHBAR";
486 dev_priv->mch_res.flags = IORESOURCE_MEM;
487 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
489 MCHBAR_SIZE, MCHBAR_SIZE,
491 0, pcibios_align_resource,
492 dev_priv->bridge_dev);
494 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
495 dev_priv->mch_res.start = 0;
499 if (INTEL_GEN(dev_priv) >= 4)
500 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
501 upper_32_bits(dev_priv->mch_res.start));
503 pci_write_config_dword(dev_priv->bridge_dev, reg,
504 lower_32_bits(dev_priv->mch_res.start));
508 /* Setup MCHBAR if possible, return true if we should disable it again */
510 intel_setup_mchbar(struct drm_i915_private *dev_priv)
512 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
516 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
519 dev_priv->mchbar_need_disable = false;
521 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
522 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
523 enabled = !!(temp & DEVEN_MCHBAR_EN);
525 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
529 /* If it's already enabled, don't have to do anything */
533 if (intel_alloc_mchbar_resource(dev_priv))
536 dev_priv->mchbar_need_disable = true;
538 /* Space is allocated or reserved, so enable it. */
539 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
540 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
541 temp | DEVEN_MCHBAR_EN);
543 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
544 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
549 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
551 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
553 if (dev_priv->mchbar_need_disable) {
554 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
557 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
559 deven_val &= ~DEVEN_MCHBAR_EN;
560 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
565 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
568 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
573 if (dev_priv->mch_res.start)
574 release_resource(&dev_priv->mch_res);
577 /* true = enable decode, false = disable decoder */
578 static unsigned int i915_vga_set_decode(void *cookie, bool state)
580 struct drm_i915_private *dev_priv = cookie;
582 intel_modeset_vga_set_state(dev_priv, state);
584 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
585 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
587 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
590 static int i915_resume_switcheroo(struct drm_device *dev);
591 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
593 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
595 struct drm_device *dev = pci_get_drvdata(pdev);
596 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
598 if (state == VGA_SWITCHEROO_ON) {
599 pr_info("switched on\n");
600 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
601 /* i915 resume handler doesn't set to D0 */
602 pci_set_power_state(pdev, PCI_D0);
603 i915_resume_switcheroo(dev);
604 dev->switch_power_state = DRM_SWITCH_POWER_ON;
606 pr_info("switched off\n");
607 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
608 i915_suspend_switcheroo(dev, pmm);
609 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
613 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
615 struct drm_device *dev = pci_get_drvdata(pdev);
618 * FIXME: open_count is protected by drm_global_mutex but that would lead to
619 * locking inversion with the driver load path. And the access here is
620 * completely racy anyway. So don't bother with locking for now.
622 return dev->open_count == 0;
625 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
626 .set_gpu_state = i915_switcheroo_set_state,
628 .can_switch = i915_switcheroo_can_switch,
631 static void i915_gem_fini(struct drm_i915_private *dev_priv)
633 /* Flush any outstanding unpin_work. */
634 i915_gem_drain_workqueue(dev_priv);
636 mutex_lock(&dev_priv->drm.struct_mutex);
637 intel_uc_fini_hw(dev_priv);
638 intel_uc_fini(dev_priv);
639 i915_gem_cleanup_engines(dev_priv);
640 i915_gem_contexts_fini(dev_priv);
641 mutex_unlock(&dev_priv->drm.struct_mutex);
643 intel_uc_fini_misc(dev_priv);
644 i915_gem_cleanup_userptr(dev_priv);
646 i915_gem_drain_freed_objects(dev_priv);
648 WARN_ON(!list_empty(&dev_priv->contexts.list));
651 static int i915_load_modeset_init(struct drm_device *dev)
653 struct drm_i915_private *dev_priv = to_i915(dev);
654 struct pci_dev *pdev = dev_priv->drm.pdev;
657 if (i915_inject_load_failure())
660 intel_bios_init(dev_priv);
662 /* If we have > 1 VGA cards, then we need to arbitrate access
663 * to the common VGA resources.
665 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
666 * then we do not take part in VGA arbitration and the
667 * vga_client_register() fails with -ENODEV.
669 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
670 if (ret && ret != -ENODEV)
673 intel_register_dsm_handler();
675 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
677 goto cleanup_vga_client;
679 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
680 intel_update_rawclk(dev_priv);
682 intel_power_domains_init_hw(dev_priv, false);
684 intel_csr_ucode_init(dev_priv);
686 ret = intel_irq_install(dev_priv);
690 intel_setup_gmbus(dev_priv);
692 /* Important: The output setup functions called by modeset_init need
693 * working irqs for e.g. gmbus and dp aux transfers. */
694 ret = intel_modeset_init(dev);
698 intel_uc_init_fw(dev_priv);
700 ret = i915_gem_init(dev_priv);
704 intel_setup_overlay(dev_priv);
706 if (INTEL_INFO(dev_priv)->num_pipes == 0)
709 ret = intel_fbdev_init(dev);
713 /* Only enable hotplug handling once the fbdev is fully set up. */
714 intel_hpd_init(dev_priv);
719 if (i915_gem_suspend(dev_priv))
720 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
721 i915_gem_fini(dev_priv);
723 intel_uc_fini_fw(dev_priv);
725 drm_irq_uninstall(dev);
726 intel_teardown_gmbus(dev_priv);
728 intel_csr_ucode_fini(dev_priv);
729 intel_power_domains_fini(dev_priv);
730 vga_switcheroo_unregister_client(pdev);
732 vga_client_register(pdev, NULL, NULL, NULL);
737 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
739 struct apertures_struct *ap;
740 struct pci_dev *pdev = dev_priv->drm.pdev;
741 struct i915_ggtt *ggtt = &dev_priv->ggtt;
745 ap = alloc_apertures(1);
749 ap->ranges[0].base = ggtt->gmadr.start;
750 ap->ranges[0].size = ggtt->mappable_end;
753 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
755 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
762 #if !defined(CONFIG_VGA_CONSOLE)
763 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
767 #elif !defined(CONFIG_DUMMY_CONSOLE)
768 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
773 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
777 DRM_INFO("Replacing VGA console driver\n");
780 if (con_is_bound(&vga_con))
781 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
783 ret = do_unregister_con_driver(&vga_con);
785 /* Ignore "already unregistered". */
795 static void intel_init_dpio(struct drm_i915_private *dev_priv)
798 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
799 * CHV x1 PHY (DP/HDMI D)
800 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
802 if (IS_CHERRYVIEW(dev_priv)) {
803 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
804 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
805 } else if (IS_VALLEYVIEW(dev_priv)) {
806 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
810 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
813 * The i915 workqueue is primarily used for batched retirement of
814 * requests (and thus managing bo) once the task has been completed
815 * by the GPU. i915_retire_requests() is called directly when we
816 * need high-priority retirement, such as waiting for an explicit
819 * It is also used for periodic low-priority events, such as
820 * idle-timers and recording error state.
822 * All tasks on the workqueue are expected to acquire the dev mutex
823 * so there is no point in running more than one instance of the
824 * workqueue at any time. Use an ordered one.
826 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
827 if (dev_priv->wq == NULL)
830 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
831 if (dev_priv->hotplug.dp_wq == NULL)
837 destroy_workqueue(dev_priv->wq);
839 DRM_ERROR("Failed to allocate workqueues.\n");
844 static void i915_engines_cleanup(struct drm_i915_private *i915)
846 struct intel_engine_cs *engine;
847 enum intel_engine_id id;
849 for_each_engine(engine, i915, id)
853 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
855 destroy_workqueue(dev_priv->hotplug.dp_wq);
856 destroy_workqueue(dev_priv->wq);
860 * We don't keep the workarounds for pre-production hardware, so we expect our
861 * driver to fail on these machines in one way or another. A little warning on
862 * dmesg may help both the user and the bug triagers.
864 * Our policy for removing pre-production workarounds is to keep the
865 * current gen workarounds as a guide to the bring-up of the next gen
866 * (workarounds have a habit of persisting!). Anything older than that
867 * should be removed along with the complications they introduce.
869 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
873 pre |= IS_HSW_EARLY_SDV(dev_priv);
874 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
875 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
878 DRM_ERROR("This is a pre-production stepping. "
879 "It may not be fully functional.\n");
880 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
885 * i915_driver_init_early - setup state not requiring device access
886 * @dev_priv: device private
887 * @ent: the matching pci_device_id
889 * Initialize everything that is a "SW-only" state, that is state not
890 * requiring accessing the device or exposing the driver via kernel internal
891 * or userspace interfaces. Example steps belonging here: lock initialization,
892 * system memory allocation, setting up device specific attributes and
893 * function hooks not requiring accessing the device.
895 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
896 const struct pci_device_id *ent)
898 const struct intel_device_info *match_info =
899 (struct intel_device_info *)ent->driver_data;
900 struct intel_device_info *device_info;
903 if (i915_inject_load_failure())
906 /* Setup the write-once "constant" device info */
907 device_info = mkwrite_device_info(dev_priv);
908 memcpy(device_info, match_info, sizeof(*device_info));
909 device_info->device_id = dev_priv->drm.pdev->device;
911 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
912 sizeof(device_info->platform_mask) * BITS_PER_BYTE);
913 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
914 spin_lock_init(&dev_priv->irq_lock);
915 spin_lock_init(&dev_priv->gpu_error.lock);
916 mutex_init(&dev_priv->backlight_lock);
917 spin_lock_init(&dev_priv->uncore.lock);
919 mutex_init(&dev_priv->sb_lock);
920 mutex_init(&dev_priv->modeset_restore_lock);
921 mutex_init(&dev_priv->av_mutex);
922 mutex_init(&dev_priv->wm.wm_mutex);
923 mutex_init(&dev_priv->pps_mutex);
925 intel_uc_init_early(dev_priv);
926 i915_memcpy_init_early(dev_priv);
928 ret = i915_workqueues_init(dev_priv);
932 /* This must be called before any calls to HAS_PCH_* */
933 intel_detect_pch(dev_priv);
935 intel_pm_setup(dev_priv);
936 intel_init_dpio(dev_priv);
937 intel_power_domains_init(dev_priv);
938 intel_irq_init(dev_priv);
939 intel_hangcheck_init(dev_priv);
940 intel_init_display_hooks(dev_priv);
941 intel_init_clock_gating_hooks(dev_priv);
942 intel_init_audio_hooks(dev_priv);
943 ret = i915_gem_load_init(dev_priv);
947 intel_display_crc_init(dev_priv);
949 intel_detect_preproduction_hw(dev_priv);
954 intel_irq_fini(dev_priv);
955 i915_workqueues_cleanup(dev_priv);
957 i915_engines_cleanup(dev_priv);
962 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
963 * @dev_priv: device private
965 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
967 i915_gem_load_cleanup(dev_priv);
968 intel_irq_fini(dev_priv);
969 i915_workqueues_cleanup(dev_priv);
970 i915_engines_cleanup(dev_priv);
973 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
975 struct pci_dev *pdev = dev_priv->drm.pdev;
979 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
981 * Before gen4, the registers and the GTT are behind different BARs.
982 * However, from gen4 onwards, the registers and the GTT are shared
983 * in the same BAR, so we want to restrict this ioremap from
984 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
985 * the register BAR remains the same size for all the earlier
986 * generations up to Ironlake.
988 if (INTEL_GEN(dev_priv) < 5)
989 mmio_size = 512 * 1024;
991 mmio_size = 2 * 1024 * 1024;
992 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
993 if (dev_priv->regs == NULL) {
994 DRM_ERROR("failed to map registers\n");
999 /* Try to make sure MCHBAR is enabled before poking at it */
1000 intel_setup_mchbar(dev_priv);
1005 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1007 struct pci_dev *pdev = dev_priv->drm.pdev;
1009 intel_teardown_mchbar(dev_priv);
1010 pci_iounmap(pdev, dev_priv->regs);
1014 * i915_driver_init_mmio - setup device MMIO
1015 * @dev_priv: device private
1017 * Setup minimal device state necessary for MMIO accesses later in the
1018 * initialization sequence. The setup here should avoid any other device-wide
1019 * side effects or exposing the driver via kernel internal or user space
1022 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1026 if (i915_inject_load_failure())
1029 if (i915_get_bridge_dev(dev_priv))
1032 ret = i915_mmio_setup(dev_priv);
1036 intel_uncore_init(dev_priv);
1038 intel_uc_init_mmio(dev_priv);
1040 ret = intel_engines_init_mmio(dev_priv);
1044 i915_gem_init_mmio(dev_priv);
1049 intel_uncore_fini(dev_priv);
1051 pci_dev_put(dev_priv->bridge_dev);
1057 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1058 * @dev_priv: device private
1060 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1062 intel_uncore_fini(dev_priv);
1063 i915_mmio_cleanup(dev_priv);
1064 pci_dev_put(dev_priv->bridge_dev);
1067 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1070 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1071 * user's requested state against the hardware/driver capabilities. We
1072 * do this now so that we can print out any log messages once rather
1073 * than every time we check intel_enable_ppgtt().
1075 i915_modparams.enable_ppgtt =
1076 intel_sanitize_enable_ppgtt(dev_priv,
1077 i915_modparams.enable_ppgtt);
1078 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1080 intel_uc_sanitize_options(dev_priv);
1082 intel_gvt_sanitize_options(dev_priv);
1086 * i915_driver_init_hw - setup state requiring device access
1087 * @dev_priv: device private
1089 * Setup state that requires accessing the device, but doesn't require
1090 * exposing the driver via kernel internal or userspace interfaces.
1092 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1094 struct pci_dev *pdev = dev_priv->drm.pdev;
1097 if (i915_inject_load_failure())
1100 intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1102 intel_sanitize_options(dev_priv);
1104 i915_perf_init(dev_priv);
1106 ret = i915_ggtt_probe_hw(dev_priv);
1111 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1112 * otherwise the vga fbdev driver falls over.
1114 ret = i915_kick_out_firmware_fb(dev_priv);
1116 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1120 ret = i915_kick_out_vgacon(dev_priv);
1122 DRM_ERROR("failed to remove conflicting VGA console\n");
1126 ret = i915_ggtt_init_hw(dev_priv);
1130 ret = i915_ggtt_enable_hw(dev_priv);
1132 DRM_ERROR("failed to enable GGTT\n");
1136 pci_set_master(pdev);
1138 /* overlay on gen2 is broken and can't address above 1G */
1139 if (IS_GEN2(dev_priv)) {
1140 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1142 DRM_ERROR("failed to set DMA mask\n");
1148 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1149 * using 32bit addressing, overwriting memory if HWS is located
1152 * The documentation also mentions an issue with undefined
1153 * behaviour if any general state is accessed within a page above 4GB,
1154 * which also needs to be handled carefully.
1156 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1157 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1160 DRM_ERROR("failed to set DMA mask\n");
1166 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1167 PM_QOS_DEFAULT_VALUE);
1169 intel_uncore_sanitize(dev_priv);
1171 intel_opregion_setup(dev_priv);
1173 i915_gem_load_init_fences(dev_priv);
1175 /* On the 945G/GM, the chipset reports the MSI capability on the
1176 * integrated graphics even though the support isn't actually there
1177 * according to the published specs. It doesn't appear to function
1178 * correctly in testing on 945G.
1179 * This may be a side effect of MSI having been made available for PEG
1180 * and the registers being closely associated.
1182 * According to chipset errata, on the 965GM, MSI interrupts may
1183 * be lost or delayed, and was defeatured. MSI interrupts seem to
1184 * get lost on g4x as well, and interrupt delivery seems to stay
1185 * properly dead afterwards. So we'll just disable them for all
1186 * pre-gen5 chipsets.
1188 if (INTEL_GEN(dev_priv) >= 5) {
1189 if (pci_enable_msi(pdev) < 0)
1190 DRM_DEBUG_DRIVER("can't enable MSI");
1193 ret = intel_gvt_init(dev_priv);
1200 i915_ggtt_cleanup_hw(dev_priv);
1202 i915_perf_fini(dev_priv);
1207 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1208 * @dev_priv: device private
1210 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1212 struct pci_dev *pdev = dev_priv->drm.pdev;
1214 i915_perf_fini(dev_priv);
1216 if (pdev->msi_enabled)
1217 pci_disable_msi(pdev);
1219 pm_qos_remove_request(&dev_priv->pm_qos);
1220 i915_ggtt_cleanup_hw(dev_priv);
1224 * i915_driver_register - register the driver with the rest of the system
1225 * @dev_priv: device private
1227 * Perform any steps necessary to make the driver available via kernel
1228 * internal or userspace interfaces.
1230 static void i915_driver_register(struct drm_i915_private *dev_priv)
1232 struct drm_device *dev = &dev_priv->drm;
1234 i915_gem_shrinker_register(dev_priv);
1235 i915_pmu_register(dev_priv);
1238 * Notify a valid surface after modesetting,
1239 * when running inside a VM.
1241 if (intel_vgpu_active(dev_priv))
1242 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1244 /* Reveal our presence to userspace */
1245 if (drm_dev_register(dev, 0) == 0) {
1246 i915_debugfs_register(dev_priv);
1247 i915_guc_log_register(dev_priv);
1248 i915_setup_sysfs(dev_priv);
1250 /* Depends on sysfs having been initialized */
1251 i915_perf_register(dev_priv);
1253 DRM_ERROR("Failed to register driver for userspace access!\n");
1255 if (INTEL_INFO(dev_priv)->num_pipes) {
1256 /* Must be done after probing outputs */
1257 intel_opregion_register(dev_priv);
1258 acpi_video_register();
1261 if (IS_GEN5(dev_priv))
1262 intel_gpu_ips_init(dev_priv);
1264 intel_audio_init(dev_priv);
1267 * Some ports require correctly set-up hpd registers for detection to
1268 * work properly (leading to ghost connected connector status), e.g. VGA
1269 * on gm45. Hence we can only set up the initial fbdev config after hpd
1270 * irqs are fully enabled. We do it last so that the async config
1271 * cannot run before the connectors are registered.
1273 intel_fbdev_initial_config_async(dev);
1276 * We need to coordinate the hotplugs with the asynchronous fbdev
1277 * configuration, for which we use the fbdev->async_cookie.
1279 if (INTEL_INFO(dev_priv)->num_pipes)
1280 drm_kms_helper_poll_init(dev);
1284 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1285 * @dev_priv: device private
1287 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1289 intel_fbdev_unregister(dev_priv);
1290 intel_audio_deinit(dev_priv);
1293 * After flushing the fbdev (incl. a late async config which will
1294 * have delayed queuing of a hotplug event), then flush the hotplug
1297 drm_kms_helper_poll_fini(&dev_priv->drm);
1299 intel_gpu_ips_teardown();
1300 acpi_video_unregister();
1301 intel_opregion_unregister(dev_priv);
1303 i915_perf_unregister(dev_priv);
1304 i915_pmu_unregister(dev_priv);
1306 i915_teardown_sysfs(dev_priv);
1307 i915_guc_log_unregister(dev_priv);
1308 drm_dev_unregister(&dev_priv->drm);
1310 i915_gem_shrinker_unregister(dev_priv);
1313 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1315 if (drm_debug & DRM_UT_DRIVER) {
1316 struct drm_printer p = drm_debug_printer("i915 device info:");
1318 intel_device_info_dump(&dev_priv->info, &p);
1319 intel_device_info_dump_runtime(&dev_priv->info, &p);
1322 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1323 DRM_INFO("DRM_I915_DEBUG enabled\n");
1324 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1325 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1329 * i915_driver_load - setup chip and create an initial config
1331 * @ent: matching PCI ID entry
1333 * The driver load routine has to do several things:
1334 * - drive output discovery via intel_modeset_init()
1335 * - initialize the memory manager
1336 * - allocate initial config memory
1337 * - setup the DRM framebuffer with the allocated memory
1339 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1341 const struct intel_device_info *match_info =
1342 (struct intel_device_info *)ent->driver_data;
1343 struct drm_i915_private *dev_priv;
1346 /* Enable nuclear pageflip on ILK+ */
1347 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1348 driver.driver_features &= ~DRIVER_ATOMIC;
1351 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1353 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1355 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1359 dev_priv->drm.pdev = pdev;
1360 dev_priv->drm.dev_private = dev_priv;
1362 ret = pci_enable_device(pdev);
1366 pci_set_drvdata(pdev, &dev_priv->drm);
1368 * Disable the system suspend direct complete optimization, which can
1369 * leave the device suspended skipping the driver's suspend handlers
1370 * if the device was already runtime suspended. This is needed due to
1371 * the difference in our runtime and system suspend sequence and
1372 * becaue the HDA driver may require us to enable the audio power
1373 * domain during system suspend.
1375 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1377 ret = i915_driver_init_early(dev_priv, ent);
1379 goto out_pci_disable;
1381 intel_runtime_pm_get(dev_priv);
1383 ret = i915_driver_init_mmio(dev_priv);
1385 goto out_runtime_pm_put;
1387 ret = i915_driver_init_hw(dev_priv);
1389 goto out_cleanup_mmio;
1392 * TODO: move the vblank init and parts of modeset init steps into one
1393 * of the i915_driver_init_/i915_driver_register functions according
1394 * to the role/effect of the given init step.
1396 if (INTEL_INFO(dev_priv)->num_pipes) {
1397 ret = drm_vblank_init(&dev_priv->drm,
1398 INTEL_INFO(dev_priv)->num_pipes);
1400 goto out_cleanup_hw;
1403 ret = i915_load_modeset_init(&dev_priv->drm);
1405 goto out_cleanup_hw;
1407 i915_driver_register(dev_priv);
1409 intel_runtime_pm_enable(dev_priv);
1411 intel_init_ipc(dev_priv);
1413 intel_runtime_pm_put(dev_priv);
1415 i915_welcome_messages(dev_priv);
1420 i915_driver_cleanup_hw(dev_priv);
1422 i915_driver_cleanup_mmio(dev_priv);
1424 intel_runtime_pm_put(dev_priv);
1425 i915_driver_cleanup_early(dev_priv);
1427 pci_disable_device(pdev);
1429 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1430 drm_dev_fini(&dev_priv->drm);
1436 void i915_driver_unload(struct drm_device *dev)
1438 struct drm_i915_private *dev_priv = to_i915(dev);
1439 struct pci_dev *pdev = dev_priv->drm.pdev;
1441 i915_driver_unregister(dev_priv);
1443 if (i915_gem_suspend(dev_priv))
1444 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1446 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1448 drm_atomic_helper_shutdown(dev);
1450 intel_gvt_cleanup(dev_priv);
1452 intel_modeset_cleanup(dev);
1454 intel_bios_cleanup(dev_priv);
1456 vga_switcheroo_unregister_client(pdev);
1457 vga_client_register(pdev, NULL, NULL, NULL);
1459 intel_csr_ucode_fini(dev_priv);
1461 /* Free error state after interrupts are fully disabled. */
1462 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1463 i915_reset_error_state(dev_priv);
1465 i915_gem_fini(dev_priv);
1466 intel_uc_fini_fw(dev_priv);
1467 intel_fbc_cleanup_cfb(dev_priv);
1469 intel_power_domains_fini(dev_priv);
1471 i915_driver_cleanup_hw(dev_priv);
1472 i915_driver_cleanup_mmio(dev_priv);
1474 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1477 static void i915_driver_release(struct drm_device *dev)
1479 struct drm_i915_private *dev_priv = to_i915(dev);
1481 i915_driver_cleanup_early(dev_priv);
1482 drm_dev_fini(&dev_priv->drm);
1487 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1489 struct drm_i915_private *i915 = to_i915(dev);
1492 ret = i915_gem_open(i915, file);
1500 * i915_driver_lastclose - clean up after all DRM clients have exited
1503 * Take care of cleaning up after all DRM clients have exited. In the
1504 * mode setting case, we want to restore the kernel's initial mode (just
1505 * in case the last client left us in a bad state).
1507 * Additionally, in the non-mode setting case, we'll tear down the GTT
1508 * and DMA structures, since the kernel won't be using them, and clea
1511 static void i915_driver_lastclose(struct drm_device *dev)
1513 intel_fbdev_restore_mode(dev);
1514 vga_switcheroo_process_delayed_switch();
1517 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1519 struct drm_i915_file_private *file_priv = file->driver_priv;
1521 mutex_lock(&dev->struct_mutex);
1522 i915_gem_context_close(file);
1523 i915_gem_release(dev, file);
1524 mutex_unlock(&dev->struct_mutex);
1529 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1531 struct drm_device *dev = &dev_priv->drm;
1532 struct intel_encoder *encoder;
1534 drm_modeset_lock_all(dev);
1535 for_each_intel_encoder(dev, encoder)
1536 if (encoder->suspend)
1537 encoder->suspend(encoder);
1538 drm_modeset_unlock_all(dev);
1541 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1543 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1545 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1547 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1548 if (acpi_target_system_state() < ACPI_STATE_S3)
1554 static int i915_drm_suspend(struct drm_device *dev)
1556 struct drm_i915_private *dev_priv = to_i915(dev);
1557 struct pci_dev *pdev = dev_priv->drm.pdev;
1558 pci_power_t opregion_target_state;
1561 /* ignore lid events during suspend */
1562 mutex_lock(&dev_priv->modeset_restore_lock);
1563 dev_priv->modeset_restore = MODESET_SUSPENDED;
1564 mutex_unlock(&dev_priv->modeset_restore_lock);
1566 disable_rpm_wakeref_asserts(dev_priv);
1568 /* We do a lot of poking in a lot of registers, make sure they work
1570 intel_display_set_init_power(dev_priv, true);
1572 drm_kms_helper_poll_disable(dev);
1574 pci_save_state(pdev);
1576 error = i915_gem_suspend(dev_priv);
1579 "GEM idle failed, resume might fail\n");
1583 intel_display_suspend(dev);
1585 intel_dp_mst_suspend(dev);
1587 intel_runtime_pm_disable_interrupts(dev_priv);
1588 intel_hpd_cancel_work(dev_priv);
1590 intel_suspend_encoders(dev_priv);
1592 intel_suspend_hw(dev_priv);
1594 i915_gem_suspend_gtt_mappings(dev_priv);
1596 i915_save_state(dev_priv);
1598 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1599 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1601 intel_uncore_suspend(dev_priv);
1602 intel_opregion_unregister(dev_priv);
1604 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1606 dev_priv->suspend_count++;
1608 intel_csr_ucode_suspend(dev_priv);
1611 enable_rpm_wakeref_asserts(dev_priv);
1616 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1618 struct drm_i915_private *dev_priv = to_i915(dev);
1619 struct pci_dev *pdev = dev_priv->drm.pdev;
1622 disable_rpm_wakeref_asserts(dev_priv);
1624 intel_display_set_init_power(dev_priv, false);
1627 * In case of firmware assisted context save/restore don't manually
1628 * deinit the power domains. This also means the CSR/DMC firmware will
1629 * stay active, it will power down any HW resources as required and
1630 * also enable deeper system power states that would be blocked if the
1631 * firmware was inactive.
1633 if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1634 dev_priv->csr.dmc_payload == NULL) {
1635 intel_power_domains_suspend(dev_priv);
1636 dev_priv->power_domains_suspended = true;
1640 if (IS_GEN9_LP(dev_priv))
1641 bxt_enable_dc9(dev_priv);
1642 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1643 hsw_enable_pc8(dev_priv);
1644 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1645 ret = vlv_suspend_complete(dev_priv);
1648 DRM_ERROR("Suspend complete failed: %d\n", ret);
1649 if (dev_priv->power_domains_suspended) {
1650 intel_power_domains_init_hw(dev_priv, true);
1651 dev_priv->power_domains_suspended = false;
1657 pci_disable_device(pdev);
1659 * During hibernation on some platforms the BIOS may try to access
1660 * the device even though it's already in D3 and hang the machine. So
1661 * leave the device in D0 on those platforms and hope the BIOS will
1662 * power down the device properly. The issue was seen on multiple old
1663 * GENs with different BIOS vendors, so having an explicit blacklist
1664 * is inpractical; apply the workaround on everything pre GEN6. The
1665 * platforms where the issue was seen:
1666 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1670 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1671 pci_set_power_state(pdev, PCI_D3hot);
1674 enable_rpm_wakeref_asserts(dev_priv);
1679 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1684 DRM_ERROR("dev: %p\n", dev);
1685 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1689 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1690 state.event != PM_EVENT_FREEZE))
1693 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1696 error = i915_drm_suspend(dev);
1700 return i915_drm_suspend_late(dev, false);
1703 static int i915_drm_resume(struct drm_device *dev)
1705 struct drm_i915_private *dev_priv = to_i915(dev);
1708 disable_rpm_wakeref_asserts(dev_priv);
1709 intel_sanitize_gt_powersave(dev_priv);
1711 ret = i915_ggtt_enable_hw(dev_priv);
1713 DRM_ERROR("failed to re-enable GGTT\n");
1715 intel_csr_ucode_resume(dev_priv);
1717 i915_restore_state(dev_priv);
1718 intel_pps_unlock_regs_wa(dev_priv);
1719 intel_opregion_setup(dev_priv);
1721 intel_init_pch_refclk(dev_priv);
1724 * Interrupts have to be enabled before any batches are run. If not the
1725 * GPU will hang. i915_gem_init_hw() will initiate batches to
1726 * update/restore the context.
1728 * drm_mode_config_reset() needs AUX interrupts.
1730 * Modeset enabling in intel_modeset_init_hw() also needs working
1733 intel_runtime_pm_enable_interrupts(dev_priv);
1735 drm_mode_config_reset(dev);
1737 i915_gem_resume(dev_priv);
1739 intel_modeset_init_hw(dev);
1740 intel_init_clock_gating(dev_priv);
1742 spin_lock_irq(&dev_priv->irq_lock);
1743 if (dev_priv->display.hpd_irq_setup)
1744 dev_priv->display.hpd_irq_setup(dev_priv);
1745 spin_unlock_irq(&dev_priv->irq_lock);
1747 intel_dp_mst_resume(dev);
1749 intel_display_resume(dev);
1751 drm_kms_helper_poll_enable(dev);
1754 * ... but also need to make sure that hotplug processing
1755 * doesn't cause havoc. Like in the driver load code we don't
1756 * bother with the tiny race here where we might loose hotplug
1759 intel_hpd_init(dev_priv);
1761 intel_opregion_register(dev_priv);
1763 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1765 mutex_lock(&dev_priv->modeset_restore_lock);
1766 dev_priv->modeset_restore = MODESET_DONE;
1767 mutex_unlock(&dev_priv->modeset_restore_lock);
1769 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1771 enable_rpm_wakeref_asserts(dev_priv);
1776 static int i915_drm_resume_early(struct drm_device *dev)
1778 struct drm_i915_private *dev_priv = to_i915(dev);
1779 struct pci_dev *pdev = dev_priv->drm.pdev;
1783 * We have a resume ordering issue with the snd-hda driver also
1784 * requiring our device to be power up. Due to the lack of a
1785 * parent/child relationship we currently solve this with an early
1788 * FIXME: This should be solved with a special hdmi sink device or
1789 * similar so that power domains can be employed.
1793 * Note that we need to set the power state explicitly, since we
1794 * powered off the device during freeze and the PCI core won't power
1795 * it back up for us during thaw. Powering off the device during
1796 * freeze is not a hard requirement though, and during the
1797 * suspend/resume phases the PCI core makes sure we get here with the
1798 * device powered on. So in case we change our freeze logic and keep
1799 * the device powered we can also remove the following set power state
1802 ret = pci_set_power_state(pdev, PCI_D0);
1804 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1809 * Note that pci_enable_device() first enables any parent bridge
1810 * device and only then sets the power state for this device. The
1811 * bridge enabling is a nop though, since bridge devices are resumed
1812 * first. The order of enabling power and enabling the device is
1813 * imposed by the PCI core as described above, so here we preserve the
1814 * same order for the freeze/thaw phases.
1816 * TODO: eventually we should remove pci_disable_device() /
1817 * pci_enable_enable_device() from suspend/resume. Due to how they
1818 * depend on the device enable refcount we can't anyway depend on them
1819 * disabling/enabling the device.
1821 if (pci_enable_device(pdev)) {
1826 pci_set_master(pdev);
1828 disable_rpm_wakeref_asserts(dev_priv);
1830 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1831 ret = vlv_resume_prepare(dev_priv, false);
1833 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1836 intel_uncore_resume_early(dev_priv);
1838 if (IS_GEN9_LP(dev_priv)) {
1839 gen9_sanitize_dc_state(dev_priv);
1840 bxt_disable_dc9(dev_priv);
1841 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1842 hsw_disable_pc8(dev_priv);
1845 intel_uncore_sanitize(dev_priv);
1847 if (dev_priv->power_domains_suspended)
1848 intel_power_domains_init_hw(dev_priv, true);
1850 intel_display_set_init_power(dev_priv, true);
1852 i915_gem_sanitize(dev_priv);
1854 enable_rpm_wakeref_asserts(dev_priv);
1857 dev_priv->power_domains_suspended = false;
1862 static int i915_resume_switcheroo(struct drm_device *dev)
1866 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1869 ret = i915_drm_resume_early(dev);
1873 return i915_drm_resume(dev);
1877 * i915_reset - reset chip after a hang
1878 * @i915: #drm_i915_private to reset
1879 * @flags: Instructions
1881 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1884 * Caller must hold the struct_mutex.
1886 * Procedure is fairly simple:
1887 * - reset the chip using the reset reg
1888 * - re-init context state
1889 * - re-init hardware status page
1890 * - re-init ring buffer
1891 * - re-init interrupt state
1894 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1896 struct i915_gpu_error *error = &i915->gpu_error;
1901 lockdep_assert_held(&i915->drm.struct_mutex);
1902 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1904 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1907 /* Clear any previous failed attempts at recovery. Time to try again. */
1908 if (!i915_gem_unset_wedged(i915))
1911 if (!(flags & I915_RESET_QUIET))
1912 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1913 error->reset_count++;
1915 disable_irq(i915->drm.irq);
1916 ret = i915_gem_reset_prepare(i915);
1918 dev_err(i915->drm.dev, "GPU recovery failed\n");
1922 if (!intel_has_gpu_reset(i915)) {
1923 if (i915_modparams.reset)
1924 dev_err(i915->drm.dev, "GPU reset not supported\n");
1926 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1930 for (i = 0; i < 3; i++) {
1931 ret = intel_gpu_reset(i915, ALL_ENGINES);
1938 dev_err(i915->drm.dev, "Failed to reset chip\n");
1942 /* Ok, now get things going again... */
1945 * Everything depends on having the GTT running, so we need to start
1948 ret = i915_ggtt_enable_hw(i915);
1950 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1955 i915_gem_reset(i915);
1956 intel_overlay_reset(i915);
1959 * Next we need to restore the context, but we don't use those
1962 * Ring buffer needs to be re-initialized in the KMS case, or if X
1963 * was running at the time of the reset (i.e. we weren't VT
1966 ret = i915_gem_init_hw(i915);
1968 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1973 i915_queue_hangcheck(i915);
1976 i915_gem_reset_finish(i915);
1977 enable_irq(i915->drm.irq);
1980 clear_bit(I915_RESET_HANDOFF, &error->flags);
1981 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1986 * History tells us that if we cannot reset the GPU now, we
1987 * never will. This then impacts everything that is run
1988 * subsequently. On failing the reset, we mark the driver
1989 * as wedged, preventing further execution on the GPU.
1990 * We also want to go one step further and add a taint to the
1991 * kernel so that any subsequent faults can be traced back to
1992 * this failure. This is important for CI, where if the
1993 * GPU/driver fails we would like to reboot and restart testing
1994 * rather than continue on into oblivion. For everyone else,
1995 * the system should still plod along, but they have been warned!
1997 add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1999 i915_gem_set_wedged(i915);
2000 i915_retire_requests(i915);
2001 intel_gpu_reset(i915, ALL_ENGINES);
2005 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2006 struct intel_engine_cs *engine)
2008 return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2012 * i915_reset_engine - reset GPU engine to recover from a hang
2013 * @engine: engine to reset
2016 * Reset a specific GPU engine. Useful if a hang is detected.
2017 * Returns zero on successful reset or otherwise an error code.
2020 * - identifies the request that caused the hang and it is dropped
2021 * - reset engine (which will force the engine to idle)
2022 * - re-init/configure engine
2024 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2026 struct i915_gpu_error *error = &engine->i915->gpu_error;
2027 struct i915_request *active_request;
2030 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2032 active_request = i915_gem_reset_prepare_engine(engine);
2033 if (IS_ERR_OR_NULL(active_request)) {
2034 /* Either the previous reset failed, or we pardon the reset. */
2035 ret = PTR_ERR(active_request);
2039 if (!(flags & I915_RESET_QUIET)) {
2040 dev_notice(engine->i915->drm.dev,
2041 "Resetting %s after gpu hang\n", engine->name);
2043 error->reset_engine_count[engine->id]++;
2045 if (!engine->i915->guc.execbuf_client)
2046 ret = intel_gt_reset_engine(engine->i915, engine);
2048 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2050 /* If we fail here, we expect to fallback to a global reset */
2051 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2052 engine->i915->guc.execbuf_client ? "GuC " : "",
2058 * The request that caused the hang is stuck on elsp, we know the
2059 * active request and can drop it, adjust head to skip the offending
2060 * request to resume executing remaining requests in the queue.
2062 i915_gem_reset_engine(engine, active_request);
2065 * The engine and its registers (and workarounds in case of render)
2066 * have been reset to their default values. Follow the init_ring
2067 * process to program RING_MODE, HWSP and re-enable submission.
2069 ret = engine->init_hw(engine);
2074 i915_gem_reset_finish_engine(engine);
2078 static int i915_pm_suspend(struct device *kdev)
2080 struct pci_dev *pdev = to_pci_dev(kdev);
2081 struct drm_device *dev = pci_get_drvdata(pdev);
2084 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2088 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2091 return i915_drm_suspend(dev);
2094 static int i915_pm_suspend_late(struct device *kdev)
2096 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2099 * We have a suspend ordering issue with the snd-hda driver also
2100 * requiring our device to be power up. Due to the lack of a
2101 * parent/child relationship we currently solve this with an late
2104 * FIXME: This should be solved with a special hdmi sink device or
2105 * similar so that power domains can be employed.
2107 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2110 return i915_drm_suspend_late(dev, false);
2113 static int i915_pm_poweroff_late(struct device *kdev)
2115 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2117 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2120 return i915_drm_suspend_late(dev, true);
2123 static int i915_pm_resume_early(struct device *kdev)
2125 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2127 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2130 return i915_drm_resume_early(dev);
2133 static int i915_pm_resume(struct device *kdev)
2135 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2137 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2140 return i915_drm_resume(dev);
2143 /* freeze: before creating the hibernation_image */
2144 static int i915_pm_freeze(struct device *kdev)
2146 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2149 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2150 ret = i915_drm_suspend(dev);
2155 ret = i915_gem_freeze(kdev_to_i915(kdev));
2162 static int i915_pm_freeze_late(struct device *kdev)
2164 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2167 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2168 ret = i915_drm_suspend_late(dev, true);
2173 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2180 /* thaw: called after creating the hibernation image, but before turning off. */
2181 static int i915_pm_thaw_early(struct device *kdev)
2183 return i915_pm_resume_early(kdev);
2186 static int i915_pm_thaw(struct device *kdev)
2188 return i915_pm_resume(kdev);
2191 /* restore: called after loading the hibernation image. */
2192 static int i915_pm_restore_early(struct device *kdev)
2194 return i915_pm_resume_early(kdev);
2197 static int i915_pm_restore(struct device *kdev)
2199 return i915_pm_resume(kdev);
2203 * Save all Gunit registers that may be lost after a D3 and a subsequent
2204 * S0i[R123] transition. The list of registers needing a save/restore is
2205 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2206 * registers in the following way:
2207 * - Driver: saved/restored by the driver
2208 * - Punit : saved/restored by the Punit firmware
2209 * - No, w/o marking: no need to save/restore, since the register is R/O or
2210 * used internally by the HW in a way that doesn't depend
2211 * keeping the content across a suspend/resume.
2212 * - Debug : used for debugging
2214 * We save/restore all registers marked with 'Driver', with the following
2216 * - Registers out of use, including also registers marked with 'Debug'.
2217 * These have no effect on the driver's operation, so we don't save/restore
2218 * them to reduce the overhead.
2219 * - Registers that are fully setup by an initialization function called from
2220 * the resume path. For example many clock gating and RPS/RC6 registers.
2221 * - Registers that provide the right functionality with their reset defaults.
2223 * TODO: Except for registers that based on the above 3 criteria can be safely
2224 * ignored, we save/restore all others, practically treating the HW context as
2225 * a black-box for the driver. Further investigation is needed to reduce the
2226 * saved/restored registers even further, by following the same 3 criteria.
2228 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2230 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2233 /* GAM 0x4000-0x4770 */
2234 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2235 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2236 s->arb_mode = I915_READ(ARB_MODE);
2237 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2238 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2240 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2241 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2243 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2244 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2246 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2247 s->ecochk = I915_READ(GAM_ECOCHK);
2248 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2249 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2251 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2253 /* MBC 0x9024-0x91D0, 0x8500 */
2254 s->g3dctl = I915_READ(VLV_G3DCTL);
2255 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2256 s->mbctl = I915_READ(GEN6_MBCTL);
2258 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2259 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2260 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2261 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2262 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2263 s->rstctl = I915_READ(GEN6_RSTCTL);
2264 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2266 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2267 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2268 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2269 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2270 s->ecobus = I915_READ(ECOBUS);
2271 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2272 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2273 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2274 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2275 s->rcedata = I915_READ(VLV_RCEDATA);
2276 s->spare2gh = I915_READ(VLV_SPAREG2H);
2278 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2279 s->gt_imr = I915_READ(GTIMR);
2280 s->gt_ier = I915_READ(GTIER);
2281 s->pm_imr = I915_READ(GEN6_PMIMR);
2282 s->pm_ier = I915_READ(GEN6_PMIER);
2284 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2285 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2287 /* GT SA CZ domain, 0x100000-0x138124 */
2288 s->tilectl = I915_READ(TILECTL);
2289 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2290 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2291 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2292 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2294 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2295 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2296 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2297 s->pcbr = I915_READ(VLV_PCBR);
2298 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2301 * Not saving any of:
2302 * DFT, 0x9800-0x9EC0
2303 * SARB, 0xB000-0xB1FC
2304 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2309 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2311 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2315 /* GAM 0x4000-0x4770 */
2316 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2317 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2318 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2319 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2320 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2322 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2323 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2325 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2326 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2328 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2329 I915_WRITE(GAM_ECOCHK, s->ecochk);
2330 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2331 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2333 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2335 /* MBC 0x9024-0x91D0, 0x8500 */
2336 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2337 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2338 I915_WRITE(GEN6_MBCTL, s->mbctl);
2340 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2341 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2342 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2343 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2344 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2345 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2346 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2348 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2349 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2350 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2351 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2352 I915_WRITE(ECOBUS, s->ecobus);
2353 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2354 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2355 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2356 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2357 I915_WRITE(VLV_RCEDATA, s->rcedata);
2358 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2360 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2361 I915_WRITE(GTIMR, s->gt_imr);
2362 I915_WRITE(GTIER, s->gt_ier);
2363 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2364 I915_WRITE(GEN6_PMIER, s->pm_ier);
2366 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2367 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2369 /* GT SA CZ domain, 0x100000-0x138124 */
2370 I915_WRITE(TILECTL, s->tilectl);
2371 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2373 * Preserve the GT allow wake and GFX force clock bit, they are not
2374 * be restored, as they are used to control the s0ix suspend/resume
2375 * sequence by the caller.
2377 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2378 val &= VLV_GTLC_ALLOWWAKEREQ;
2379 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2380 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2382 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2383 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2384 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2385 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2387 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2389 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2390 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2391 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2392 I915_WRITE(VLV_PCBR, s->pcbr);
2393 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2396 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2399 /* The HW does not like us polling for PW_STATUS frequently, so
2400 * use the sleeping loop rather than risk the busy spin within
2401 * intel_wait_for_register().
2403 * Transitioning between RC6 states should be at most 2ms (see
2404 * valleyview_enable_rps) so use a 3ms timeout.
2406 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2410 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2415 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2416 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2418 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2419 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2424 err = intel_wait_for_register(dev_priv,
2425 VLV_GTLC_SURVIVABILITY_REG,
2426 VLV_GFX_CLK_STATUS_BIT,
2427 VLV_GFX_CLK_STATUS_BIT,
2430 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2431 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2436 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2442 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2443 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2445 val |= VLV_GTLC_ALLOWWAKEREQ;
2446 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2447 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2449 mask = VLV_GTLC_ALLOWWAKEACK;
2450 val = allow ? mask : 0;
2452 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2454 DRM_ERROR("timeout disabling GT waking\n");
2459 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2465 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2466 val = wait_for_on ? mask : 0;
2469 * RC6 transitioning can be delayed up to 2 msec (see
2470 * valleyview_enable_rps), use 3 msec for safety.
2472 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2473 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2474 onoff(wait_for_on));
2477 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2479 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2482 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2483 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2486 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2492 * Bspec defines the following GT well on flags as debug only, so
2493 * don't treat them as hard failures.
2495 vlv_wait_for_gt_wells(dev_priv, false);
2497 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2498 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2500 vlv_check_no_gt_access(dev_priv);
2502 err = vlv_force_gfx_clock(dev_priv, true);
2506 err = vlv_allow_gt_wake(dev_priv, false);
2510 if (!IS_CHERRYVIEW(dev_priv))
2511 vlv_save_gunit_s0ix_state(dev_priv);
2513 err = vlv_force_gfx_clock(dev_priv, false);
2520 /* For safety always re-enable waking and disable gfx clock forcing */
2521 vlv_allow_gt_wake(dev_priv, true);
2523 vlv_force_gfx_clock(dev_priv, false);
2528 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2535 * If any of the steps fail just try to continue, that's the best we
2536 * can do at this point. Return the first error code (which will also
2537 * leave RPM permanently disabled).
2539 ret = vlv_force_gfx_clock(dev_priv, true);
2541 if (!IS_CHERRYVIEW(dev_priv))
2542 vlv_restore_gunit_s0ix_state(dev_priv);
2544 err = vlv_allow_gt_wake(dev_priv, true);
2548 err = vlv_force_gfx_clock(dev_priv, false);
2552 vlv_check_no_gt_access(dev_priv);
2555 intel_init_clock_gating(dev_priv);
2560 static int intel_runtime_suspend(struct device *kdev)
2562 struct pci_dev *pdev = to_pci_dev(kdev);
2563 struct drm_device *dev = pci_get_drvdata(pdev);
2564 struct drm_i915_private *dev_priv = to_i915(dev);
2567 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2570 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2573 DRM_DEBUG_KMS("Suspending device\n");
2575 disable_rpm_wakeref_asserts(dev_priv);
2578 * We are safe here against re-faults, since the fault handler takes
2581 i915_gem_runtime_suspend(dev_priv);
2583 intel_uc_suspend(dev_priv);
2585 intel_runtime_pm_disable_interrupts(dev_priv);
2587 intel_uncore_suspend(dev_priv);
2590 if (IS_GEN9_LP(dev_priv)) {
2591 bxt_display_core_uninit(dev_priv);
2592 bxt_enable_dc9(dev_priv);
2593 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2594 hsw_enable_pc8(dev_priv);
2595 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2596 ret = vlv_suspend_complete(dev_priv);
2600 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2601 intel_uncore_runtime_resume(dev_priv);
2603 intel_runtime_pm_enable_interrupts(dev_priv);
2605 intel_uc_resume(dev_priv);
2607 i915_gem_init_swizzling(dev_priv);
2608 i915_gem_restore_fences(dev_priv);
2610 enable_rpm_wakeref_asserts(dev_priv);
2615 enable_rpm_wakeref_asserts(dev_priv);
2616 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2618 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2619 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2621 dev_priv->runtime_pm.suspended = true;
2624 * FIXME: We really should find a document that references the arguments
2627 if (IS_BROADWELL(dev_priv)) {
2629 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2630 * being detected, and the call we do at intel_runtime_resume()
2631 * won't be able to restore them. Since PCI_D3hot matches the
2632 * actual specification and appears to be working, use it.
2634 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2637 * current versions of firmware which depend on this opregion
2638 * notification have repurposed the D1 definition to mean
2639 * "runtime suspended" vs. what you would normally expect (D3)
2640 * to distinguish it from notifications that might be sent via
2643 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2646 assert_forcewakes_inactive(dev_priv);
2648 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2649 intel_hpd_poll_init(dev_priv);
2651 DRM_DEBUG_KMS("Device suspended\n");
2655 static int intel_runtime_resume(struct device *kdev)
2657 struct pci_dev *pdev = to_pci_dev(kdev);
2658 struct drm_device *dev = pci_get_drvdata(pdev);
2659 struct drm_i915_private *dev_priv = to_i915(dev);
2662 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2665 DRM_DEBUG_KMS("Resuming device\n");
2667 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2668 disable_rpm_wakeref_asserts(dev_priv);
2670 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2671 dev_priv->runtime_pm.suspended = false;
2672 if (intel_uncore_unclaimed_mmio(dev_priv))
2673 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2675 if (IS_GEN9_LP(dev_priv)) {
2676 bxt_disable_dc9(dev_priv);
2677 bxt_display_core_init(dev_priv, true);
2678 if (dev_priv->csr.dmc_payload &&
2679 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2680 gen9_enable_dc5(dev_priv);
2681 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2682 hsw_disable_pc8(dev_priv);
2683 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2684 ret = vlv_resume_prepare(dev_priv, true);
2687 intel_uncore_runtime_resume(dev_priv);
2689 intel_runtime_pm_enable_interrupts(dev_priv);
2691 intel_uc_resume(dev_priv);
2694 * No point of rolling back things in case of an error, as the best
2695 * we can do is to hope that things will still work (and disable RPM).
2697 i915_gem_init_swizzling(dev_priv);
2698 i915_gem_restore_fences(dev_priv);
2701 * On VLV/CHV display interrupts are part of the display
2702 * power well, so hpd is reinitialized from there. For
2703 * everyone else do it here.
2705 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2706 intel_hpd_init(dev_priv);
2708 intel_enable_ipc(dev_priv);
2710 enable_rpm_wakeref_asserts(dev_priv);
2713 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2715 DRM_DEBUG_KMS("Device resumed\n");
2720 const struct dev_pm_ops i915_pm_ops = {
2722 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2725 .suspend = i915_pm_suspend,
2726 .suspend_late = i915_pm_suspend_late,
2727 .resume_early = i915_pm_resume_early,
2728 .resume = i915_pm_resume,
2732 * @freeze, @freeze_late : called (1) before creating the
2733 * hibernation image [PMSG_FREEZE] and
2734 * (2) after rebooting, before restoring
2735 * the image [PMSG_QUIESCE]
2736 * @thaw, @thaw_early : called (1) after creating the hibernation
2737 * image, before writing it [PMSG_THAW]
2738 * and (2) after failing to create or
2739 * restore the image [PMSG_RECOVER]
2740 * @poweroff, @poweroff_late: called after writing the hibernation
2741 * image, before rebooting [PMSG_HIBERNATE]
2742 * @restore, @restore_early : called after rebooting and restoring the
2743 * hibernation image [PMSG_RESTORE]
2745 .freeze = i915_pm_freeze,
2746 .freeze_late = i915_pm_freeze_late,
2747 .thaw_early = i915_pm_thaw_early,
2748 .thaw = i915_pm_thaw,
2749 .poweroff = i915_pm_suspend,
2750 .poweroff_late = i915_pm_poweroff_late,
2751 .restore_early = i915_pm_restore_early,
2752 .restore = i915_pm_restore,
2754 /* S0ix (via runtime suspend) event handlers */
2755 .runtime_suspend = intel_runtime_suspend,
2756 .runtime_resume = intel_runtime_resume,
2759 static const struct vm_operations_struct i915_gem_vm_ops = {
2760 .fault = i915_gem_fault,
2761 .open = drm_gem_vm_open,
2762 .close = drm_gem_vm_close,
2765 static const struct file_operations i915_driver_fops = {
2766 .owner = THIS_MODULE,
2768 .release = drm_release,
2769 .unlocked_ioctl = drm_ioctl,
2770 .mmap = drm_gem_mmap,
2773 .compat_ioctl = i915_compat_ioctl,
2774 .llseek = noop_llseek,
2778 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2779 struct drm_file *file)
2784 static const struct drm_ioctl_desc i915_ioctls[] = {
2785 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2786 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2787 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2788 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2789 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2790 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2791 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2792 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2793 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2794 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2795 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2796 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2797 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2798 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2799 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2800 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2801 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2802 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2803 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2804 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2805 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2806 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2807 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2808 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2809 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2810 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2811 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2812 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2813 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2814 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2815 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2816 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2817 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2818 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2819 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2820 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2821 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2822 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2823 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2824 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2825 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2826 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2827 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2828 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2829 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2830 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2831 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2832 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2833 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2834 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2835 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2836 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2837 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2838 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2839 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2840 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2843 static struct drm_driver driver = {
2844 /* Don't use MTRRs here; the Xserver or userspace app should
2845 * deal with them for Intel hardware.
2848 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2849 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2850 .release = i915_driver_release,
2851 .open = i915_driver_open,
2852 .lastclose = i915_driver_lastclose,
2853 .postclose = i915_driver_postclose,
2855 .gem_close_object = i915_gem_close_object,
2856 .gem_free_object_unlocked = i915_gem_free_object,
2857 .gem_vm_ops = &i915_gem_vm_ops,
2859 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2860 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2861 .gem_prime_export = i915_gem_prime_export,
2862 .gem_prime_import = i915_gem_prime_import,
2864 .dumb_create = i915_gem_dumb_create,
2865 .dumb_map_offset = i915_gem_mmap_gtt,
2866 .ioctls = i915_ioctls,
2867 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2868 .fops = &i915_driver_fops,
2869 .name = DRIVER_NAME,
2870 .desc = DRIVER_DESC,
2871 .date = DRIVER_DATE,
2872 .major = DRIVER_MAJOR,
2873 .minor = DRIVER_MINOR,
2874 .patchlevel = DRIVER_PATCHLEVEL,
2877 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2878 #include "selftests/mock_drm.c"