drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915_modparams.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915_modparams.inject_load_failure &&
 110                i915_load_fail_count == i915_modparams.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 139                         dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 140                 else
 141                         dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 142                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 143         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 144                 ret = PCH_SPT;
 145                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 146         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 147                 ret = PCH_CNP;
 148                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 149         }
 150
 151         return ret;
 152 }
 153
 154 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 155 {
 156         struct pci_dev *pch = NULL;
 157
 158         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 159          * (which really amounts to a PCH but no South Display).
 160          */
 161         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 162                 dev_priv->pch_type = PCH_NOP;
 163                 return;
 164         }
 165
 166         /*
 167          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 168          * make graphics device passthrough work easy for VMM, that only
 169          * need to expose ISA bridge to let driver know the real hardware
 170          * underneath. This is a requirement from virtualization team.
 171          *
 172          * In some virtualized environments (e.g. XEN), there is irrelevant
 173          * ISA bridge in the system. To work reliably, we should scan trhough
 174          * all the ISA bridge devices and check for the first match, instead
 175          * of only checking the first one.
 176          */
 177         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 178                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 179                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 180
 181                         dev_priv->pch_id = id;
 182
 183                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 184                                 dev_priv->pch_type = PCH_IBX;
 185                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 186                                 WARN_ON(!IS_GEN5(dev_priv));
 187                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_CPT;
 189                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 190                                 WARN_ON(!IS_GEN6(dev_priv) &&
 191                                         !IS_IVYBRIDGE(dev_priv));
 192                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 193                                 /* PantherPoint is CPT compatible */
 194                                 dev_priv->pch_type = PCH_CPT;
 195                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 196                                 WARN_ON(!IS_GEN6(dev_priv) &&
 197                                         !IS_IVYBRIDGE(dev_priv));
 198                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 199                                 dev_priv->pch_type = PCH_LPT;
 200                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 201                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 202                                         !IS_BROADWELL(dev_priv));
 203                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 204                                         IS_BDW_ULT(dev_priv));
 205                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 206                                 dev_priv->pch_type = PCH_LPT;
 207                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 208                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 209                                         !IS_BROADWELL(dev_priv));
 210                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 211                                         !IS_BDW_ULT(dev_priv));
 212                         } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
 213                                 /* WildcatPoint is LPT compatible */
 214                                 dev_priv->pch_type = PCH_LPT;
 215                                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 216                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 217                                         !IS_BROADWELL(dev_priv));
 218                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 219                                         IS_BDW_ULT(dev_priv));
 220                         } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
 221                                 /* WildcatPoint is LPT compatible */
 222                                 dev_priv->pch_type = PCH_LPT;
 223                                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 224                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 225                                         !IS_BROADWELL(dev_priv));
 226                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 227                                         !IS_BDW_ULT(dev_priv));
 228                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 229                                 dev_priv->pch_type = PCH_SPT;
 230                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 231                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 232                                         !IS_KABYLAKE(dev_priv));
 233                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 234                                 dev_priv->pch_type = PCH_SPT;
 235                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 236                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 237                                         !IS_KABYLAKE(dev_priv));
 238                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 239                                 dev_priv->pch_type = PCH_KBP;
 240                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 241                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 242                                         !IS_KABYLAKE(dev_priv) &&
 243                                         !IS_COFFEELAKE(dev_priv));
 244                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 245                                 dev_priv->pch_type = PCH_CNP;
 246                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 247                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 248                                         !IS_COFFEELAKE(dev_priv));
 249                         } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 250                                 dev_priv->pch_type = PCH_CNP;
 251                                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 252                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 253                                         !IS_COFFEELAKE(dev_priv));
 254                         } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 255                                    id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 256                                    (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 257                                     pch->subsystem_vendor ==
 258                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 259                                     pch->subsystem_device ==
 260                                             PCI_SUBDEVICE_ID_QEMU)) {
 261                                 dev_priv->pch_type =
 262                                         intel_virt_detect_pch(dev_priv);
 263                         } else
 264                                 continue;
 265
 266                         break;
 267                 }
 268         }
 269         if (!pch)
 270                 DRM_DEBUG_KMS("No PCH found.\n");
 271
 272         pci_dev_put(pch);
 273 }
 274
 275 static int i915_getparam(struct drm_device *dev, void *data,
 276                          struct drm_file *file_priv)
 277 {
 278         struct drm_i915_private *dev_priv = to_i915(dev);
 279         struct pci_dev *pdev = dev_priv->drm.pdev;
 280         drm_i915_getparam_t *param = data;
 281         int value;
 282
 283         switch (param->param) {
 284         case I915_PARAM_IRQ_ACTIVE:
 285         case I915_PARAM_ALLOW_BATCHBUFFER:
 286         case I915_PARAM_LAST_DISPATCH:
 287         case I915_PARAM_HAS_EXEC_CONSTANTS:
 288                 /* Reject all old ums/dri params. */
 289                 return -ENODEV;
 290         case I915_PARAM_CHIPSET_ID:
 291                 value = pdev->device;
 292                 break;
 293         case I915_PARAM_REVISION:
 294                 value = pdev->revision;
 295                 break;
 296         case I915_PARAM_NUM_FENCES_AVAIL:
 297                 value = dev_priv->num_fence_regs;
 298                 break;
 299         case I915_PARAM_HAS_OVERLAY:
 300                 value = dev_priv->overlay ? 1 : 0;
 301                 break;
 302         case I915_PARAM_HAS_BSD:
 303                 value = !!dev_priv->engine[VCS];
 304                 break;
 305         case I915_PARAM_HAS_BLT:
 306                 value = !!dev_priv->engine[BCS];
 307                 break;
 308         case I915_PARAM_HAS_VEBOX:
 309                 value = !!dev_priv->engine[VECS];
 310                 break;
 311         case I915_PARAM_HAS_BSD2:
 312                 value = !!dev_priv->engine[VCS2];
 313                 break;
 314         case I915_PARAM_HAS_LLC:
 315                 value = HAS_LLC(dev_priv);
 316                 break;
 317         case I915_PARAM_HAS_WT:
 318                 value = HAS_WT(dev_priv);
 319                 break;
 320         case I915_PARAM_HAS_ALIASING_PPGTT:
 321                 value = USES_PPGTT(dev_priv);
 322                 break;
 323         case I915_PARAM_HAS_SEMAPHORES:
 324                 value = i915_modparams.semaphores;
 325                 break;
 326         case I915_PARAM_HAS_SECURE_BATCHES:
 327                 value = capable(CAP_SYS_ADMIN);
 328                 break;
 329         case I915_PARAM_CMD_PARSER_VERSION:
 330                 value = i915_cmd_parser_get_version(dev_priv);
 331                 break;
 332         case I915_PARAM_SUBSLICE_TOTAL:
 333                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 334                 if (!value)
 335                         return -ENODEV;
 336                 break;
 337         case I915_PARAM_EU_TOTAL:
 338                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 339                 if (!value)
 340                         return -ENODEV;
 341                 break;
 342         case I915_PARAM_HAS_GPU_RESET:
 343                 value = i915_modparams.enable_hangcheck &&
 344                         intel_has_gpu_reset(dev_priv);
 345                 if (value && intel_has_reset_engine(dev_priv))
 346                         value = 2;
 347                 break;
 348         case I915_PARAM_HAS_RESOURCE_STREAMER:
 349                 value = HAS_RESOURCE_STREAMER(dev_priv);
 350                 break;
 351         case I915_PARAM_HAS_POOLED_EU:
 352                 value = HAS_POOLED_EU(dev_priv);
 353                 break;
 354         case I915_PARAM_MIN_EU_IN_POOL:
 355                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 356                 break;
 357         case I915_PARAM_HUC_STATUS:
 358                 intel_runtime_pm_get(dev_priv);
 359                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 360                 intel_runtime_pm_put(dev_priv);
 361                 break;
 362         case I915_PARAM_MMAP_GTT_VERSION:
 363                 /* Though we've started our numbering from 1, and so class all
 364                  * earlier versions as 0, in effect their value is undefined as
 365                  * the ioctl will report EINVAL for the unknown param!
 366                  */
 367                 value = i915_gem_mmap_gtt_version();
 368                 break;
 369         case I915_PARAM_HAS_SCHEDULER:
 370                 value = 0;
 371                 if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
 372                         value |= I915_SCHEDULER_CAP_ENABLED;
 373                         value |= I915_SCHEDULER_CAP_PRIORITY;
 374
 375                         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 376                             i915_modparams.enable_execlists)
 377                                 value |= I915_SCHEDULER_CAP_PREEMPTION;
 378                 }
 379                 break;
 380
 381         case I915_PARAM_MMAP_VERSION:
 382                 /* Remember to bump this if the version changes! */
 383         case I915_PARAM_HAS_GEM:
 384         case I915_PARAM_HAS_PAGEFLIPPING:
 385         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 386         case I915_PARAM_HAS_RELAXED_FENCING:
 387         case I915_PARAM_HAS_COHERENT_RINGS:
 388         case I915_PARAM_HAS_RELAXED_DELTA:
 389         case I915_PARAM_HAS_GEN7_SOL_RESET:
 390         case I915_PARAM_HAS_WAIT_TIMEOUT:
 391         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 392         case I915_PARAM_HAS_PINNED_BATCHES:
 393         case I915_PARAM_HAS_EXEC_NO_RELOC:
 394         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 395         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 396         case I915_PARAM_HAS_EXEC_SOFTPIN:
 397         case I915_PARAM_HAS_EXEC_ASYNC:
 398         case I915_PARAM_HAS_EXEC_FENCE:
 399         case I915_PARAM_HAS_EXEC_CAPTURE:
 400         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 401         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 402                 /* For the time being all of these are always true;
 403                  * if some supported hardware does not have one of these
 404                  * features this value needs to be provided from
 405                  * INTEL_INFO(), a feature macro, or similar.
 406                  */
 407                 value = 1;
 408                 break;
 409         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 410                 value = intel_engines_has_context_isolation(dev_priv);
 411                 break;
 412         case I915_PARAM_SLICE_MASK:
 413                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 414                 if (!value)
 415                         return -ENODEV;
 416                 break;
 417         case I915_PARAM_SUBSLICE_MASK:
 418                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 419                 if (!value)
 420                         return -ENODEV;
 421                 break;
 422         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 423                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 424                 break;
 425         default:
 426                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 427                 return -EINVAL;
 428         }
 429
 430         if (put_user(value, param->value))
 431                 return -EFAULT;
 432
 433         return 0;
 434 }
 435
 436 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 437 {
 438         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 439         if (!dev_priv->bridge_dev) {
 440                 DRM_ERROR("bridge device not found\n");
 441                 return -1;
 442         }
 443         return 0;
 444 }
 445
 446 /* Allocate space for the MCH regs if needed, return nonzero on error */
 447 static int
 448 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 449 {
 450         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 451         u32 temp_lo, temp_hi = 0;
 452         u64 mchbar_addr;
 453         int ret;
 454
 455         if (INTEL_GEN(dev_priv) >= 4)
 456                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 457         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 458         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 459
 460         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 461 #ifdef CONFIG_PNP
 462         if (mchbar_addr &&
 463             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 464                 return 0;
 465 #endif
 466
 467         /* Get some space for it */
 468         dev_priv->mch_res.name = "i915 MCHBAR";
 469         dev_priv->mch_res.flags = IORESOURCE_MEM;
 470         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 471                                      &dev_priv->mch_res,
 472                                      MCHBAR_SIZE, MCHBAR_SIZE,
 473                                      PCIBIOS_MIN_MEM,
 474                                      0, pcibios_align_resource,
 475                                      dev_priv->bridge_dev);
 476         if (ret) {
 477                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 478                 dev_priv->mch_res.start = 0;
 479                 return ret;
 480         }
 481
 482         if (INTEL_GEN(dev_priv) >= 4)
 483                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 484                                        upper_32_bits(dev_priv->mch_res.start));
 485
 486         pci_write_config_dword(dev_priv->bridge_dev, reg,
 487                                lower_32_bits(dev_priv->mch_res.start));
 488         return 0;
 489 }
 490
 491 /* Setup MCHBAR if possible, return true if we should disable it again */
 492 static void
 493 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 494 {
 495         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 496         u32 temp;
 497         bool enabled;
 498
 499         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 500                 return;
 501
 502         dev_priv->mchbar_need_disable = false;
 503
 504         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 505                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 506                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 507         } else {
 508                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 509                 enabled = temp & 1;
 510         }
 511
 512         /* If it's already enabled, don't have to do anything */
 513         if (enabled)
 514                 return;
 515
 516         if (intel_alloc_mchbar_resource(dev_priv))
 517                 return;
 518
 519         dev_priv->mchbar_need_disable = true;
 520
 521         /* Space is allocated or reserved, so enable it. */
 522         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 523                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 524                                        temp | DEVEN_MCHBAR_EN);
 525         } else {
 526                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 527                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 528         }
 529 }
 530
 531 static void
 532 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 533 {
 534         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 535
 536         if (dev_priv->mchbar_need_disable) {
 537                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 538                         u32 deven_val;
 539
 540                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 541                                               &deven_val);
 542                         deven_val &= ~DEVEN_MCHBAR_EN;
 543                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 544                                                deven_val);
 545                 } else {
 546                         u32 mchbar_val;
 547
 548                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 549                                               &mchbar_val);
 550                         mchbar_val &= ~1;
 551                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 552                                                mchbar_val);
 553                 }
 554         }
 555
 556         if (dev_priv->mch_res.start)
 557                 release_resource(&dev_priv->mch_res);
 558 }
 559
 560 /* true = enable decode, false = disable decoder */
 561 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 562 {
 563         struct drm_i915_private *dev_priv = cookie;
 564
 565         intel_modeset_vga_set_state(dev_priv, state);
 566         if (state)
 567                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 568                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 569         else
 570                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 571 }
 572
 573 static int i915_resume_switcheroo(struct drm_device *dev);
 574 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 575
 576 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 577 {
 578         struct drm_device *dev = pci_get_drvdata(pdev);
 579         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 580
 581         if (state == VGA_SWITCHEROO_ON) {
 582                 pr_info("switched on\n");
 583                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 584                 /* i915 resume handler doesn't set to D0 */
 585                 pci_set_power_state(pdev, PCI_D0);
 586                 i915_resume_switcheroo(dev);
 587                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 588         } else {
 589                 pr_info("switched off\n");
 590                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 591                 i915_suspend_switcheroo(dev, pmm);
 592                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 593         }
 594 }
 595
 596 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 597 {
 598         struct drm_device *dev = pci_get_drvdata(pdev);
 599
 600         /*
 601          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 602          * locking inversion with the driver load path. And the access here is
 603          * completely racy anyway. So don't bother with locking for now.
 604          */
 605         return dev->open_count == 0;
 606 }
 607
 608 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 609         .set_gpu_state = i915_switcheroo_set_state,
 610         .reprobe = NULL,
 611         .can_switch = i915_switcheroo_can_switch,
 612 };
 613
 614 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 615 {
 616         /* Flush any outstanding unpin_work. */
 617         i915_gem_drain_workqueue(dev_priv);
 618
 619         mutex_lock(&dev_priv->drm.struct_mutex);
 620         intel_uc_fini_hw(dev_priv);
 621         i915_gem_cleanup_engines(dev_priv);
 622         i915_gem_contexts_fini(dev_priv);
 623         mutex_unlock(&dev_priv->drm.struct_mutex);
 624
 625         i915_gem_cleanup_userptr(dev_priv);
 626
 627         i915_gem_drain_freed_objects(dev_priv);
 628
 629         WARN_ON(!list_empty(&dev_priv->contexts.list));
 630 }
 631
 632 static int i915_load_modeset_init(struct drm_device *dev)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(dev);
 635         struct pci_dev *pdev = dev_priv->drm.pdev;
 636         int ret;
 637
 638         if (i915_inject_load_failure())
 639                 return -ENODEV;
 640
 641         intel_bios_init(dev_priv);
 642
 643         /* If we have > 1 VGA cards, then we need to arbitrate access
 644          * to the common VGA resources.
 645          *
 646          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 647          * then we do not take part in VGA arbitration and the
 648          * vga_client_register() fails with -ENODEV.
 649          */
 650         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 651         if (ret && ret != -ENODEV)
 652                 goto out;
 653
 654         intel_register_dsm_handler();
 655
 656         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 657         if (ret)
 658                 goto cleanup_vga_client;
 659
 660         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 661         intel_update_rawclk(dev_priv);
 662
 663         intel_power_domains_init_hw(dev_priv, false);
 664
 665         intel_csr_ucode_init(dev_priv);
 666
 667         ret = intel_irq_install(dev_priv);
 668         if (ret)
 669                 goto cleanup_csr;
 670
 671         intel_setup_gmbus(dev_priv);
 672
 673         /* Important: The output setup functions called by modeset_init need
 674          * working irqs for e.g. gmbus and dp aux transfers. */
 675         ret = intel_modeset_init(dev);
 676         if (ret)
 677                 goto cleanup_irq;
 678
 679         intel_uc_init_fw(dev_priv);
 680
 681         ret = i915_gem_init(dev_priv);
 682         if (ret)
 683                 goto cleanup_uc;
 684
 685         intel_setup_overlay(dev_priv);
 686
 687         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 688                 return 0;
 689
 690         ret = intel_fbdev_init(dev);
 691         if (ret)
 692                 goto cleanup_gem;
 693
 694         /* Only enable hotplug handling once the fbdev is fully set up. */
 695         intel_hpd_init(dev_priv);
 696
 697         drm_kms_helper_poll_init(dev);
 698
 699         return 0;
 700
 701 cleanup_gem:
 702         if (i915_gem_suspend(dev_priv))
 703                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 704         i915_gem_fini(dev_priv);
 705 cleanup_uc:
 706         intel_uc_fini_fw(dev_priv);
 707 cleanup_irq:
 708         drm_irq_uninstall(dev);
 709         intel_teardown_gmbus(dev_priv);
 710 cleanup_csr:
 711         intel_csr_ucode_fini(dev_priv);
 712         intel_power_domains_fini(dev_priv);
 713         vga_switcheroo_unregister_client(pdev);
 714 cleanup_vga_client:
 715         vga_client_register(pdev, NULL, NULL, NULL);
 716 out:
 717         return ret;
 718 }
 719
 720 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 721 {
 722         struct apertures_struct *ap;
 723         struct pci_dev *pdev = dev_priv->drm.pdev;
 724         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 725         bool primary;
 726         int ret;
 727
 728         ap = alloc_apertures(1);
 729         if (!ap)
 730                 return -ENOMEM;
 731
 732         ap->ranges[0].base = ggtt->mappable_base;
 733         ap->ranges[0].size = ggtt->mappable_end;
 734
 735         primary =
 736                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 737
 738         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 739
 740         kfree(ap);
 741
 742         return ret;
 743 }
 744
 745 #if !defined(CONFIG_VGA_CONSOLE)
 746 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 747 {
 748         return 0;
 749 }
 750 #elif !defined(CONFIG_DUMMY_CONSOLE)
 751 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 752 {
 753         return -ENODEV;
 754 }
 755 #else
 756 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 757 {
 758         int ret = 0;
 759
 760         DRM_INFO("Replacing VGA console driver\n");
 761
 762         console_lock();
 763         if (con_is_bound(&vga_con))
 764                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 765         if (ret == 0) {
 766                 ret = do_unregister_con_driver(&vga_con);
 767
 768                 /* Ignore "already unregistered". */
 769                 if (ret == -ENODEV)
 770                         ret = 0;
 771         }
 772         console_unlock();
 773
 774         return ret;
 775 }
 776 #endif
 777
 778 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 779 {
 780         /*
 781          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 782          * CHV x1 PHY (DP/HDMI D)
 783          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 784          */
 785         if (IS_CHERRYVIEW(dev_priv)) {
 786                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 787                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 788         } else if (IS_VALLEYVIEW(dev_priv)) {
 789                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 790         }
 791 }
 792
 793 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 794 {
 795         /*
 796          * The i915 workqueue is primarily used for batched retirement of
 797          * requests (and thus managing bo) once the task has been completed
 798          * by the GPU. i915_gem_retire_requests() is called directly when we
 799          * need high-priority retirement, such as waiting for an explicit
 800          * bo.
 801          *
 802          * It is also used for periodic low-priority events, such as
 803          * idle-timers and recording error state.
 804          *
 805          * All tasks on the workqueue are expected to acquire the dev mutex
 806          * so there is no point in running more than one instance of the
 807          * workqueue at any time.  Use an ordered one.
 808          */
 809         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 810         if (dev_priv->wq == NULL)
 811                 goto out_err;
 812
 813         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 814         if (dev_priv->hotplug.dp_wq == NULL)
 815                 goto out_free_wq;
 816
 817         return 0;
 818
 819 out_free_wq:
 820         destroy_workqueue(dev_priv->wq);
 821 out_err:
 822         DRM_ERROR("Failed to allocate workqueues.\n");
 823
 824         return -ENOMEM;
 825 }
 826
 827 static void i915_engines_cleanup(struct drm_i915_private *i915)
 828 {
 829         struct intel_engine_cs *engine;
 830         enum intel_engine_id id;
 831
 832         for_each_engine(engine, i915, id)
 833                 kfree(engine);
 834 }
 835
 836 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 837 {
 838         destroy_workqueue(dev_priv->hotplug.dp_wq);
 839         destroy_workqueue(dev_priv->wq);
 840 }
 841
 842 /*
 843  * We don't keep the workarounds for pre-production hardware, so we expect our
 844  * driver to fail on these machines in one way or another. A little warning on
 845  * dmesg may help both the user and the bug triagers.
 846  */
 847 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 848 {
 849         bool pre = false;
 850
 851         pre |= IS_HSW_EARLY_SDV(dev_priv);
 852         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 853         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 854
 855         if (pre) {
 856                 DRM_ERROR("This is a pre-production stepping. "
 857                           "It may not be fully functional.\n");
 858                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 859         }
 860 }
 861
 862 /**
 863  * i915_driver_init_early - setup state not requiring device access
 864  * @dev_priv: device private
 865  *
 866  * Initialize everything that is a "SW-only" state, that is state not
 867  * requiring accessing the device or exposing the driver via kernel internal
 868  * or userspace interfaces. Example steps belonging here: lock initialization,
 869  * system memory allocation, setting up device specific attributes and
 870  * function hooks not requiring accessing the device.
 871  */
 872 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 873                                   const struct pci_device_id *ent)
 874 {
 875         const struct intel_device_info *match_info =
 876                 (struct intel_device_info *)ent->driver_data;
 877         struct intel_device_info *device_info;
 878         int ret = 0;
 879
 880         if (i915_inject_load_failure())
 881                 return -ENODEV;
 882
 883         /* Setup the write-once "constant" device info */
 884         device_info = mkwrite_device_info(dev_priv);
 885         memcpy(device_info, match_info, sizeof(*device_info));
 886         device_info->device_id = dev_priv->drm.pdev->device;
 887
 888         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 889                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 890         device_info->platform_mask = BIT(device_info->platform);
 891
 892         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 893         device_info->gen_mask = BIT(device_info->gen - 1);
 894
 895         spin_lock_init(&dev_priv->irq_lock);
 896         spin_lock_init(&dev_priv->gpu_error.lock);
 897         mutex_init(&dev_priv->backlight_lock);
 898         spin_lock_init(&dev_priv->uncore.lock);
 899
 900         mutex_init(&dev_priv->sb_lock);
 901         mutex_init(&dev_priv->modeset_restore_lock);
 902         mutex_init(&dev_priv->av_mutex);
 903         mutex_init(&dev_priv->wm.wm_mutex);
 904         mutex_init(&dev_priv->pps_mutex);
 905
 906         intel_uc_init_early(dev_priv);
 907         i915_memcpy_init_early(dev_priv);
 908
 909         ret = i915_workqueues_init(dev_priv);
 910         if (ret < 0)
 911                 goto err_engines;
 912
 913         /* This must be called before any calls to HAS_PCH_* */
 914         intel_detect_pch(dev_priv);
 915
 916         intel_pm_setup(dev_priv);
 917         intel_init_dpio(dev_priv);
 918         intel_power_domains_init(dev_priv);
 919         intel_irq_init(dev_priv);
 920         intel_hangcheck_init(dev_priv);
 921         intel_init_display_hooks(dev_priv);
 922         intel_init_clock_gating_hooks(dev_priv);
 923         intel_init_audio_hooks(dev_priv);
 924         ret = i915_gem_load_init(dev_priv);
 925         if (ret < 0)
 926                 goto err_irq;
 927
 928         intel_display_crc_init(dev_priv);
 929
 930         intel_device_info_dump(dev_priv);
 931
 932         intel_detect_preproduction_hw(dev_priv);
 933
 934         i915_perf_init(dev_priv);
 935
 936         return 0;
 937
 938 err_irq:
 939         intel_irq_fini(dev_priv);
 940         i915_workqueues_cleanup(dev_priv);
 941 err_engines:
 942         i915_engines_cleanup(dev_priv);
 943         return ret;
 944 }
 945
 946 /**
 947  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 948  * @dev_priv: device private
 949  */
 950 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 951 {
 952         i915_perf_fini(dev_priv);
 953         i915_gem_load_cleanup(dev_priv);
 954         intel_irq_fini(dev_priv);
 955         i915_workqueues_cleanup(dev_priv);
 956         i915_engines_cleanup(dev_priv);
 957 }
 958
 959 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 960 {
 961         struct pci_dev *pdev = dev_priv->drm.pdev;
 962         int mmio_bar;
 963         int mmio_size;
 964
 965         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 966         /*
 967          * Before gen4, the registers and the GTT are behind different BARs.
 968          * However, from gen4 onwards, the registers and the GTT are shared
 969          * in the same BAR, so we want to restrict this ioremap from
 970          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 971          * the register BAR remains the same size for all the earlier
 972          * generations up to Ironlake.
 973          */
 974         if (INTEL_GEN(dev_priv) < 5)
 975                 mmio_size = 512 * 1024;
 976         else
 977                 mmio_size = 2 * 1024 * 1024;
 978         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 979         if (dev_priv->regs == NULL) {
 980                 DRM_ERROR("failed to map registers\n");
 981
 982                 return -EIO;
 983         }
 984
 985         /* Try to make sure MCHBAR is enabled before poking at it */
 986         intel_setup_mchbar(dev_priv);
 987
 988         return 0;
 989 }
 990
 991 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 992 {
 993         struct pci_dev *pdev = dev_priv->drm.pdev;
 994
 995         intel_teardown_mchbar(dev_priv);
 996         pci_iounmap(pdev, dev_priv->regs);
 997 }
 998
 999 /**
1000  * i915_driver_init_mmio - setup device MMIO
1001  * @dev_priv: device private
1002  *
1003  * Setup minimal device state necessary for MMIO accesses later in the
1004  * initialization sequence. The setup here should avoid any other device-wide
1005  * side effects or exposing the driver via kernel internal or user space
1006  * interfaces.
1007  */
1008 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1009 {
1010         int ret;
1011
1012         if (i915_inject_load_failure())
1013                 return -ENODEV;
1014
1015         if (i915_get_bridge_dev(dev_priv))
1016                 return -EIO;
1017
1018         ret = i915_mmio_setup(dev_priv);
1019         if (ret < 0)
1020                 goto err_bridge;
1021
1022         intel_uncore_init(dev_priv);
1023
1024         intel_uc_init_mmio(dev_priv);
1025
1026         ret = intel_engines_init_mmio(dev_priv);
1027         if (ret)
1028                 goto err_uncore;
1029
1030         i915_gem_init_mmio(dev_priv);
1031
1032         return 0;
1033
1034 err_uncore:
1035         intel_uncore_fini(dev_priv);
1036 err_bridge:
1037         pci_dev_put(dev_priv->bridge_dev);
1038
1039         return ret;
1040 }
1041
1042 /**
1043  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1044  * @dev_priv: device private
1045  */
1046 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1047 {
1048         intel_uncore_fini(dev_priv);
1049         i915_mmio_cleanup(dev_priv);
1050         pci_dev_put(dev_priv->bridge_dev);
1051 }
1052
1053 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1054 {
1055         i915_modparams.enable_execlists =
1056                 intel_sanitize_enable_execlists(dev_priv,
1057                                                 i915_modparams.enable_execlists);
1058
1059         /*
1060          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1061          * user's requested state against the hardware/driver capabilities.  We
1062          * do this now so that we can print out any log messages once rather
1063          * than every time we check intel_enable_ppgtt().
1064          */
1065         i915_modparams.enable_ppgtt =
1066                 intel_sanitize_enable_ppgtt(dev_priv,
1067                                             i915_modparams.enable_ppgtt);
1068         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1069
1070         i915_modparams.semaphores =
1071                 intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
1072         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
1073                          yesno(i915_modparams.semaphores));
1074
1075         intel_uc_sanitize_options(dev_priv);
1076
1077         intel_gvt_sanitize_options(dev_priv);
1078 }
1079
1080 /**
1081  * i915_driver_init_hw - setup state requiring device access
1082  * @dev_priv: device private
1083  *
1084  * Setup state that requires accessing the device, but doesn't require
1085  * exposing the driver via kernel internal or userspace interfaces.
1086  */
1087 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1088 {
1089         struct pci_dev *pdev = dev_priv->drm.pdev;
1090         int ret;
1091
1092         if (i915_inject_load_failure())
1093                 return -ENODEV;
1094
1095         intel_device_info_runtime_init(dev_priv);
1096
1097         intel_sanitize_options(dev_priv);
1098
1099         ret = i915_ggtt_probe_hw(dev_priv);
1100         if (ret)
1101                 return ret;
1102
1103         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1104          * otherwise the vga fbdev driver falls over. */
1105         ret = i915_kick_out_firmware_fb(dev_priv);
1106         if (ret) {
1107                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1108                 goto out_ggtt;
1109         }
1110
1111         ret = i915_kick_out_vgacon(dev_priv);
1112         if (ret) {
1113                 DRM_ERROR("failed to remove conflicting VGA console\n");
1114                 goto out_ggtt;
1115         }
1116
1117         ret = i915_ggtt_init_hw(dev_priv);
1118         if (ret)
1119                 return ret;
1120
1121         ret = i915_ggtt_enable_hw(dev_priv);
1122         if (ret) {
1123                 DRM_ERROR("failed to enable GGTT\n");
1124                 goto out_ggtt;
1125         }
1126
1127         pci_set_master(pdev);
1128
1129         /* overlay on gen2 is broken and can't address above 1G */
1130         if (IS_GEN2(dev_priv)) {
1131                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1132                 if (ret) {
1133                         DRM_ERROR("failed to set DMA mask\n");
1134
1135                         goto out_ggtt;
1136                 }
1137         }
1138
1139         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1140          * using 32bit addressing, overwriting memory if HWS is located
1141          * above 4GB.
1142          *
1143          * The documentation also mentions an issue with undefined
1144          * behaviour if any general state is accessed within a page above 4GB,
1145          * which also needs to be handled carefully.
1146          */
1147         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1148                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1149
1150                 if (ret) {
1151                         DRM_ERROR("failed to set DMA mask\n");
1152
1153                         goto out_ggtt;
1154                 }
1155         }
1156
1157         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1158                            PM_QOS_DEFAULT_VALUE);
1159
1160         intel_uncore_sanitize(dev_priv);
1161
1162         intel_opregion_setup(dev_priv);
1163
1164         i915_gem_load_init_fences(dev_priv);
1165
1166         /* On the 945G/GM, the chipset reports the MSI capability on the
1167          * integrated graphics even though the support isn't actually there
1168          * according to the published specs.  It doesn't appear to function
1169          * correctly in testing on 945G.
1170          * This may be a side effect of MSI having been made available for PEG
1171          * and the registers being closely associated.
1172          *
1173          * According to chipset errata, on the 965GM, MSI interrupts may
1174          * be lost or delayed, and was defeatured. MSI interrupts seem to
1175          * get lost on g4x as well, and interrupt delivery seems to stay
1176          * properly dead afterwards. So we'll just disable them for all
1177          * pre-gen5 chipsets.
1178          */
1179         if (INTEL_GEN(dev_priv) >= 5) {
1180                 if (pci_enable_msi(pdev) < 0)
1181                         DRM_DEBUG_DRIVER("can't enable MSI");
1182         }
1183
1184         ret = intel_gvt_init(dev_priv);
1185         if (ret)
1186                 goto out_ggtt;
1187
1188         return 0;
1189
1190 out_ggtt:
1191         i915_ggtt_cleanup_hw(dev_priv);
1192
1193         return ret;
1194 }
1195
1196 /**
1197  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1198  * @dev_priv: device private
1199  */
1200 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1201 {
1202         struct pci_dev *pdev = dev_priv->drm.pdev;
1203
1204         if (pdev->msi_enabled)
1205                 pci_disable_msi(pdev);
1206
1207         pm_qos_remove_request(&dev_priv->pm_qos);
1208         i915_ggtt_cleanup_hw(dev_priv);
1209 }
1210
1211 /**
1212  * i915_driver_register - register the driver with the rest of the system
1213  * @dev_priv: device private
1214  *
1215  * Perform any steps necessary to make the driver available via kernel
1216  * internal or userspace interfaces.
1217  */
1218 static void i915_driver_register(struct drm_i915_private *dev_priv)
1219 {
1220         struct drm_device *dev = &dev_priv->drm;
1221
1222         i915_gem_shrinker_init(dev_priv);
1223
1224         /*
1225          * Notify a valid surface after modesetting,
1226          * when running inside a VM.
1227          */
1228         if (intel_vgpu_active(dev_priv))
1229                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1230
1231         /* Reveal our presence to userspace */
1232         if (drm_dev_register(dev, 0) == 0) {
1233                 i915_debugfs_register(dev_priv);
1234                 i915_guc_log_register(dev_priv);
1235                 i915_setup_sysfs(dev_priv);
1236
1237                 /* Depends on sysfs having been initialized */
1238                 i915_perf_register(dev_priv);
1239         } else
1240                 DRM_ERROR("Failed to register driver for userspace access!\n");
1241
1242         if (INTEL_INFO(dev_priv)->num_pipes) {
1243                 /* Must be done after probing outputs */
1244                 intel_opregion_register(dev_priv);
1245                 acpi_video_register();
1246         }
1247
1248         if (IS_GEN5(dev_priv))
1249                 intel_gpu_ips_init(dev_priv);
1250
1251         intel_audio_init(dev_priv);
1252
1253         /*
1254          * Some ports require correctly set-up hpd registers for detection to
1255          * work properly (leading to ghost connected connector status), e.g. VGA
1256          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1257          * irqs are fully enabled. We do it last so that the async config
1258          * cannot run before the connectors are registered.
1259          */
1260         intel_fbdev_initial_config_async(dev);
1261 }
1262
1263 /**
1264  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1265  * @dev_priv: device private
1266  */
1267 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1268 {
1269         intel_fbdev_unregister(dev_priv);
1270         intel_audio_deinit(dev_priv);
1271
1272         intel_gpu_ips_teardown();
1273         acpi_video_unregister();
1274         intel_opregion_unregister(dev_priv);
1275
1276         i915_perf_unregister(dev_priv);
1277
1278         i915_teardown_sysfs(dev_priv);
1279         i915_guc_log_unregister(dev_priv);
1280         drm_dev_unregister(&dev_priv->drm);
1281
1282         i915_gem_shrinker_cleanup(dev_priv);
1283 }
1284
1285 /**
1286  * i915_driver_load - setup chip and create an initial config
1287  * @pdev: PCI device
1288  * @ent: matching PCI ID entry
1289  *
1290  * The driver load routine has to do several things:
1291  *   - drive output discovery via intel_modeset_init()
1292  *   - initialize the memory manager
1293  *   - allocate initial config memory
1294  *   - setup the DRM framebuffer with the allocated memory
1295  */
1296 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1297 {
1298         const struct intel_device_info *match_info =
1299                 (struct intel_device_info *)ent->driver_data;
1300         struct drm_i915_private *dev_priv;
1301         int ret;
1302
1303         /* Enable nuclear pageflip on ILK+ */
1304         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1305                 driver.driver_features &= ~DRIVER_ATOMIC;
1306
1307         ret = -ENOMEM;
1308         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1309         if (dev_priv)
1310                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1311         if (ret) {
1312                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1313                 goto out_free;
1314         }
1315
1316         dev_priv->drm.pdev = pdev;
1317         dev_priv->drm.dev_private = dev_priv;
1318
1319         ret = pci_enable_device(pdev);
1320         if (ret)
1321                 goto out_fini;
1322
1323         pci_set_drvdata(pdev, &dev_priv->drm);
1324         /*
1325          * Disable the system suspend direct complete optimization, which can
1326          * leave the device suspended skipping the driver's suspend handlers
1327          * if the device was already runtime suspended. This is needed due to
1328          * the difference in our runtime and system suspend sequence and
1329          * becaue the HDA driver may require us to enable the audio power
1330          * domain during system suspend.
1331          */
1332         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1333
1334         ret = i915_driver_init_early(dev_priv, ent);
1335         if (ret < 0)
1336                 goto out_pci_disable;
1337
1338         intel_runtime_pm_get(dev_priv);
1339
1340         ret = i915_driver_init_mmio(dev_priv);
1341         if (ret < 0)
1342                 goto out_runtime_pm_put;
1343
1344         ret = i915_driver_init_hw(dev_priv);
1345         if (ret < 0)
1346                 goto out_cleanup_mmio;
1347
1348         /*
1349          * TODO: move the vblank init and parts of modeset init steps into one
1350          * of the i915_driver_init_/i915_driver_register functions according
1351          * to the role/effect of the given init step.
1352          */
1353         if (INTEL_INFO(dev_priv)->num_pipes) {
1354                 ret = drm_vblank_init(&dev_priv->drm,
1355                                       INTEL_INFO(dev_priv)->num_pipes);
1356                 if (ret)
1357                         goto out_cleanup_hw;
1358         }
1359
1360         ret = i915_load_modeset_init(&dev_priv->drm);
1361         if (ret < 0)
1362                 goto out_cleanup_hw;
1363
1364         i915_driver_register(dev_priv);
1365
1366         intel_runtime_pm_enable(dev_priv);
1367
1368         intel_init_ipc(dev_priv);
1369
1370         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1371                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1372         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1373                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1374
1375         intel_runtime_pm_put(dev_priv);
1376
1377         return 0;
1378
1379 out_cleanup_hw:
1380         i915_driver_cleanup_hw(dev_priv);
1381 out_cleanup_mmio:
1382         i915_driver_cleanup_mmio(dev_priv);
1383 out_runtime_pm_put:
1384         intel_runtime_pm_put(dev_priv);
1385         i915_driver_cleanup_early(dev_priv);
1386 out_pci_disable:
1387         pci_disable_device(pdev);
1388 out_fini:
1389         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1390         drm_dev_fini(&dev_priv->drm);
1391 out_free:
1392         kfree(dev_priv);
1393         return ret;
1394 }
1395
1396 void i915_driver_unload(struct drm_device *dev)
1397 {
1398         struct drm_i915_private *dev_priv = to_i915(dev);
1399         struct pci_dev *pdev = dev_priv->drm.pdev;
1400
1401         i915_driver_unregister(dev_priv);
1402
1403         if (i915_gem_suspend(dev_priv))
1404                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1405
1406         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1407
1408         drm_atomic_helper_shutdown(dev);
1409
1410         intel_gvt_cleanup(dev_priv);
1411
1412         intel_modeset_cleanup(dev);
1413
1414         /*
1415          * free the memory space allocated for the child device
1416          * config parsed from VBT
1417          */
1418         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1419                 kfree(dev_priv->vbt.child_dev);
1420                 dev_priv->vbt.child_dev = NULL;
1421                 dev_priv->vbt.child_dev_num = 0;
1422         }
1423         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1424         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1425         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1426         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1427
1428         vga_switcheroo_unregister_client(pdev);
1429         vga_client_register(pdev, NULL, NULL, NULL);
1430
1431         intel_csr_ucode_fini(dev_priv);
1432
1433         /* Free error state after interrupts are fully disabled. */
1434         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1435         i915_reset_error_state(dev_priv);
1436
1437         i915_gem_fini(dev_priv);
1438         intel_uc_fini_fw(dev_priv);
1439         intel_fbc_cleanup_cfb(dev_priv);
1440
1441         intel_power_domains_fini(dev_priv);
1442
1443         i915_driver_cleanup_hw(dev_priv);
1444         i915_driver_cleanup_mmio(dev_priv);
1445
1446         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1447 }
1448
1449 static void i915_driver_release(struct drm_device *dev)
1450 {
1451         struct drm_i915_private *dev_priv = to_i915(dev);
1452
1453         i915_driver_cleanup_early(dev_priv);
1454         drm_dev_fini(&dev_priv->drm);
1455
1456         kfree(dev_priv);
1457 }
1458
1459 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1460 {
1461         struct drm_i915_private *i915 = to_i915(dev);
1462         int ret;
1463
1464         ret = i915_gem_open(i915, file);
1465         if (ret)
1466                 return ret;
1467
1468         return 0;
1469 }
1470
1471 /**
1472  * i915_driver_lastclose - clean up after all DRM clients have exited
1473  * @dev: DRM device
1474  *
1475  * Take care of cleaning up after all DRM clients have exited.  In the
1476  * mode setting case, we want to restore the kernel's initial mode (just
1477  * in case the last client left us in a bad state).
1478  *
1479  * Additionally, in the non-mode setting case, we'll tear down the GTT
1480  * and DMA structures, since the kernel won't be using them, and clea
1481  * up any GEM state.
1482  */
1483 static void i915_driver_lastclose(struct drm_device *dev)
1484 {
1485         intel_fbdev_restore_mode(dev);
1486         vga_switcheroo_process_delayed_switch();
1487 }
1488
1489 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1490 {
1491         struct drm_i915_file_private *file_priv = file->driver_priv;
1492
1493         mutex_lock(&dev->struct_mutex);
1494         i915_gem_context_close(file);
1495         i915_gem_release(dev, file);
1496         mutex_unlock(&dev->struct_mutex);
1497
1498         kfree(file_priv);
1499 }
1500
1501 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1502 {
1503         struct drm_device *dev = &dev_priv->drm;
1504         struct intel_encoder *encoder;
1505
1506         drm_modeset_lock_all(dev);
1507         for_each_intel_encoder(dev, encoder)
1508                 if (encoder->suspend)
1509                         encoder->suspend(encoder);
1510         drm_modeset_unlock_all(dev);
1511 }
1512
1513 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1514                               bool rpm_resume);
1515 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1516
1517 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1518 {
1519 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1520         if (acpi_target_system_state() < ACPI_STATE_S3)
1521                 return true;
1522 #endif
1523         return false;
1524 }
1525
1526 static int i915_drm_suspend(struct drm_device *dev)
1527 {
1528         struct drm_i915_private *dev_priv = to_i915(dev);
1529         struct pci_dev *pdev = dev_priv->drm.pdev;
1530         pci_power_t opregion_target_state;
1531         int error;
1532
1533         /* ignore lid events during suspend */
1534         mutex_lock(&dev_priv->modeset_restore_lock);
1535         dev_priv->modeset_restore = MODESET_SUSPENDED;
1536         mutex_unlock(&dev_priv->modeset_restore_lock);
1537
1538         disable_rpm_wakeref_asserts(dev_priv);
1539
1540         /* We do a lot of poking in a lot of registers, make sure they work
1541          * properly. */
1542         intel_display_set_init_power(dev_priv, true);
1543
1544         drm_kms_helper_poll_disable(dev);
1545
1546         pci_save_state(pdev);
1547
1548         error = i915_gem_suspend(dev_priv);
1549         if (error) {
1550                 dev_err(&pdev->dev,
1551                         "GEM idle failed, resume might fail\n");
1552                 goto out;
1553         }
1554
1555         intel_display_suspend(dev);
1556
1557         intel_dp_mst_suspend(dev);
1558
1559         intel_runtime_pm_disable_interrupts(dev_priv);
1560         intel_hpd_cancel_work(dev_priv);
1561
1562         intel_suspend_encoders(dev_priv);
1563
1564         intel_suspend_hw(dev_priv);
1565
1566         i915_gem_suspend_gtt_mappings(dev_priv);
1567
1568         i915_save_state(dev_priv);
1569
1570         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1571         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1572
1573         intel_uncore_suspend(dev_priv);
1574         intel_opregion_unregister(dev_priv);
1575
1576         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1577
1578         dev_priv->suspend_count++;
1579
1580         intel_csr_ucode_suspend(dev_priv);
1581
1582 out:
1583         enable_rpm_wakeref_asserts(dev_priv);
1584
1585         return error;
1586 }
1587
1588 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1589 {
1590         struct drm_i915_private *dev_priv = to_i915(dev);
1591         struct pci_dev *pdev = dev_priv->drm.pdev;
1592         bool fw_csr;
1593         int ret;
1594
1595         disable_rpm_wakeref_asserts(dev_priv);
1596
1597         intel_display_set_init_power(dev_priv, false);
1598
1599         fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1600                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1601         /*
1602          * In case of firmware assisted context save/restore don't manually
1603          * deinit the power domains. This also means the CSR/DMC firmware will
1604          * stay active, it will power down any HW resources as required and
1605          * also enable deeper system power states that would be blocked if the
1606          * firmware was inactive.
1607          */
1608         if (!fw_csr)
1609                 intel_power_domains_suspend(dev_priv);
1610
1611         ret = 0;
1612         if (IS_GEN9_LP(dev_priv))
1613                 bxt_enable_dc9(dev_priv);
1614         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1615                 hsw_enable_pc8(dev_priv);
1616         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1617                 ret = vlv_suspend_complete(dev_priv);
1618
1619         if (ret) {
1620                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1621                 if (!fw_csr)
1622                         intel_power_domains_init_hw(dev_priv, true);
1623
1624                 goto out;
1625         }
1626
1627         pci_disable_device(pdev);
1628         /*
1629          * During hibernation on some platforms the BIOS may try to access
1630          * the device even though it's already in D3 and hang the machine. So
1631          * leave the device in D0 on those platforms and hope the BIOS will
1632          * power down the device properly. The issue was seen on multiple old
1633          * GENs with different BIOS vendors, so having an explicit blacklist
1634          * is inpractical; apply the workaround on everything pre GEN6. The
1635          * platforms where the issue was seen:
1636          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1637          * Fujitsu FSC S7110
1638          * Acer Aspire 1830T
1639          */
1640         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1641                 pci_set_power_state(pdev, PCI_D3hot);
1642
1643         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1644
1645 out:
1646         enable_rpm_wakeref_asserts(dev_priv);
1647
1648         return ret;
1649 }
1650
1651 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1652 {
1653         int error;
1654
1655         if (!dev) {
1656                 DRM_ERROR("dev: %p\n", dev);
1657                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1658                 return -ENODEV;
1659         }
1660
1661         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1662                          state.event != PM_EVENT_FREEZE))
1663                 return -EINVAL;
1664
1665         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1666                 return 0;
1667
1668         error = i915_drm_suspend(dev);
1669         if (error)
1670                 return error;
1671
1672         return i915_drm_suspend_late(dev, false);
1673 }
1674
1675 static int i915_drm_resume(struct drm_device *dev)
1676 {
1677         struct drm_i915_private *dev_priv = to_i915(dev);
1678         int ret;
1679
1680         disable_rpm_wakeref_asserts(dev_priv);
1681         intel_sanitize_gt_powersave(dev_priv);
1682
1683         ret = i915_ggtt_enable_hw(dev_priv);
1684         if (ret)
1685                 DRM_ERROR("failed to re-enable GGTT\n");
1686
1687         intel_csr_ucode_resume(dev_priv);
1688
1689         i915_restore_state(dev_priv);
1690         intel_pps_unlock_regs_wa(dev_priv);
1691         intel_opregion_setup(dev_priv);
1692
1693         intel_init_pch_refclk(dev_priv);
1694
1695         /*
1696          * Interrupts have to be enabled before any batches are run. If not the
1697          * GPU will hang. i915_gem_init_hw() will initiate batches to
1698          * update/restore the context.
1699          *
1700          * drm_mode_config_reset() needs AUX interrupts.
1701          *
1702          * Modeset enabling in intel_modeset_init_hw() also needs working
1703          * interrupts.
1704          */
1705         intel_runtime_pm_enable_interrupts(dev_priv);
1706
1707         drm_mode_config_reset(dev);
1708
1709         i915_gem_resume(dev_priv);
1710
1711         intel_modeset_init_hw(dev);
1712
1713         spin_lock_irq(&dev_priv->irq_lock);
1714         if (dev_priv->display.hpd_irq_setup)
1715                 dev_priv->display.hpd_irq_setup(dev_priv);
1716         spin_unlock_irq(&dev_priv->irq_lock);
1717
1718         intel_dp_mst_resume(dev);
1719
1720         intel_display_resume(dev);
1721
1722         drm_kms_helper_poll_enable(dev);
1723
1724         /*
1725          * ... but also need to make sure that hotplug processing
1726          * doesn't cause havoc. Like in the driver load code we don't
1727          * bother with the tiny race here where we might loose hotplug
1728          * notifications.
1729          * */
1730         intel_hpd_init(dev_priv);
1731
1732         intel_opregion_register(dev_priv);
1733
1734         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1735
1736         mutex_lock(&dev_priv->modeset_restore_lock);
1737         dev_priv->modeset_restore = MODESET_DONE;
1738         mutex_unlock(&dev_priv->modeset_restore_lock);
1739
1740         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1741
1742         enable_rpm_wakeref_asserts(dev_priv);
1743
1744         return 0;
1745 }
1746
1747 static int i915_drm_resume_early(struct drm_device *dev)
1748 {
1749         struct drm_i915_private *dev_priv = to_i915(dev);
1750         struct pci_dev *pdev = dev_priv->drm.pdev;
1751         int ret;
1752
1753         /*
1754          * We have a resume ordering issue with the snd-hda driver also
1755          * requiring our device to be power up. Due to the lack of a
1756          * parent/child relationship we currently solve this with an early
1757          * resume hook.
1758          *
1759          * FIXME: This should be solved with a special hdmi sink device or
1760          * similar so that power domains can be employed.
1761          */
1762
1763         /*
1764          * Note that we need to set the power state explicitly, since we
1765          * powered off the device during freeze and the PCI core won't power
1766          * it back up for us during thaw. Powering off the device during
1767          * freeze is not a hard requirement though, and during the
1768          * suspend/resume phases the PCI core makes sure we get here with the
1769          * device powered on. So in case we change our freeze logic and keep
1770          * the device powered we can also remove the following set power state
1771          * call.
1772          */
1773         ret = pci_set_power_state(pdev, PCI_D0);
1774         if (ret) {
1775                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1776                 goto out;
1777         }
1778
1779         /*
1780          * Note that pci_enable_device() first enables any parent bridge
1781          * device and only then sets the power state for this device. The
1782          * bridge enabling is a nop though, since bridge devices are resumed
1783          * first. The order of enabling power and enabling the device is
1784          * imposed by the PCI core as described above, so here we preserve the
1785          * same order for the freeze/thaw phases.
1786          *
1787          * TODO: eventually we should remove pci_disable_device() /
1788          * pci_enable_enable_device() from suspend/resume. Due to how they
1789          * depend on the device enable refcount we can't anyway depend on them
1790          * disabling/enabling the device.
1791          */
1792         if (pci_enable_device(pdev)) {
1793                 ret = -EIO;
1794                 goto out;
1795         }
1796
1797         pci_set_master(pdev);
1798
1799         disable_rpm_wakeref_asserts(dev_priv);
1800
1801         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1802                 ret = vlv_resume_prepare(dev_priv, false);
1803         if (ret)
1804                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1805                           ret);
1806
1807         intel_uncore_resume_early(dev_priv);
1808
1809         if (IS_GEN9_LP(dev_priv)) {
1810                 if (!dev_priv->suspended_to_idle)
1811                         gen9_sanitize_dc_state(dev_priv);
1812                 bxt_disable_dc9(dev_priv);
1813         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1814                 hsw_disable_pc8(dev_priv);
1815         }
1816
1817         intel_uncore_sanitize(dev_priv);
1818
1819         if (IS_GEN9_LP(dev_priv) ||
1820             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1821                 intel_power_domains_init_hw(dev_priv, true);
1822
1823         i915_gem_sanitize(dev_priv);
1824
1825         enable_rpm_wakeref_asserts(dev_priv);
1826
1827 out:
1828         dev_priv->suspended_to_idle = false;
1829
1830         return ret;
1831 }
1832
1833 static int i915_resume_switcheroo(struct drm_device *dev)
1834 {
1835         int ret;
1836
1837         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1838                 return 0;
1839
1840         ret = i915_drm_resume_early(dev);
1841         if (ret)
1842                 return ret;
1843
1844         return i915_drm_resume(dev);
1845 }
1846
1847 /**
1848  * i915_reset - reset chip after a hang
1849  * @i915: #drm_i915_private to reset
1850  * @flags: Instructions
1851  *
1852  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1853  * on failure.
1854  *
1855  * Caller must hold the struct_mutex.
1856  *
1857  * Procedure is fairly simple:
1858  *   - reset the chip using the reset reg
1859  *   - re-init context state
1860  *   - re-init hardware status page
1861  *   - re-init ring buffer
1862  *   - re-init interrupt state
1863  *   - re-init display
1864  */
1865 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1866 {
1867         struct i915_gpu_error *error = &i915->gpu_error;
1868         int ret;
1869
1870         lockdep_assert_held(&i915->drm.struct_mutex);
1871         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1872
1873         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1874                 return;
1875
1876         /* Clear any previous failed attempts at recovery. Time to try again. */
1877         if (!i915_gem_unset_wedged(i915))
1878                 goto wakeup;
1879
1880         if (!(flags & I915_RESET_QUIET))
1881                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1882         error->reset_count++;
1883
1884         disable_irq(i915->drm.irq);
1885         ret = i915_gem_reset_prepare(i915);
1886         if (ret) {
1887                 DRM_ERROR("GPU recovery failed\n");
1888                 intel_gpu_reset(i915, ALL_ENGINES);
1889                 goto error;
1890         }
1891
1892         ret = intel_gpu_reset(i915, ALL_ENGINES);
1893         if (ret) {
1894                 if (ret != -ENODEV)
1895                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1896                 else
1897                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1898                 goto error;
1899         }
1900
1901         i915_gem_reset(i915);
1902         intel_overlay_reset(i915);
1903
1904         /* Ok, now get things going again... */
1905
1906         /*
1907          * Everything depends on having the GTT running, so we need to start
1908          * there.
1909          */
1910         ret = i915_ggtt_enable_hw(i915);
1911         if (ret) {
1912                 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1913                 goto error;
1914         }
1915
1916         /*
1917          * Next we need to restore the context, but we don't use those
1918          * yet either...
1919          *
1920          * Ring buffer needs to be re-initialized in the KMS case, or if X
1921          * was running at the time of the reset (i.e. we weren't VT
1922          * switched away).
1923          */
1924         ret = i915_gem_init_hw(i915);
1925         if (ret) {
1926                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1927                 goto error;
1928         }
1929
1930         i915_queue_hangcheck(i915);
1931
1932 finish:
1933         i915_gem_reset_finish(i915);
1934         enable_irq(i915->drm.irq);
1935
1936 wakeup:
1937         clear_bit(I915_RESET_HANDOFF, &error->flags);
1938         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1939         return;
1940
1941 error:
1942         i915_gem_set_wedged(i915);
1943         i915_gem_retire_requests(i915);
1944         goto finish;
1945 }
1946
1947 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
1948                                         struct intel_engine_cs *engine)
1949 {
1950         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
1951 }
1952
1953 /**
1954  * i915_reset_engine - reset GPU engine to recover from a hang
1955  * @engine: engine to reset
1956  * @flags: options
1957  *
1958  * Reset a specific GPU engine. Useful if a hang is detected.
1959  * Returns zero on successful reset or otherwise an error code.
1960  *
1961  * Procedure is:
1962  *  - identifies the request that caused the hang and it is dropped
1963  *  - reset engine (which will force the engine to idle)
1964  *  - re-init/configure engine
1965  */
1966 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
1967 {
1968         struct i915_gpu_error *error = &engine->i915->gpu_error;
1969         struct drm_i915_gem_request *active_request;
1970         int ret;
1971
1972         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1973
1974         if (!(flags & I915_RESET_QUIET)) {
1975                 dev_notice(engine->i915->drm.dev,
1976                            "Resetting %s after gpu hang\n", engine->name);
1977         }
1978         error->reset_engine_count[engine->id]++;
1979
1980         active_request = i915_gem_reset_prepare_engine(engine);
1981         if (IS_ERR(active_request)) {
1982                 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1983                 ret = PTR_ERR(active_request);
1984                 goto out;
1985         }
1986
1987         if (!engine->i915->guc.execbuf_client)
1988                 ret = intel_gt_reset_engine(engine->i915, engine);
1989         else
1990                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
1991         if (ret) {
1992                 /* If we fail here, we expect to fallback to a global reset */
1993                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
1994                                  engine->i915->guc.execbuf_client ? "GuC " : "",
1995                                  engine->name, ret);
1996                 goto out;
1997         }
1998
1999         /*
2000          * The request that caused the hang is stuck on elsp, we know the
2001          * active request and can drop it, adjust head to skip the offending
2002          * request to resume executing remaining requests in the queue.
2003          */
2004         i915_gem_reset_engine(engine, active_request);
2005
2006         /*
2007          * The engine and its registers (and workarounds in case of render)
2008          * have been reset to their default values. Follow the init_ring
2009          * process to program RING_MODE, HWSP and re-enable submission.
2010          */
2011         ret = engine->init_hw(engine);
2012         if (ret)
2013                 goto out;
2014
2015 out:
2016         i915_gem_reset_finish_engine(engine);
2017         return ret;
2018 }
2019
2020 static int i915_pm_suspend(struct device *kdev)
2021 {
2022         struct pci_dev *pdev = to_pci_dev(kdev);
2023         struct drm_device *dev = pci_get_drvdata(pdev);
2024
2025         if (!dev) {
2026                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2027                 return -ENODEV;
2028         }
2029
2030         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2031                 return 0;
2032
2033         return i915_drm_suspend(dev);
2034 }
2035
2036 static int i915_pm_suspend_late(struct device *kdev)
2037 {
2038         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2039
2040         /*
2041          * We have a suspend ordering issue with the snd-hda driver also
2042          * requiring our device to be power up. Due to the lack of a
2043          * parent/child relationship we currently solve this with an late
2044          * suspend hook.
2045          *
2046          * FIXME: This should be solved with a special hdmi sink device or
2047          * similar so that power domains can be employed.
2048          */
2049         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2050                 return 0;
2051
2052         return i915_drm_suspend_late(dev, false);
2053 }
2054
2055 static int i915_pm_poweroff_late(struct device *kdev)
2056 {
2057         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2058
2059         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2060                 return 0;
2061
2062         return i915_drm_suspend_late(dev, true);
2063 }
2064
2065 static int i915_pm_resume_early(struct device *kdev)
2066 {
2067         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2068
2069         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2070                 return 0;
2071
2072         return i915_drm_resume_early(dev);
2073 }
2074
2075 static int i915_pm_resume(struct device *kdev)
2076 {
2077         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2078
2079         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2080                 return 0;
2081
2082         return i915_drm_resume(dev);
2083 }
2084
2085 /* freeze: before creating the hibernation_image */
2086 static int i915_pm_freeze(struct device *kdev)
2087 {
2088         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2089         int ret;
2090
2091         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2092                 ret = i915_drm_suspend(dev);
2093                 if (ret)
2094                         return ret;
2095         }
2096
2097         ret = i915_gem_freeze(kdev_to_i915(kdev));
2098         if (ret)
2099                 return ret;
2100
2101         return 0;
2102 }
2103
2104 static int i915_pm_freeze_late(struct device *kdev)
2105 {
2106         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2107         int ret;
2108
2109         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2110                 ret = i915_drm_suspend_late(dev, true);
2111                 if (ret)
2112                         return ret;
2113         }
2114
2115         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2116         if (ret)
2117                 return ret;
2118
2119         return 0;
2120 }
2121
2122 /* thaw: called after creating the hibernation image, but before turning off. */
2123 static int i915_pm_thaw_early(struct device *kdev)
2124 {
2125         return i915_pm_resume_early(kdev);
2126 }
2127
2128 static int i915_pm_thaw(struct device *kdev)
2129 {
2130         return i915_pm_resume(kdev);
2131 }
2132
2133 /* restore: called after loading the hibernation image. */
2134 static int i915_pm_restore_early(struct device *kdev)
2135 {
2136         return i915_pm_resume_early(kdev);
2137 }
2138
2139 static int i915_pm_restore(struct device *kdev)
2140 {
2141         return i915_pm_resume(kdev);
2142 }
2143
2144 /*
2145  * Save all Gunit registers that may be lost after a D3 and a subsequent
2146  * S0i[R123] transition. The list of registers needing a save/restore is
2147  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2148  * registers in the following way:
2149  * - Driver: saved/restored by the driver
2150  * - Punit : saved/restored by the Punit firmware
2151  * - No, w/o marking: no need to save/restore, since the register is R/O or
2152  *                    used internally by the HW in a way that doesn't depend
2153  *                    keeping the content across a suspend/resume.
2154  * - Debug : used for debugging
2155  *
2156  * We save/restore all registers marked with 'Driver', with the following
2157  * exceptions:
2158  * - Registers out of use, including also registers marked with 'Debug'.
2159  *   These have no effect on the driver's operation, so we don't save/restore
2160  *   them to reduce the overhead.
2161  * - Registers that are fully setup by an initialization function called from
2162  *   the resume path. For example many clock gating and RPS/RC6 registers.
2163  * - Registers that provide the right functionality with their reset defaults.
2164  *
2165  * TODO: Except for registers that based on the above 3 criteria can be safely
2166  * ignored, we save/restore all others, practically treating the HW context as
2167  * a black-box for the driver. Further investigation is needed to reduce the
2168  * saved/restored registers even further, by following the same 3 criteria.
2169  */
2170 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2171 {
2172         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2173         int i;
2174
2175         /* GAM 0x4000-0x4770 */
2176         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2177         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2178         s->arb_mode             = I915_READ(ARB_MODE);
2179         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2180         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2181
2182         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2183                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2184
2185         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2186         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2187
2188         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2189         s->ecochk               = I915_READ(GAM_ECOCHK);
2190         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2191         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2192
2193         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2194
2195         /* MBC 0x9024-0x91D0, 0x8500 */
2196         s->g3dctl               = I915_READ(VLV_G3DCTL);
2197         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2198         s->mbctl                = I915_READ(GEN6_MBCTL);
2199
2200         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2201         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2202         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2203         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2204         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2205         s->rstctl               = I915_READ(GEN6_RSTCTL);
2206         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2207
2208         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2209         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2210         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2211         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2212         s->ecobus               = I915_READ(ECOBUS);
2213         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2214         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2215         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2216         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2217         s->rcedata              = I915_READ(VLV_RCEDATA);
2218         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2219
2220         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2221         s->gt_imr               = I915_READ(GTIMR);
2222         s->gt_ier               = I915_READ(GTIER);
2223         s->pm_imr               = I915_READ(GEN6_PMIMR);
2224         s->pm_ier               = I915_READ(GEN6_PMIER);
2225
2226         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2227                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2228
2229         /* GT SA CZ domain, 0x100000-0x138124 */
2230         s->tilectl              = I915_READ(TILECTL);
2231         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2232         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2233         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2234         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2235
2236         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2237         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2238         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2239         s->pcbr                 = I915_READ(VLV_PCBR);
2240         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2241
2242         /*
2243          * Not saving any of:
2244          * DFT,         0x9800-0x9EC0
2245          * SARB,        0xB000-0xB1FC
2246          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2247          * PCI CFG
2248          */
2249 }
2250
2251 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2252 {
2253         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2254         u32 val;
2255         int i;
2256
2257         /* GAM 0x4000-0x4770 */
2258         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2259         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2260         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2261         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2262         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2263
2264         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2265                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2266
2267         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2268         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2269
2270         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2271         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2272         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2273         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2274
2275         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2276
2277         /* MBC 0x9024-0x91D0, 0x8500 */
2278         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2279         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2280         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2281
2282         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2283         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2284         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2285         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2286         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2287         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2288         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2289
2290         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2291         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2292         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2293         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2294         I915_WRITE(ECOBUS,              s->ecobus);
2295         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2296         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2297         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2298         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2299         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2300         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2301
2302         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2303         I915_WRITE(GTIMR,               s->gt_imr);
2304         I915_WRITE(GTIER,               s->gt_ier);
2305         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2306         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2307
2308         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2309                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2310
2311         /* GT SA CZ domain, 0x100000-0x138124 */
2312         I915_WRITE(TILECTL,                     s->tilectl);
2313         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2314         /*
2315          * Preserve the GT allow wake and GFX force clock bit, they are not
2316          * be restored, as they are used to control the s0ix suspend/resume
2317          * sequence by the caller.
2318          */
2319         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2320         val &= VLV_GTLC_ALLOWWAKEREQ;
2321         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2322         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2323
2324         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2325         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2326         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2327         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2328
2329         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2330
2331         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2332         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2333         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2334         I915_WRITE(VLV_PCBR,                    s->pcbr);
2335         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2336 }
2337
2338 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2339                                   u32 mask, u32 val)
2340 {
2341         /* The HW does not like us polling for PW_STATUS frequently, so
2342          * use the sleeping loop rather than risk the busy spin within
2343          * intel_wait_for_register().
2344          *
2345          * Transitioning between RC6 states should be at most 2ms (see
2346          * valleyview_enable_rps) so use a 3ms timeout.
2347          */
2348         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2349                         3);
2350 }
2351
2352 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2353 {
2354         u32 val;
2355         int err;
2356
2357         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2358         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2359         if (force_on)
2360                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2361         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2362
2363         if (!force_on)
2364                 return 0;
2365
2366         err = intel_wait_for_register(dev_priv,
2367                                       VLV_GTLC_SURVIVABILITY_REG,
2368                                       VLV_GFX_CLK_STATUS_BIT,
2369                                       VLV_GFX_CLK_STATUS_BIT,
2370                                       20);
2371         if (err)
2372                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2373                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2374
2375         return err;
2376 }
2377
2378 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2379 {
2380         u32 mask;
2381         u32 val;
2382         int err;
2383
2384         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2385         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2386         if (allow)
2387                 val |= VLV_GTLC_ALLOWWAKEREQ;
2388         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2389         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2390
2391         mask = VLV_GTLC_ALLOWWAKEACK;
2392         val = allow ? mask : 0;
2393
2394         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2395         if (err)
2396                 DRM_ERROR("timeout disabling GT waking\n");
2397
2398         return err;
2399 }
2400
2401 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2402                                   bool wait_for_on)
2403 {
2404         u32 mask;
2405         u32 val;
2406
2407         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2408         val = wait_for_on ? mask : 0;
2409
2410         /*
2411          * RC6 transitioning can be delayed up to 2 msec (see
2412          * valleyview_enable_rps), use 3 msec for safety.
2413          */
2414         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2415                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2416                           onoff(wait_for_on));
2417 }
2418
2419 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2420 {
2421         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2422                 return;
2423
2424         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2425         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2426 }
2427
2428 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2429 {
2430         u32 mask;
2431         int err;
2432
2433         /*
2434          * Bspec defines the following GT well on flags as debug only, so
2435          * don't treat them as hard failures.
2436          */
2437         vlv_wait_for_gt_wells(dev_priv, false);
2438
2439         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2440         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2441
2442         vlv_check_no_gt_access(dev_priv);
2443
2444         err = vlv_force_gfx_clock(dev_priv, true);
2445         if (err)
2446                 goto err1;
2447
2448         err = vlv_allow_gt_wake(dev_priv, false);
2449         if (err)
2450                 goto err2;
2451
2452         if (!IS_CHERRYVIEW(dev_priv))
2453                 vlv_save_gunit_s0ix_state(dev_priv);
2454
2455         err = vlv_force_gfx_clock(dev_priv, false);
2456         if (err)
2457                 goto err2;
2458
2459         return 0;
2460
2461 err2:
2462         /* For safety always re-enable waking and disable gfx clock forcing */
2463         vlv_allow_gt_wake(dev_priv, true);
2464 err1:
2465         vlv_force_gfx_clock(dev_priv, false);
2466
2467         return err;
2468 }
2469
2470 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2471                                 bool rpm_resume)
2472 {
2473         int err;
2474         int ret;
2475
2476         /*
2477          * If any of the steps fail just try to continue, that's the best we
2478          * can do at this point. Return the first error code (which will also
2479          * leave RPM permanently disabled).
2480          */
2481         ret = vlv_force_gfx_clock(dev_priv, true);
2482
2483         if (!IS_CHERRYVIEW(dev_priv))
2484                 vlv_restore_gunit_s0ix_state(dev_priv);
2485
2486         err = vlv_allow_gt_wake(dev_priv, true);
2487         if (!ret)
2488                 ret = err;
2489
2490         err = vlv_force_gfx_clock(dev_priv, false);
2491         if (!ret)
2492                 ret = err;
2493
2494         vlv_check_no_gt_access(dev_priv);
2495
2496         if (rpm_resume)
2497                 intel_init_clock_gating(dev_priv);
2498
2499         return ret;
2500 }
2501
2502 static int intel_runtime_suspend(struct device *kdev)
2503 {
2504         struct pci_dev *pdev = to_pci_dev(kdev);
2505         struct drm_device *dev = pci_get_drvdata(pdev);
2506         struct drm_i915_private *dev_priv = to_i915(dev);
2507         int ret;
2508
2509         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled())))
2510                 return -ENODEV;
2511
2512         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2513                 return -ENODEV;
2514
2515         DRM_DEBUG_KMS("Suspending device\n");
2516
2517         disable_rpm_wakeref_asserts(dev_priv);
2518
2519         /*
2520          * We are safe here against re-faults, since the fault handler takes
2521          * an RPM reference.
2522          */
2523         i915_gem_runtime_suspend(dev_priv);
2524
2525         intel_guc_suspend(dev_priv);
2526
2527         intel_runtime_pm_disable_interrupts(dev_priv);
2528
2529         intel_uncore_suspend(dev_priv);
2530
2531         ret = 0;
2532         if (IS_GEN9_LP(dev_priv)) {
2533                 bxt_display_core_uninit(dev_priv);
2534                 bxt_enable_dc9(dev_priv);
2535         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2536                 hsw_enable_pc8(dev_priv);
2537         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2538                 ret = vlv_suspend_complete(dev_priv);
2539         }
2540
2541         if (ret) {
2542                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2543                 intel_uncore_runtime_resume(dev_priv);
2544
2545                 intel_runtime_pm_enable_interrupts(dev_priv);
2546
2547                 enable_rpm_wakeref_asserts(dev_priv);
2548
2549                 return ret;
2550         }
2551
2552         enable_rpm_wakeref_asserts(dev_priv);
2553         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2554
2555         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2556                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2557
2558         dev_priv->runtime_pm.suspended = true;
2559
2560         /*
2561          * FIXME: We really should find a document that references the arguments
2562          * used below!
2563          */
2564         if (IS_BROADWELL(dev_priv)) {
2565                 /*
2566                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2567                  * being detected, and the call we do at intel_runtime_resume()
2568                  * won't be able to restore them. Since PCI_D3hot matches the
2569                  * actual specification and appears to be working, use it.
2570                  */
2571                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2572         } else {
2573                 /*
2574                  * current versions of firmware which depend on this opregion
2575                  * notification have repurposed the D1 definition to mean
2576                  * "runtime suspended" vs. what you would normally expect (D3)
2577                  * to distinguish it from notifications that might be sent via
2578                  * the suspend path.
2579                  */
2580                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2581         }
2582
2583         assert_forcewakes_inactive(dev_priv);
2584
2585         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2586                 intel_hpd_poll_init(dev_priv);
2587
2588         DRM_DEBUG_KMS("Device suspended\n");
2589         return 0;
2590 }
2591
2592 static int intel_runtime_resume(struct device *kdev)
2593 {
2594         struct pci_dev *pdev = to_pci_dev(kdev);
2595         struct drm_device *dev = pci_get_drvdata(pdev);
2596         struct drm_i915_private *dev_priv = to_i915(dev);
2597         int ret = 0;
2598
2599         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2600                 return -ENODEV;
2601
2602         DRM_DEBUG_KMS("Resuming device\n");
2603
2604         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2605         disable_rpm_wakeref_asserts(dev_priv);
2606
2607         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2608         dev_priv->runtime_pm.suspended = false;
2609         if (intel_uncore_unclaimed_mmio(dev_priv))
2610                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2611
2612         intel_guc_resume(dev_priv);
2613
2614         if (IS_GEN9_LP(dev_priv)) {
2615                 bxt_disable_dc9(dev_priv);
2616                 bxt_display_core_init(dev_priv, true);
2617                 if (dev_priv->csr.dmc_payload &&
2618                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2619                         gen9_enable_dc5(dev_priv);
2620         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2621                 hsw_disable_pc8(dev_priv);
2622         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2623                 ret = vlv_resume_prepare(dev_priv, true);
2624         }
2625
2626         intel_uncore_runtime_resume(dev_priv);
2627
2628         /*
2629          * No point of rolling back things in case of an error, as the best
2630          * we can do is to hope that things will still work (and disable RPM).
2631          */
2632         i915_gem_init_swizzling(dev_priv);
2633         i915_gem_restore_fences(dev_priv);
2634
2635         intel_runtime_pm_enable_interrupts(dev_priv);
2636
2637         /*
2638          * On VLV/CHV display interrupts are part of the display
2639          * power well, so hpd is reinitialized from there. For
2640          * everyone else do it here.
2641          */
2642         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2643                 intel_hpd_init(dev_priv);
2644
2645         intel_enable_ipc(dev_priv);
2646
2647         enable_rpm_wakeref_asserts(dev_priv);
2648
2649         if (ret)
2650                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2651         else
2652                 DRM_DEBUG_KMS("Device resumed\n");
2653
2654         return ret;
2655 }
2656
2657 const struct dev_pm_ops i915_pm_ops = {
2658         /*
2659          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2660          * PMSG_RESUME]
2661          */
2662         .suspend = i915_pm_suspend,
2663         .suspend_late = i915_pm_suspend_late,
2664         .resume_early = i915_pm_resume_early,
2665         .resume = i915_pm_resume,
2666
2667         /*
2668          * S4 event handlers
2669          * @freeze, @freeze_late    : called (1) before creating the
2670          *                            hibernation image [PMSG_FREEZE] and
2671          *                            (2) after rebooting, before restoring
2672          *                            the image [PMSG_QUIESCE]
2673          * @thaw, @thaw_early       : called (1) after creating the hibernation
2674          *                            image, before writing it [PMSG_THAW]
2675          *                            and (2) after failing to create or
2676          *                            restore the image [PMSG_RECOVER]
2677          * @poweroff, @poweroff_late: called after writing the hibernation
2678          *                            image, before rebooting [PMSG_HIBERNATE]
2679          * @restore, @restore_early : called after rebooting and restoring the
2680          *                            hibernation image [PMSG_RESTORE]
2681          */
2682         .freeze = i915_pm_freeze,
2683         .freeze_late = i915_pm_freeze_late,
2684         .thaw_early = i915_pm_thaw_early,
2685         .thaw = i915_pm_thaw,
2686         .poweroff = i915_pm_suspend,
2687         .poweroff_late = i915_pm_poweroff_late,
2688         .restore_early = i915_pm_restore_early,
2689         .restore = i915_pm_restore,
2690
2691         /* S0ix (via runtime suspend) event handlers */
2692         .runtime_suspend = intel_runtime_suspend,
2693         .runtime_resume = intel_runtime_resume,
2694 };
2695
2696 static const struct vm_operations_struct i915_gem_vm_ops = {
2697         .fault = i915_gem_fault,
2698         .open = drm_gem_vm_open,
2699         .close = drm_gem_vm_close,
2700 };
2701
2702 static const struct file_operations i915_driver_fops = {
2703         .owner = THIS_MODULE,
2704         .open = drm_open,
2705         .release = drm_release,
2706         .unlocked_ioctl = drm_ioctl,
2707         .mmap = drm_gem_mmap,
2708         .poll = drm_poll,
2709         .read = drm_read,
2710         .compat_ioctl = i915_compat_ioctl,
2711         .llseek = noop_llseek,
2712 };
2713
2714 static int
2715 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2716                           struct drm_file *file)
2717 {
2718         return -ENODEV;
2719 }
2720
2721 static const struct drm_ioctl_desc i915_ioctls[] = {
2722         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2723         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2724         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2725         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2726         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2727         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2728         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2729         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2730         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2731         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2732         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2733         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2734         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2735         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2736         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2737         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2738         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2739         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2740         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2741         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2742         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2743         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2744         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2745         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2746         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2747         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2748         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2749         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2750         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2751         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2752         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2753         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2754         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2755         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2756         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2757         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2758         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2759         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2760         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2761         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2762         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2763         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2764         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2765         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2766         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2767         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2768         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2769         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2770         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2771         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2772         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2773         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2774         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2775         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2776         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2777 };
2778
2779 static struct drm_driver driver = {
2780         /* Don't use MTRRs here; the Xserver or userspace app should
2781          * deal with them for Intel hardware.
2782          */
2783         .driver_features =
2784             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2785             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2786         .release = i915_driver_release,
2787         .open = i915_driver_open,
2788         .lastclose = i915_driver_lastclose,
2789         .postclose = i915_driver_postclose,
2790
2791         .gem_close_object = i915_gem_close_object,
2792         .gem_free_object_unlocked = i915_gem_free_object,
2793         .gem_vm_ops = &i915_gem_vm_ops,
2794
2795         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2796         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2797         .gem_prime_export = i915_gem_prime_export,
2798         .gem_prime_import = i915_gem_prime_import,
2799
2800         .dumb_create = i915_gem_dumb_create,
2801         .dumb_map_offset = i915_gem_mmap_gtt,
2802         .ioctls = i915_ioctls,
2803         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2804         .fops = &i915_driver_fops,
2805         .name = DRIVER_NAME,
2806         .desc = DRIVER_DESC,
2807         .date = DRIVER_DATE,
2808         .major = DRIVER_MAJOR,
2809         .minor = DRIVER_MINOR,
2810         .patchlevel = DRIVER_PATCHLEVEL,
2811 };
2812
2813 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2814 #include "selftests/mock_drm.c"
2815 #endif