drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *dev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(dev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 182                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 183                                 /* PantherPoint is CPT compatible */
 184                                 dev_priv->pch_type = PCH_CPT;
 185                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 186                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 187                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_LPT;
 189                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 190                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 191                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 192                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 193                                 dev_priv->pch_type = PCH_LPT;
 194                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 195                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 196                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 197                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_SPT;
 199                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 200                                 WARN_ON(!IS_SKYLAKE(dev) &&
 201                                         !IS_KABYLAKE(dev));
 202                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 203                                 dev_priv->pch_type = PCH_SPT;
 204                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 205                                 WARN_ON(!IS_SKYLAKE(dev) &&
 206                                         !IS_KABYLAKE(dev));
 207                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 208                                 dev_priv->pch_type = PCH_KBP;
 209                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 210                                 WARN_ON(!IS_KABYLAKE(dev));
 211                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 212                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 213                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 214                                     pch->subsystem_vendor ==
 215                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 216                                     pch->subsystem_device ==
 217                                             PCI_SUBDEVICE_ID_QEMU)) {
 218                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 219                         } else
 220                                 continue;
 221
 222                         break;
 223                 }
 224         }
 225         if (!pch)
 226                 DRM_DEBUG_KMS("No PCH found.\n");
 227
 228         pci_dev_put(pch);
 229 }
 230
 231 static int i915_getparam(struct drm_device *dev, void *data,
 232                          struct drm_file *file_priv)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(dev);
 235         drm_i915_getparam_t *param = data;
 236         int value;
 237
 238         switch (param->param) {
 239         case I915_PARAM_IRQ_ACTIVE:
 240         case I915_PARAM_ALLOW_BATCHBUFFER:
 241         case I915_PARAM_LAST_DISPATCH:
 242                 /* Reject all old ums/dri params. */
 243                 return -ENODEV;
 244         case I915_PARAM_CHIPSET_ID:
 245                 value = dev->pdev->device;
 246                 break;
 247         case I915_PARAM_REVISION:
 248                 value = dev->pdev->revision;
 249                 break;
 250         case I915_PARAM_HAS_GEM:
 251                 value = 1;
 252                 break;
 253         case I915_PARAM_NUM_FENCES_AVAIL:
 254                 value = dev_priv->num_fence_regs;
 255                 break;
 256         case I915_PARAM_HAS_OVERLAY:
 257                 value = dev_priv->overlay ? 1 : 0;
 258                 break;
 259         case I915_PARAM_HAS_PAGEFLIPPING:
 260                 value = 1;
 261                 break;
 262         case I915_PARAM_HAS_EXECBUF2:
 263                 /* depends on GEM */
 264                 value = 1;
 265                 break;
 266         case I915_PARAM_HAS_BSD:
 267                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 268                 break;
 269         case I915_PARAM_HAS_BLT:
 270                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 271                 break;
 272         case I915_PARAM_HAS_VEBOX:
 273                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 274                 break;
 275         case I915_PARAM_HAS_BSD2:
 276                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 277                 break;
 278         case I915_PARAM_HAS_RELAXED_FENCING:
 279                 value = 1;
 280                 break;
 281         case I915_PARAM_HAS_COHERENT_RINGS:
 282                 value = 1;
 283                 break;
 284         case I915_PARAM_HAS_EXEC_CONSTANTS:
 285                 value = INTEL_INFO(dev)->gen >= 4;
 286                 break;
 287         case I915_PARAM_HAS_RELAXED_DELTA:
 288                 value = 1;
 289                 break;
 290         case I915_PARAM_HAS_GEN7_SOL_RESET:
 291                 value = 1;
 292                 break;
 293         case I915_PARAM_HAS_LLC:
 294                 value = HAS_LLC(dev);
 295                 break;
 296         case I915_PARAM_HAS_WT:
 297                 value = HAS_WT(dev);
 298                 break;
 299         case I915_PARAM_HAS_ALIASING_PPGTT:
 300                 value = USES_PPGTT(dev);
 301                 break;
 302         case I915_PARAM_HAS_WAIT_TIMEOUT:
 303                 value = 1;
 304                 break;
 305         case I915_PARAM_HAS_SEMAPHORES:
 306                 value = i915.semaphores;
 307                 break;
 308         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 309                 value = 1;
 310                 break;
 311         case I915_PARAM_HAS_SECURE_BATCHES:
 312                 value = capable(CAP_SYS_ADMIN);
 313                 break;
 314         case I915_PARAM_HAS_PINNED_BATCHES:
 315                 value = 1;
 316                 break;
 317         case I915_PARAM_HAS_EXEC_NO_RELOC:
 318                 value = 1;
 319                 break;
 320         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 321                 value = 1;
 322                 break;
 323         case I915_PARAM_CMD_PARSER_VERSION:
 324                 value = i915_cmd_parser_get_version(dev_priv);
 325                 break;
 326         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 327                 value = 1;
 328                 break;
 329         case I915_PARAM_MMAP_VERSION:
 330                 value = 1;
 331                 break;
 332         case I915_PARAM_SUBSLICE_TOTAL:
 333                 value = INTEL_INFO(dev)->subslice_total;
 334                 if (!value)
 335                         return -ENODEV;
 336                 break;
 337         case I915_PARAM_EU_TOTAL:
 338                 value = INTEL_INFO(dev)->eu_total;
 339                 if (!value)
 340                         return -ENODEV;
 341                 break;
 342         case I915_PARAM_HAS_GPU_RESET:
 343                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 344                 break;
 345         case I915_PARAM_HAS_RESOURCE_STREAMER:
 346                 value = HAS_RESOURCE_STREAMER(dev);
 347                 break;
 348         case I915_PARAM_HAS_EXEC_SOFTPIN:
 349                 value = 1;
 350                 break;
 351         case I915_PARAM_HAS_POOLED_EU:
 352                 value = HAS_POOLED_EU(dev);
 353                 break;
 354         case I915_PARAM_MIN_EU_IN_POOL:
 355                 value = INTEL_INFO(dev)->min_eu_in_pool;
 356                 break;
 357         default:
 358                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 359                 return -EINVAL;
 360         }
 361
 362         if (put_user(value, param->value))
 363                 return -EFAULT;
 364
 365         return 0;
 366 }
 367
 368 static int i915_get_bridge_dev(struct drm_device *dev)
 369 {
 370         struct drm_i915_private *dev_priv = to_i915(dev);
 371
 372         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 373         if (!dev_priv->bridge_dev) {
 374                 DRM_ERROR("bridge device not found\n");
 375                 return -1;
 376         }
 377         return 0;
 378 }
 379
 380 /* Allocate space for the MCH regs if needed, return nonzero on error */
 381 static int
 382 intel_alloc_mchbar_resource(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = to_i915(dev);
 385         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 386         u32 temp_lo, temp_hi = 0;
 387         u64 mchbar_addr;
 388         int ret;
 389
 390         if (INTEL_INFO(dev)->gen >= 4)
 391                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 392         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 393         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 394
 395         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 396 #ifdef CONFIG_PNP
 397         if (mchbar_addr &&
 398             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 399                 return 0;
 400 #endif
 401
 402         /* Get some space for it */
 403         dev_priv->mch_res.name = "i915 MCHBAR";
 404         dev_priv->mch_res.flags = IORESOURCE_MEM;
 405         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 406                                      &dev_priv->mch_res,
 407                                      MCHBAR_SIZE, MCHBAR_SIZE,
 408                                      PCIBIOS_MIN_MEM,
 409                                      0, pcibios_align_resource,
 410                                      dev_priv->bridge_dev);
 411         if (ret) {
 412                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 413                 dev_priv->mch_res.start = 0;
 414                 return ret;
 415         }
 416
 417         if (INTEL_INFO(dev)->gen >= 4)
 418                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 419                                        upper_32_bits(dev_priv->mch_res.start));
 420
 421         pci_write_config_dword(dev_priv->bridge_dev, reg,
 422                                lower_32_bits(dev_priv->mch_res.start));
 423         return 0;
 424 }
 425
 426 /* Setup MCHBAR if possible, return true if we should disable it again */
 427 static void
 428 intel_setup_mchbar(struct drm_device *dev)
 429 {
 430         struct drm_i915_private *dev_priv = to_i915(dev);
 431         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 432         u32 temp;
 433         bool enabled;
 434
 435         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 436                 return;
 437
 438         dev_priv->mchbar_need_disable = false;
 439
 440         if (IS_I915G(dev) || IS_I915GM(dev)) {
 441                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 442                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 443         } else {
 444                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 445                 enabled = temp & 1;
 446         }
 447
 448         /* If it's already enabled, don't have to do anything */
 449         if (enabled)
 450                 return;
 451
 452         if (intel_alloc_mchbar_resource(dev))
 453                 return;
 454
 455         dev_priv->mchbar_need_disable = true;
 456
 457         /* Space is allocated or reserved, so enable it. */
 458         if (IS_I915G(dev) || IS_I915GM(dev)) {
 459                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 460                                        temp | DEVEN_MCHBAR_EN);
 461         } else {
 462                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 463                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 464         }
 465 }
 466
 467 static void
 468 intel_teardown_mchbar(struct drm_device *dev)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(dev);
 471         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 472
 473         if (dev_priv->mchbar_need_disable) {
 474                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 475                         u32 deven_val;
 476
 477                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 478                                               &deven_val);
 479                         deven_val &= ~DEVEN_MCHBAR_EN;
 480                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 481                                                deven_val);
 482                 } else {
 483                         u32 mchbar_val;
 484
 485                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 486                                               &mchbar_val);
 487                         mchbar_val &= ~1;
 488                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 489                                                mchbar_val);
 490                 }
 491         }
 492
 493         if (dev_priv->mch_res.start)
 494                 release_resource(&dev_priv->mch_res);
 495 }
 496
 497 /* true = enable decode, false = disable decoder */
 498 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 499 {
 500         struct drm_device *dev = cookie;
 501
 502         intel_modeset_vga_set_state(dev, state);
 503         if (state)
 504                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 505                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 506         else
 507                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 508 }
 509
 510 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 511 {
 512         struct drm_device *dev = pci_get_drvdata(pdev);
 513         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 514
 515         if (state == VGA_SWITCHEROO_ON) {
 516                 pr_info("switched on\n");
 517                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 518                 /* i915 resume handler doesn't set to D0 */
 519                 pci_set_power_state(dev->pdev, PCI_D0);
 520                 i915_resume_switcheroo(dev);
 521                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 522         } else {
 523                 pr_info("switched off\n");
 524                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 525                 i915_suspend_switcheroo(dev, pmm);
 526                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 527         }
 528 }
 529
 530 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 531 {
 532         struct drm_device *dev = pci_get_drvdata(pdev);
 533
 534         /*
 535          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 536          * locking inversion with the driver load path. And the access here is
 537          * completely racy anyway. So don't bother with locking for now.
 538          */
 539         return dev->open_count == 0;
 540 }
 541
 542 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 543         .set_gpu_state = i915_switcheroo_set_state,
 544         .reprobe = NULL,
 545         .can_switch = i915_switcheroo_can_switch,
 546 };
 547
 548 static void i915_gem_fini(struct drm_device *dev)
 549 {
 550         struct drm_i915_private *dev_priv = to_i915(dev);
 551
 552         /*
 553          * Neither the BIOS, ourselves or any other kernel
 554          * expects the system to be in execlists mode on startup,
 555          * so we need to reset the GPU back to legacy mode. And the only
 556          * known way to disable logical contexts is through a GPU reset.
 557          *
 558          * So in order to leave the system in a known default configuration,
 559          * always reset the GPU upon unload. Afterwards we then clean up the
 560          * GEM state tracking, flushing off the requests and leaving the
 561          * system in a known idle state.
 562          *
 563          * Note that is of the upmost importance that the GPU is idle and
 564          * all stray writes are flushed *before* we dismantle the backing
 565          * storage for the pinned objects.
 566          *
 567          * However, since we are uncertain that reseting the GPU on older
 568          * machines is a good idea, we don't - just in case it leaves the
 569          * machine in an unusable condition.
 570          */
 571         if (HAS_HW_CONTEXTS(dev)) {
 572                 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 573                 WARN_ON(reset && reset != -ENODEV);
 574         }
 575
 576         mutex_lock(&dev->struct_mutex);
 577         i915_gem_reset(dev);
 578         i915_gem_cleanup_engines(dev);
 579         i915_gem_context_fini(dev);
 580         mutex_unlock(&dev->struct_mutex);
 581
 582         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 583 }
 584
 585 static int i915_load_modeset_init(struct drm_device *dev)
 586 {
 587         struct drm_i915_private *dev_priv = to_i915(dev);
 588         int ret;
 589
 590         if (i915_inject_load_failure())
 591                 return -ENODEV;
 592
 593         ret = intel_bios_init(dev_priv);
 594         if (ret)
 595                 DRM_INFO("failed to find VBIOS tables\n");
 596
 597         /* If we have > 1 VGA cards, then we need to arbitrate access
 598          * to the common VGA resources.
 599          *
 600          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 601          * then we do not take part in VGA arbitration and the
 602          * vga_client_register() fails with -ENODEV.
 603          */
 604         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 605         if (ret && ret != -ENODEV)
 606                 goto out;
 607
 608         intel_register_dsm_handler();
 609
 610         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 611         if (ret)
 612                 goto cleanup_vga_client;
 613
 614         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 615         intel_update_rawclk(dev_priv);
 616
 617         intel_power_domains_init_hw(dev_priv, false);
 618
 619         intel_csr_ucode_init(dev_priv);
 620
 621         ret = intel_irq_install(dev_priv);
 622         if (ret)
 623                 goto cleanup_csr;
 624
 625         intel_setup_gmbus(dev);
 626
 627         /* Important: The output setup functions called by modeset_init need
 628          * working irqs for e.g. gmbus and dp aux transfers. */
 629         intel_modeset_init(dev);
 630
 631         intel_guc_init(dev);
 632
 633         ret = i915_gem_init(dev);
 634         if (ret)
 635                 goto cleanup_irq;
 636
 637         intel_modeset_gem_init(dev);
 638
 639         if (INTEL_INFO(dev)->num_pipes == 0)
 640                 return 0;
 641
 642         ret = intel_fbdev_init(dev);
 643         if (ret)
 644                 goto cleanup_gem;
 645
 646         /* Only enable hotplug handling once the fbdev is fully set up. */
 647         intel_hpd_init(dev_priv);
 648
 649         drm_kms_helper_poll_init(dev);
 650
 651         return 0;
 652
 653 cleanup_gem:
 654         i915_gem_fini(dev);
 655 cleanup_irq:
 656         intel_guc_fini(dev);
 657         drm_irq_uninstall(dev);
 658         intel_teardown_gmbus(dev);
 659 cleanup_csr:
 660         intel_csr_ucode_fini(dev_priv);
 661         intel_power_domains_fini(dev_priv);
 662         vga_switcheroo_unregister_client(dev->pdev);
 663 cleanup_vga_client:
 664         vga_client_register(dev->pdev, NULL, NULL, NULL);
 665 out:
 666         return ret;
 667 }
 668
 669 #if IS_ENABLED(CONFIG_FB)
 670 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 671 {
 672         struct apertures_struct *ap;
 673         struct pci_dev *pdev = dev_priv->drm.pdev;
 674         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 675         bool primary;
 676         int ret;
 677
 678         ap = alloc_apertures(1);
 679         if (!ap)
 680                 return -ENOMEM;
 681
 682         ap->ranges[0].base = ggtt->mappable_base;
 683         ap->ranges[0].size = ggtt->mappable_end;
 684
 685         primary =
 686                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 687
 688         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 689
 690         kfree(ap);
 691
 692         return ret;
 693 }
 694 #else
 695 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 696 {
 697         return 0;
 698 }
 699 #endif
 700
 701 #if !defined(CONFIG_VGA_CONSOLE)
 702 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 703 {
 704         return 0;
 705 }
 706 #elif !defined(CONFIG_DUMMY_CONSOLE)
 707 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 708 {
 709         return -ENODEV;
 710 }
 711 #else
 712 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 713 {
 714         int ret = 0;
 715
 716         DRM_INFO("Replacing VGA console driver\n");
 717
 718         console_lock();
 719         if (con_is_bound(&vga_con))
 720                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 721         if (ret == 0) {
 722                 ret = do_unregister_con_driver(&vga_con);
 723
 724                 /* Ignore "already unregistered". */
 725                 if (ret == -ENODEV)
 726                         ret = 0;
 727         }
 728         console_unlock();
 729
 730         return ret;
 731 }
 732 #endif
 733
 734 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 735 {
 736         /*
 737          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 738          * CHV x1 PHY (DP/HDMI D)
 739          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 740          */
 741         if (IS_CHERRYVIEW(dev_priv)) {
 742                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 743                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 744         } else if (IS_VALLEYVIEW(dev_priv)) {
 745                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 746         }
 747 }
 748
 749 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 750 {
 751         /*
 752          * The i915 workqueue is primarily used for batched retirement of
 753          * requests (and thus managing bo) once the task has been completed
 754          * by the GPU. i915_gem_retire_requests() is called directly when we
 755          * need high-priority retirement, such as waiting for an explicit
 756          * bo.
 757          *
 758          * It is also used for periodic low-priority events, such as
 759          * idle-timers and recording error state.
 760          *
 761          * All tasks on the workqueue are expected to acquire the dev mutex
 762          * so there is no point in running more than one instance of the
 763          * workqueue at any time.  Use an ordered one.
 764          */
 765         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 766         if (dev_priv->wq == NULL)
 767                 goto out_err;
 768
 769         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 770         if (dev_priv->hotplug.dp_wq == NULL)
 771                 goto out_free_wq;
 772
 773         return 0;
 774
 775 out_free_wq:
 776         destroy_workqueue(dev_priv->wq);
 777 out_err:
 778         DRM_ERROR("Failed to allocate workqueues.\n");
 779
 780         return -ENOMEM;
 781 }
 782
 783 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 784 {
 785         destroy_workqueue(dev_priv->hotplug.dp_wq);
 786         destroy_workqueue(dev_priv->wq);
 787 }
 788
 789 /**
 790  * i915_driver_init_early - setup state not requiring device access
 791  * @dev_priv: device private
 792  *
 793  * Initialize everything that is a "SW-only" state, that is state not
 794  * requiring accessing the device or exposing the driver via kernel internal
 795  * or userspace interfaces. Example steps belonging here: lock initialization,
 796  * system memory allocation, setting up device specific attributes and
 797  * function hooks not requiring accessing the device.
 798  */
 799 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 800                                   const struct pci_device_id *ent)
 801 {
 802         const struct intel_device_info *match_info =
 803                 (struct intel_device_info *)ent->driver_data;
 804         struct intel_device_info *device_info;
 805         int ret = 0;
 806
 807         if (i915_inject_load_failure())
 808                 return -ENODEV;
 809
 810         /* Setup the write-once "constant" device info */
 811         device_info = mkwrite_device_info(dev_priv);
 812         memcpy(device_info, match_info, sizeof(*device_info));
 813         device_info->device_id = dev_priv->drm.pdev->device;
 814
 815         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 816         device_info->gen_mask = BIT(device_info->gen - 1);
 817
 818         spin_lock_init(&dev_priv->irq_lock);
 819         spin_lock_init(&dev_priv->gpu_error.lock);
 820         mutex_init(&dev_priv->backlight_lock);
 821         spin_lock_init(&dev_priv->uncore.lock);
 822         spin_lock_init(&dev_priv->mm.object_stat_lock);
 823         spin_lock_init(&dev_priv->mmio_flip_lock);
 824         mutex_init(&dev_priv->sb_lock);
 825         mutex_init(&dev_priv->modeset_restore_lock);
 826         mutex_init(&dev_priv->av_mutex);
 827         mutex_init(&dev_priv->wm.wm_mutex);
 828         mutex_init(&dev_priv->pps_mutex);
 829
 830         i915_memcpy_init_early(dev_priv);
 831
 832         ret = i915_workqueues_init(dev_priv);
 833         if (ret < 0)
 834                 return ret;
 835
 836         ret = intel_gvt_init(dev_priv);
 837         if (ret < 0)
 838                 goto err_workqueues;
 839
 840         /* This must be called before any calls to HAS_PCH_* */
 841         intel_detect_pch(&dev_priv->drm);
 842
 843         intel_pm_setup(&dev_priv->drm);
 844         intel_init_dpio(dev_priv);
 845         intel_power_domains_init(dev_priv);
 846         intel_irq_init(dev_priv);
 847         intel_init_display_hooks(dev_priv);
 848         intel_init_clock_gating_hooks(dev_priv);
 849         intel_init_audio_hooks(dev_priv);
 850         i915_gem_load_init(&dev_priv->drm);
 851
 852         intel_display_crc_init(&dev_priv->drm);
 853
 854         intel_device_info_dump(dev_priv);
 855
 856         /* Not all pre-production machines fall into this category, only the
 857          * very first ones. Almost everything should work, except for maybe
 858          * suspend/resume. And we don't implement workarounds that affect only
 859          * pre-production machines. */
 860         if (IS_HSW_EARLY_SDV(dev_priv))
 861                 DRM_INFO("This is an early pre-production Haswell machine. "
 862                          "It may not be fully functional.\n");
 863
 864         return 0;
 865
 866 err_workqueues:
 867         i915_workqueues_cleanup(dev_priv);
 868         return ret;
 869 }
 870
 871 /**
 872  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 873  * @dev_priv: device private
 874  */
 875 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 876 {
 877         i915_gem_load_cleanup(&dev_priv->drm);
 878         i915_workqueues_cleanup(dev_priv);
 879 }
 880
 881 static int i915_mmio_setup(struct drm_device *dev)
 882 {
 883         struct drm_i915_private *dev_priv = to_i915(dev);
 884         int mmio_bar;
 885         int mmio_size;
 886
 887         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 888         /*
 889          * Before gen4, the registers and the GTT are behind different BARs.
 890          * However, from gen4 onwards, the registers and the GTT are shared
 891          * in the same BAR, so we want to restrict this ioremap from
 892          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 893          * the register BAR remains the same size for all the earlier
 894          * generations up to Ironlake.
 895          */
 896         if (INTEL_INFO(dev)->gen < 5)
 897                 mmio_size = 512 * 1024;
 898         else
 899                 mmio_size = 2 * 1024 * 1024;
 900         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 901         if (dev_priv->regs == NULL) {
 902                 DRM_ERROR("failed to map registers\n");
 903
 904                 return -EIO;
 905         }
 906
 907         /* Try to make sure MCHBAR is enabled before poking at it */
 908         intel_setup_mchbar(dev);
 909
 910         return 0;
 911 }
 912
 913 static void i915_mmio_cleanup(struct drm_device *dev)
 914 {
 915         struct drm_i915_private *dev_priv = to_i915(dev);
 916
 917         intel_teardown_mchbar(dev);
 918         pci_iounmap(dev->pdev, dev_priv->regs);
 919 }
 920
 921 /**
 922  * i915_driver_init_mmio - setup device MMIO
 923  * @dev_priv: device private
 924  *
 925  * Setup minimal device state necessary for MMIO accesses later in the
 926  * initialization sequence. The setup here should avoid any other device-wide
 927  * side effects or exposing the driver via kernel internal or user space
 928  * interfaces.
 929  */
 930 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 931 {
 932         struct drm_device *dev = &dev_priv->drm;
 933         int ret;
 934
 935         if (i915_inject_load_failure())
 936                 return -ENODEV;
 937
 938         if (i915_get_bridge_dev(dev))
 939                 return -EIO;
 940
 941         ret = i915_mmio_setup(dev);
 942         if (ret < 0)
 943                 goto put_bridge;
 944
 945         intel_uncore_init(dev_priv);
 946
 947         return 0;
 948
 949 put_bridge:
 950         pci_dev_put(dev_priv->bridge_dev);
 951
 952         return ret;
 953 }
 954
 955 /**
 956  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 957  * @dev_priv: device private
 958  */
 959 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 960 {
 961         struct drm_device *dev = &dev_priv->drm;
 962
 963         intel_uncore_fini(dev_priv);
 964         i915_mmio_cleanup(dev);
 965         pci_dev_put(dev_priv->bridge_dev);
 966 }
 967
 968 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 969 {
 970         i915.enable_execlists =
 971                 intel_sanitize_enable_execlists(dev_priv,
 972                                                 i915.enable_execlists);
 973
 974         /*
 975          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 976          * user's requested state against the hardware/driver capabilities.  We
 977          * do this now so that we can print out any log messages once rather
 978          * than every time we check intel_enable_ppgtt().
 979          */
 980         i915.enable_ppgtt =
 981                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 982         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 983
 984         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 985         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 986 }
 987
 988 /**
 989  * i915_driver_init_hw - setup state requiring device access
 990  * @dev_priv: device private
 991  *
 992  * Setup state that requires accessing the device, but doesn't require
 993  * exposing the driver via kernel internal or userspace interfaces.
 994  */
 995 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 996 {
 997         struct drm_device *dev = &dev_priv->drm;
 998         int ret;
 999
1000         if (i915_inject_load_failure())
1001                 return -ENODEV;
1002
1003         intel_device_info_runtime_init(dev_priv);
1004
1005         intel_sanitize_options(dev_priv);
1006
1007         ret = i915_ggtt_probe_hw(dev_priv);
1008         if (ret)
1009                 return ret;
1010
1011         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1012          * otherwise the vga fbdev driver falls over. */
1013         ret = i915_kick_out_firmware_fb(dev_priv);
1014         if (ret) {
1015                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1016                 goto out_ggtt;
1017         }
1018
1019         ret = i915_kick_out_vgacon(dev_priv);
1020         if (ret) {
1021                 DRM_ERROR("failed to remove conflicting VGA console\n");
1022                 goto out_ggtt;
1023         }
1024
1025         ret = i915_ggtt_init_hw(dev_priv);
1026         if (ret)
1027                 return ret;
1028
1029         ret = i915_ggtt_enable_hw(dev_priv);
1030         if (ret) {
1031                 DRM_ERROR("failed to enable GGTT\n");
1032                 goto out_ggtt;
1033         }
1034
1035         pci_set_master(dev->pdev);
1036
1037         /* overlay on gen2 is broken and can't address above 1G */
1038         if (IS_GEN2(dev)) {
1039                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1040                 if (ret) {
1041                         DRM_ERROR("failed to set DMA mask\n");
1042
1043                         goto out_ggtt;
1044                 }
1045         }
1046
1047         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1048          * using 32bit addressing, overwriting memory if HWS is located
1049          * above 4GB.
1050          *
1051          * The documentation also mentions an issue with undefined
1052          * behaviour if any general state is accessed within a page above 4GB,
1053          * which also needs to be handled carefully.
1054          */
1055         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1056                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1057
1058                 if (ret) {
1059                         DRM_ERROR("failed to set DMA mask\n");
1060
1061                         goto out_ggtt;
1062                 }
1063         }
1064
1065         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1066                            PM_QOS_DEFAULT_VALUE);
1067
1068         intel_uncore_sanitize(dev_priv);
1069
1070         intel_opregion_setup(dev_priv);
1071
1072         i915_gem_load_init_fences(dev_priv);
1073
1074         /* On the 945G/GM, the chipset reports the MSI capability on the
1075          * integrated graphics even though the support isn't actually there
1076          * according to the published specs.  It doesn't appear to function
1077          * correctly in testing on 945G.
1078          * This may be a side effect of MSI having been made available for PEG
1079          * and the registers being closely associated.
1080          *
1081          * According to chipset errata, on the 965GM, MSI interrupts may
1082          * be lost or delayed, but we use them anyways to avoid
1083          * stuck interrupts on some machines.
1084          */
1085         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1086                 if (pci_enable_msi(dev->pdev) < 0)
1087                         DRM_DEBUG_DRIVER("can't enable MSI");
1088         }
1089
1090         return 0;
1091
1092 out_ggtt:
1093         i915_ggtt_cleanup_hw(dev_priv);
1094
1095         return ret;
1096 }
1097
1098 /**
1099  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1100  * @dev_priv: device private
1101  */
1102 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1103 {
1104         struct drm_device *dev = &dev_priv->drm;
1105
1106         if (dev->pdev->msi_enabled)
1107                 pci_disable_msi(dev->pdev);
1108
1109         pm_qos_remove_request(&dev_priv->pm_qos);
1110         i915_ggtt_cleanup_hw(dev_priv);
1111 }
1112
1113 /**
1114  * i915_driver_register - register the driver with the rest of the system
1115  * @dev_priv: device private
1116  *
1117  * Perform any steps necessary to make the driver available via kernel
1118  * internal or userspace interfaces.
1119  */
1120 static void i915_driver_register(struct drm_i915_private *dev_priv)
1121 {
1122         struct drm_device *dev = &dev_priv->drm;
1123
1124         i915_gem_shrinker_init(dev_priv);
1125
1126         /*
1127          * Notify a valid surface after modesetting,
1128          * when running inside a VM.
1129          */
1130         if (intel_vgpu_active(dev_priv))
1131                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1132
1133         /* Reveal our presence to userspace */
1134         if (drm_dev_register(dev, 0) == 0) {
1135                 i915_debugfs_register(dev_priv);
1136                 i915_setup_sysfs(dev);
1137         } else
1138                 DRM_ERROR("Failed to register driver for userspace access!\n");
1139
1140         if (INTEL_INFO(dev_priv)->num_pipes) {
1141                 /* Must be done after probing outputs */
1142                 intel_opregion_register(dev_priv);
1143                 acpi_video_register();
1144         }
1145
1146         if (IS_GEN5(dev_priv))
1147                 intel_gpu_ips_init(dev_priv);
1148
1149         i915_audio_component_init(dev_priv);
1150
1151         /*
1152          * Some ports require correctly set-up hpd registers for detection to
1153          * work properly (leading to ghost connected connector status), e.g. VGA
1154          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1155          * irqs are fully enabled. We do it last so that the async config
1156          * cannot run before the connectors are registered.
1157          */
1158         intel_fbdev_initial_config_async(dev);
1159 }
1160
1161 /**
1162  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1163  * @dev_priv: device private
1164  */
1165 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1166 {
1167         i915_audio_component_cleanup(dev_priv);
1168
1169         intel_gpu_ips_teardown();
1170         acpi_video_unregister();
1171         intel_opregion_unregister(dev_priv);
1172
1173         i915_teardown_sysfs(&dev_priv->drm);
1174         i915_debugfs_unregister(dev_priv);
1175         drm_dev_unregister(&dev_priv->drm);
1176
1177         i915_gem_shrinker_cleanup(dev_priv);
1178 }
1179
1180 /**
1181  * i915_driver_load - setup chip and create an initial config
1182  * @dev: DRM device
1183  * @flags: startup flags
1184  *
1185  * The driver load routine has to do several things:
1186  *   - drive output discovery via intel_modeset_init()
1187  *   - initialize the memory manager
1188  *   - allocate initial config memory
1189  *   - setup the DRM framebuffer with the allocated memory
1190  */
1191 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1192 {
1193         struct drm_i915_private *dev_priv;
1194         int ret;
1195
1196         if (i915.nuclear_pageflip)
1197                 driver.driver_features |= DRIVER_ATOMIC;
1198
1199         ret = -ENOMEM;
1200         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1201         if (dev_priv)
1202                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1203         if (ret) {
1204                 dev_printk(KERN_ERR, &pdev->dev,
1205                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1206                 kfree(dev_priv);
1207                 return ret;
1208         }
1209
1210         dev_priv->drm.pdev = pdev;
1211         dev_priv->drm.dev_private = dev_priv;
1212
1213         ret = pci_enable_device(pdev);
1214         if (ret)
1215                 goto out_free_priv;
1216
1217         pci_set_drvdata(pdev, &dev_priv->drm);
1218
1219         ret = i915_driver_init_early(dev_priv, ent);
1220         if (ret < 0)
1221                 goto out_pci_disable;
1222
1223         intel_runtime_pm_get(dev_priv);
1224
1225         ret = i915_driver_init_mmio(dev_priv);
1226         if (ret < 0)
1227                 goto out_runtime_pm_put;
1228
1229         ret = i915_driver_init_hw(dev_priv);
1230         if (ret < 0)
1231                 goto out_cleanup_mmio;
1232
1233         /*
1234          * TODO: move the vblank init and parts of modeset init steps into one
1235          * of the i915_driver_init_/i915_driver_register functions according
1236          * to the role/effect of the given init step.
1237          */
1238         if (INTEL_INFO(dev_priv)->num_pipes) {
1239                 ret = drm_vblank_init(&dev_priv->drm,
1240                                       INTEL_INFO(dev_priv)->num_pipes);
1241                 if (ret)
1242                         goto out_cleanup_hw;
1243         }
1244
1245         ret = i915_load_modeset_init(&dev_priv->drm);
1246         if (ret < 0)
1247                 goto out_cleanup_vblank;
1248
1249         i915_driver_register(dev_priv);
1250
1251         intel_runtime_pm_enable(dev_priv);
1252
1253         intel_runtime_pm_put(dev_priv);
1254
1255         return 0;
1256
1257 out_cleanup_vblank:
1258         drm_vblank_cleanup(&dev_priv->drm);
1259 out_cleanup_hw:
1260         i915_driver_cleanup_hw(dev_priv);
1261 out_cleanup_mmio:
1262         i915_driver_cleanup_mmio(dev_priv);
1263 out_runtime_pm_put:
1264         intel_runtime_pm_put(dev_priv);
1265         i915_driver_cleanup_early(dev_priv);
1266 out_pci_disable:
1267         pci_disable_device(pdev);
1268 out_free_priv:
1269         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1270         drm_dev_unref(&dev_priv->drm);
1271         return ret;
1272 }
1273
1274 void i915_driver_unload(struct drm_device *dev)
1275 {
1276         struct drm_i915_private *dev_priv = to_i915(dev);
1277
1278         intel_fbdev_fini(dev);
1279
1280         if (i915_gem_suspend(dev))
1281                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1282
1283         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1284
1285         i915_driver_unregister(dev_priv);
1286
1287         drm_vblank_cleanup(dev);
1288
1289         intel_modeset_cleanup(dev);
1290
1291         /*
1292          * free the memory space allocated for the child device
1293          * config parsed from VBT
1294          */
1295         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1296                 kfree(dev_priv->vbt.child_dev);
1297                 dev_priv->vbt.child_dev = NULL;
1298                 dev_priv->vbt.child_dev_num = 0;
1299         }
1300         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1301         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1302         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1303         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1304
1305         vga_switcheroo_unregister_client(dev->pdev);
1306         vga_client_register(dev->pdev, NULL, NULL, NULL);
1307
1308         intel_csr_ucode_fini(dev_priv);
1309
1310         /* Free error state after interrupts are fully disabled. */
1311         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1312         i915_destroy_error_state(dev);
1313
1314         /* Flush any outstanding unpin_work. */
1315         drain_workqueue(dev_priv->wq);
1316
1317         intel_guc_fini(dev);
1318         i915_gem_fini(dev);
1319         intel_fbc_cleanup_cfb(dev_priv);
1320
1321         intel_power_domains_fini(dev_priv);
1322
1323         i915_driver_cleanup_hw(dev_priv);
1324         i915_driver_cleanup_mmio(dev_priv);
1325
1326         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1327
1328         i915_driver_cleanup_early(dev_priv);
1329 }
1330
1331 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1332 {
1333         int ret;
1334
1335         ret = i915_gem_open(dev, file);
1336         if (ret)
1337                 return ret;
1338
1339         return 0;
1340 }
1341
1342 /**
1343  * i915_driver_lastclose - clean up after all DRM clients have exited
1344  * @dev: DRM device
1345  *
1346  * Take care of cleaning up after all DRM clients have exited.  In the
1347  * mode setting case, we want to restore the kernel's initial mode (just
1348  * in case the last client left us in a bad state).
1349  *
1350  * Additionally, in the non-mode setting case, we'll tear down the GTT
1351  * and DMA structures, since the kernel won't be using them, and clea
1352  * up any GEM state.
1353  */
1354 static void i915_driver_lastclose(struct drm_device *dev)
1355 {
1356         intel_fbdev_restore_mode(dev);
1357         vga_switcheroo_process_delayed_switch();
1358 }
1359
1360 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1361 {
1362         mutex_lock(&dev->struct_mutex);
1363         i915_gem_context_close(dev, file);
1364         i915_gem_release(dev, file);
1365         mutex_unlock(&dev->struct_mutex);
1366 }
1367
1368 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1369 {
1370         struct drm_i915_file_private *file_priv = file->driver_priv;
1371
1372         kfree(file_priv);
1373 }
1374
1375 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1376 {
1377         struct drm_device *dev = &dev_priv->drm;
1378         struct intel_encoder *encoder;
1379
1380         drm_modeset_lock_all(dev);
1381         for_each_intel_encoder(dev, encoder)
1382                 if (encoder->suspend)
1383                         encoder->suspend(encoder);
1384         drm_modeset_unlock_all(dev);
1385 }
1386
1387 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1388                               bool rpm_resume);
1389 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1390
1391 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1392 {
1393 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1394         if (acpi_target_system_state() < ACPI_STATE_S3)
1395                 return true;
1396 #endif
1397         return false;
1398 }
1399
1400 static int i915_drm_suspend(struct drm_device *dev)
1401 {
1402         struct drm_i915_private *dev_priv = to_i915(dev);
1403         pci_power_t opregion_target_state;
1404         int error;
1405
1406         /* ignore lid events during suspend */
1407         mutex_lock(&dev_priv->modeset_restore_lock);
1408         dev_priv->modeset_restore = MODESET_SUSPENDED;
1409         mutex_unlock(&dev_priv->modeset_restore_lock);
1410
1411         disable_rpm_wakeref_asserts(dev_priv);
1412
1413         /* We do a lot of poking in a lot of registers, make sure they work
1414          * properly. */
1415         intel_display_set_init_power(dev_priv, true);
1416
1417         drm_kms_helper_poll_disable(dev);
1418
1419         pci_save_state(dev->pdev);
1420
1421         error = i915_gem_suspend(dev);
1422         if (error) {
1423                 dev_err(&dev->pdev->dev,
1424                         "GEM idle failed, resume might fail\n");
1425                 goto out;
1426         }
1427
1428         intel_guc_suspend(dev);
1429
1430         intel_display_suspend(dev);
1431
1432         intel_dp_mst_suspend(dev);
1433
1434         intel_runtime_pm_disable_interrupts(dev_priv);
1435         intel_hpd_cancel_work(dev_priv);
1436
1437         intel_suspend_encoders(dev_priv);
1438
1439         intel_suspend_hw(dev);
1440
1441         i915_gem_suspend_gtt_mappings(dev);
1442
1443         i915_save_state(dev);
1444
1445         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1446         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1447
1448         intel_uncore_forcewake_reset(dev_priv, false);
1449         intel_opregion_unregister(dev_priv);
1450
1451         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1452
1453         dev_priv->suspend_count++;
1454
1455         intel_display_set_init_power(dev_priv, false);
1456
1457         intel_csr_ucode_suspend(dev_priv);
1458
1459 out:
1460         enable_rpm_wakeref_asserts(dev_priv);
1461
1462         return error;
1463 }
1464
1465 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
1466 {
1467         struct drm_i915_private *dev_priv = to_i915(drm_dev);
1468         bool fw_csr;
1469         int ret;
1470
1471         disable_rpm_wakeref_asserts(dev_priv);
1472
1473         fw_csr = !IS_BROXTON(dev_priv) &&
1474                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1475         /*
1476          * In case of firmware assisted context save/restore don't manually
1477          * deinit the power domains. This also means the CSR/DMC firmware will
1478          * stay active, it will power down any HW resources as required and
1479          * also enable deeper system power states that would be blocked if the
1480          * firmware was inactive.
1481          */
1482         if (!fw_csr)
1483                 intel_power_domains_suspend(dev_priv);
1484
1485         ret = 0;
1486         if (IS_BROXTON(dev_priv))
1487                 bxt_enable_dc9(dev_priv);
1488         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1489                 hsw_enable_pc8(dev_priv);
1490         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1491                 ret = vlv_suspend_complete(dev_priv);
1492
1493         if (ret) {
1494                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1495                 if (!fw_csr)
1496                         intel_power_domains_init_hw(dev_priv, true);
1497
1498                 goto out;
1499         }
1500
1501         pci_disable_device(drm_dev->pdev);
1502         /*
1503          * During hibernation on some platforms the BIOS may try to access
1504          * the device even though it's already in D3 and hang the machine. So
1505          * leave the device in D0 on those platforms and hope the BIOS will
1506          * power down the device properly. The issue was seen on multiple old
1507          * GENs with different BIOS vendors, so having an explicit blacklist
1508          * is inpractical; apply the workaround on everything pre GEN6. The
1509          * platforms where the issue was seen:
1510          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1511          * Fujitsu FSC S7110
1512          * Acer Aspire 1830T
1513          */
1514         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1515                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
1516
1517         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1518
1519 out:
1520         enable_rpm_wakeref_asserts(dev_priv);
1521
1522         return ret;
1523 }
1524
1525 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1526 {
1527         int error;
1528
1529         if (!dev) {
1530                 DRM_ERROR("dev: %p\n", dev);
1531                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1532                 return -ENODEV;
1533         }
1534
1535         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1536                          state.event != PM_EVENT_FREEZE))
1537                 return -EINVAL;
1538
1539         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1540                 return 0;
1541
1542         error = i915_drm_suspend(dev);
1543         if (error)
1544                 return error;
1545
1546         return i915_drm_suspend_late(dev, false);
1547 }
1548
1549 static int i915_drm_resume(struct drm_device *dev)
1550 {
1551         struct drm_i915_private *dev_priv = to_i915(dev);
1552         int ret;
1553
1554         disable_rpm_wakeref_asserts(dev_priv);
1555
1556         ret = i915_ggtt_enable_hw(dev_priv);
1557         if (ret)
1558                 DRM_ERROR("failed to re-enable GGTT\n");
1559
1560         intel_csr_ucode_resume(dev_priv);
1561
1562         i915_gem_resume(dev);
1563
1564         i915_restore_state(dev);
1565         intel_pps_unlock_regs_wa(dev_priv);
1566         intel_opregion_setup(dev_priv);
1567
1568         intel_init_pch_refclk(dev);
1569         drm_mode_config_reset(dev);
1570
1571         /*
1572          * Interrupts have to be enabled before any batches are run. If not the
1573          * GPU will hang. i915_gem_init_hw() will initiate batches to
1574          * update/restore the context.
1575          *
1576          * Modeset enabling in intel_modeset_init_hw() also needs working
1577          * interrupts.
1578          */
1579         intel_runtime_pm_enable_interrupts(dev_priv);
1580
1581         mutex_lock(&dev->struct_mutex);
1582         if (i915_gem_init_hw(dev)) {
1583                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1584                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
1585         }
1586         mutex_unlock(&dev->struct_mutex);
1587
1588         intel_guc_resume(dev);
1589
1590         intel_modeset_init_hw(dev);
1591
1592         spin_lock_irq(&dev_priv->irq_lock);
1593         if (dev_priv->display.hpd_irq_setup)
1594                 dev_priv->display.hpd_irq_setup(dev_priv);
1595         spin_unlock_irq(&dev_priv->irq_lock);
1596
1597         intel_dp_mst_resume(dev);
1598
1599         intel_display_resume(dev);
1600
1601         /*
1602          * ... but also need to make sure that hotplug processing
1603          * doesn't cause havoc. Like in the driver load code we don't
1604          * bother with the tiny race here where we might loose hotplug
1605          * notifications.
1606          * */
1607         intel_hpd_init(dev_priv);
1608         /* Config may have changed between suspend and resume */
1609         drm_helper_hpd_irq_event(dev);
1610
1611         intel_opregion_register(dev_priv);
1612
1613         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1614
1615         mutex_lock(&dev_priv->modeset_restore_lock);
1616         dev_priv->modeset_restore = MODESET_DONE;
1617         mutex_unlock(&dev_priv->modeset_restore_lock);
1618
1619         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1620
1621         intel_autoenable_gt_powersave(dev_priv);
1622         drm_kms_helper_poll_enable(dev);
1623
1624         enable_rpm_wakeref_asserts(dev_priv);
1625
1626         return 0;
1627 }
1628
1629 static int i915_drm_resume_early(struct drm_device *dev)
1630 {
1631         struct drm_i915_private *dev_priv = to_i915(dev);
1632         int ret;
1633
1634         /*
1635          * We have a resume ordering issue with the snd-hda driver also
1636          * requiring our device to be power up. Due to the lack of a
1637          * parent/child relationship we currently solve this with an early
1638          * resume hook.
1639          *
1640          * FIXME: This should be solved with a special hdmi sink device or
1641          * similar so that power domains can be employed.
1642          */
1643
1644         /*
1645          * Note that we need to set the power state explicitly, since we
1646          * powered off the device during freeze and the PCI core won't power
1647          * it back up for us during thaw. Powering off the device during
1648          * freeze is not a hard requirement though, and during the
1649          * suspend/resume phases the PCI core makes sure we get here with the
1650          * device powered on. So in case we change our freeze logic and keep
1651          * the device powered we can also remove the following set power state
1652          * call.
1653          */
1654         ret = pci_set_power_state(dev->pdev, PCI_D0);
1655         if (ret) {
1656                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1657                 goto out;
1658         }
1659
1660         /*
1661          * Note that pci_enable_device() first enables any parent bridge
1662          * device and only then sets the power state for this device. The
1663          * bridge enabling is a nop though, since bridge devices are resumed
1664          * first. The order of enabling power and enabling the device is
1665          * imposed by the PCI core as described above, so here we preserve the
1666          * same order for the freeze/thaw phases.
1667          *
1668          * TODO: eventually we should remove pci_disable_device() /
1669          * pci_enable_enable_device() from suspend/resume. Due to how they
1670          * depend on the device enable refcount we can't anyway depend on them
1671          * disabling/enabling the device.
1672          */
1673         if (pci_enable_device(dev->pdev)) {
1674                 ret = -EIO;
1675                 goto out;
1676         }
1677
1678         pci_set_master(dev->pdev);
1679
1680         disable_rpm_wakeref_asserts(dev_priv);
1681
1682         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1683                 ret = vlv_resume_prepare(dev_priv, false);
1684         if (ret)
1685                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1686                           ret);
1687
1688         intel_uncore_early_sanitize(dev_priv, true);
1689
1690         if (IS_BROXTON(dev_priv)) {
1691                 if (!dev_priv->suspended_to_idle)
1692                         gen9_sanitize_dc_state(dev_priv);
1693                 bxt_disable_dc9(dev_priv);
1694         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1695                 hsw_disable_pc8(dev_priv);
1696         }
1697
1698         intel_uncore_sanitize(dev_priv);
1699
1700         if (IS_BROXTON(dev_priv) ||
1701             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1702                 intel_power_domains_init_hw(dev_priv, true);
1703
1704         enable_rpm_wakeref_asserts(dev_priv);
1705
1706 out:
1707         dev_priv->suspended_to_idle = false;
1708
1709         return ret;
1710 }
1711
1712 int i915_resume_switcheroo(struct drm_device *dev)
1713 {
1714         int ret;
1715
1716         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1717                 return 0;
1718
1719         ret = i915_drm_resume_early(dev);
1720         if (ret)
1721                 return ret;
1722
1723         return i915_drm_resume(dev);
1724 }
1725
1726 /**
1727  * i915_reset - reset chip after a hang
1728  * @dev: drm device to reset
1729  *
1730  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
1731  * reset or otherwise an error code.
1732  *
1733  * Procedure is fairly simple:
1734  *   - reset the chip using the reset reg
1735  *   - re-init context state
1736  *   - re-init hardware status page
1737  *   - re-init ring buffer
1738  *   - re-init interrupt state
1739  *   - re-init display
1740  */
1741 int i915_reset(struct drm_i915_private *dev_priv)
1742 {
1743         struct drm_device *dev = &dev_priv->drm;
1744         struct i915_gpu_error *error = &dev_priv->gpu_error;
1745         unsigned reset_counter;
1746         int ret;
1747
1748         mutex_lock(&dev->struct_mutex);
1749
1750         /* Clear any previous failed attempts at recovery. Time to try again. */
1751         atomic_andnot(I915_WEDGED, &error->reset_counter);
1752
1753         /* Clear the reset-in-progress flag and increment the reset epoch. */
1754         reset_counter = atomic_inc_return(&error->reset_counter);
1755         if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1756                 ret = -EIO;
1757                 goto error;
1758         }
1759
1760         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1761
1762         i915_gem_reset(dev);
1763
1764         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1765         if (ret) {
1766                 if (ret != -ENODEV)
1767                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1768                 else
1769                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1770                 goto error;
1771         }
1772
1773         intel_overlay_reset(dev_priv);
1774
1775         /* Ok, now get things going again... */
1776
1777         /*
1778          * Everything depends on having the GTT running, so we need to start
1779          * there.  Fortunately we don't need to do this unless we reset the
1780          * chip at a PCI level.
1781          *
1782          * Next we need to restore the context, but we don't use those
1783          * yet either...
1784          *
1785          * Ring buffer needs to be re-initialized in the KMS case, or if X
1786          * was running at the time of the reset (i.e. we weren't VT
1787          * switched away).
1788          */
1789         ret = i915_gem_init_hw(dev);
1790         if (ret) {
1791                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1792                 goto error;
1793         }
1794
1795         mutex_unlock(&dev->struct_mutex);
1796
1797         /*
1798          * rps/rc6 re-init is necessary to restore state lost after the
1799          * reset and the re-install of gt irqs. Skip for ironlake per
1800          * previous concerns that it doesn't respond well to some forms
1801          * of re-init after reset.
1802          */
1803         intel_autoenable_gt_powersave(dev_priv);
1804
1805         return 0;
1806
1807 error:
1808         atomic_or(I915_WEDGED, &error->reset_counter);
1809         mutex_unlock(&dev->struct_mutex);
1810         return ret;
1811 }
1812
1813 static int i915_pm_suspend(struct device *dev)
1814 {
1815         struct pci_dev *pdev = to_pci_dev(dev);
1816         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1817
1818         if (!drm_dev) {
1819                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1820                 return -ENODEV;
1821         }
1822
1823         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1824                 return 0;
1825
1826         return i915_drm_suspend(drm_dev);
1827 }
1828
1829 static int i915_pm_suspend_late(struct device *dev)
1830 {
1831         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1832
1833         /*
1834          * We have a suspend ordering issue with the snd-hda driver also
1835          * requiring our device to be power up. Due to the lack of a
1836          * parent/child relationship we currently solve this with an late
1837          * suspend hook.
1838          *
1839          * FIXME: This should be solved with a special hdmi sink device or
1840          * similar so that power domains can be employed.
1841          */
1842         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1843                 return 0;
1844
1845         return i915_drm_suspend_late(drm_dev, false);
1846 }
1847
1848 static int i915_pm_poweroff_late(struct device *dev)
1849 {
1850         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1851
1852         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1853                 return 0;
1854
1855         return i915_drm_suspend_late(drm_dev, true);
1856 }
1857
1858 static int i915_pm_resume_early(struct device *dev)
1859 {
1860         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1861
1862         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1863                 return 0;
1864
1865         return i915_drm_resume_early(drm_dev);
1866 }
1867
1868 static int i915_pm_resume(struct device *dev)
1869 {
1870         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1871
1872         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1873                 return 0;
1874
1875         return i915_drm_resume(drm_dev);
1876 }
1877
1878 /* freeze: before creating the hibernation_image */
1879 static int i915_pm_freeze(struct device *dev)
1880 {
1881         return i915_pm_suspend(dev);
1882 }
1883
1884 static int i915_pm_freeze_late(struct device *dev)
1885 {
1886         int ret;
1887
1888         ret = i915_pm_suspend_late(dev);
1889         if (ret)
1890                 return ret;
1891
1892         ret = i915_gem_freeze_late(dev_to_i915(dev));
1893         if (ret)
1894                 return ret;
1895
1896         return 0;
1897 }
1898
1899 /* thaw: called after creating the hibernation image, but before turning off. */
1900 static int i915_pm_thaw_early(struct device *dev)
1901 {
1902         return i915_pm_resume_early(dev);
1903 }
1904
1905 static int i915_pm_thaw(struct device *dev)
1906 {
1907         return i915_pm_resume(dev);
1908 }
1909
1910 /* restore: called after loading the hibernation image. */
1911 static int i915_pm_restore_early(struct device *dev)
1912 {
1913         return i915_pm_resume_early(dev);
1914 }
1915
1916 static int i915_pm_restore(struct device *dev)
1917 {
1918         return i915_pm_resume(dev);
1919 }
1920
1921 /*
1922  * Save all Gunit registers that may be lost after a D3 and a subsequent
1923  * S0i[R123] transition. The list of registers needing a save/restore is
1924  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1925  * registers in the following way:
1926  * - Driver: saved/restored by the driver
1927  * - Punit : saved/restored by the Punit firmware
1928  * - No, w/o marking: no need to save/restore, since the register is R/O or
1929  *                    used internally by the HW in a way that doesn't depend
1930  *                    keeping the content across a suspend/resume.
1931  * - Debug : used for debugging
1932  *
1933  * We save/restore all registers marked with 'Driver', with the following
1934  * exceptions:
1935  * - Registers out of use, including also registers marked with 'Debug'.
1936  *   These have no effect on the driver's operation, so we don't save/restore
1937  *   them to reduce the overhead.
1938  * - Registers that are fully setup by an initialization function called from
1939  *   the resume path. For example many clock gating and RPS/RC6 registers.
1940  * - Registers that provide the right functionality with their reset defaults.
1941  *
1942  * TODO: Except for registers that based on the above 3 criteria can be safely
1943  * ignored, we save/restore all others, practically treating the HW context as
1944  * a black-box for the driver. Further investigation is needed to reduce the
1945  * saved/restored registers even further, by following the same 3 criteria.
1946  */
1947 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1948 {
1949         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1950         int i;
1951
1952         /* GAM 0x4000-0x4770 */
1953         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1954         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1955         s->arb_mode             = I915_READ(ARB_MODE);
1956         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1957         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1958
1959         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1960                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1961
1962         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1963         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1964
1965         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1966         s->ecochk               = I915_READ(GAM_ECOCHK);
1967         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1968         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1969
1970         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1971
1972         /* MBC 0x9024-0x91D0, 0x8500 */
1973         s->g3dctl               = I915_READ(VLV_G3DCTL);
1974         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1975         s->mbctl                = I915_READ(GEN6_MBCTL);
1976
1977         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1978         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1979         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1980         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1981         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1982         s->rstctl               = I915_READ(GEN6_RSTCTL);
1983         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1984
1985         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1986         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1987         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1988         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1989         s->ecobus               = I915_READ(ECOBUS);
1990         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1991         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1992         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1993         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1994         s->rcedata              = I915_READ(VLV_RCEDATA);
1995         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1996
1997         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1998         s->gt_imr               = I915_READ(GTIMR);
1999         s->gt_ier               = I915_READ(GTIER);
2000         s->pm_imr               = I915_READ(GEN6_PMIMR);
2001         s->pm_ier               = I915_READ(GEN6_PMIER);
2002
2003         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2004                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2005
2006         /* GT SA CZ domain, 0x100000-0x138124 */
2007         s->tilectl              = I915_READ(TILECTL);
2008         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2009         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2010         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2011         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2012
2013         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2014         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2015         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2016         s->pcbr                 = I915_READ(VLV_PCBR);
2017         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2018
2019         /*
2020          * Not saving any of:
2021          * DFT,         0x9800-0x9EC0
2022          * SARB,        0xB000-0xB1FC
2023          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2024          * PCI CFG
2025          */
2026 }
2027
2028 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2029 {
2030         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2031         u32 val;
2032         int i;
2033
2034         /* GAM 0x4000-0x4770 */
2035         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2036         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2037         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2038         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2039         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2040
2041         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2042                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2043
2044         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2045         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2046
2047         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2048         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2049         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2050         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2051
2052         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2053
2054         /* MBC 0x9024-0x91D0, 0x8500 */
2055         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2056         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2057         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2058
2059         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2060         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2061         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2062         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2063         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2064         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2065         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2066
2067         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2068         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2069         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2070         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2071         I915_WRITE(ECOBUS,              s->ecobus);
2072         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2073         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2074         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2075         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2076         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2077         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2078
2079         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2080         I915_WRITE(GTIMR,               s->gt_imr);
2081         I915_WRITE(GTIER,               s->gt_ier);
2082         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2083         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2084
2085         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2086                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2087
2088         /* GT SA CZ domain, 0x100000-0x138124 */
2089         I915_WRITE(TILECTL,                     s->tilectl);
2090         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2091         /*
2092          * Preserve the GT allow wake and GFX force clock bit, they are not
2093          * be restored, as they are used to control the s0ix suspend/resume
2094          * sequence by the caller.
2095          */
2096         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2097         val &= VLV_GTLC_ALLOWWAKEREQ;
2098         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2099         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2100
2101         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2102         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2103         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2104         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2105
2106         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2107
2108         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2109         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2110         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2111         I915_WRITE(VLV_PCBR,                    s->pcbr);
2112         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2113 }
2114
2115 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2116 {
2117         u32 val;
2118         int err;
2119
2120         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2121         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2122         if (force_on)
2123                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2124         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2125
2126         if (!force_on)
2127                 return 0;
2128
2129         err = intel_wait_for_register(dev_priv,
2130                                       VLV_GTLC_SURVIVABILITY_REG,
2131                                       VLV_GFX_CLK_STATUS_BIT,
2132                                       VLV_GFX_CLK_STATUS_BIT,
2133                                       20);
2134         if (err)
2135                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2136                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2137
2138         return err;
2139 }
2140
2141 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2142 {
2143         u32 val;
2144         int err = 0;
2145
2146         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2147         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2148         if (allow)
2149                 val |= VLV_GTLC_ALLOWWAKEREQ;
2150         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2151         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2152
2153         err = intel_wait_for_register(dev_priv,
2154                                       VLV_GTLC_PW_STATUS,
2155                                       VLV_GTLC_ALLOWWAKEACK,
2156                                       allow,
2157                                       1);
2158         if (err)
2159                 DRM_ERROR("timeout disabling GT waking\n");
2160
2161         return err;
2162 }
2163
2164 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2165                                  bool wait_for_on)
2166 {
2167         u32 mask;
2168         u32 val;
2169         int err;
2170
2171         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2172         val = wait_for_on ? mask : 0;
2173         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2174                 return 0;
2175
2176         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2177                       onoff(wait_for_on),
2178                       I915_READ(VLV_GTLC_PW_STATUS));
2179
2180         /*
2181          * RC6 transitioning can be delayed up to 2 msec (see
2182          * valleyview_enable_rps), use 3 msec for safety.
2183          */
2184         err = intel_wait_for_register(dev_priv,
2185                                       VLV_GTLC_PW_STATUS, mask, val,
2186                                       3);
2187         if (err)
2188                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2189                           onoff(wait_for_on));
2190
2191         return err;
2192 }
2193
2194 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2195 {
2196         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2197                 return;
2198
2199         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2200         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2201 }
2202
2203 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2204 {
2205         u32 mask;
2206         int err;
2207
2208         /*
2209          * Bspec defines the following GT well on flags as debug only, so
2210          * don't treat them as hard failures.
2211          */
2212         (void)vlv_wait_for_gt_wells(dev_priv, false);
2213
2214         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2215         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2216
2217         vlv_check_no_gt_access(dev_priv);
2218
2219         err = vlv_force_gfx_clock(dev_priv, true);
2220         if (err)
2221                 goto err1;
2222
2223         err = vlv_allow_gt_wake(dev_priv, false);
2224         if (err)
2225                 goto err2;
2226
2227         if (!IS_CHERRYVIEW(dev_priv))
2228                 vlv_save_gunit_s0ix_state(dev_priv);
2229
2230         err = vlv_force_gfx_clock(dev_priv, false);
2231         if (err)
2232                 goto err2;
2233
2234         return 0;
2235
2236 err2:
2237         /* For safety always re-enable waking and disable gfx clock forcing */
2238         vlv_allow_gt_wake(dev_priv, true);
2239 err1:
2240         vlv_force_gfx_clock(dev_priv, false);
2241
2242         return err;
2243 }
2244
2245 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2246                                 bool rpm_resume)
2247 {
2248         struct drm_device *dev = &dev_priv->drm;
2249         int err;
2250         int ret;
2251
2252         /*
2253          * If any of the steps fail just try to continue, that's the best we
2254          * can do at this point. Return the first error code (which will also
2255          * leave RPM permanently disabled).
2256          */
2257         ret = vlv_force_gfx_clock(dev_priv, true);
2258
2259         if (!IS_CHERRYVIEW(dev_priv))
2260                 vlv_restore_gunit_s0ix_state(dev_priv);
2261
2262         err = vlv_allow_gt_wake(dev_priv, true);
2263         if (!ret)
2264                 ret = err;
2265
2266         err = vlv_force_gfx_clock(dev_priv, false);
2267         if (!ret)
2268                 ret = err;
2269
2270         vlv_check_no_gt_access(dev_priv);
2271
2272         if (rpm_resume) {
2273                 intel_init_clock_gating(dev);
2274                 i915_gem_restore_fences(dev);
2275         }
2276
2277         return ret;
2278 }
2279
2280 static int intel_runtime_suspend(struct device *device)
2281 {
2282         struct pci_dev *pdev = to_pci_dev(device);
2283         struct drm_device *dev = pci_get_drvdata(pdev);
2284         struct drm_i915_private *dev_priv = to_i915(dev);
2285         int ret;
2286
2287         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2288                 return -ENODEV;
2289
2290         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2291                 return -ENODEV;
2292
2293         DRM_DEBUG_KMS("Suspending device\n");
2294
2295         /*
2296          * We could deadlock here in case another thread holding struct_mutex
2297          * calls RPM suspend concurrently, since the RPM suspend will wait
2298          * first for this RPM suspend to finish. In this case the concurrent
2299          * RPM resume will be followed by its RPM suspend counterpart. Still
2300          * for consistency return -EAGAIN, which will reschedule this suspend.
2301          */
2302         if (!mutex_trylock(&dev->struct_mutex)) {
2303                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2304                 /*
2305                  * Bump the expiration timestamp, otherwise the suspend won't
2306                  * be rescheduled.
2307                  */
2308                 pm_runtime_mark_last_busy(device);
2309
2310                 return -EAGAIN;
2311         }
2312
2313         disable_rpm_wakeref_asserts(dev_priv);
2314
2315         /*
2316          * We are safe here against re-faults, since the fault handler takes
2317          * an RPM reference.
2318          */
2319         i915_gem_release_all_mmaps(dev_priv);
2320         mutex_unlock(&dev->struct_mutex);
2321
2322         intel_guc_suspend(dev);
2323
2324         intel_runtime_pm_disable_interrupts(dev_priv);
2325
2326         ret = 0;
2327         if (IS_BROXTON(dev_priv)) {
2328                 bxt_display_core_uninit(dev_priv);
2329                 bxt_enable_dc9(dev_priv);
2330         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2331                 hsw_enable_pc8(dev_priv);
2332         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2333                 ret = vlv_suspend_complete(dev_priv);
2334         }
2335
2336         if (ret) {
2337                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2338                 intel_runtime_pm_enable_interrupts(dev_priv);
2339
2340                 enable_rpm_wakeref_asserts(dev_priv);
2341
2342                 return ret;
2343         }
2344
2345         intel_uncore_forcewake_reset(dev_priv, false);
2346
2347         enable_rpm_wakeref_asserts(dev_priv);
2348         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2349
2350         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2351                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2352
2353         dev_priv->pm.suspended = true;
2354
2355         /*
2356          * FIXME: We really should find a document that references the arguments
2357          * used below!
2358          */
2359         if (IS_BROADWELL(dev_priv)) {
2360                 /*
2361                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2362                  * being detected, and the call we do at intel_runtime_resume()
2363                  * won't be able to restore them. Since PCI_D3hot matches the
2364                  * actual specification and appears to be working, use it.
2365                  */
2366                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2367         } else {
2368                 /*
2369                  * current versions of firmware which depend on this opregion
2370                  * notification have repurposed the D1 definition to mean
2371                  * "runtime suspended" vs. what you would normally expect (D3)
2372                  * to distinguish it from notifications that might be sent via
2373                  * the suspend path.
2374                  */
2375                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2376         }
2377
2378         assert_forcewakes_inactive(dev_priv);
2379
2380         if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2381                 intel_hpd_poll_init(dev_priv);
2382
2383         DRM_DEBUG_KMS("Device suspended\n");
2384         return 0;
2385 }
2386
2387 static int intel_runtime_resume(struct device *device)
2388 {
2389         struct pci_dev *pdev = to_pci_dev(device);
2390         struct drm_device *dev = pci_get_drvdata(pdev);
2391         struct drm_i915_private *dev_priv = to_i915(dev);
2392         int ret = 0;
2393
2394         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2395                 return -ENODEV;
2396
2397         DRM_DEBUG_KMS("Resuming device\n");
2398
2399         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2400         disable_rpm_wakeref_asserts(dev_priv);
2401
2402         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2403         dev_priv->pm.suspended = false;
2404         if (intel_uncore_unclaimed_mmio(dev_priv))
2405                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2406
2407         intel_guc_resume(dev);
2408
2409         if (IS_GEN6(dev_priv))
2410                 intel_init_pch_refclk(dev);
2411
2412         if (IS_BROXTON(dev)) {
2413                 bxt_disable_dc9(dev_priv);
2414                 bxt_display_core_init(dev_priv, true);
2415                 if (dev_priv->csr.dmc_payload &&
2416                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2417                         gen9_enable_dc5(dev_priv);
2418         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2419                 hsw_disable_pc8(dev_priv);
2420         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2421                 ret = vlv_resume_prepare(dev_priv, true);
2422         }
2423
2424         /*
2425          * No point of rolling back things in case of an error, as the best
2426          * we can do is to hope that things will still work (and disable RPM).
2427          */
2428         i915_gem_init_swizzling(dev);
2429
2430         intel_runtime_pm_enable_interrupts(dev_priv);
2431
2432         /*
2433          * On VLV/CHV display interrupts are part of the display
2434          * power well, so hpd is reinitialized from there. For
2435          * everyone else do it here.
2436          */
2437         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2438                 intel_hpd_init(dev_priv);
2439
2440         enable_rpm_wakeref_asserts(dev_priv);
2441
2442         if (ret)
2443                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2444         else
2445                 DRM_DEBUG_KMS("Device resumed\n");
2446
2447         return ret;
2448 }
2449
2450 const struct dev_pm_ops i915_pm_ops = {
2451         /*
2452          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2453          * PMSG_RESUME]
2454          */
2455         .suspend = i915_pm_suspend,
2456         .suspend_late = i915_pm_suspend_late,
2457         .resume_early = i915_pm_resume_early,
2458         .resume = i915_pm_resume,
2459
2460         /*
2461          * S4 event handlers
2462          * @freeze, @freeze_late    : called (1) before creating the
2463          *                            hibernation image [PMSG_FREEZE] and
2464          *                            (2) after rebooting, before restoring
2465          *                            the image [PMSG_QUIESCE]
2466          * @thaw, @thaw_early       : called (1) after creating the hibernation
2467          *                            image, before writing it [PMSG_THAW]
2468          *                            and (2) after failing to create or
2469          *                            restore the image [PMSG_RECOVER]
2470          * @poweroff, @poweroff_late: called after writing the hibernation
2471          *                            image, before rebooting [PMSG_HIBERNATE]
2472          * @restore, @restore_early : called after rebooting and restoring the
2473          *                            hibernation image [PMSG_RESTORE]
2474          */
2475         .freeze = i915_pm_freeze,
2476         .freeze_late = i915_pm_freeze_late,
2477         .thaw_early = i915_pm_thaw_early,
2478         .thaw = i915_pm_thaw,
2479         .poweroff = i915_pm_suspend,
2480         .poweroff_late = i915_pm_poweroff_late,
2481         .restore_early = i915_pm_restore_early,
2482         .restore = i915_pm_restore,
2483
2484         /* S0ix (via runtime suspend) event handlers */
2485         .runtime_suspend = intel_runtime_suspend,
2486         .runtime_resume = intel_runtime_resume,
2487 };
2488
2489 static const struct vm_operations_struct i915_gem_vm_ops = {
2490         .fault = i915_gem_fault,
2491         .open = drm_gem_vm_open,
2492         .close = drm_gem_vm_close,
2493 };
2494
2495 static const struct file_operations i915_driver_fops = {
2496         .owner = THIS_MODULE,
2497         .open = drm_open,
2498         .release = drm_release,
2499         .unlocked_ioctl = drm_ioctl,
2500         .mmap = drm_gem_mmap,
2501         .poll = drm_poll,
2502         .read = drm_read,
2503 #ifdef CONFIG_COMPAT
2504         .compat_ioctl = i915_compat_ioctl,
2505 #endif
2506         .llseek = noop_llseek,
2507 };
2508
2509 static int
2510 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2511                           struct drm_file *file)
2512 {
2513         return -ENODEV;
2514 }
2515
2516 static const struct drm_ioctl_desc i915_ioctls[] = {
2517         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2518         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2519         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2520         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2521         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2522         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2523         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2524         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2525         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2526         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2527         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2528         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2529         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2530         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2531         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2532         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2533         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2534         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2536         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2537         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2538         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2539         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2540         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2541         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2542         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2543         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2544         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2545         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2546         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2547         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2548         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2549         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2550         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2551         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2552         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2553         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2554         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2556         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2557         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2558         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2559         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2560         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2561         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2562         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2563         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2564         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2565         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2566         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2567         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2568         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2569 };
2570
2571 static struct drm_driver driver = {
2572         /* Don't use MTRRs here; the Xserver or userspace app should
2573          * deal with them for Intel hardware.
2574          */
2575         .driver_features =
2576             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2577             DRIVER_RENDER | DRIVER_MODESET,
2578         .open = i915_driver_open,
2579         .lastclose = i915_driver_lastclose,
2580         .preclose = i915_driver_preclose,
2581         .postclose = i915_driver_postclose,
2582         .set_busid = drm_pci_set_busid,
2583
2584         .gem_close_object = i915_gem_close_object,
2585         .gem_free_object = i915_gem_free_object,
2586         .gem_vm_ops = &i915_gem_vm_ops,
2587
2588         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2589         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2590         .gem_prime_export = i915_gem_prime_export,
2591         .gem_prime_import = i915_gem_prime_import,
2592
2593         .dumb_create = i915_gem_dumb_create,
2594         .dumb_map_offset = i915_gem_mmap_gtt,
2595         .dumb_destroy = drm_gem_dumb_destroy,
2596         .ioctls = i915_ioctls,
2597         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2598         .fops = &i915_driver_fops,
2599         .name = DRIVER_NAME,
2600         .desc = DRIVER_DESC,
2601         .date = DRIVER_DATE,
2602         .major = DRIVER_MAJOR,
2603         .minor = DRIVER_MINOR,
2604         .patchlevel = DRIVER_PATCHLEVEL,
2605 };