1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_irq.h>
47 #include <drm/drm_probe_helper.h>
48 #include <drm/i915_drm.h>
50 #include "display/intel_acpi.h"
51 #include "display/intel_audio.h"
52 #include "display/intel_bw.h"
53 #include "display/intel_cdclk.h"
54 #include "display/intel_display_types.h"
55 #include "display/intel_dp.h"
56 #include "display/intel_fbdev.h"
57 #include "display/intel_gmbus.h"
58 #include "display/intel_hotplug.h"
59 #include "display/intel_overlay.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_sprite.h"
63 #include "gem/i915_gem_context.h"
64 #include "gem/i915_gem_ioctls.h"
65 #include "gt/intel_gt.h"
66 #include "gt/intel_gt_pm.h"
68 #include "i915_debugfs.h"
71 #include "i915_memcpy.h"
72 #include "i915_perf.h"
73 #include "i915_query.h"
74 #include "i915_suspend.h"
75 #include "i915_sysfs.h"
76 #include "i915_trace.h"
77 #include "i915_vgpu.h"
78 #include "intel_csr.h"
81 static struct drm_driver driver;
83 struct vlv_s0ix_state {
90 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
91 u32 media_max_req_count;
92 u32 gfx_max_req_count;
124 /* Display 1 CZ domain */
129 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
131 /* GT SA CZ domain */
138 /* Display 2 CZ domain */
145 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
147 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
149 dev_priv->bridge_dev =
150 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
151 if (!dev_priv->bridge_dev) {
152 DRM_ERROR("bridge device not found\n");
158 /* Allocate space for the MCH regs if needed, return nonzero on error */
160 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
162 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
163 u32 temp_lo, temp_hi = 0;
167 if (INTEL_GEN(dev_priv) >= 4)
168 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
169 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
170 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
172 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
175 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
179 /* Get some space for it */
180 dev_priv->mch_res.name = "i915 MCHBAR";
181 dev_priv->mch_res.flags = IORESOURCE_MEM;
182 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
184 MCHBAR_SIZE, MCHBAR_SIZE,
186 0, pcibios_align_resource,
187 dev_priv->bridge_dev);
189 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
190 dev_priv->mch_res.start = 0;
194 if (INTEL_GEN(dev_priv) >= 4)
195 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
196 upper_32_bits(dev_priv->mch_res.start));
198 pci_write_config_dword(dev_priv->bridge_dev, reg,
199 lower_32_bits(dev_priv->mch_res.start));
203 /* Setup MCHBAR if possible, return true if we should disable it again */
205 intel_setup_mchbar(struct drm_i915_private *dev_priv)
207 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
211 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
214 dev_priv->mchbar_need_disable = false;
216 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
217 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
218 enabled = !!(temp & DEVEN_MCHBAR_EN);
220 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
224 /* If it's already enabled, don't have to do anything */
228 if (intel_alloc_mchbar_resource(dev_priv))
231 dev_priv->mchbar_need_disable = true;
233 /* Space is allocated or reserved, so enable it. */
234 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
235 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
236 temp | DEVEN_MCHBAR_EN);
238 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
239 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
244 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
246 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
248 if (dev_priv->mchbar_need_disable) {
249 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
252 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
254 deven_val &= ~DEVEN_MCHBAR_EN;
255 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
260 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
263 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
268 if (dev_priv->mch_res.start)
269 release_resource(&dev_priv->mch_res);
272 /* true = enable decode, false = disable decoder */
273 static unsigned int i915_vga_set_decode(void *cookie, bool state)
275 struct drm_i915_private *dev_priv = cookie;
277 intel_modeset_vga_set_state(dev_priv, state);
279 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
280 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
282 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
285 static int i915_resume_switcheroo(struct drm_i915_private *i915);
286 static int i915_suspend_switcheroo(struct drm_i915_private *i915,
289 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
291 struct drm_i915_private *i915 = pdev_to_i915(pdev);
292 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
295 dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n");
299 if (state == VGA_SWITCHEROO_ON) {
300 pr_info("switched on\n");
301 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
302 /* i915 resume handler doesn't set to D0 */
303 pci_set_power_state(pdev, PCI_D0);
304 i915_resume_switcheroo(i915);
305 i915->drm.switch_power_state = DRM_SWITCH_POWER_ON;
307 pr_info("switched off\n");
308 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
309 i915_suspend_switcheroo(i915, pmm);
310 i915->drm.switch_power_state = DRM_SWITCH_POWER_OFF;
314 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
316 struct drm_i915_private *i915 = pdev_to_i915(pdev);
319 * FIXME: open_count is protected by drm_global_mutex but that would lead to
320 * locking inversion with the driver load path. And the access here is
321 * completely racy anyway. So don't bother with locking for now.
323 return i915 && i915->drm.open_count == 0;
326 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
327 .set_gpu_state = i915_switcheroo_set_state,
329 .can_switch = i915_switcheroo_can_switch,
332 static int i915_driver_modeset_probe(struct drm_device *dev)
334 struct drm_i915_private *dev_priv = to_i915(dev);
335 struct pci_dev *pdev = dev_priv->drm.pdev;
338 if (i915_inject_probe_failure(dev_priv))
341 if (HAS_DISPLAY(dev_priv)) {
342 ret = drm_vblank_init(&dev_priv->drm,
343 INTEL_INFO(dev_priv)->num_pipes);
348 intel_bios_init(dev_priv);
350 /* If we have > 1 VGA cards, then we need to arbitrate access
351 * to the common VGA resources.
353 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
354 * then we do not take part in VGA arbitration and the
355 * vga_client_register() fails with -ENODEV.
357 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
358 if (ret && ret != -ENODEV)
361 intel_register_dsm_handler();
363 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
365 goto cleanup_vga_client;
367 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
368 intel_update_rawclk(dev_priv);
370 intel_power_domains_init_hw(dev_priv, false);
372 intel_csr_ucode_init(dev_priv);
374 ret = intel_irq_install(dev_priv);
378 intel_gmbus_setup(dev_priv);
380 /* Important: The output setup functions called by modeset_init need
381 * working irqs for e.g. gmbus and dp aux transfers. */
382 ret = intel_modeset_init(dev);
386 ret = i915_gem_init(dev_priv);
388 goto cleanup_modeset;
390 intel_overlay_setup(dev_priv);
392 if (!HAS_DISPLAY(dev_priv))
395 ret = intel_fbdev_init(dev);
399 /* Only enable hotplug handling once the fbdev is fully set up. */
400 intel_hpd_init(dev_priv);
402 intel_init_ipc(dev_priv);
407 i915_gem_suspend(dev_priv);
408 i915_gem_driver_remove(dev_priv);
409 i915_gem_driver_release(dev_priv);
411 intel_modeset_driver_remove(dev);
413 intel_irq_uninstall(dev_priv);
414 intel_gmbus_teardown(dev_priv);
416 intel_csr_ucode_fini(dev_priv);
417 intel_power_domains_driver_remove(dev_priv);
418 vga_switcheroo_unregister_client(pdev);
420 vga_client_register(pdev, NULL, NULL, NULL);
425 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
427 struct apertures_struct *ap;
428 struct pci_dev *pdev = dev_priv->drm.pdev;
429 struct i915_ggtt *ggtt = &dev_priv->ggtt;
433 ap = alloc_apertures(1);
437 ap->ranges[0].base = ggtt->gmadr.start;
438 ap->ranges[0].size = ggtt->mappable_end;
441 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
443 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
450 static void intel_init_dpio(struct drm_i915_private *dev_priv)
453 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
454 * CHV x1 PHY (DP/HDMI D)
455 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
457 if (IS_CHERRYVIEW(dev_priv)) {
458 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
459 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
460 } else if (IS_VALLEYVIEW(dev_priv)) {
461 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
465 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
468 * The i915 workqueue is primarily used for batched retirement of
469 * requests (and thus managing bo) once the task has been completed
470 * by the GPU. i915_retire_requests() is called directly when we
471 * need high-priority retirement, such as waiting for an explicit
474 * It is also used for periodic low-priority events, such as
475 * idle-timers and recording error state.
477 * All tasks on the workqueue are expected to acquire the dev mutex
478 * so there is no point in running more than one instance of the
479 * workqueue at any time. Use an ordered one.
481 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
482 if (dev_priv->wq == NULL)
485 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
486 if (dev_priv->hotplug.dp_wq == NULL)
492 destroy_workqueue(dev_priv->wq);
494 DRM_ERROR("Failed to allocate workqueues.\n");
499 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
501 destroy_workqueue(dev_priv->hotplug.dp_wq);
502 destroy_workqueue(dev_priv->wq);
506 * We don't keep the workarounds for pre-production hardware, so we expect our
507 * driver to fail on these machines in one way or another. A little warning on
508 * dmesg may help both the user and the bug triagers.
510 * Our policy for removing pre-production workarounds is to keep the
511 * current gen workarounds as a guide to the bring-up of the next gen
512 * (workarounds have a habit of persisting!). Anything older than that
513 * should be removed along with the complications they introduce.
515 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
519 pre |= IS_HSW_EARLY_SDV(dev_priv);
520 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
521 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
522 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
525 DRM_ERROR("This is a pre-production stepping. "
526 "It may not be fully functional.\n");
527 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
531 static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
533 if (!IS_VALLEYVIEW(i915))
536 /* we write all the values in the struct, so no need to zero it out */
537 i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
539 if (!i915->vlv_s0ix_state)
545 static void vlv_free_s0ix_state(struct drm_i915_private *i915)
547 if (!i915->vlv_s0ix_state)
550 kfree(i915->vlv_s0ix_state);
551 i915->vlv_s0ix_state = NULL;
555 * i915_driver_early_probe - setup state not requiring device access
556 * @dev_priv: device private
558 * Initialize everything that is a "SW-only" state, that is state not
559 * requiring accessing the device or exposing the driver via kernel internal
560 * or userspace interfaces. Example steps belonging here: lock initialization,
561 * system memory allocation, setting up device specific attributes and
562 * function hooks not requiring accessing the device.
564 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
568 if (i915_inject_probe_failure(dev_priv))
571 intel_device_info_subplatform_init(dev_priv);
573 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
574 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
576 spin_lock_init(&dev_priv->irq_lock);
577 spin_lock_init(&dev_priv->gpu_error.lock);
578 mutex_init(&dev_priv->backlight_lock);
580 mutex_init(&dev_priv->sb_lock);
581 pm_qos_add_request(&dev_priv->sb_qos,
582 PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
584 mutex_init(&dev_priv->av_mutex);
585 mutex_init(&dev_priv->wm.wm_mutex);
586 mutex_init(&dev_priv->pps_mutex);
587 mutex_init(&dev_priv->hdcp_comp_mutex);
589 i915_memcpy_init_early(dev_priv);
590 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
592 ret = i915_workqueues_init(dev_priv);
596 ret = vlv_alloc_s0ix_state(dev_priv);
600 intel_wopcm_init_early(&dev_priv->wopcm);
602 intel_gt_init_early(&dev_priv->gt, dev_priv);
604 ret = i915_gem_init_early(dev_priv);
608 /* This must be called before any calls to HAS_PCH_* */
609 intel_detect_pch(dev_priv);
611 intel_pm_setup(dev_priv);
612 intel_init_dpio(dev_priv);
613 ret = intel_power_domains_init(dev_priv);
616 intel_irq_init(dev_priv);
617 intel_init_display_hooks(dev_priv);
618 intel_init_clock_gating_hooks(dev_priv);
619 intel_init_audio_hooks(dev_priv);
620 intel_display_crc_init(dev_priv);
622 intel_detect_preproduction_hw(dev_priv);
627 i915_gem_cleanup_early(dev_priv);
629 intel_gt_driver_late_release(&dev_priv->gt);
630 vlv_free_s0ix_state(dev_priv);
632 i915_workqueues_cleanup(dev_priv);
637 * i915_driver_late_release - cleanup the setup done in
638 * i915_driver_early_probe()
639 * @dev_priv: device private
641 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
643 intel_irq_fini(dev_priv);
644 intel_power_domains_cleanup(dev_priv);
645 i915_gem_cleanup_early(dev_priv);
646 intel_gt_driver_late_release(&dev_priv->gt);
647 vlv_free_s0ix_state(dev_priv);
648 i915_workqueues_cleanup(dev_priv);
650 pm_qos_remove_request(&dev_priv->sb_qos);
651 mutex_destroy(&dev_priv->sb_lock);
655 * i915_driver_mmio_probe - setup device MMIO
656 * @dev_priv: device private
658 * Setup minimal device state necessary for MMIO accesses later in the
659 * initialization sequence. The setup here should avoid any other device-wide
660 * side effects or exposing the driver via kernel internal or user space
663 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
667 if (i915_inject_probe_failure(dev_priv))
670 if (i915_get_bridge_dev(dev_priv))
673 ret = intel_uncore_init_mmio(&dev_priv->uncore);
677 /* Try to make sure MCHBAR is enabled before poking at it */
678 intel_setup_mchbar(dev_priv);
680 intel_device_info_init_mmio(dev_priv);
682 intel_uncore_prune_mmio_domains(&dev_priv->uncore);
684 intel_uc_init_mmio(&dev_priv->gt.uc);
686 ret = intel_engines_init_mmio(dev_priv);
690 i915_gem_init_mmio(dev_priv);
695 intel_teardown_mchbar(dev_priv);
696 intel_uncore_fini_mmio(&dev_priv->uncore);
698 pci_dev_put(dev_priv->bridge_dev);
704 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
705 * @dev_priv: device private
707 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
709 intel_engines_cleanup(dev_priv);
710 intel_teardown_mchbar(dev_priv);
711 intel_uncore_fini_mmio(&dev_priv->uncore);
712 pci_dev_put(dev_priv->bridge_dev);
715 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
717 intel_gvt_sanitize_options(dev_priv);
720 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
722 static const char *intel_dram_type_str(enum intel_dram_type type)
724 static const char * const str[] = {
725 DRAM_TYPE_STR(UNKNOWN),
728 DRAM_TYPE_STR(LPDDR3),
729 DRAM_TYPE_STR(LPDDR4),
732 if (type >= ARRAY_SIZE(str))
733 type = INTEL_DRAM_UNKNOWN;
740 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
742 return dimm->ranks * 64 / (dimm->width ?: 1);
745 /* Returns total GB for the whole DIMM */
746 static int skl_get_dimm_size(u16 val)
748 return val & SKL_DRAM_SIZE_MASK;
751 static int skl_get_dimm_width(u16 val)
753 if (skl_get_dimm_size(val) == 0)
756 switch (val & SKL_DRAM_WIDTH_MASK) {
757 case SKL_DRAM_WIDTH_X8:
758 case SKL_DRAM_WIDTH_X16:
759 case SKL_DRAM_WIDTH_X32:
760 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
768 static int skl_get_dimm_ranks(u16 val)
770 if (skl_get_dimm_size(val) == 0)
773 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
778 /* Returns total GB for the whole DIMM */
779 static int cnl_get_dimm_size(u16 val)
781 return (val & CNL_DRAM_SIZE_MASK) / 2;
784 static int cnl_get_dimm_width(u16 val)
786 if (cnl_get_dimm_size(val) == 0)
789 switch (val & CNL_DRAM_WIDTH_MASK) {
790 case CNL_DRAM_WIDTH_X8:
791 case CNL_DRAM_WIDTH_X16:
792 case CNL_DRAM_WIDTH_X32:
793 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
801 static int cnl_get_dimm_ranks(u16 val)
803 if (cnl_get_dimm_size(val) == 0)
806 val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
812 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
814 /* Convert total GB to Gb per DRAM device */
815 return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
819 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
820 struct dram_dimm_info *dimm,
821 int channel, char dimm_name, u16 val)
823 if (INTEL_GEN(dev_priv) >= 10) {
824 dimm->size = cnl_get_dimm_size(val);
825 dimm->width = cnl_get_dimm_width(val);
826 dimm->ranks = cnl_get_dimm_ranks(val);
828 dimm->size = skl_get_dimm_size(val);
829 dimm->width = skl_get_dimm_width(val);
830 dimm->ranks = skl_get_dimm_ranks(val);
833 DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
834 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
835 yesno(skl_is_16gb_dimm(dimm)));
839 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
840 struct dram_channel_info *ch,
841 int channel, u32 val)
843 skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
844 channel, 'L', val & 0xffff);
845 skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
846 channel, 'S', val >> 16);
848 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
849 DRM_DEBUG_KMS("CH%u not populated\n", channel);
853 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
855 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
861 skl_is_16gb_dimm(&ch->dimm_l) ||
862 skl_is_16gb_dimm(&ch->dimm_s);
864 DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
865 channel, ch->ranks, yesno(ch->is_16gb_dimm));
871 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
872 const struct dram_channel_info *ch1)
874 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
875 (ch0->dimm_s.size == 0 ||
876 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
880 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
882 struct dram_info *dram_info = &dev_priv->dram_info;
883 struct dram_channel_info ch0 = {}, ch1 = {};
887 val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
888 ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
890 dram_info->num_channels++;
892 val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
893 ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
895 dram_info->num_channels++;
897 if (dram_info->num_channels == 0) {
898 DRM_INFO("Number of memory channels is zero\n");
903 * If any of the channel is single rank channel, worst case output
904 * will be same as if single rank memory, so consider single rank
907 if (ch0.ranks == 1 || ch1.ranks == 1)
908 dram_info->ranks = 1;
910 dram_info->ranks = max(ch0.ranks, ch1.ranks);
912 if (dram_info->ranks == 0) {
913 DRM_INFO("couldn't get memory rank information\n");
917 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
919 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
921 DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
922 yesno(dram_info->symmetric_memory));
926 static enum intel_dram_type
927 skl_get_dram_type(struct drm_i915_private *dev_priv)
931 val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
933 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
934 case SKL_DRAM_DDR_TYPE_DDR3:
935 return INTEL_DRAM_DDR3;
936 case SKL_DRAM_DDR_TYPE_DDR4:
937 return INTEL_DRAM_DDR4;
938 case SKL_DRAM_DDR_TYPE_LPDDR3:
939 return INTEL_DRAM_LPDDR3;
940 case SKL_DRAM_DDR_TYPE_LPDDR4:
941 return INTEL_DRAM_LPDDR4;
944 return INTEL_DRAM_UNKNOWN;
949 skl_get_dram_info(struct drm_i915_private *dev_priv)
951 struct dram_info *dram_info = &dev_priv->dram_info;
952 u32 mem_freq_khz, val;
955 dram_info->type = skl_get_dram_type(dev_priv);
956 DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
958 ret = skl_dram_get_channels_info(dev_priv);
962 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
963 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
964 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
966 dram_info->bandwidth_kbps = dram_info->num_channels *
969 if (dram_info->bandwidth_kbps == 0) {
970 DRM_INFO("Couldn't get system memory bandwidth\n");
974 dram_info->valid = true;
978 /* Returns Gb per DRAM device */
979 static int bxt_get_dimm_size(u32 val)
981 switch (val & BXT_DRAM_SIZE_MASK) {
982 case BXT_DRAM_SIZE_4GBIT:
984 case BXT_DRAM_SIZE_6GBIT:
986 case BXT_DRAM_SIZE_8GBIT:
988 case BXT_DRAM_SIZE_12GBIT:
990 case BXT_DRAM_SIZE_16GBIT:
998 static int bxt_get_dimm_width(u32 val)
1000 if (!bxt_get_dimm_size(val))
1003 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1008 static int bxt_get_dimm_ranks(u32 val)
1010 if (!bxt_get_dimm_size(val))
1013 switch (val & BXT_DRAM_RANK_MASK) {
1014 case BXT_DRAM_RANK_SINGLE:
1016 case BXT_DRAM_RANK_DUAL:
1024 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1026 if (!bxt_get_dimm_size(val))
1027 return INTEL_DRAM_UNKNOWN;
1029 switch (val & BXT_DRAM_TYPE_MASK) {
1030 case BXT_DRAM_TYPE_DDR3:
1031 return INTEL_DRAM_DDR3;
1032 case BXT_DRAM_TYPE_LPDDR3:
1033 return INTEL_DRAM_LPDDR3;
1034 case BXT_DRAM_TYPE_DDR4:
1035 return INTEL_DRAM_DDR4;
1036 case BXT_DRAM_TYPE_LPDDR4:
1037 return INTEL_DRAM_LPDDR4;
1040 return INTEL_DRAM_UNKNOWN;
1044 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1047 dimm->width = bxt_get_dimm_width(val);
1048 dimm->ranks = bxt_get_dimm_ranks(val);
1051 * Size in register is Gb per DRAM device. Convert to total
1052 * GB to match the way we report this for non-LP platforms.
1054 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1058 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1060 struct dram_info *dram_info = &dev_priv->dram_info;
1062 u32 mem_freq_khz, val;
1063 u8 num_active_channels;
1066 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1067 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1068 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1070 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1071 num_active_channels = hweight32(dram_channels);
1073 /* Each active bit represents 4-byte channel */
1074 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1076 if (dram_info->bandwidth_kbps == 0) {
1077 DRM_INFO("Couldn't get system memory bandwidth\n");
1082 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1084 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1085 struct dram_dimm_info dimm;
1086 enum intel_dram_type type;
1088 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1089 if (val == 0xFFFFFFFF)
1092 dram_info->num_channels++;
1094 bxt_get_dimm_info(&dimm, val);
1095 type = bxt_get_dimm_type(val);
1097 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1098 dram_info->type != INTEL_DRAM_UNKNOWN &&
1099 dram_info->type != type);
1101 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1102 i - BXT_D_CR_DRP0_DUNIT_START,
1103 dimm.size, dimm.width, dimm.ranks,
1104 intel_dram_type_str(type));
1107 * If any of the channel is single rank channel,
1108 * worst case output will be same as if single rank
1109 * memory, so consider single rank memory.
1111 if (dram_info->ranks == 0)
1112 dram_info->ranks = dimm.ranks;
1113 else if (dimm.ranks == 1)
1114 dram_info->ranks = 1;
1116 if (type != INTEL_DRAM_UNKNOWN)
1117 dram_info->type = type;
1120 if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1121 dram_info->ranks == 0) {
1122 DRM_INFO("couldn't get memory information\n");
1126 dram_info->valid = true;
1131 intel_get_dram_info(struct drm_i915_private *dev_priv)
1133 struct dram_info *dram_info = &dev_priv->dram_info;
1137 * Assume 16Gb DIMMs are present until proven otherwise.
1138 * This is only used for the level 0 watermark latency
1139 * w/a which does not apply to bxt/glk.
1141 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1143 if (INTEL_GEN(dev_priv) < 9)
1146 if (IS_GEN9_LP(dev_priv))
1147 ret = bxt_get_dram_info(dev_priv);
1149 ret = skl_get_dram_info(dev_priv);
1153 DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1154 dram_info->bandwidth_kbps,
1155 dram_info->num_channels);
1157 DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1158 dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1161 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1163 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1164 const unsigned int sets[4] = { 1, 1, 2, 2 };
1166 return EDRAM_NUM_BANKS(cap) *
1167 ways[EDRAM_WAYS_IDX(cap)] *
1168 sets[EDRAM_SETS_IDX(cap)];
1171 static void edram_detect(struct drm_i915_private *dev_priv)
1175 if (!(IS_HASWELL(dev_priv) ||
1176 IS_BROADWELL(dev_priv) ||
1177 INTEL_GEN(dev_priv) >= 9))
1180 edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1182 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1184 if (!(edram_cap & EDRAM_ENABLED))
1188 * The needed capability bits for size calculation are not there with
1189 * pre gen9 so return 128MB always.
1191 if (INTEL_GEN(dev_priv) < 9)
1192 dev_priv->edram_size_mb = 128;
1194 dev_priv->edram_size_mb =
1195 gen9_edram_size_mb(dev_priv, edram_cap);
1197 dev_info(dev_priv->drm.dev,
1198 "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1202 * i915_driver_hw_probe - setup state requiring device access
1203 * @dev_priv: device private
1205 * Setup state that requires accessing the device, but doesn't require
1206 * exposing the driver via kernel internal or userspace interfaces.
1208 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1210 struct pci_dev *pdev = dev_priv->drm.pdev;
1213 if (i915_inject_probe_failure(dev_priv))
1216 intel_device_info_runtime_init(dev_priv);
1218 if (HAS_PPGTT(dev_priv)) {
1219 if (intel_vgpu_active(dev_priv) &&
1220 !intel_vgpu_has_full_ppgtt(dev_priv)) {
1221 i915_report_error(dev_priv,
1222 "incompatible vGPU found, support for isolated ppGTT required\n");
1227 if (HAS_EXECLISTS(dev_priv)) {
1229 * Older GVT emulation depends upon intercepting CSB mmio,
1230 * which we no longer use, preferring to use the HWSP cache
1233 if (intel_vgpu_active(dev_priv) &&
1234 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1235 i915_report_error(dev_priv,
1236 "old vGPU host found, support for HWSP emulation required\n");
1241 intel_sanitize_options(dev_priv);
1243 /* needs to be done before ggtt probe */
1244 edram_detect(dev_priv);
1246 i915_perf_init(dev_priv);
1248 ret = i915_ggtt_probe_hw(dev_priv);
1253 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1254 * otherwise the vga fbdev driver falls over.
1256 ret = i915_kick_out_firmware_fb(dev_priv);
1258 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1262 ret = vga_remove_vgacon(pdev);
1264 DRM_ERROR("failed to remove conflicting VGA console\n");
1268 ret = i915_ggtt_init_hw(dev_priv);
1272 intel_gt_init_hw(dev_priv);
1274 ret = i915_ggtt_enable_hw(dev_priv);
1276 DRM_ERROR("failed to enable GGTT\n");
1280 pci_set_master(pdev);
1283 * We don't have a max segment size, so set it to the max so sg's
1284 * debugging layer doesn't complain
1286 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1288 /* overlay on gen2 is broken and can't address above 1G */
1289 if (IS_GEN(dev_priv, 2)) {
1290 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1292 DRM_ERROR("failed to set DMA mask\n");
1298 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1299 * using 32bit addressing, overwriting memory if HWS is located
1302 * The documentation also mentions an issue with undefined
1303 * behaviour if any general state is accessed within a page above 4GB,
1304 * which also needs to be handled carefully.
1306 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1307 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1310 DRM_ERROR("failed to set DMA mask\n");
1316 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1317 PM_QOS_DEFAULT_VALUE);
1319 intel_gt_init_workarounds(dev_priv);
1321 /* On the 945G/GM, the chipset reports the MSI capability on the
1322 * integrated graphics even though the support isn't actually there
1323 * according to the published specs. It doesn't appear to function
1324 * correctly in testing on 945G.
1325 * This may be a side effect of MSI having been made available for PEG
1326 * and the registers being closely associated.
1328 * According to chipset errata, on the 965GM, MSI interrupts may
1329 * be lost or delayed, and was defeatured. MSI interrupts seem to
1330 * get lost on g4x as well, and interrupt delivery seems to stay
1331 * properly dead afterwards. So we'll just disable them for all
1332 * pre-gen5 chipsets.
1334 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1335 * interrupts even when in MSI mode. This results in spurious
1336 * interrupt warnings if the legacy irq no. is shared with another
1337 * device. The kernel then disables that interrupt source and so
1338 * prevents the other device from working properly.
1340 if (INTEL_GEN(dev_priv) >= 5) {
1341 if (pci_enable_msi(pdev) < 0)
1342 DRM_DEBUG_DRIVER("can't enable MSI");
1345 ret = intel_gvt_init(dev_priv);
1349 intel_opregion_setup(dev_priv);
1351 * Fill the dram structure to get the system raw bandwidth and
1352 * dram info. This will be used for memory latency calculation.
1354 intel_get_dram_info(dev_priv);
1356 intel_bw_init_hw(dev_priv);
1361 if (pdev->msi_enabled)
1362 pci_disable_msi(pdev);
1363 pm_qos_remove_request(&dev_priv->pm_qos);
1365 i915_ggtt_driver_release(dev_priv);
1367 i915_perf_fini(dev_priv);
1372 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1373 * @dev_priv: device private
1375 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1377 struct pci_dev *pdev = dev_priv->drm.pdev;
1379 i915_perf_fini(dev_priv);
1381 if (pdev->msi_enabled)
1382 pci_disable_msi(pdev);
1384 pm_qos_remove_request(&dev_priv->pm_qos);
1388 * i915_driver_register - register the driver with the rest of the system
1389 * @dev_priv: device private
1391 * Perform any steps necessary to make the driver available via kernel
1392 * internal or userspace interfaces.
1394 static void i915_driver_register(struct drm_i915_private *dev_priv)
1396 struct drm_device *dev = &dev_priv->drm;
1398 i915_gem_driver_register(dev_priv);
1399 i915_pmu_register(dev_priv);
1402 * Notify a valid surface after modesetting,
1403 * when running inside a VM.
1405 if (intel_vgpu_active(dev_priv))
1406 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1408 /* Reveal our presence to userspace */
1409 if (drm_dev_register(dev, 0) == 0) {
1410 i915_debugfs_register(dev_priv);
1411 i915_setup_sysfs(dev_priv);
1413 /* Depends on sysfs having been initialized */
1414 i915_perf_register(dev_priv);
1416 DRM_ERROR("Failed to register driver for userspace access!\n");
1418 if (HAS_DISPLAY(dev_priv)) {
1419 /* Must be done after probing outputs */
1420 intel_opregion_register(dev_priv);
1421 acpi_video_register();
1424 intel_gt_driver_register(&dev_priv->gt);
1426 intel_audio_init(dev_priv);
1429 * Some ports require correctly set-up hpd registers for detection to
1430 * work properly (leading to ghost connected connector status), e.g. VGA
1431 * on gm45. Hence we can only set up the initial fbdev config after hpd
1432 * irqs are fully enabled. We do it last so that the async config
1433 * cannot run before the connectors are registered.
1435 intel_fbdev_initial_config_async(dev);
1438 * We need to coordinate the hotplugs with the asynchronous fbdev
1439 * configuration, for which we use the fbdev->async_cookie.
1441 if (HAS_DISPLAY(dev_priv))
1442 drm_kms_helper_poll_init(dev);
1444 intel_power_domains_enable(dev_priv);
1445 intel_runtime_pm_enable(&dev_priv->runtime_pm);
1449 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1450 * @dev_priv: device private
1452 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1454 intel_runtime_pm_disable(&dev_priv->runtime_pm);
1455 intel_power_domains_disable(dev_priv);
1457 intel_fbdev_unregister(dev_priv);
1458 intel_audio_deinit(dev_priv);
1461 * After flushing the fbdev (incl. a late async config which will
1462 * have delayed queuing of a hotplug event), then flush the hotplug
1465 drm_kms_helper_poll_fini(&dev_priv->drm);
1467 intel_gt_driver_unregister(&dev_priv->gt);
1468 acpi_video_unregister();
1469 intel_opregion_unregister(dev_priv);
1471 i915_perf_unregister(dev_priv);
1472 i915_pmu_unregister(dev_priv);
1474 i915_teardown_sysfs(dev_priv);
1475 drm_dev_unplug(&dev_priv->drm);
1477 i915_gem_driver_unregister(dev_priv);
1480 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1482 if (drm_debug & DRM_UT_DRIVER) {
1483 struct drm_printer p = drm_debug_printer("i915 device info:");
1485 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1486 INTEL_DEVID(dev_priv),
1487 INTEL_REVID(dev_priv),
1488 intel_platform_name(INTEL_INFO(dev_priv)->platform),
1489 intel_subplatform(RUNTIME_INFO(dev_priv),
1490 INTEL_INFO(dev_priv)->platform),
1491 INTEL_GEN(dev_priv));
1493 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1494 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1497 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1498 DRM_INFO("DRM_I915_DEBUG enabled\n");
1499 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1500 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1501 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1502 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1505 static struct drm_i915_private *
1506 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1508 const struct intel_device_info *match_info =
1509 (struct intel_device_info *)ent->driver_data;
1510 struct intel_device_info *device_info;
1511 struct drm_i915_private *i915;
1514 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1516 return ERR_PTR(-ENOMEM);
1518 err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1521 return ERR_PTR(err);
1524 i915->drm.dev_private = i915;
1526 i915->drm.pdev = pdev;
1527 pci_set_drvdata(pdev, i915);
1529 /* Setup the write-once "constant" device info */
1530 device_info = mkwrite_device_info(i915);
1531 memcpy(device_info, match_info, sizeof(*device_info));
1532 RUNTIME_INFO(i915)->device_id = pdev->device;
1534 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1539 static void i915_driver_destroy(struct drm_i915_private *i915)
1541 struct pci_dev *pdev = i915->drm.pdev;
1543 drm_dev_fini(&i915->drm);
1546 /* And make sure we never chase our dangling pointer from pci_dev */
1547 pci_set_drvdata(pdev, NULL);
1551 * i915_driver_probe - setup chip and create an initial config
1553 * @ent: matching PCI ID entry
1555 * The driver probe routine has to do several things:
1556 * - drive output discovery via intel_modeset_init()
1557 * - initialize the memory manager
1558 * - allocate initial config memory
1559 * - setup the DRM framebuffer with the allocated memory
1561 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1563 const struct intel_device_info *match_info =
1564 (struct intel_device_info *)ent->driver_data;
1565 struct drm_i915_private *dev_priv;
1568 dev_priv = i915_driver_create(pdev, ent);
1569 if (IS_ERR(dev_priv))
1570 return PTR_ERR(dev_priv);
1572 /* Disable nuclear pageflip by default on pre-ILK */
1573 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1574 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1576 ret = pci_enable_device(pdev);
1580 ret = i915_driver_early_probe(dev_priv);
1582 goto out_pci_disable;
1584 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1586 i915_detect_vgpu(dev_priv);
1588 ret = i915_driver_mmio_probe(dev_priv);
1590 goto out_runtime_pm_put;
1592 ret = i915_driver_hw_probe(dev_priv);
1594 goto out_cleanup_mmio;
1596 ret = i915_driver_modeset_probe(&dev_priv->drm);
1598 goto out_cleanup_hw;
1600 i915_driver_register(dev_priv);
1602 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1604 i915_welcome_messages(dev_priv);
1609 i915_driver_hw_remove(dev_priv);
1610 i915_ggtt_driver_release(dev_priv);
1612 i915_driver_mmio_release(dev_priv);
1614 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1615 i915_driver_late_release(dev_priv);
1617 pci_disable_device(pdev);
1619 i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
1620 i915_driver_destroy(dev_priv);
1624 void i915_driver_remove(struct drm_i915_private *i915)
1626 struct pci_dev *pdev = i915->drm.pdev;
1628 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1630 i915_driver_unregister(i915);
1633 * After unregistering the device to prevent any new users, cancel
1634 * all in-flight requests so that we can quickly unbind the active
1637 intel_gt_set_wedged(&i915->gt);
1639 /* Flush any external code that still may be under the RCU lock */
1642 i915_gem_suspend(i915);
1644 drm_atomic_helper_shutdown(&i915->drm);
1646 intel_gvt_driver_remove(i915);
1648 intel_modeset_driver_remove(&i915->drm);
1650 intel_bios_driver_remove(i915);
1652 vga_switcheroo_unregister_client(pdev);
1653 vga_client_register(pdev, NULL, NULL, NULL);
1655 intel_csr_ucode_fini(i915);
1657 /* Free error state after interrupts are fully disabled. */
1658 cancel_delayed_work_sync(&i915->gt.hangcheck.work);
1659 i915_reset_error_state(i915);
1661 i915_gem_driver_remove(i915);
1663 intel_power_domains_driver_remove(i915);
1665 i915_driver_hw_remove(i915);
1667 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1670 static void i915_driver_release(struct drm_device *dev)
1672 struct drm_i915_private *dev_priv = to_i915(dev);
1673 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1675 disable_rpm_wakeref_asserts(rpm);
1677 i915_gem_driver_release(dev_priv);
1679 i915_ggtt_driver_release(dev_priv);
1681 i915_driver_mmio_release(dev_priv);
1683 enable_rpm_wakeref_asserts(rpm);
1684 intel_runtime_pm_driver_release(rpm);
1686 i915_driver_late_release(dev_priv);
1687 i915_driver_destroy(dev_priv);
1690 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1692 struct drm_i915_private *i915 = to_i915(dev);
1695 ret = i915_gem_open(i915, file);
1703 * i915_driver_lastclose - clean up after all DRM clients have exited
1706 * Take care of cleaning up after all DRM clients have exited. In the
1707 * mode setting case, we want to restore the kernel's initial mode (just
1708 * in case the last client left us in a bad state).
1710 * Additionally, in the non-mode setting case, we'll tear down the GTT
1711 * and DMA structures, since the kernel won't be using them, and clea
1714 static void i915_driver_lastclose(struct drm_device *dev)
1716 intel_fbdev_restore_mode(dev);
1717 vga_switcheroo_process_delayed_switch();
1720 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1722 struct drm_i915_file_private *file_priv = file->driver_priv;
1724 mutex_lock(&dev->struct_mutex);
1725 i915_gem_context_close(file);
1726 i915_gem_release(dev, file);
1727 mutex_unlock(&dev->struct_mutex);
1729 kfree_rcu(file_priv, rcu);
1731 /* Catch up with all the deferred frees from "this" client */
1732 i915_gem_flush_free_objects(to_i915(dev));
1735 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1737 struct drm_device *dev = &dev_priv->drm;
1738 struct intel_encoder *encoder;
1740 drm_modeset_lock_all(dev);
1741 for_each_intel_encoder(dev, encoder)
1742 if (encoder->suspend)
1743 encoder->suspend(encoder);
1744 drm_modeset_unlock_all(dev);
1747 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1749 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1751 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1753 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1754 if (acpi_target_system_state() < ACPI_STATE_S3)
1760 static int i915_drm_prepare(struct drm_device *dev)
1762 struct drm_i915_private *i915 = to_i915(dev);
1765 * NB intel_display_suspend() may issue new requests after we've
1766 * ostensibly marked the GPU as ready-to-sleep here. We need to
1767 * split out that work and pull it forward so that after point,
1768 * the GPU is not woken again.
1770 i915_gem_suspend(i915);
1775 static int i915_drm_suspend(struct drm_device *dev)
1777 struct drm_i915_private *dev_priv = to_i915(dev);
1778 struct pci_dev *pdev = dev_priv->drm.pdev;
1779 pci_power_t opregion_target_state;
1781 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1783 /* We do a lot of poking in a lot of registers, make sure they work
1785 intel_power_domains_disable(dev_priv);
1787 drm_kms_helper_poll_disable(dev);
1789 pci_save_state(pdev);
1791 intel_display_suspend(dev);
1793 intel_dp_mst_suspend(dev_priv);
1795 intel_runtime_pm_disable_interrupts(dev_priv);
1796 intel_hpd_cancel_work(dev_priv);
1798 intel_suspend_encoders(dev_priv);
1800 intel_suspend_hw(dev_priv);
1802 i915_gem_suspend_gtt_mappings(dev_priv);
1804 i915_save_state(dev_priv);
1806 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1807 intel_opregion_suspend(dev_priv, opregion_target_state);
1809 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1811 dev_priv->suspend_count++;
1813 intel_csr_ucode_suspend(dev_priv);
1815 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1820 static enum i915_drm_suspend_mode
1821 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1824 return I915_DRM_SUSPEND_HIBERNATE;
1826 if (suspend_to_idle(dev_priv))
1827 return I915_DRM_SUSPEND_IDLE;
1829 return I915_DRM_SUSPEND_MEM;
1832 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1834 struct drm_i915_private *dev_priv = to_i915(dev);
1835 struct pci_dev *pdev = dev_priv->drm.pdev;
1836 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1839 disable_rpm_wakeref_asserts(rpm);
1841 i915_gem_suspend_late(dev_priv);
1843 intel_uncore_suspend(&dev_priv->uncore);
1845 intel_power_domains_suspend(dev_priv,
1846 get_suspend_mode(dev_priv, hibernation));
1848 intel_display_power_suspend_late(dev_priv);
1850 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1851 ret = vlv_suspend_complete(dev_priv);
1854 DRM_ERROR("Suspend complete failed: %d\n", ret);
1855 intel_power_domains_resume(dev_priv);
1860 pci_disable_device(pdev);
1862 * During hibernation on some platforms the BIOS may try to access
1863 * the device even though it's already in D3 and hang the machine. So
1864 * leave the device in D0 on those platforms and hope the BIOS will
1865 * power down the device properly. The issue was seen on multiple old
1866 * GENs with different BIOS vendors, so having an explicit blacklist
1867 * is inpractical; apply the workaround on everything pre GEN6. The
1868 * platforms where the issue was seen:
1869 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1873 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1874 pci_set_power_state(pdev, PCI_D3hot);
1877 enable_rpm_wakeref_asserts(rpm);
1878 if (!dev_priv->uncore.user_forcewake_count)
1879 intel_runtime_pm_driver_release(rpm);
1885 i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1889 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1890 state.event != PM_EVENT_FREEZE))
1893 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1896 error = i915_drm_suspend(&i915->drm);
1900 return i915_drm_suspend_late(&i915->drm, false);
1903 static int i915_drm_resume(struct drm_device *dev)
1905 struct drm_i915_private *dev_priv = to_i915(dev);
1908 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1909 intel_gt_pm_disable(&dev_priv->gt);
1911 i915_gem_sanitize(dev_priv);
1913 ret = i915_ggtt_enable_hw(dev_priv);
1915 DRM_ERROR("failed to re-enable GGTT\n");
1917 mutex_lock(&dev_priv->drm.struct_mutex);
1918 i915_gem_restore_gtt_mappings(dev_priv);
1919 i915_gem_restore_fences(dev_priv);
1920 mutex_unlock(&dev_priv->drm.struct_mutex);
1922 intel_csr_ucode_resume(dev_priv);
1924 i915_restore_state(dev_priv);
1925 intel_pps_unlock_regs_wa(dev_priv);
1927 intel_init_pch_refclk(dev_priv);
1930 * Interrupts have to be enabled before any batches are run. If not the
1931 * GPU will hang. i915_gem_init_hw() will initiate batches to
1932 * update/restore the context.
1934 * drm_mode_config_reset() needs AUX interrupts.
1936 * Modeset enabling in intel_modeset_init_hw() also needs working
1939 intel_runtime_pm_enable_interrupts(dev_priv);
1941 drm_mode_config_reset(dev);
1943 i915_gem_resume(dev_priv);
1945 intel_modeset_init_hw(dev);
1946 intel_init_clock_gating(dev_priv);
1948 spin_lock_irq(&dev_priv->irq_lock);
1949 if (dev_priv->display.hpd_irq_setup)
1950 dev_priv->display.hpd_irq_setup(dev_priv);
1951 spin_unlock_irq(&dev_priv->irq_lock);
1953 intel_dp_mst_resume(dev_priv);
1955 intel_display_resume(dev);
1957 drm_kms_helper_poll_enable(dev);
1960 * ... but also need to make sure that hotplug processing
1961 * doesn't cause havoc. Like in the driver load code we don't
1962 * bother with the tiny race here where we might lose hotplug
1965 intel_hpd_init(dev_priv);
1967 intel_opregion_resume(dev_priv);
1969 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1971 intel_power_domains_enable(dev_priv);
1973 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1978 static int i915_drm_resume_early(struct drm_device *dev)
1980 struct drm_i915_private *dev_priv = to_i915(dev);
1981 struct pci_dev *pdev = dev_priv->drm.pdev;
1985 * We have a resume ordering issue with the snd-hda driver also
1986 * requiring our device to be power up. Due to the lack of a
1987 * parent/child relationship we currently solve this with an early
1990 * FIXME: This should be solved with a special hdmi sink device or
1991 * similar so that power domains can be employed.
1995 * Note that we need to set the power state explicitly, since we
1996 * powered off the device during freeze and the PCI core won't power
1997 * it back up for us during thaw. Powering off the device during
1998 * freeze is not a hard requirement though, and during the
1999 * suspend/resume phases the PCI core makes sure we get here with the
2000 * device powered on. So in case we change our freeze logic and keep
2001 * the device powered we can also remove the following set power state
2004 ret = pci_set_power_state(pdev, PCI_D0);
2006 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2011 * Note that pci_enable_device() first enables any parent bridge
2012 * device and only then sets the power state for this device. The
2013 * bridge enabling is a nop though, since bridge devices are resumed
2014 * first. The order of enabling power and enabling the device is
2015 * imposed by the PCI core as described above, so here we preserve the
2016 * same order for the freeze/thaw phases.
2018 * TODO: eventually we should remove pci_disable_device() /
2019 * pci_enable_enable_device() from suspend/resume. Due to how they
2020 * depend on the device enable refcount we can't anyway depend on them
2021 * disabling/enabling the device.
2023 if (pci_enable_device(pdev))
2026 pci_set_master(pdev);
2028 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2030 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2031 ret = vlv_resume_prepare(dev_priv, false);
2033 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2036 intel_uncore_resume_early(&dev_priv->uncore);
2038 intel_gt_check_and_clear_faults(&dev_priv->gt);
2040 intel_display_power_resume_early(dev_priv);
2042 intel_gt_pm_disable(&dev_priv->gt);
2044 intel_power_domains_resume(dev_priv);
2046 intel_gt_sanitize(&dev_priv->gt, true);
2048 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2053 static int i915_resume_switcheroo(struct drm_i915_private *i915)
2057 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2060 ret = i915_drm_resume_early(&i915->drm);
2064 return i915_drm_resume(&i915->drm);
2067 static int i915_pm_prepare(struct device *kdev)
2069 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2072 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2076 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2079 return i915_drm_prepare(&i915->drm);
2082 static int i915_pm_suspend(struct device *kdev)
2084 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2087 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2091 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2094 return i915_drm_suspend(&i915->drm);
2097 static int i915_pm_suspend_late(struct device *kdev)
2099 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2102 * We have a suspend ordering issue with the snd-hda driver also
2103 * requiring our device to be power up. Due to the lack of a
2104 * parent/child relationship we currently solve this with an late
2107 * FIXME: This should be solved with a special hdmi sink device or
2108 * similar so that power domains can be employed.
2110 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2113 return i915_drm_suspend_late(&i915->drm, false);
2116 static int i915_pm_poweroff_late(struct device *kdev)
2118 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2120 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2123 return i915_drm_suspend_late(&i915->drm, true);
2126 static int i915_pm_resume_early(struct device *kdev)
2128 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2130 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2133 return i915_drm_resume_early(&i915->drm);
2136 static int i915_pm_resume(struct device *kdev)
2138 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2140 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2143 return i915_drm_resume(&i915->drm);
2146 /* freeze: before creating the hibernation_image */
2147 static int i915_pm_freeze(struct device *kdev)
2149 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2152 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2153 ret = i915_drm_suspend(&i915->drm);
2158 ret = i915_gem_freeze(i915);
2165 static int i915_pm_freeze_late(struct device *kdev)
2167 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2170 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2171 ret = i915_drm_suspend_late(&i915->drm, true);
2176 ret = i915_gem_freeze_late(i915);
2183 /* thaw: called after creating the hibernation image, but before turning off. */
2184 static int i915_pm_thaw_early(struct device *kdev)
2186 return i915_pm_resume_early(kdev);
2189 static int i915_pm_thaw(struct device *kdev)
2191 return i915_pm_resume(kdev);
2194 /* restore: called after loading the hibernation image. */
2195 static int i915_pm_restore_early(struct device *kdev)
2197 return i915_pm_resume_early(kdev);
2200 static int i915_pm_restore(struct device *kdev)
2202 return i915_pm_resume(kdev);
2206 * Save all Gunit registers that may be lost after a D3 and a subsequent
2207 * S0i[R123] transition. The list of registers needing a save/restore is
2208 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2209 * registers in the following way:
2210 * - Driver: saved/restored by the driver
2211 * - Punit : saved/restored by the Punit firmware
2212 * - No, w/o marking: no need to save/restore, since the register is R/O or
2213 * used internally by the HW in a way that doesn't depend
2214 * keeping the content across a suspend/resume.
2215 * - Debug : used for debugging
2217 * We save/restore all registers marked with 'Driver', with the following
2219 * - Registers out of use, including also registers marked with 'Debug'.
2220 * These have no effect on the driver's operation, so we don't save/restore
2221 * them to reduce the overhead.
2222 * - Registers that are fully setup by an initialization function called from
2223 * the resume path. For example many clock gating and RPS/RC6 registers.
2224 * - Registers that provide the right functionality with their reset defaults.
2226 * TODO: Except for registers that based on the above 3 criteria can be safely
2227 * ignored, we save/restore all others, practically treating the HW context as
2228 * a black-box for the driver. Further investigation is needed to reduce the
2229 * saved/restored registers even further, by following the same 3 criteria.
2231 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2233 struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2239 /* GAM 0x4000-0x4770 */
2240 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2241 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2242 s->arb_mode = I915_READ(ARB_MODE);
2243 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2244 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2246 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2247 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2249 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2250 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2252 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2253 s->ecochk = I915_READ(GAM_ECOCHK);
2254 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2255 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2257 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2259 /* MBC 0x9024-0x91D0, 0x8500 */
2260 s->g3dctl = I915_READ(VLV_G3DCTL);
2261 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2262 s->mbctl = I915_READ(GEN6_MBCTL);
2264 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2265 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2266 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2267 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2268 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2269 s->rstctl = I915_READ(GEN6_RSTCTL);
2270 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2272 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2273 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2274 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2275 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2276 s->ecobus = I915_READ(ECOBUS);
2277 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2278 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2279 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2280 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2281 s->rcedata = I915_READ(VLV_RCEDATA);
2282 s->spare2gh = I915_READ(VLV_SPAREG2H);
2284 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2285 s->gt_imr = I915_READ(GTIMR);
2286 s->gt_ier = I915_READ(GTIER);
2287 s->pm_imr = I915_READ(GEN6_PMIMR);
2288 s->pm_ier = I915_READ(GEN6_PMIER);
2290 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2291 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2293 /* GT SA CZ domain, 0x100000-0x138124 */
2294 s->tilectl = I915_READ(TILECTL);
2295 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2296 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2297 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2298 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2300 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2301 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2302 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2303 s->pcbr = I915_READ(VLV_PCBR);
2304 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2307 * Not saving any of:
2308 * DFT, 0x9800-0x9EC0
2309 * SARB, 0xB000-0xB1FC
2310 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2315 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2317 struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2324 /* GAM 0x4000-0x4770 */
2325 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2326 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2327 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2328 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2329 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2331 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2332 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2334 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2335 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2337 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2338 I915_WRITE(GAM_ECOCHK, s->ecochk);
2339 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2340 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2342 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2344 /* MBC 0x9024-0x91D0, 0x8500 */
2345 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2346 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2347 I915_WRITE(GEN6_MBCTL, s->mbctl);
2349 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2350 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2351 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2352 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2353 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2354 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2355 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2357 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2358 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2359 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2360 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2361 I915_WRITE(ECOBUS, s->ecobus);
2362 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2363 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2364 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2365 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2366 I915_WRITE(VLV_RCEDATA, s->rcedata);
2367 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2369 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2370 I915_WRITE(GTIMR, s->gt_imr);
2371 I915_WRITE(GTIER, s->gt_ier);
2372 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2373 I915_WRITE(GEN6_PMIER, s->pm_ier);
2375 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2376 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2378 /* GT SA CZ domain, 0x100000-0x138124 */
2379 I915_WRITE(TILECTL, s->tilectl);
2380 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2382 * Preserve the GT allow wake and GFX force clock bit, they are not
2383 * be restored, as they are used to control the s0ix suspend/resume
2384 * sequence by the caller.
2386 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2387 val &= VLV_GTLC_ALLOWWAKEREQ;
2388 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2389 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2391 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2392 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2393 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2394 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2396 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2398 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2399 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2400 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2401 I915_WRITE(VLV_PCBR, s->pcbr);
2402 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2405 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2408 i915_reg_t reg = VLV_GTLC_PW_STATUS;
2412 /* The HW does not like us polling for PW_STATUS frequently, so
2413 * use the sleeping loop rather than risk the busy spin within
2414 * intel_wait_for_register().
2416 * Transitioning between RC6 states should be at most 2ms (see
2417 * valleyview_enable_rps) so use a 3ms timeout.
2419 ret = wait_for(((reg_value =
2420 intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2423 /* just trace the final value */
2424 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2429 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2434 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2435 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2437 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2438 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2443 err = intel_wait_for_register(&dev_priv->uncore,
2444 VLV_GTLC_SURVIVABILITY_REG,
2445 VLV_GFX_CLK_STATUS_BIT,
2446 VLV_GFX_CLK_STATUS_BIT,
2449 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2450 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2455 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2461 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2462 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2464 val |= VLV_GTLC_ALLOWWAKEREQ;
2465 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2466 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2468 mask = VLV_GTLC_ALLOWWAKEACK;
2469 val = allow ? mask : 0;
2471 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2473 DRM_ERROR("timeout disabling GT waking\n");
2478 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2484 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2485 val = wait_for_on ? mask : 0;
2488 * RC6 transitioning can be delayed up to 2 msec (see
2489 * valleyview_enable_rps), use 3 msec for safety.
2491 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2492 * reset and we are trying to force the machine to sleep.
2494 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2495 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2496 onoff(wait_for_on));
2499 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2501 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2504 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2505 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2508 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2514 * Bspec defines the following GT well on flags as debug only, so
2515 * don't treat them as hard failures.
2517 vlv_wait_for_gt_wells(dev_priv, false);
2519 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2520 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2522 vlv_check_no_gt_access(dev_priv);
2524 err = vlv_force_gfx_clock(dev_priv, true);
2528 err = vlv_allow_gt_wake(dev_priv, false);
2532 vlv_save_gunit_s0ix_state(dev_priv);
2534 err = vlv_force_gfx_clock(dev_priv, false);
2541 /* For safety always re-enable waking and disable gfx clock forcing */
2542 vlv_allow_gt_wake(dev_priv, true);
2544 vlv_force_gfx_clock(dev_priv, false);
2549 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2556 * If any of the steps fail just try to continue, that's the best we
2557 * can do at this point. Return the first error code (which will also
2558 * leave RPM permanently disabled).
2560 ret = vlv_force_gfx_clock(dev_priv, true);
2562 vlv_restore_gunit_s0ix_state(dev_priv);
2564 err = vlv_allow_gt_wake(dev_priv, true);
2568 err = vlv_force_gfx_clock(dev_priv, false);
2572 vlv_check_no_gt_access(dev_priv);
2575 intel_init_clock_gating(dev_priv);
2580 static int intel_runtime_suspend(struct device *kdev)
2582 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2583 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2586 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2589 DRM_DEBUG_KMS("Suspending device\n");
2591 disable_rpm_wakeref_asserts(rpm);
2594 * We are safe here against re-faults, since the fault handler takes
2597 i915_gem_runtime_suspend(dev_priv);
2599 intel_gt_runtime_suspend(&dev_priv->gt);
2601 intel_runtime_pm_disable_interrupts(dev_priv);
2603 intel_uncore_suspend(&dev_priv->uncore);
2605 intel_display_power_suspend(dev_priv);
2607 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2608 ret = vlv_suspend_complete(dev_priv);
2611 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2612 intel_uncore_runtime_resume(&dev_priv->uncore);
2614 intel_runtime_pm_enable_interrupts(dev_priv);
2616 intel_gt_runtime_resume(&dev_priv->gt);
2618 i915_gem_restore_fences(dev_priv);
2620 enable_rpm_wakeref_asserts(rpm);
2625 enable_rpm_wakeref_asserts(rpm);
2626 intel_runtime_pm_driver_release(rpm);
2628 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2629 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2631 rpm->suspended = true;
2634 * FIXME: We really should find a document that references the arguments
2637 if (IS_BROADWELL(dev_priv)) {
2639 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2640 * being detected, and the call we do at intel_runtime_resume()
2641 * won't be able to restore them. Since PCI_D3hot matches the
2642 * actual specification and appears to be working, use it.
2644 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2647 * current versions of firmware which depend on this opregion
2648 * notification have repurposed the D1 definition to mean
2649 * "runtime suspended" vs. what you would normally expect (D3)
2650 * to distinguish it from notifications that might be sent via
2653 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2656 assert_forcewakes_inactive(&dev_priv->uncore);
2658 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2659 intel_hpd_poll_init(dev_priv);
2661 DRM_DEBUG_KMS("Device suspended\n");
2665 static int intel_runtime_resume(struct device *kdev)
2667 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2668 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2671 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2674 DRM_DEBUG_KMS("Resuming device\n");
2676 WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
2677 disable_rpm_wakeref_asserts(rpm);
2679 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2680 rpm->suspended = false;
2681 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2682 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2684 intel_display_power_resume(dev_priv);
2686 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2687 ret = vlv_resume_prepare(dev_priv, true);
2689 intel_uncore_runtime_resume(&dev_priv->uncore);
2691 intel_runtime_pm_enable_interrupts(dev_priv);
2694 * No point of rolling back things in case of an error, as the best
2695 * we can do is to hope that things will still work (and disable RPM).
2697 intel_gt_runtime_resume(&dev_priv->gt);
2698 i915_gem_restore_fences(dev_priv);
2701 * On VLV/CHV display interrupts are part of the display
2702 * power well, so hpd is reinitialized from there. For
2703 * everyone else do it here.
2705 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2706 intel_hpd_init(dev_priv);
2708 intel_enable_ipc(dev_priv);
2710 enable_rpm_wakeref_asserts(rpm);
2713 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2715 DRM_DEBUG_KMS("Device resumed\n");
2720 const struct dev_pm_ops i915_pm_ops = {
2722 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2725 .prepare = i915_pm_prepare,
2726 .suspend = i915_pm_suspend,
2727 .suspend_late = i915_pm_suspend_late,
2728 .resume_early = i915_pm_resume_early,
2729 .resume = i915_pm_resume,
2733 * @freeze, @freeze_late : called (1) before creating the
2734 * hibernation image [PMSG_FREEZE] and
2735 * (2) after rebooting, before restoring
2736 * the image [PMSG_QUIESCE]
2737 * @thaw, @thaw_early : called (1) after creating the hibernation
2738 * image, before writing it [PMSG_THAW]
2739 * and (2) after failing to create or
2740 * restore the image [PMSG_RECOVER]
2741 * @poweroff, @poweroff_late: called after writing the hibernation
2742 * image, before rebooting [PMSG_HIBERNATE]
2743 * @restore, @restore_early : called after rebooting and restoring the
2744 * hibernation image [PMSG_RESTORE]
2746 .freeze = i915_pm_freeze,
2747 .freeze_late = i915_pm_freeze_late,
2748 .thaw_early = i915_pm_thaw_early,
2749 .thaw = i915_pm_thaw,
2750 .poweroff = i915_pm_suspend,
2751 .poweroff_late = i915_pm_poweroff_late,
2752 .restore_early = i915_pm_restore_early,
2753 .restore = i915_pm_restore,
2755 /* S0ix (via runtime suspend) event handlers */
2756 .runtime_suspend = intel_runtime_suspend,
2757 .runtime_resume = intel_runtime_resume,
2760 static const struct vm_operations_struct i915_gem_vm_ops = {
2761 .fault = i915_gem_fault,
2762 .open = drm_gem_vm_open,
2763 .close = drm_gem_vm_close,
2766 static const struct file_operations i915_driver_fops = {
2767 .owner = THIS_MODULE,
2769 .release = drm_release,
2770 .unlocked_ioctl = drm_ioctl,
2771 .mmap = drm_gem_mmap,
2774 .compat_ioctl = i915_compat_ioctl,
2775 .llseek = noop_llseek,
2779 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2780 struct drm_file *file)
2785 static const struct drm_ioctl_desc i915_ioctls[] = {
2786 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2787 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2788 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2789 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2790 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2791 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2792 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2793 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2794 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2795 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2796 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2797 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2798 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2799 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2800 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2801 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2802 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2803 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2804 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2805 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2806 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2807 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2808 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2809 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2810 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2811 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2812 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2813 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2814 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2815 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2816 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2817 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2818 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2819 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2820 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2821 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2822 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2823 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2824 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2825 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2826 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2827 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2828 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2829 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2830 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2831 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2832 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2833 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2834 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2835 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2836 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2837 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2838 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2839 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2840 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2841 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2842 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2843 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2846 static struct drm_driver driver = {
2847 /* Don't use MTRRs here; the Xserver or userspace app should
2848 * deal with them for Intel hardware.
2852 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2853 .release = i915_driver_release,
2854 .open = i915_driver_open,
2855 .lastclose = i915_driver_lastclose,
2856 .postclose = i915_driver_postclose,
2858 .gem_close_object = i915_gem_close_object,
2859 .gem_free_object_unlocked = i915_gem_free_object,
2860 .gem_vm_ops = &i915_gem_vm_ops,
2862 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2863 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2864 .gem_prime_export = i915_gem_prime_export,
2865 .gem_prime_import = i915_gem_prime_import,
2867 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2868 .get_scanout_position = i915_get_crtc_scanoutpos,
2870 .dumb_create = i915_gem_dumb_create,
2871 .dumb_map_offset = i915_gem_mmap_gtt,
2872 .ioctls = i915_ioctls,
2873 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2874 .fops = &i915_driver_fops,
2875 .name = DRIVER_NAME,
2876 .desc = DRIVER_DESC,
2877 .date = DRIVER_DATE,
2878 .major = DRIVER_MAJOR,
2879 .minor = DRIVER_MINOR,
2880 .patchlevel = DRIVER_PATCHLEVEL,
2883 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2884 #include "selftests/mock_drm.c"