1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info = {
67 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
68 .has_overlay = 1, .overlay_needs_physical = 1,
69 .ring_mask = RENDER_RING,
70 GEN_DEFAULT_PIPEOFFSETS,
74 static const struct intel_device_info intel_845g_info = {
75 .gen = 2, .num_pipes = 1,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
82 static const struct intel_device_info intel_i85x_info = {
83 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
84 .cursor_needs_physical = 1,
85 .has_overlay = 1, .overlay_needs_physical = 1,
87 .ring_mask = RENDER_RING,
88 GEN_DEFAULT_PIPEOFFSETS,
92 static const struct intel_device_info intel_i865g_info = {
93 .gen = 2, .num_pipes = 1,
94 .has_overlay = 1, .overlay_needs_physical = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
100 static const struct intel_device_info intel_i915g_info = {
101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
107 static const struct intel_device_info intel_i915gm_info = {
108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
109 .cursor_needs_physical = 1,
110 .has_overlay = 1, .overlay_needs_physical = 1,
113 .ring_mask = RENDER_RING,
114 GEN_DEFAULT_PIPEOFFSETS,
117 static const struct intel_device_info intel_i945g_info = {
118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
119 .has_overlay = 1, .overlay_needs_physical = 1,
120 .ring_mask = RENDER_RING,
121 GEN_DEFAULT_PIPEOFFSETS,
124 static const struct intel_device_info intel_i945gm_info = {
125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
126 .has_hotplug = 1, .cursor_needs_physical = 1,
127 .has_overlay = 1, .overlay_needs_physical = 1,
130 .ring_mask = RENDER_RING,
131 GEN_DEFAULT_PIPEOFFSETS,
135 static const struct intel_device_info intel_i965g_info = {
136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
139 .ring_mask = RENDER_RING,
140 GEN_DEFAULT_PIPEOFFSETS,
144 static const struct intel_device_info intel_i965gm_info = {
145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
149 .ring_mask = RENDER_RING,
150 GEN_DEFAULT_PIPEOFFSETS,
154 static const struct intel_device_info intel_g33_info = {
155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
156 .need_gfx_hws = 1, .has_hotplug = 1,
158 .ring_mask = RENDER_RING,
159 GEN_DEFAULT_PIPEOFFSETS,
163 static const struct intel_device_info intel_g45_info = {
164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
165 .has_pipe_cxsr = 1, .has_hotplug = 1,
166 .ring_mask = RENDER_RING | BSD_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
171 static const struct intel_device_info intel_gm45_info = {
172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
174 .has_pipe_cxsr = 1, .has_hotplug = 1,
176 .ring_mask = RENDER_RING | BSD_RING,
177 GEN_DEFAULT_PIPEOFFSETS,
181 static const struct intel_device_info intel_pineview_info = {
182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
183 .need_gfx_hws = 1, .has_hotplug = 1,
185 GEN_DEFAULT_PIPEOFFSETS,
189 static const struct intel_device_info intel_ironlake_d_info = {
190 .gen = 5, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .ring_mask = RENDER_RING | BSD_RING,
193 GEN_DEFAULT_PIPEOFFSETS,
197 static const struct intel_device_info intel_ironlake_m_info = {
198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
201 .ring_mask = RENDER_RING | BSD_RING,
202 GEN_DEFAULT_PIPEOFFSETS,
206 static const struct intel_device_info intel_sandybridge_d_info = {
207 .gen = 6, .num_pipes = 2,
208 .need_gfx_hws = 1, .has_hotplug = 1,
210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
212 GEN_DEFAULT_PIPEOFFSETS,
216 static const struct intel_device_info intel_sandybridge_m_info = {
217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
218 .need_gfx_hws = 1, .has_hotplug = 1,
220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
222 GEN_DEFAULT_PIPEOFFSETS,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
233 static const struct intel_device_info intel_ivybridge_d_info = {
236 GEN_DEFAULT_PIPEOFFSETS,
240 static const struct intel_device_info intel_ivybridge_m_info = {
244 GEN_DEFAULT_PIPEOFFSETS,
248 static const struct intel_device_info intel_ivybridge_q_info = {
251 .num_pipes = 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS,
256 static const struct intel_device_info intel_valleyview_m_info = {
261 .display_mmio_offset = VLV_DISPLAY_BASE,
262 .has_fbc = 0, /* legal, last one wins */
263 .has_llc = 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS,
268 static const struct intel_device_info intel_valleyview_d_info = {
272 .display_mmio_offset = VLV_DISPLAY_BASE,
273 .has_fbc = 0, /* legal, last one wins */
274 .has_llc = 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS,
279 static const struct intel_device_info intel_haswell_d_info = {
284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
285 GEN_DEFAULT_PIPEOFFSETS,
289 static const struct intel_device_info intel_haswell_m_info = {
295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
296 GEN_DEFAULT_PIPEOFFSETS,
300 static const struct intel_device_info intel_broadwell_d_info = {
301 .gen = 8, .num_pipes = 3,
302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
308 GEN_DEFAULT_PIPEOFFSETS,
312 static const struct intel_device_info intel_broadwell_m_info = {
313 .gen = 8, .is_mobile = 1, .num_pipes = 3,
314 .need_gfx_hws = 1, .has_hotplug = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
320 GEN_DEFAULT_PIPEOFFSETS,
324 static const struct intel_device_info intel_broadwell_gt3d_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
332 GEN_DEFAULT_PIPEOFFSETS,
336 static const struct intel_device_info intel_broadwell_gt3m_info = {
337 .gen = 8, .is_mobile = 1, .num_pipes = 3,
338 .need_gfx_hws = 1, .has_hotplug = 1,
339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
344 GEN_DEFAULT_PIPEOFFSETS,
348 static const struct intel_device_info intel_cherryview_info = {
350 .gen = 8, .num_pipes = 3,
351 .need_gfx_hws = 1, .has_hotplug = 1,
352 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
354 .display_mmio_offset = VLV_DISPLAY_BASE,
360 * Make sure any device matches here are from most specific to most
361 * general. For example, since the Quanta match is based on the subsystem
362 * and subvendor IDs, we need it to come before the more general IVB
363 * PCI ID matches, otherwise we'll use the wrong info struct above.
365 #define INTEL_PCI_IDS \
366 INTEL_I830_IDS(&intel_i830_info), \
367 INTEL_I845G_IDS(&intel_845g_info), \
368 INTEL_I85X_IDS(&intel_i85x_info), \
369 INTEL_I865G_IDS(&intel_i865g_info), \
370 INTEL_I915G_IDS(&intel_i915g_info), \
371 INTEL_I915GM_IDS(&intel_i915gm_info), \
372 INTEL_I945G_IDS(&intel_i945g_info), \
373 INTEL_I945GM_IDS(&intel_i945gm_info), \
374 INTEL_I965G_IDS(&intel_i965g_info), \
375 INTEL_G33_IDS(&intel_g33_info), \
376 INTEL_I965GM_IDS(&intel_i965gm_info), \
377 INTEL_GM45_IDS(&intel_gm45_info), \
378 INTEL_G45_IDS(&intel_g45_info), \
379 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
380 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
381 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
382 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
383 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
384 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
385 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
386 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
387 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
388 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
389 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
390 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
391 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
392 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
393 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
394 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
395 INTEL_CHV_IDS(&intel_cherryview_info)
397 static const struct pci_device_id pciidlist[] = { /* aka */
402 #if defined(CONFIG_DRM_I915_KMS)
403 MODULE_DEVICE_TABLE(pci, pciidlist);
406 void intel_detect_pch(struct drm_device *dev)
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 struct pci_dev *pch = NULL;
411 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
412 * (which really amounts to a PCH but no South Display).
414 if (INTEL_INFO(dev)->num_pipes == 0) {
415 dev_priv->pch_type = PCH_NOP;
420 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
421 * make graphics device passthrough work easy for VMM, that only
422 * need to expose ISA bridge to let driver know the real hardware
423 * underneath. This is a requirement from virtualization team.
425 * In some virtualized environments (e.g. XEN), there is irrelevant
426 * ISA bridge in the system. To work reliably, we should scan trhough
427 * all the ISA bridge devices and check for the first match, instead
428 * of only checking the first one.
430 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
431 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
432 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
433 dev_priv->pch_id = id;
435 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
436 dev_priv->pch_type = PCH_IBX;
437 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
438 WARN_ON(!IS_GEN5(dev));
439 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
440 dev_priv->pch_type = PCH_CPT;
441 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
442 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
443 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
444 /* PantherPoint is CPT compatible */
445 dev_priv->pch_type = PCH_CPT;
446 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
447 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
448 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
449 dev_priv->pch_type = PCH_LPT;
450 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
451 WARN_ON(!IS_HASWELL(dev));
452 WARN_ON(IS_ULT(dev));
453 } else if (IS_BROADWELL(dev)) {
454 dev_priv->pch_type = PCH_LPT;
456 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
457 DRM_DEBUG_KMS("This is Broadwell, assuming "
458 "LynxPoint LP PCH\n");
459 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
460 dev_priv->pch_type = PCH_LPT;
461 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
462 WARN_ON(!IS_HASWELL(dev));
463 WARN_ON(!IS_ULT(dev));
471 DRM_DEBUG_KMS("No PCH found.\n");
476 bool i915_semaphore_is_enabled(struct drm_device *dev)
478 if (INTEL_INFO(dev)->gen < 6)
481 if (i915.semaphores >= 0)
482 return i915.semaphores;
484 /* Until we get further testing... */
488 #ifdef CONFIG_INTEL_IOMMU
489 /* Enable semaphores on SNB when IO remapping is off */
490 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
497 static int i915_drm_freeze(struct drm_device *dev)
499 struct drm_i915_private *dev_priv = dev->dev_private;
500 struct drm_crtc *crtc;
501 pci_power_t opregion_target_state;
503 /* ignore lid events during suspend */
504 mutex_lock(&dev_priv->modeset_restore_lock);
505 dev_priv->modeset_restore = MODESET_SUSPENDED;
506 mutex_unlock(&dev_priv->modeset_restore_lock);
508 /* We do a lot of poking in a lot of registers, make sure they work
510 intel_display_set_init_power(dev_priv, true);
512 drm_kms_helper_poll_disable(dev);
514 pci_save_state(dev->pdev);
516 /* If KMS is active, we do the leavevt stuff here */
517 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
520 error = i915_gem_suspend(dev);
522 dev_err(&dev->pdev->dev,
523 "GEM idle failed, resume might fail\n");
528 * Disable CRTCs directly since we want to preserve sw state
529 * for _thaw. Also, power gate the CRTC power wells.
531 drm_modeset_lock_all(dev);
532 for_each_crtc(dev, crtc)
533 intel_crtc_control(crtc, false);
534 drm_modeset_unlock_all(dev);
536 intel_dp_mst_suspend(dev);
538 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
540 intel_runtime_pm_disable_interrupts(dev);
542 intel_suspend_gt_powersave(dev);
544 intel_modeset_suspend_hw(dev);
547 i915_gem_suspend_gtt_mappings(dev);
549 i915_save_state(dev);
551 opregion_target_state = PCI_D3cold;
552 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
553 if (acpi_target_system_state() < ACPI_STATE_S3)
554 opregion_target_state = PCI_D1;
556 intel_opregion_notify_adapter(dev, opregion_target_state);
558 intel_uncore_forcewake_reset(dev, false);
559 intel_opregion_fini(dev);
561 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
563 dev_priv->suspend_count++;
565 intel_display_set_init_power(dev_priv, false);
570 int i915_suspend(struct drm_device *dev, pm_message_t state)
574 if (!dev || !dev->dev_private) {
575 DRM_ERROR("dev: %p\n", dev);
576 DRM_ERROR("DRM not initialized, aborting suspend.\n");
580 if (state.event == PM_EVENT_PRETHAW)
584 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
587 error = i915_drm_freeze(dev);
591 if (state.event == PM_EVENT_SUSPEND) {
592 /* Shut down the device */
593 pci_disable_device(dev->pdev);
594 pci_set_power_state(dev->pdev, PCI_D3hot);
600 static int i915_drm_thaw_early(struct drm_device *dev)
602 struct drm_i915_private *dev_priv = dev->dev_private;
604 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
605 hsw_disable_pc8(dev_priv);
607 intel_uncore_early_sanitize(dev, true);
608 intel_uncore_sanitize(dev);
609 intel_power_domains_init_hw(dev_priv);
614 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
616 struct drm_i915_private *dev_priv = dev->dev_private;
618 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
619 restore_gtt_mappings) {
620 mutex_lock(&dev->struct_mutex);
621 i915_gem_restore_gtt_mappings(dev);
622 mutex_unlock(&dev->struct_mutex);
625 i915_restore_state(dev);
626 intel_opregion_setup(dev);
628 /* KMS EnterVT equivalent */
629 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
630 intel_init_pch_refclk(dev);
631 drm_mode_config_reset(dev);
633 mutex_lock(&dev->struct_mutex);
634 if (i915_gem_init_hw(dev)) {
635 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
636 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
638 mutex_unlock(&dev->struct_mutex);
640 intel_runtime_pm_restore_interrupts(dev);
642 intel_modeset_init_hw(dev);
645 unsigned long irqflags;
646 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
647 if (dev_priv->display.hpd_irq_setup)
648 dev_priv->display.hpd_irq_setup(dev);
649 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
652 intel_dp_mst_resume(dev);
653 drm_modeset_lock_all(dev);
654 intel_modeset_setup_hw_state(dev, true);
655 drm_modeset_unlock_all(dev);
658 * ... but also need to make sure that hotplug processing
659 * doesn't cause havoc. Like in the driver load code we don't
660 * bother with the tiny race here where we might loose hotplug
664 /* Config may have changed between suspend and resume */
665 drm_helper_hpd_irq_event(dev);
668 intel_opregion_init(dev);
670 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
672 mutex_lock(&dev_priv->modeset_restore_lock);
673 dev_priv->modeset_restore = MODESET_DONE;
674 mutex_unlock(&dev_priv->modeset_restore_lock);
676 intel_opregion_notify_adapter(dev, PCI_D0);
681 static int i915_drm_thaw(struct drm_device *dev)
683 if (drm_core_check_feature(dev, DRIVER_MODESET))
684 i915_check_and_clear_faults(dev);
686 return __i915_drm_thaw(dev, true);
689 static int i915_resume_early(struct drm_device *dev)
691 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
695 * We have a resume ordering issue with the snd-hda driver also
696 * requiring our device to be power up. Due to the lack of a
697 * parent/child relationship we currently solve this with an early
700 * FIXME: This should be solved with a special hdmi sink device or
701 * similar so that power domains can be employed.
703 if (pci_enable_device(dev->pdev))
706 pci_set_master(dev->pdev);
708 return i915_drm_thaw_early(dev);
711 int i915_resume(struct drm_device *dev)
713 struct drm_i915_private *dev_priv = dev->dev_private;
717 * Platforms with opregion should have sane BIOS, older ones (gen3 and
718 * earlier) need to restore the GTT mappings since the BIOS might clear
719 * all our scratch PTEs.
721 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
725 drm_kms_helper_poll_enable(dev);
729 static int i915_resume_legacy(struct drm_device *dev)
731 i915_resume_early(dev);
738 * i915_reset - reset chip after a hang
739 * @dev: drm device to reset
741 * Reset the chip. Useful if a hang is detected. Returns zero on successful
742 * reset or otherwise an error code.
744 * Procedure is fairly simple:
745 * - reset the chip using the reset reg
746 * - re-init context state
747 * - re-init hardware status page
748 * - re-init ring buffer
749 * - re-init interrupt state
752 int i915_reset(struct drm_device *dev)
754 struct drm_i915_private *dev_priv = dev->dev_private;
761 mutex_lock(&dev->struct_mutex);
765 simulated = dev_priv->gpu_error.stop_rings != 0;
767 ret = intel_gpu_reset(dev);
769 /* Also reset the gpu hangman. */
771 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
772 dev_priv->gpu_error.stop_rings = 0;
773 if (ret == -ENODEV) {
774 DRM_INFO("Reset not implemented, but ignoring "
775 "error for simulated gpu hangs\n");
781 DRM_ERROR("Failed to reset chip: %i\n", ret);
782 mutex_unlock(&dev->struct_mutex);
786 /* Ok, now get things going again... */
789 * Everything depends on having the GTT running, so we need to start
790 * there. Fortunately we don't need to do this unless we reset the
791 * chip at a PCI level.
793 * Next we need to restore the context, but we don't use those
796 * Ring buffer needs to be re-initialized in the KMS case, or if X
797 * was running at the time of the reset (i.e. we weren't VT
800 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
801 !dev_priv->ums.mm_suspended) {
802 dev_priv->ums.mm_suspended = 0;
804 ret = i915_gem_init_hw(dev);
805 mutex_unlock(&dev->struct_mutex);
807 DRM_ERROR("Failed hw init on reset %d\n", ret);
812 * FIXME: This races pretty badly against concurrent holders of
813 * ring interrupts. This is possible since we've started to drop
814 * dev->struct_mutex in select places when waiting for the gpu.
818 * rps/rc6 re-init is necessary to restore state lost after the
819 * reset and the re-install of gt irqs. Skip for ironlake per
820 * previous concerns that it doesn't respond well to some forms
821 * of re-init after reset.
823 if (INTEL_INFO(dev)->gen > 5)
824 intel_reset_gt_powersave(dev);
828 mutex_unlock(&dev->struct_mutex);
834 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
836 struct intel_device_info *intel_info =
837 (struct intel_device_info *) ent->driver_data;
839 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
840 DRM_INFO("This hardware requires preliminary hardware support.\n"
841 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
845 /* Only bind to function 0 of the device. Early generations
846 * used function 1 as a placeholder for multi-head. This causes
847 * us confusion instead, especially on the systems where both
848 * functions have the same PCI-ID!
850 if (PCI_FUNC(pdev->devfn))
853 driver.driver_features &= ~(DRIVER_USE_AGP);
855 return drm_get_pci_dev(pdev, ent, &driver);
859 i915_pci_remove(struct pci_dev *pdev)
861 struct drm_device *dev = pci_get_drvdata(pdev);
866 static int i915_pm_suspend(struct device *dev)
868 struct pci_dev *pdev = to_pci_dev(dev);
869 struct drm_device *drm_dev = pci_get_drvdata(pdev);
871 if (!drm_dev || !drm_dev->dev_private) {
872 dev_err(dev, "DRM not initialized, aborting suspend.\n");
876 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
879 return i915_drm_freeze(drm_dev);
882 static int i915_pm_suspend_late(struct device *dev)
884 struct pci_dev *pdev = to_pci_dev(dev);
885 struct drm_device *drm_dev = pci_get_drvdata(pdev);
886 struct drm_i915_private *dev_priv = drm_dev->dev_private;
889 * We have a suspedn ordering issue with the snd-hda driver also
890 * requiring our device to be power up. Due to the lack of a
891 * parent/child relationship we currently solve this with an late
894 * FIXME: This should be solved with a special hdmi sink device or
895 * similar so that power domains can be employed.
897 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
900 if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev))
901 hsw_enable_pc8(dev_priv);
903 pci_disable_device(pdev);
904 pci_set_power_state(pdev, PCI_D3hot);
909 static int i915_pm_resume_early(struct device *dev)
911 struct pci_dev *pdev = to_pci_dev(dev);
912 struct drm_device *drm_dev = pci_get_drvdata(pdev);
914 return i915_resume_early(drm_dev);
917 static int i915_pm_resume(struct device *dev)
919 struct pci_dev *pdev = to_pci_dev(dev);
920 struct drm_device *drm_dev = pci_get_drvdata(pdev);
922 return i915_resume(drm_dev);
925 static int i915_pm_freeze(struct device *dev)
927 struct pci_dev *pdev = to_pci_dev(dev);
928 struct drm_device *drm_dev = pci_get_drvdata(pdev);
930 if (!drm_dev || !drm_dev->dev_private) {
931 dev_err(dev, "DRM not initialized, aborting suspend.\n");
935 return i915_drm_freeze(drm_dev);
938 static int i915_pm_thaw_early(struct device *dev)
940 struct pci_dev *pdev = to_pci_dev(dev);
941 struct drm_device *drm_dev = pci_get_drvdata(pdev);
943 return i915_drm_thaw_early(drm_dev);
946 static int i915_pm_thaw(struct device *dev)
948 struct pci_dev *pdev = to_pci_dev(dev);
949 struct drm_device *drm_dev = pci_get_drvdata(pdev);
951 return i915_drm_thaw(drm_dev);
954 static int i915_pm_poweroff(struct device *dev)
956 struct pci_dev *pdev = to_pci_dev(dev);
957 struct drm_device *drm_dev = pci_get_drvdata(pdev);
959 return i915_drm_freeze(drm_dev);
962 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
964 hsw_enable_pc8(dev_priv);
969 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
971 struct drm_device *dev = dev_priv->dev;
973 intel_init_pch_refclk(dev);
978 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
980 hsw_disable_pc8(dev_priv);
986 * Save all Gunit registers that may be lost after a D3 and a subsequent
987 * S0i[R123] transition. The list of registers needing a save/restore is
988 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
989 * registers in the following way:
990 * - Driver: saved/restored by the driver
991 * - Punit : saved/restored by the Punit firmware
992 * - No, w/o marking: no need to save/restore, since the register is R/O or
993 * used internally by the HW in a way that doesn't depend
994 * keeping the content across a suspend/resume.
995 * - Debug : used for debugging
997 * We save/restore all registers marked with 'Driver', with the following
999 * - Registers out of use, including also registers marked with 'Debug'.
1000 * These have no effect on the driver's operation, so we don't save/restore
1001 * them to reduce the overhead.
1002 * - Registers that are fully setup by an initialization function called from
1003 * the resume path. For example many clock gating and RPS/RC6 registers.
1004 * - Registers that provide the right functionality with their reset defaults.
1006 * TODO: Except for registers that based on the above 3 criteria can be safely
1007 * ignored, we save/restore all others, practically treating the HW context as
1008 * a black-box for the driver. Further investigation is needed to reduce the
1009 * saved/restored registers even further, by following the same 3 criteria.
1011 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1013 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1016 /* GAM 0x4000-0x4770 */
1017 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1018 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1019 s->arb_mode = I915_READ(ARB_MODE);
1020 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1021 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1023 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1024 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1026 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1027 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1029 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1030 s->ecochk = I915_READ(GAM_ECOCHK);
1031 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1032 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1034 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1036 /* MBC 0x9024-0x91D0, 0x8500 */
1037 s->g3dctl = I915_READ(VLV_G3DCTL);
1038 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1039 s->mbctl = I915_READ(GEN6_MBCTL);
1041 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1042 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1043 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1044 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1045 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1046 s->rstctl = I915_READ(GEN6_RSTCTL);
1047 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1049 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1050 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1051 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1052 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1053 s->ecobus = I915_READ(ECOBUS);
1054 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1055 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1056 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1057 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1058 s->rcedata = I915_READ(VLV_RCEDATA);
1059 s->spare2gh = I915_READ(VLV_SPAREG2H);
1061 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1062 s->gt_imr = I915_READ(GTIMR);
1063 s->gt_ier = I915_READ(GTIER);
1064 s->pm_imr = I915_READ(GEN6_PMIMR);
1065 s->pm_ier = I915_READ(GEN6_PMIER);
1067 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1068 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1070 /* GT SA CZ domain, 0x100000-0x138124 */
1071 s->tilectl = I915_READ(TILECTL);
1072 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1073 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1074 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1075 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1077 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1078 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1079 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1080 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1083 * Not saving any of:
1084 * DFT, 0x9800-0x9EC0
1085 * SARB, 0xB000-0xB1FC
1086 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1091 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1093 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1097 /* GAM 0x4000-0x4770 */
1098 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1099 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1100 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1101 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1102 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1104 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1105 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1107 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1108 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1110 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1111 I915_WRITE(GAM_ECOCHK, s->ecochk);
1112 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1113 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1115 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1117 /* MBC 0x9024-0x91D0, 0x8500 */
1118 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1119 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1120 I915_WRITE(GEN6_MBCTL, s->mbctl);
1122 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1123 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1124 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1125 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1126 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1127 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1128 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1130 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1131 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1132 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1133 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1134 I915_WRITE(ECOBUS, s->ecobus);
1135 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1136 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1137 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1138 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1139 I915_WRITE(VLV_RCEDATA, s->rcedata);
1140 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1142 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1143 I915_WRITE(GTIMR, s->gt_imr);
1144 I915_WRITE(GTIER, s->gt_ier);
1145 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1146 I915_WRITE(GEN6_PMIER, s->pm_ier);
1148 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1149 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1151 /* GT SA CZ domain, 0x100000-0x138124 */
1152 I915_WRITE(TILECTL, s->tilectl);
1153 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1155 * Preserve the GT allow wake and GFX force clock bit, they are not
1156 * be restored, as they are used to control the s0ix suspend/resume
1157 * sequence by the caller.
1159 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1160 val &= VLV_GTLC_ALLOWWAKEREQ;
1161 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1162 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1164 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1165 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1166 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1167 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1169 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1171 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1172 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1173 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1174 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1177 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1182 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1183 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1185 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1186 /* Wait for a previous force-off to settle */
1188 err = wait_for(!COND, 20);
1190 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1191 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1196 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1197 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1199 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1200 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1205 err = wait_for(COND, 20);
1207 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1208 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1214 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1219 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1220 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1222 val |= VLV_GTLC_ALLOWWAKEREQ;
1223 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1224 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1226 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1228 err = wait_for(COND, 1);
1230 DRM_ERROR("timeout disabling GT waking\n");
1235 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1242 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1243 val = wait_for_on ? mask : 0;
1244 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1248 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1249 wait_for_on ? "on" : "off",
1250 I915_READ(VLV_GTLC_PW_STATUS));
1253 * RC6 transitioning can be delayed up to 2 msec (see
1254 * valleyview_enable_rps), use 3 msec for safety.
1256 err = wait_for(COND, 3);
1258 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1259 wait_for_on ? "on" : "off");
1265 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1267 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1270 DRM_ERROR("GT register access while GT waking disabled\n");
1271 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1274 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1280 * Bspec defines the following GT well on flags as debug only, so
1281 * don't treat them as hard failures.
1283 (void)vlv_wait_for_gt_wells(dev_priv, false);
1285 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1286 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1288 vlv_check_no_gt_access(dev_priv);
1290 err = vlv_force_gfx_clock(dev_priv, true);
1294 err = vlv_allow_gt_wake(dev_priv, false);
1297 vlv_save_gunit_s0ix_state(dev_priv);
1299 err = vlv_force_gfx_clock(dev_priv, false);
1306 /* For safety always re-enable waking and disable gfx clock forcing */
1307 vlv_allow_gt_wake(dev_priv, true);
1309 vlv_force_gfx_clock(dev_priv, false);
1314 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1316 struct drm_device *dev = dev_priv->dev;
1321 * If any of the steps fail just try to continue, that's the best we
1322 * can do at this point. Return the first error code (which will also
1323 * leave RPM permanently disabled).
1325 ret = vlv_force_gfx_clock(dev_priv, true);
1327 vlv_restore_gunit_s0ix_state(dev_priv);
1329 err = vlv_allow_gt_wake(dev_priv, true);
1333 err = vlv_force_gfx_clock(dev_priv, false);
1337 vlv_check_no_gt_access(dev_priv);
1339 intel_init_clock_gating(dev);
1340 i915_gem_restore_fences(dev);
1345 static int intel_runtime_suspend(struct device *device)
1347 struct pci_dev *pdev = to_pci_dev(device);
1348 struct drm_device *dev = pci_get_drvdata(pdev);
1349 struct drm_i915_private *dev_priv = dev->dev_private;
1352 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1355 WARN_ON(!HAS_RUNTIME_PM(dev));
1356 assert_force_wake_inactive(dev_priv);
1358 DRM_DEBUG_KMS("Suspending device\n");
1361 * We could deadlock here in case another thread holding struct_mutex
1362 * calls RPM suspend concurrently, since the RPM suspend will wait
1363 * first for this RPM suspend to finish. In this case the concurrent
1364 * RPM resume will be followed by its RPM suspend counterpart. Still
1365 * for consistency return -EAGAIN, which will reschedule this suspend.
1367 if (!mutex_trylock(&dev->struct_mutex)) {
1368 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1370 * Bump the expiration timestamp, otherwise the suspend won't
1373 pm_runtime_mark_last_busy(device);
1378 * We are safe here against re-faults, since the fault handler takes
1381 i915_gem_release_all_mmaps(dev_priv);
1382 mutex_unlock(&dev->struct_mutex);
1385 * rps.work can't be rearmed here, since we get here only after making
1386 * sure the GPU is idle and the RPS freq is set to the minimum. See
1387 * intel_mark_idle().
1389 cancel_work_sync(&dev_priv->rps.work);
1390 intel_runtime_pm_disable_interrupts(dev);
1394 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1395 ret = hsw_runtime_suspend(dev_priv);
1396 } else if (IS_VALLEYVIEW(dev)) {
1397 ret = vlv_runtime_suspend(dev_priv);
1404 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1405 intel_runtime_pm_restore_interrupts(dev);
1410 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1411 dev_priv->pm.suspended = true;
1414 * current versions of firmware which depend on this opregion
1415 * notification have repurposed the D1 definition to mean
1416 * "runtime suspended" vs. what you would normally expect (D3)
1417 * to distinguish it from notifications that might be sent
1418 * via the suspend path.
1420 intel_opregion_notify_adapter(dev, PCI_D1);
1422 DRM_DEBUG_KMS("Device suspended\n");
1426 static int intel_runtime_resume(struct device *device)
1428 struct pci_dev *pdev = to_pci_dev(device);
1429 struct drm_device *dev = pci_get_drvdata(pdev);
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1433 WARN_ON(!HAS_RUNTIME_PM(dev));
1435 DRM_DEBUG_KMS("Resuming device\n");
1437 intel_opregion_notify_adapter(dev, PCI_D0);
1438 dev_priv->pm.suspended = false;
1441 ret = snb_runtime_resume(dev_priv);
1442 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1443 ret = hsw_runtime_resume(dev_priv);
1444 } else if (IS_VALLEYVIEW(dev)) {
1445 ret = vlv_runtime_resume(dev_priv);
1452 * No point of rolling back things in case of an error, as the best
1453 * we can do is to hope that things will still work (and disable RPM).
1455 i915_gem_init_swizzling(dev);
1456 gen6_update_ring_freq(dev);
1458 intel_runtime_pm_restore_interrupts(dev);
1459 intel_reset_gt_powersave(dev);
1462 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1464 DRM_DEBUG_KMS("Device resumed\n");
1469 static const struct dev_pm_ops i915_pm_ops = {
1470 .suspend = i915_pm_suspend,
1471 .suspend_late = i915_pm_suspend_late,
1472 .resume_early = i915_pm_resume_early,
1473 .resume = i915_pm_resume,
1474 .freeze = i915_pm_freeze,
1475 .thaw_early = i915_pm_thaw_early,
1476 .thaw = i915_pm_thaw,
1477 .poweroff = i915_pm_poweroff,
1478 .restore_early = i915_pm_resume_early,
1479 .restore = i915_pm_resume,
1480 .runtime_suspend = intel_runtime_suspend,
1481 .runtime_resume = intel_runtime_resume,
1484 static const struct vm_operations_struct i915_gem_vm_ops = {
1485 .fault = i915_gem_fault,
1486 .open = drm_gem_vm_open,
1487 .close = drm_gem_vm_close,
1490 static const struct file_operations i915_driver_fops = {
1491 .owner = THIS_MODULE,
1493 .release = drm_release,
1494 .unlocked_ioctl = drm_ioctl,
1495 .mmap = drm_gem_mmap,
1498 #ifdef CONFIG_COMPAT
1499 .compat_ioctl = i915_compat_ioctl,
1501 .llseek = noop_llseek,
1504 static struct drm_driver driver = {
1505 /* Don't use MTRRs here; the Xserver or userspace app should
1506 * deal with them for Intel hardware.
1510 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1512 .load = i915_driver_load,
1513 .unload = i915_driver_unload,
1514 .open = i915_driver_open,
1515 .lastclose = i915_driver_lastclose,
1516 .preclose = i915_driver_preclose,
1517 .postclose = i915_driver_postclose,
1519 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1520 .suspend = i915_suspend,
1521 .resume = i915_resume_legacy,
1523 .device_is_agp = i915_driver_device_is_agp,
1524 .master_create = i915_master_create,
1525 .master_destroy = i915_master_destroy,
1526 #if defined(CONFIG_DEBUG_FS)
1527 .debugfs_init = i915_debugfs_init,
1528 .debugfs_cleanup = i915_debugfs_cleanup,
1530 .gem_free_object = i915_gem_free_object,
1531 .gem_vm_ops = &i915_gem_vm_ops,
1533 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1534 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1535 .gem_prime_export = i915_gem_prime_export,
1536 .gem_prime_import = i915_gem_prime_import,
1538 .dumb_create = i915_gem_dumb_create,
1539 .dumb_map_offset = i915_gem_mmap_gtt,
1540 .dumb_destroy = drm_gem_dumb_destroy,
1541 .ioctls = i915_ioctls,
1542 .fops = &i915_driver_fops,
1543 .name = DRIVER_NAME,
1544 .desc = DRIVER_DESC,
1545 .date = DRIVER_DATE,
1546 .major = DRIVER_MAJOR,
1547 .minor = DRIVER_MINOR,
1548 .patchlevel = DRIVER_PATCHLEVEL,
1551 static struct pci_driver i915_pci_driver = {
1552 .name = DRIVER_NAME,
1553 .id_table = pciidlist,
1554 .probe = i915_pci_probe,
1555 .remove = i915_pci_remove,
1556 .driver.pm = &i915_pm_ops,
1559 static int __init i915_init(void)
1561 driver.num_ioctls = i915_max_ioctl;
1564 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1565 * explicitly disabled with the module pararmeter.
1567 * Otherwise, just follow the parameter (defaulting to off).
1569 * Allow optional vga_text_mode_force boot option to override
1570 * the default behavior.
1572 #if defined(CONFIG_DRM_I915_KMS)
1573 if (i915.modeset != 0)
1574 driver.driver_features |= DRIVER_MODESET;
1576 if (i915.modeset == 1)
1577 driver.driver_features |= DRIVER_MODESET;
1579 #ifdef CONFIG_VGA_CONSOLE
1580 if (vgacon_text_force() && i915.modeset == -1)
1581 driver.driver_features &= ~DRIVER_MODESET;
1584 if (!(driver.driver_features & DRIVER_MODESET)) {
1585 driver.get_vblank_timestamp = NULL;
1586 #ifndef CONFIG_DRM_I915_UMS
1587 /* Silently fail loading to not upset userspace. */
1588 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1593 return drm_pci_init(&driver, &i915_pci_driver);
1596 static void __exit i915_exit(void)
1598 #ifndef CONFIG_DRM_I915_UMS
1599 if (!(driver.driver_features & DRIVER_MODESET))
1600 return; /* Never loaded a driver. */
1603 drm_pci_exit(&driver, &i915_pci_driver);
1606 module_init(i915_init);
1607 module_exit(i915_exit);
1609 MODULE_AUTHOR(DRIVER_AUTHOR);
1610 MODULE_DESCRIPTION(DRIVER_DESC);
1611 MODULE_LICENSE("GPL and additional rights");