drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/string_helpers.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42
  43 #include <drm/drm_aperture.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_bw.h"
  51 #include "display/intel_cdclk.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dmc.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dpt.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pch_refclk.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64 #include "display/skl_watermark.h"
  65
  66 #include "gem/i915_gem_context.h"
  67 #include "gem/i915_gem_create.h"
  68 #include "gem/i915_gem_dmabuf.h"
  69 #include "gem/i915_gem_ioctls.h"
  70 #include "gem/i915_gem_mman.h"
  71 #include "gem/i915_gem_pm.h"
  72 #include "gt/intel_gt.h"
  73 #include "gt/intel_gt_pm.h"
  74 #include "gt/intel_rc6.h"
  75
  76 #include "pxp/intel_pxp_pm.h"
  77
  78 #include "i915_file_private.h"
  79 #include "i915_debugfs.h"
  80 #include "i915_driver.h"
  81 #include "i915_drm_client.h"
  82 #include "i915_drv.h"
  83 #include "i915_getparam.h"
  84 #include "i915_hwmon.h"
  85 #include "i915_ioc32.h"
  86 #include "i915_ioctl.h"
  87 #include "i915_irq.h"
  88 #include "i915_memcpy.h"
  89 #include "i915_perf.h"
  90 #include "i915_query.h"
  91 #include "i915_suspend.h"
  92 #include "i915_switcheroo.h"
  93 #include "i915_sysfs.h"
  94 #include "i915_utils.h"
  95 #include "i915_vgpu.h"
  96 #include "intel_dram.h"
  97 #include "intel_gvt.h"
  98 #include "intel_memory_region.h"
  99 #include "intel_pci_config.h"
 100 #include "intel_pcode.h"
 101 #include "intel_pm.h"
 102 #include "intel_region_ttm.h"
 103 #include "vlv_suspend.h"
 104
 105 /* Intel Rapid Start Technology ACPI device name */
 106 static const char irst_name[] = "INT3392";
 107
 108 static const struct drm_driver i915_drm_driver;
 109
 110 static void i915_release_bridge_dev(struct drm_device *dev,
 111                                     void *bridge)
 112 {
 113         pci_dev_put(bridge);
 114 }
 115
 116 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 117 {
 118         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
 119
 120         dev_priv->bridge_dev =
 121                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 122         if (!dev_priv->bridge_dev) {
 123                 drm_err(&dev_priv->drm, "bridge device not found\n");
 124                 return -EIO;
 125         }
 126
 127         return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,
 128                                         dev_priv->bridge_dev);
 129 }
 130
 131 /* Allocate space for the MCH regs if needed, return nonzero on error */
 132 static int
 133 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 134 {
 135         int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 136         u32 temp_lo, temp_hi = 0;
 137         u64 mchbar_addr;
 138         int ret;
 139
 140         if (GRAPHICS_VER(dev_priv) >= 4)
 141                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 142         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 143         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 144
 145         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 146 #ifdef CONFIG_PNP
 147         if (mchbar_addr &&
 148             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 149                 return 0;
 150 #endif
 151
 152         /* Get some space for it */
 153         dev_priv->mch_res.name = "i915 MCHBAR";
 154         dev_priv->mch_res.flags = IORESOURCE_MEM;
 155         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 156                                      &dev_priv->mch_res,
 157                                      MCHBAR_SIZE, MCHBAR_SIZE,
 158                                      PCIBIOS_MIN_MEM,
 159                                      0, pcibios_align_resource,
 160                                      dev_priv->bridge_dev);
 161         if (ret) {
 162                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 163                 dev_priv->mch_res.start = 0;
 164                 return ret;
 165         }
 166
 167         if (GRAPHICS_VER(dev_priv) >= 4)
 168                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 169                                        upper_32_bits(dev_priv->mch_res.start));
 170
 171         pci_write_config_dword(dev_priv->bridge_dev, reg,
 172                                lower_32_bits(dev_priv->mch_res.start));
 173         return 0;
 174 }
 175
 176 /* Setup MCHBAR if possible, return true if we should disable it again */
 177 static void
 178 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 179 {
 180         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 181         u32 temp;
 182         bool enabled;
 183
 184         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 185                 return;
 186
 187         dev_priv->mchbar_need_disable = false;
 188
 189         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 190                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 191                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 192         } else {
 193                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 194                 enabled = temp & 1;
 195         }
 196
 197         /* If it's already enabled, don't have to do anything */
 198         if (enabled)
 199                 return;
 200
 201         if (intel_alloc_mchbar_resource(dev_priv))
 202                 return;
 203
 204         dev_priv->mchbar_need_disable = true;
 205
 206         /* Space is allocated or reserved, so enable it. */
 207         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 208                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 209                                        temp | DEVEN_MCHBAR_EN);
 210         } else {
 211                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 212                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 213         }
 214 }
 215
 216 static void
 217 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 218 {
 219         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 220
 221         if (dev_priv->mchbar_need_disable) {
 222                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 223                         u32 deven_val;
 224
 225                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 226                                               &deven_val);
 227                         deven_val &= ~DEVEN_MCHBAR_EN;
 228                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 229                                                deven_val);
 230                 } else {
 231                         u32 mchbar_val;
 232
 233                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 234                                               &mchbar_val);
 235                         mchbar_val &= ~1;
 236                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 237                                                mchbar_val);
 238                 }
 239         }
 240
 241         if (dev_priv->mch_res.start)
 242                 release_resource(&dev_priv->mch_res);
 243 }
 244
 245 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 246 {
 247         /*
 248          * The i915 workqueue is primarily used for batched retirement of
 249          * requests (and thus managing bo) once the task has been completed
 250          * by the GPU. i915_retire_requests() is called directly when we
 251          * need high-priority retirement, such as waiting for an explicit
 252          * bo.
 253          *
 254          * It is also used for periodic low-priority events, such as
 255          * idle-timers and recording error state.
 256          *
 257          * All tasks on the workqueue are expected to acquire the dev mutex
 258          * so there is no point in running more than one instance of the
 259          * workqueue at any time.  Use an ordered one.
 260          */
 261         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 262         if (dev_priv->wq == NULL)
 263                 goto out_err;
 264
 265         dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 266         if (dev_priv->display.hotplug.dp_wq == NULL)
 267                 goto out_free_wq;
 268
 269         return 0;
 270
 271 out_free_wq:
 272         destroy_workqueue(dev_priv->wq);
 273 out_err:
 274         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 275
 276         return -ENOMEM;
 277 }
 278
 279 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 280 {
 281         destroy_workqueue(dev_priv->display.hotplug.dp_wq);
 282         destroy_workqueue(dev_priv->wq);
 283 }
 284
 285 /*
 286  * We don't keep the workarounds for pre-production hardware, so we expect our
 287  * driver to fail on these machines in one way or another. A little warning on
 288  * dmesg may help both the user and the bug triagers.
 289  *
 290  * Our policy for removing pre-production workarounds is to keep the
 291  * current gen workarounds as a guide to the bring-up of the next gen
 292  * (workarounds have a habit of persisting!). Anything older than that
 293  * should be removed along with the complications they introduce.
 294  */
 295 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 296 {
 297         bool pre = false;
 298
 299         pre |= IS_HSW_EARLY_SDV(dev_priv);
 300         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 301         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 302         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 303         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 304         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 305
 306         if (pre) {
 307                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 308                           "It may not be fully functional.\n");
 309                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 310         }
 311 }
 312
 313 static void sanitize_gpu(struct drm_i915_private *i915)
 314 {
 315         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
 316                 struct intel_gt *gt;
 317                 unsigned int i;
 318
 319                 for_each_gt(gt, i915, i)
 320                         __intel_gt_reset(gt, ALL_ENGINES);
 321         }
 322 }
 323
 324 /**
 325  * i915_driver_early_probe - setup state not requiring device access
 326  * @dev_priv: device private
 327  *
 328  * Initialize everything that is a "SW-only" state, that is state not
 329  * requiring accessing the device or exposing the driver via kernel internal
 330  * or userspace interfaces. Example steps belonging here: lock initialization,
 331  * system memory allocation, setting up device specific attributes and
 332  * function hooks not requiring accessing the device.
 333  */
 334 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 335 {
 336         int ret = 0;
 337
 338         if (i915_inject_probe_failure(dev_priv))
 339                 return -ENODEV;
 340
 341         intel_device_info_runtime_init_early(dev_priv);
 342
 343         intel_step_init(dev_priv);
 344
 345         intel_uncore_mmio_debug_init_early(dev_priv);
 346
 347         spin_lock_init(&dev_priv->irq_lock);
 348         spin_lock_init(&dev_priv->gpu_error.lock);
 349         mutex_init(&dev_priv->display.backlight.lock);
 350
 351         mutex_init(&dev_priv->sb_lock);
 352         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 353
 354         mutex_init(&dev_priv->display.audio.mutex);
 355         mutex_init(&dev_priv->display.wm.wm_mutex);
 356         mutex_init(&dev_priv->display.pps.mutex);
 357         mutex_init(&dev_priv->display.hdcp.comp_mutex);
 358         spin_lock_init(&dev_priv->display.dkl.phy_lock);
 359
 360         i915_memcpy_init_early(dev_priv);
 361         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 362
 363         ret = i915_workqueues_init(dev_priv);
 364         if (ret < 0)
 365                 return ret;
 366
 367         ret = vlv_suspend_init(dev_priv);
 368         if (ret < 0)
 369                 goto err_workqueues;
 370
 371         ret = intel_region_ttm_device_init(dev_priv);
 372         if (ret)
 373                 goto err_ttm;
 374
 375         intel_wopcm_init_early(&dev_priv->wopcm);
 376
 377         ret = intel_root_gt_init_early(dev_priv);
 378         if (ret < 0)
 379                 goto err_rootgt;
 380
 381         i915_drm_clients_init(&dev_priv->clients, dev_priv);
 382
 383         i915_gem_init_early(dev_priv);
 384
 385         /* This must be called before any calls to HAS_PCH_* */
 386         intel_detect_pch(dev_priv);
 387
 388         intel_pm_setup(dev_priv);
 389         ret = intel_power_domains_init(dev_priv);
 390         if (ret < 0)
 391                 goto err_gem;
 392         intel_irq_init(dev_priv);
 393         intel_init_display_hooks(dev_priv);
 394         intel_init_clock_gating_hooks(dev_priv);
 395
 396         intel_detect_preproduction_hw(dev_priv);
 397
 398         return 0;
 399
 400 err_gem:
 401         i915_gem_cleanup_early(dev_priv);
 402         intel_gt_driver_late_release_all(dev_priv);
 403         i915_drm_clients_fini(&dev_priv->clients);
 404 err_rootgt:
 405         intel_region_ttm_device_fini(dev_priv);
 406 err_ttm:
 407         vlv_suspend_cleanup(dev_priv);
 408 err_workqueues:
 409         i915_workqueues_cleanup(dev_priv);
 410         return ret;
 411 }
 412
 413 /**
 414  * i915_driver_late_release - cleanup the setup done in
 415  *                             i915_driver_early_probe()
 416  * @dev_priv: device private
 417  */
 418 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 419 {
 420         intel_irq_fini(dev_priv);
 421         intel_power_domains_cleanup(dev_priv);
 422         i915_gem_cleanup_early(dev_priv);
 423         intel_gt_driver_late_release_all(dev_priv);
 424         i915_drm_clients_fini(&dev_priv->clients);
 425         intel_region_ttm_device_fini(dev_priv);
 426         vlv_suspend_cleanup(dev_priv);
 427         i915_workqueues_cleanup(dev_priv);
 428
 429         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 430         mutex_destroy(&dev_priv->sb_lock);
 431
 432         i915_params_free(&dev_priv->params);
 433 }
 434
 435 /**
 436  * i915_driver_mmio_probe - setup device MMIO
 437  * @dev_priv: device private
 438  *
 439  * Setup minimal device state necessary for MMIO accesses later in the
 440  * initialization sequence. The setup here should avoid any other device-wide
 441  * side effects or exposing the driver via kernel internal or user space
 442  * interfaces.
 443  */
 444 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 445 {
 446         struct intel_gt *gt;
 447         int ret, i;
 448
 449         if (i915_inject_probe_failure(dev_priv))
 450                 return -ENODEV;
 451
 452         ret = i915_get_bridge_dev(dev_priv);
 453         if (ret < 0)
 454                 return ret;
 455
 456         for_each_gt(gt, dev_priv, i) {
 457                 ret = intel_uncore_init_mmio(gt->uncore);
 458                 if (ret)
 459                         return ret;
 460
 461                 ret = drmm_add_action_or_reset(&dev_priv->drm,
 462                                                intel_uncore_fini_mmio,
 463                                                gt->uncore);
 464                 if (ret)
 465                         return ret;
 466         }
 467
 468         /* Try to make sure MCHBAR is enabled before poking at it */
 469         intel_setup_mchbar(dev_priv);
 470         intel_device_info_runtime_init(dev_priv);
 471
 472         for_each_gt(gt, dev_priv, i) {
 473                 ret = intel_gt_init_mmio(gt);
 474                 if (ret)
 475                         goto err_uncore;
 476         }
 477
 478         /* As early as possible, scrub existing GPU state before clobbering */
 479         sanitize_gpu(dev_priv);
 480
 481         return 0;
 482
 483 err_uncore:
 484         intel_teardown_mchbar(dev_priv);
 485
 486         return ret;
 487 }
 488
 489 /**
 490  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 491  * @dev_priv: device private
 492  */
 493 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 494 {
 495         intel_teardown_mchbar(dev_priv);
 496 }
 497
 498 /**
 499  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 500  * platform
 501  * @i915: valid i915 instance
 502  *
 503  * Set the dma max segment size, device and coherent masks.  The dma mask set
 504  * needs to occur before i915_ggtt_probe_hw.
 505  *
 506  * A couple of platforms have special needs.  Address them as well.
 507  *
 508  */
 509 static int i915_set_dma_info(struct drm_i915_private *i915)
 510 {
 511         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 512         int ret;
 513
 514         GEM_BUG_ON(!mask_size);
 515
 516         /*
 517          * We don't have a max segment size, so set it to the max so sg's
 518          * debugging layer doesn't complain
 519          */
 520         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 521
 522         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 523         if (ret)
 524                 goto mask_err;
 525
 526         /* overlay on gen2 is broken and can't address above 1G */
 527         if (GRAPHICS_VER(i915) == 2)
 528                 mask_size = 30;
 529
 530         /*
 531          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 532          * using 32bit addressing, overwriting memory if HWS is located
 533          * above 4GB.
 534          *
 535          * The documentation also mentions an issue with undefined
 536          * behaviour if any general state is accessed within a page above 4GB,
 537          * which also needs to be handled carefully.
 538          */
 539         if (IS_I965G(i915) || IS_I965GM(i915))
 540                 mask_size = 32;
 541
 542         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 543         if (ret)
 544                 goto mask_err;
 545
 546         return 0;
 547
 548 mask_err:
 549         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 550         return ret;
 551 }
 552
 553 static int i915_pcode_init(struct drm_i915_private *i915)
 554 {
 555         struct intel_gt *gt;
 556         int id, ret;
 557
 558         for_each_gt(gt, i915, id) {
 559                 ret = intel_pcode_init(gt->uncore);
 560                 if (ret) {
 561                         drm_err(&gt->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
 562                         return ret;
 563                 }
 564         }
 565
 566         return 0;
 567 }
 568
 569 /**
 570  * i915_driver_hw_probe - setup state requiring device access
 571  * @dev_priv: device private
 572  *
 573  * Setup state that requires accessing the device, but doesn't require
 574  * exposing the driver via kernel internal or userspace interfaces.
 575  */
 576 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 577 {
 578         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 579         struct pci_dev *root_pdev;
 580         int ret;
 581
 582         if (i915_inject_probe_failure(dev_priv))
 583                 return -ENODEV;
 584
 585         if (HAS_PPGTT(dev_priv)) {
 586                 if (intel_vgpu_active(dev_priv) &&
 587                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 588                         i915_report_error(dev_priv,
 589                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 590                         return -ENXIO;
 591                 }
 592         }
 593
 594         if (HAS_EXECLISTS(dev_priv)) {
 595                 /*
 596                  * Older GVT emulation depends upon intercepting CSB mmio,
 597                  * which we no longer use, preferring to use the HWSP cache
 598                  * instead.
 599                  */
 600                 if (intel_vgpu_active(dev_priv) &&
 601                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 602                         i915_report_error(dev_priv,
 603                                           "old vGPU host found, support for HWSP emulation required\n");
 604                         return -ENXIO;
 605                 }
 606         }
 607
 608         /* needs to be done before ggtt probe */
 609         intel_dram_edram_detect(dev_priv);
 610
 611         ret = i915_set_dma_info(dev_priv);
 612         if (ret)
 613                 return ret;
 614
 615         i915_perf_init(dev_priv);
 616
 617         ret = intel_gt_assign_ggtt(to_gt(dev_priv));
 618         if (ret)
 619                 goto err_perf;
 620
 621         ret = i915_ggtt_probe_hw(dev_priv);
 622         if (ret)
 623                 goto err_perf;
 624
 625         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 626         if (ret)
 627                 goto err_ggtt;
 628
 629         ret = i915_ggtt_init_hw(dev_priv);
 630         if (ret)
 631                 goto err_ggtt;
 632
 633         ret = intel_memory_regions_hw_probe(dev_priv);
 634         if (ret)
 635                 goto err_ggtt;
 636
 637         ret = intel_gt_tiles_init(dev_priv);
 638         if (ret)
 639                 goto err_mem_regions;
 640
 641         ret = i915_ggtt_enable_hw(dev_priv);
 642         if (ret) {
 643                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 644                 goto err_mem_regions;
 645         }
 646
 647         pci_set_master(pdev);
 648
 649         /* On the 945G/GM, the chipset reports the MSI capability on the
 650          * integrated graphics even though the support isn't actually there
 651          * according to the published specs.  It doesn't appear to function
 652          * correctly in testing on 945G.
 653          * This may be a side effect of MSI having been made available for PEG
 654          * and the registers being closely associated.
 655          *
 656          * According to chipset errata, on the 965GM, MSI interrupts may
 657          * be lost or delayed, and was defeatured. MSI interrupts seem to
 658          * get lost on g4x as well, and interrupt delivery seems to stay
 659          * properly dead afterwards. So we'll just disable them for all
 660          * pre-gen5 chipsets.
 661          *
 662          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 663          * interrupts even when in MSI mode. This results in spurious
 664          * interrupt warnings if the legacy irq no. is shared with another
 665          * device. The kernel then disables that interrupt source and so
 666          * prevents the other device from working properly.
 667          */
 668         if (GRAPHICS_VER(dev_priv) >= 5) {
 669                 if (pci_enable_msi(pdev) < 0)
 670                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 671         }
 672
 673         ret = intel_gvt_init(dev_priv);
 674         if (ret)
 675                 goto err_msi;
 676
 677         intel_opregion_setup(dev_priv);
 678
 679         ret = i915_pcode_init(dev_priv);
 680         if (ret)
 681                 goto err_msi;
 682
 683         /*
 684          * Fill the dram structure to get the system dram info. This will be
 685          * used for memory latency calculation.
 686          */
 687         intel_dram_detect(dev_priv);
 688
 689         intel_bw_init_hw(dev_priv);
 690
 691         /*
 692          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
 693          * This should be totally removed when we handle the pci states properly
 694          * on runtime PM and on s2idle cases.
 695          */
 696         root_pdev = pcie_find_root_port(pdev);
 697         if (root_pdev)
 698                 pci_d3cold_disable(root_pdev);
 699
 700         return 0;
 701
 702 err_msi:
 703         if (pdev->msi_enabled)
 704                 pci_disable_msi(pdev);
 705 err_mem_regions:
 706         intel_memory_regions_driver_release(dev_priv);
 707 err_ggtt:
 708         i915_ggtt_driver_release(dev_priv);
 709         i915_gem_drain_freed_objects(dev_priv);
 710         i915_ggtt_driver_late_release(dev_priv);
 711 err_perf:
 712         i915_perf_fini(dev_priv);
 713         return ret;
 714 }
 715
 716 /**
 717  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 718  * @dev_priv: device private
 719  */
 720 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 721 {
 722         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 723         struct pci_dev *root_pdev;
 724
 725         i915_perf_fini(dev_priv);
 726
 727         if (pdev->msi_enabled)
 728                 pci_disable_msi(pdev);
 729
 730         root_pdev = pcie_find_root_port(pdev);
 731         if (root_pdev)
 732                 pci_d3cold_enable(root_pdev);
 733 }
 734
 735 /**
 736  * i915_driver_register - register the driver with the rest of the system
 737  * @dev_priv: device private
 738  *
 739  * Perform any steps necessary to make the driver available via kernel
 740  * internal or userspace interfaces.
 741  */
 742 static void i915_driver_register(struct drm_i915_private *dev_priv)
 743 {
 744         struct intel_gt *gt;
 745         unsigned int i;
 746
 747         i915_gem_driver_register(dev_priv);
 748         i915_pmu_register(dev_priv);
 749
 750         intel_vgpu_register(dev_priv);
 751
 752         /* Reveal our presence to userspace */
 753         if (drm_dev_register(&dev_priv->drm, 0)) {
 754                 drm_err(&dev_priv->drm,
 755                         "Failed to register driver for userspace access!\n");
 756                 return;
 757         }
 758
 759         i915_debugfs_register(dev_priv);
 760         i915_setup_sysfs(dev_priv);
 761
 762         /* Depends on sysfs having been initialized */
 763         i915_perf_register(dev_priv);
 764
 765         for_each_gt(gt, dev_priv, i)
 766                 intel_gt_driver_register(gt);
 767
 768         i915_hwmon_register(dev_priv);
 769
 770         intel_display_driver_register(dev_priv);
 771
 772         intel_power_domains_enable(dev_priv);
 773         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 774
 775         intel_register_dsm_handler();
 776
 777         if (i915_switcheroo_register(dev_priv))
 778                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 779 }
 780
 781 /**
 782  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 783  * @dev_priv: device private
 784  */
 785 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 786 {
 787         struct intel_gt *gt;
 788         unsigned int i;
 789
 790         i915_switcheroo_unregister(dev_priv);
 791
 792         intel_unregister_dsm_handler();
 793
 794         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 795         intel_power_domains_disable(dev_priv);
 796
 797         intel_display_driver_unregister(dev_priv);
 798
 799         for_each_gt(gt, dev_priv, i)
 800                 intel_gt_driver_unregister(gt);
 801
 802         i915_hwmon_unregister(dev_priv);
 803
 804         i915_perf_unregister(dev_priv);
 805         i915_pmu_unregister(dev_priv);
 806
 807         i915_teardown_sysfs(dev_priv);
 808         drm_dev_unplug(&dev_priv->drm);
 809
 810         i915_gem_driver_unregister(dev_priv);
 811 }
 812
 813 void
 814 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 815 {
 816         drm_printf(p, "iommu: %s\n",
 817                    str_enabled_disabled(i915_vtd_active(i915)));
 818 }
 819
 820 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 821 {
 822         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 823                 struct drm_printer p = drm_debug_printer("i915 device info:");
 824                 struct intel_gt *gt;
 825                 unsigned int i;
 826
 827                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 828                            INTEL_DEVID(dev_priv),
 829                            INTEL_REVID(dev_priv),
 830                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 831                            intel_subplatform(RUNTIME_INFO(dev_priv),
 832                                              INTEL_INFO(dev_priv)->platform),
 833                            GRAPHICS_VER(dev_priv));
 834
 835                 intel_device_info_print(INTEL_INFO(dev_priv),
 836                                         RUNTIME_INFO(dev_priv), &p);
 837                 i915_print_iommu_status(dev_priv, &p);
 838                 for_each_gt(gt, dev_priv, i)
 839                         intel_gt_info_print(&gt->info, &p);
 840         }
 841
 842         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 843                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 844         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 845                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 846         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 847                 drm_info(&dev_priv->drm,
 848                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 849 }
 850
 851 static struct drm_i915_private *
 852 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 853 {
 854         const struct intel_device_info *match_info =
 855                 (struct intel_device_info *)ent->driver_data;
 856         struct intel_device_info *device_info;
 857         struct intel_runtime_info *runtime;
 858         struct drm_i915_private *i915;
 859
 860         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 861                                   struct drm_i915_private, drm);
 862         if (IS_ERR(i915))
 863                 return i915;
 864
 865         pci_set_drvdata(pdev, i915);
 866
 867         /* Device parameters start as a copy of module parameters. */
 868         i915_params_copy(&i915->params, &i915_modparams);
 869
 870         /* Setup the write-once "constant" device info */
 871         device_info = mkwrite_device_info(i915);
 872         memcpy(device_info, match_info, sizeof(*device_info));
 873
 874         /* Initialize initial runtime info from static const data and pdev. */
 875         runtime = RUNTIME_INFO(i915);
 876         memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
 877         runtime->device_id = pdev->device;
 878
 879         return i915;
 880 }
 881
 882 /**
 883  * i915_driver_probe - setup chip and create an initial config
 884  * @pdev: PCI device
 885  * @ent: matching PCI ID entry
 886  *
 887  * The driver probe routine has to do several things:
 888  *   - drive output discovery via intel_modeset_init()
 889  *   - initialize the memory manager
 890  *   - allocate initial config memory
 891  *   - setup the DRM framebuffer with the allocated memory
 892  */
 893 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 894 {
 895         struct drm_i915_private *i915;
 896         int ret;
 897
 898         i915 = i915_driver_create(pdev, ent);
 899         if (IS_ERR(i915))
 900                 return PTR_ERR(i915);
 901
 902         ret = pci_enable_device(pdev);
 903         if (ret)
 904                 goto out_fini;
 905
 906         ret = i915_driver_early_probe(i915);
 907         if (ret < 0)
 908                 goto out_pci_disable;
 909
 910         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 911
 912         intel_vgpu_detect(i915);
 913
 914         ret = intel_gt_probe_all(i915);
 915         if (ret < 0)
 916                 goto out_runtime_pm_put;
 917
 918         ret = i915_driver_mmio_probe(i915);
 919         if (ret < 0)
 920                 goto out_tiles_cleanup;
 921
 922         ret = i915_driver_hw_probe(i915);
 923         if (ret < 0)
 924                 goto out_cleanup_mmio;
 925
 926         ret = intel_modeset_init_noirq(i915);
 927         if (ret < 0)
 928                 goto out_cleanup_hw;
 929
 930         ret = intel_irq_install(i915);
 931         if (ret)
 932                 goto out_cleanup_modeset;
 933
 934         ret = intel_modeset_init_nogem(i915);
 935         if (ret)
 936                 goto out_cleanup_irq;
 937
 938         ret = i915_gem_init(i915);
 939         if (ret)
 940                 goto out_cleanup_modeset2;
 941
 942         ret = intel_modeset_init(i915);
 943         if (ret)
 944                 goto out_cleanup_gem;
 945
 946         i915_driver_register(i915);
 947
 948         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 949
 950         i915_welcome_messages(i915);
 951
 952         i915->do_release = true;
 953
 954         return 0;
 955
 956 out_cleanup_gem:
 957         i915_gem_suspend(i915);
 958         i915_gem_driver_remove(i915);
 959         i915_gem_driver_release(i915);
 960 out_cleanup_modeset2:
 961         /* FIXME clean up the error path */
 962         intel_modeset_driver_remove(i915);
 963         intel_irq_uninstall(i915);
 964         intel_modeset_driver_remove_noirq(i915);
 965         goto out_cleanup_modeset;
 966 out_cleanup_irq:
 967         intel_irq_uninstall(i915);
 968 out_cleanup_modeset:
 969         intel_modeset_driver_remove_nogem(i915);
 970 out_cleanup_hw:
 971         i915_driver_hw_remove(i915);
 972         intel_memory_regions_driver_release(i915);
 973         i915_ggtt_driver_release(i915);
 974         i915_gem_drain_freed_objects(i915);
 975         i915_ggtt_driver_late_release(i915);
 976 out_cleanup_mmio:
 977         i915_driver_mmio_release(i915);
 978 out_tiles_cleanup:
 979         intel_gt_release_all(i915);
 980 out_runtime_pm_put:
 981         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 982         i915_driver_late_release(i915);
 983 out_pci_disable:
 984         pci_disable_device(pdev);
 985 out_fini:
 986         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 987         return ret;
 988 }
 989
 990 void i915_driver_remove(struct drm_i915_private *i915)
 991 {
 992         intel_wakeref_t wakeref;
 993
 994         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 995
 996         i915_driver_unregister(i915);
 997
 998         /* Flush any external code that still may be under the RCU lock */
 999         synchronize_rcu();
1000
1001         i915_gem_suspend(i915);
1002
1003         intel_gvt_driver_remove(i915);
1004
1005         intel_modeset_driver_remove(i915);
1006
1007         intel_irq_uninstall(i915);
1008
1009         intel_modeset_driver_remove_noirq(i915);
1010
1011         i915_reset_error_state(i915);
1012         i915_gem_driver_remove(i915);
1013
1014         intel_modeset_driver_remove_nogem(i915);
1015
1016         i915_driver_hw_remove(i915);
1017
1018         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1019 }
1020
1021 static void i915_driver_release(struct drm_device *dev)
1022 {
1023         struct drm_i915_private *dev_priv = to_i915(dev);
1024         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1025         intel_wakeref_t wakeref;
1026
1027         if (!dev_priv->do_release)
1028                 return;
1029
1030         wakeref = intel_runtime_pm_get(rpm);
1031
1032         i915_gem_driver_release(dev_priv);
1033
1034         intel_memory_regions_driver_release(dev_priv);
1035         i915_ggtt_driver_release(dev_priv);
1036         i915_gem_drain_freed_objects(dev_priv);
1037         i915_ggtt_driver_late_release(dev_priv);
1038
1039         i915_driver_mmio_release(dev_priv);
1040
1041         intel_runtime_pm_put(rpm, wakeref);
1042
1043         intel_runtime_pm_driver_release(rpm);
1044
1045         i915_driver_late_release(dev_priv);
1046 }
1047
1048 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1049 {
1050         struct drm_i915_private *i915 = to_i915(dev);
1051         int ret;
1052
1053         ret = i915_gem_open(i915, file);
1054         if (ret)
1055                 return ret;
1056
1057         return 0;
1058 }
1059
1060 /**
1061  * i915_driver_lastclose - clean up after all DRM clients have exited
1062  * @dev: DRM device
1063  *
1064  * Take care of cleaning up after all DRM clients have exited.  In the
1065  * mode setting case, we want to restore the kernel's initial mode (just
1066  * in case the last client left us in a bad state).
1067  *
1068  * Additionally, in the non-mode setting case, we'll tear down the GTT
1069  * and DMA structures, since the kernel won't be using them, and clea
1070  * up any GEM state.
1071  */
1072 static void i915_driver_lastclose(struct drm_device *dev)
1073 {
1074         struct drm_i915_private *i915 = to_i915(dev);
1075
1076         intel_fbdev_restore_mode(dev);
1077
1078         if (HAS_DISPLAY(i915))
1079                 vga_switcheroo_process_delayed_switch();
1080 }
1081
1082 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1083 {
1084         struct drm_i915_file_private *file_priv = file->driver_priv;
1085
1086         i915_gem_context_close(file);
1087         i915_drm_client_put(file_priv->client);
1088
1089         kfree_rcu(file_priv, rcu);
1090
1091         /* Catch up with all the deferred frees from "this" client */
1092         i915_gem_flush_free_objects(to_i915(dev));
1093 }
1094
1095 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1096 {
1097         struct intel_encoder *encoder;
1098
1099         if (!HAS_DISPLAY(dev_priv))
1100                 return;
1101
1102         drm_modeset_lock_all(&dev_priv->drm);
1103         for_each_intel_encoder(&dev_priv->drm, encoder)
1104                 if (encoder->suspend)
1105                         encoder->suspend(encoder);
1106         drm_modeset_unlock_all(&dev_priv->drm);
1107 }
1108
1109 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1110 {
1111         struct intel_encoder *encoder;
1112
1113         if (!HAS_DISPLAY(dev_priv))
1114                 return;
1115
1116         drm_modeset_lock_all(&dev_priv->drm);
1117         for_each_intel_encoder(&dev_priv->drm, encoder)
1118                 if (encoder->shutdown)
1119                         encoder->shutdown(encoder);
1120         drm_modeset_unlock_all(&dev_priv->drm);
1121 }
1122
1123 void i915_driver_shutdown(struct drm_i915_private *i915)
1124 {
1125         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1126         intel_runtime_pm_disable(&i915->runtime_pm);
1127         intel_power_domains_disable(i915);
1128
1129         if (HAS_DISPLAY(i915)) {
1130                 drm_kms_helper_poll_disable(&i915->drm);
1131
1132                 drm_atomic_helper_shutdown(&i915->drm);
1133         }
1134
1135         intel_dp_mst_suspend(i915);
1136
1137         intel_runtime_pm_disable_interrupts(i915);
1138         intel_hpd_cancel_work(i915);
1139
1140         intel_suspend_encoders(i915);
1141         intel_shutdown_encoders(i915);
1142
1143         intel_dmc_ucode_suspend(i915);
1144
1145         i915_gem_suspend(i915);
1146
1147         /*
1148          * The only requirement is to reboot with display DC states disabled,
1149          * for now leaving all display power wells in the INIT power domain
1150          * enabled.
1151          *
1152          * TODO:
1153          * - unify the pci_driver::shutdown sequence here with the
1154          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1155          * - unify the driver remove and system/runtime suspend sequences with
1156          *   the above unified shutdown/poweroff sequence.
1157          */
1158         intel_power_domains_driver_remove(i915);
1159         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1160
1161         intel_runtime_pm_driver_release(&i915->runtime_pm);
1162 }
1163
1164 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1165 {
1166 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1167         if (acpi_target_system_state() < ACPI_STATE_S3)
1168                 return true;
1169 #endif
1170         return false;
1171 }
1172
1173 static int i915_drm_prepare(struct drm_device *dev)
1174 {
1175         struct drm_i915_private *i915 = to_i915(dev);
1176
1177         /*
1178          * NB intel_display_suspend() may issue new requests after we've
1179          * ostensibly marked the GPU as ready-to-sleep here. We need to
1180          * split out that work and pull it forward so that after point,
1181          * the GPU is not woken again.
1182          */
1183         return i915_gem_backup_suspend(i915);
1184 }
1185
1186 static int i915_drm_suspend(struct drm_device *dev)
1187 {
1188         struct drm_i915_private *dev_priv = to_i915(dev);
1189         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1190         pci_power_t opregion_target_state;
1191
1192         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1193
1194         /* We do a lot of poking in a lot of registers, make sure they work
1195          * properly. */
1196         intel_power_domains_disable(dev_priv);
1197         if (HAS_DISPLAY(dev_priv))
1198                 drm_kms_helper_poll_disable(dev);
1199
1200         pci_save_state(pdev);
1201
1202         intel_display_suspend(dev);
1203
1204         intel_dp_mst_suspend(dev_priv);
1205
1206         intel_runtime_pm_disable_interrupts(dev_priv);
1207         intel_hpd_cancel_work(dev_priv);
1208
1209         intel_suspend_encoders(dev_priv);
1210
1211         intel_suspend_hw(dev_priv);
1212
1213         /* Must be called before GGTT is suspended. */
1214         intel_dpt_suspend(dev_priv);
1215         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1216
1217         i915_save_display(dev_priv);
1218
1219         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1220         intel_opregion_suspend(dev_priv, opregion_target_state);
1221
1222         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1223
1224         dev_priv->suspend_count++;
1225
1226         intel_dmc_ucode_suspend(dev_priv);
1227
1228         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1229
1230         i915_gem_drain_freed_objects(dev_priv);
1231
1232         return 0;
1233 }
1234
1235 static enum i915_drm_suspend_mode
1236 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1237 {
1238         if (hibernate)
1239                 return I915_DRM_SUSPEND_HIBERNATE;
1240
1241         if (suspend_to_idle(dev_priv))
1242                 return I915_DRM_SUSPEND_IDLE;
1243
1244         return I915_DRM_SUSPEND_MEM;
1245 }
1246
1247 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1248 {
1249         struct drm_i915_private *dev_priv = to_i915(dev);
1250         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1251         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1252         struct intel_gt *gt;
1253         int ret, i;
1254
1255         disable_rpm_wakeref_asserts(rpm);
1256
1257         i915_gem_suspend_late(dev_priv);
1258
1259         for_each_gt(gt, dev_priv, i)
1260                 intel_uncore_suspend(gt->uncore);
1261
1262         intel_power_domains_suspend(dev_priv,
1263                                     get_suspend_mode(dev_priv, hibernation));
1264
1265         intel_display_power_suspend_late(dev_priv);
1266
1267         ret = vlv_suspend_complete(dev_priv);
1268         if (ret) {
1269                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1270                 intel_power_domains_resume(dev_priv);
1271
1272                 goto out;
1273         }
1274
1275         pci_disable_device(pdev);
1276         /*
1277          * During hibernation on some platforms the BIOS may try to access
1278          * the device even though it's already in D3 and hang the machine. So
1279          * leave the device in D0 on those platforms and hope the BIOS will
1280          * power down the device properly. The issue was seen on multiple old
1281          * GENs with different BIOS vendors, so having an explicit blacklist
1282          * is inpractical; apply the workaround on everything pre GEN6. The
1283          * platforms where the issue was seen:
1284          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1285          * Fujitsu FSC S7110
1286          * Acer Aspire 1830T
1287          */
1288         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1289                 pci_set_power_state(pdev, PCI_D3hot);
1290
1291 out:
1292         enable_rpm_wakeref_asserts(rpm);
1293         if (!dev_priv->uncore.user_forcewake_count)
1294                 intel_runtime_pm_driver_release(rpm);
1295
1296         return ret;
1297 }
1298
1299 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1300                                    pm_message_t state)
1301 {
1302         int error;
1303
1304         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1305                              state.event != PM_EVENT_FREEZE))
1306                 return -EINVAL;
1307
1308         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1309                 return 0;
1310
1311         error = i915_drm_suspend(&i915->drm);
1312         if (error)
1313                 return error;
1314
1315         return i915_drm_suspend_late(&i915->drm, false);
1316 }
1317
1318 static int i915_drm_resume(struct drm_device *dev)
1319 {
1320         struct drm_i915_private *dev_priv = to_i915(dev);
1321         int ret;
1322
1323         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1324
1325         ret = i915_pcode_init(dev_priv);
1326         if (ret)
1327                 return ret;
1328
1329         sanitize_gpu(dev_priv);
1330
1331         ret = i915_ggtt_enable_hw(dev_priv);
1332         if (ret)
1333                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1334
1335         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1336         /* Must be called after GGTT is resumed. */
1337         intel_dpt_resume(dev_priv);
1338
1339         intel_dmc_ucode_resume(dev_priv);
1340
1341         i915_restore_display(dev_priv);
1342         intel_pps_unlock_regs_wa(dev_priv);
1343
1344         intel_init_pch_refclk(dev_priv);
1345
1346         /*
1347          * Interrupts have to be enabled before any batches are run. If not the
1348          * GPU will hang. i915_gem_init_hw() will initiate batches to
1349          * update/restore the context.
1350          *
1351          * drm_mode_config_reset() needs AUX interrupts.
1352          *
1353          * Modeset enabling in intel_modeset_init_hw() also needs working
1354          * interrupts.
1355          */
1356         intel_runtime_pm_enable_interrupts(dev_priv);
1357
1358         if (HAS_DISPLAY(dev_priv))
1359                 drm_mode_config_reset(dev);
1360
1361         i915_gem_resume(dev_priv);
1362
1363         intel_modeset_init_hw(dev_priv);
1364         intel_init_clock_gating(dev_priv);
1365         intel_hpd_init(dev_priv);
1366
1367         /* MST sideband requires HPD interrupts enabled */
1368         intel_dp_mst_resume(dev_priv);
1369         intel_display_resume(dev);
1370
1371         intel_hpd_poll_disable(dev_priv);
1372         if (HAS_DISPLAY(dev_priv))
1373                 drm_kms_helper_poll_enable(dev);
1374
1375         intel_opregion_resume(dev_priv);
1376
1377         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1378
1379         intel_power_domains_enable(dev_priv);
1380
1381         intel_gvt_resume(dev_priv);
1382
1383         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1384
1385         return 0;
1386 }
1387
1388 static int i915_drm_resume_early(struct drm_device *dev)
1389 {
1390         struct drm_i915_private *dev_priv = to_i915(dev);
1391         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1392         struct intel_gt *gt;
1393         int ret, i;
1394
1395         /*
1396          * We have a resume ordering issue with the snd-hda driver also
1397          * requiring our device to be power up. Due to the lack of a
1398          * parent/child relationship we currently solve this with an early
1399          * resume hook.
1400          *
1401          * FIXME: This should be solved with a special hdmi sink device or
1402          * similar so that power domains can be employed.
1403          */
1404
1405         /*
1406          * Note that we need to set the power state explicitly, since we
1407          * powered off the device during freeze and the PCI core won't power
1408          * it back up for us during thaw. Powering off the device during
1409          * freeze is not a hard requirement though, and during the
1410          * suspend/resume phases the PCI core makes sure we get here with the
1411          * device powered on. So in case we change our freeze logic and keep
1412          * the device powered we can also remove the following set power state
1413          * call.
1414          */
1415         ret = pci_set_power_state(pdev, PCI_D0);
1416         if (ret) {
1417                 drm_err(&dev_priv->drm,
1418                         "failed to set PCI D0 power state (%d)\n", ret);
1419                 return ret;
1420         }
1421
1422         /*
1423          * Note that pci_enable_device() first enables any parent bridge
1424          * device and only then sets the power state for this device. The
1425          * bridge enabling is a nop though, since bridge devices are resumed
1426          * first. The order of enabling power and enabling the device is
1427          * imposed by the PCI core as described above, so here we preserve the
1428          * same order for the freeze/thaw phases.
1429          *
1430          * TODO: eventually we should remove pci_disable_device() /
1431          * pci_enable_enable_device() from suspend/resume. Due to how they
1432          * depend on the device enable refcount we can't anyway depend on them
1433          * disabling/enabling the device.
1434          */
1435         if (pci_enable_device(pdev))
1436                 return -EIO;
1437
1438         pci_set_master(pdev);
1439
1440         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1441
1442         ret = vlv_resume_prepare(dev_priv, false);
1443         if (ret)
1444                 drm_err(&dev_priv->drm,
1445                         "Resume prepare failed: %d, continuing anyway\n", ret);
1446
1447         for_each_gt(gt, dev_priv, i) {
1448                 intel_uncore_resume_early(gt->uncore);
1449                 intel_gt_check_and_clear_faults(gt);
1450         }
1451
1452         intel_display_power_resume_early(dev_priv);
1453
1454         intel_power_domains_resume(dev_priv);
1455
1456         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1457
1458         return ret;
1459 }
1460
1461 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1462 {
1463         int ret;
1464
1465         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1466                 return 0;
1467
1468         ret = i915_drm_resume_early(&i915->drm);
1469         if (ret)
1470                 return ret;
1471
1472         return i915_drm_resume(&i915->drm);
1473 }
1474
1475 static int i915_pm_prepare(struct device *kdev)
1476 {
1477         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1478
1479         if (!i915) {
1480                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1481                 return -ENODEV;
1482         }
1483
1484         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1485                 return 0;
1486
1487         return i915_drm_prepare(&i915->drm);
1488 }
1489
1490 static int i915_pm_suspend(struct device *kdev)
1491 {
1492         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1493
1494         if (!i915) {
1495                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1496                 return -ENODEV;
1497         }
1498
1499         i915_ggtt_mark_pte_lost(i915, false);
1500
1501         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1502                 return 0;
1503
1504         return i915_drm_suspend(&i915->drm);
1505 }
1506
1507 static int i915_pm_suspend_late(struct device *kdev)
1508 {
1509         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1510
1511         /*
1512          * We have a suspend ordering issue with the snd-hda driver also
1513          * requiring our device to be power up. Due to the lack of a
1514          * parent/child relationship we currently solve this with an late
1515          * suspend hook.
1516          *
1517          * FIXME: This should be solved with a special hdmi sink device or
1518          * similar so that power domains can be employed.
1519          */
1520         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1521                 return 0;
1522
1523         return i915_drm_suspend_late(&i915->drm, false);
1524 }
1525
1526 static int i915_pm_poweroff_late(struct device *kdev)
1527 {
1528         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1529
1530         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1531                 return 0;
1532
1533         return i915_drm_suspend_late(&i915->drm, true);
1534 }
1535
1536 static int i915_pm_resume_early(struct device *kdev)
1537 {
1538         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1539
1540         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1541                 return 0;
1542
1543         return i915_drm_resume_early(&i915->drm);
1544 }
1545
1546 static int i915_pm_resume(struct device *kdev)
1547 {
1548         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1549
1550         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1551                 return 0;
1552
1553         /*
1554          * If IRST is enabled, or if we can't detect whether it's enabled,
1555          * then we must assume we lost the GGTT page table entries, since
1556          * they are not retained if IRST decided to enter S4.
1557          */
1558         if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1))
1559                 i915_ggtt_mark_pte_lost(i915, true);
1560
1561         return i915_drm_resume(&i915->drm);
1562 }
1563
1564 /* freeze: before creating the hibernation_image */
1565 static int i915_pm_freeze(struct device *kdev)
1566 {
1567         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1568         int ret;
1569
1570         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1571                 ret = i915_drm_suspend(&i915->drm);
1572                 if (ret)
1573                         return ret;
1574         }
1575
1576         ret = i915_gem_freeze(i915);
1577         if (ret)
1578                 return ret;
1579
1580         return 0;
1581 }
1582
1583 static int i915_pm_freeze_late(struct device *kdev)
1584 {
1585         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1586         int ret;
1587
1588         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1589                 ret = i915_drm_suspend_late(&i915->drm, true);
1590                 if (ret)
1591                         return ret;
1592         }
1593
1594         ret = i915_gem_freeze_late(i915);
1595         if (ret)
1596                 return ret;
1597
1598         return 0;
1599 }
1600
1601 /* thaw: called after creating the hibernation image, but before turning off. */
1602 static int i915_pm_thaw_early(struct device *kdev)
1603 {
1604         return i915_pm_resume_early(kdev);
1605 }
1606
1607 static int i915_pm_thaw(struct device *kdev)
1608 {
1609         return i915_pm_resume(kdev);
1610 }
1611
1612 /* restore: called after loading the hibernation image. */
1613 static int i915_pm_restore_early(struct device *kdev)
1614 {
1615         return i915_pm_resume_early(kdev);
1616 }
1617
1618 static int i915_pm_restore(struct device *kdev)
1619 {
1620         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1621
1622         i915_ggtt_mark_pte_lost(i915, true);
1623         return i915_pm_resume(kdev);
1624 }
1625
1626 static int intel_runtime_suspend(struct device *kdev)
1627 {
1628         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1629         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1630         struct intel_gt *gt;
1631         int ret, i;
1632
1633         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1634                 return -ENODEV;
1635
1636         drm_dbg(&dev_priv->drm, "Suspending device\n");
1637
1638         disable_rpm_wakeref_asserts(rpm);
1639
1640         /*
1641          * We are safe here against re-faults, since the fault handler takes
1642          * an RPM reference.
1643          */
1644         i915_gem_runtime_suspend(dev_priv);
1645
1646         for_each_gt(gt, dev_priv, i)
1647                 intel_gt_runtime_suspend(gt);
1648
1649         intel_runtime_pm_disable_interrupts(dev_priv);
1650
1651         for_each_gt(gt, dev_priv, i)
1652                 intel_uncore_suspend(gt->uncore);
1653
1654         intel_display_power_suspend(dev_priv);
1655
1656         ret = vlv_suspend_complete(dev_priv);
1657         if (ret) {
1658                 drm_err(&dev_priv->drm,
1659                         "Runtime suspend failed, disabling it (%d)\n", ret);
1660                 intel_uncore_runtime_resume(&dev_priv->uncore);
1661
1662                 intel_runtime_pm_enable_interrupts(dev_priv);
1663
1664                 for_each_gt(gt, dev_priv, i)
1665                         intel_gt_runtime_resume(gt);
1666
1667                 enable_rpm_wakeref_asserts(rpm);
1668
1669                 return ret;
1670         }
1671
1672         enable_rpm_wakeref_asserts(rpm);
1673         intel_runtime_pm_driver_release(rpm);
1674
1675         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1676                 drm_err(&dev_priv->drm,
1677                         "Unclaimed access detected prior to suspending\n");
1678
1679         rpm->suspended = true;
1680
1681         /*
1682          * FIXME: We really should find a document that references the arguments
1683          * used below!
1684          */
1685         if (IS_BROADWELL(dev_priv)) {
1686                 /*
1687                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1688                  * being detected, and the call we do at intel_runtime_resume()
1689                  * won't be able to restore them. Since PCI_D3hot matches the
1690                  * actual specification and appears to be working, use it.
1691                  */
1692                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1693         } else {
1694                 /*
1695                  * current versions of firmware which depend on this opregion
1696                  * notification have repurposed the D1 definition to mean
1697                  * "runtime suspended" vs. what you would normally expect (D3)
1698                  * to distinguish it from notifications that might be sent via
1699                  * the suspend path.
1700                  */
1701                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1702         }
1703
1704         assert_forcewakes_inactive(&dev_priv->uncore);
1705
1706         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1707                 intel_hpd_poll_enable(dev_priv);
1708
1709         drm_dbg(&dev_priv->drm, "Device suspended\n");
1710         return 0;
1711 }
1712
1713 static int intel_runtime_resume(struct device *kdev)
1714 {
1715         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1716         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1717         struct intel_gt *gt;
1718         int ret, i;
1719
1720         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1721                 return -ENODEV;
1722
1723         drm_dbg(&dev_priv->drm, "Resuming device\n");
1724
1725         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1726         disable_rpm_wakeref_asserts(rpm);
1727
1728         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1729         rpm->suspended = false;
1730         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1731                 drm_dbg(&dev_priv->drm,
1732                         "Unclaimed access during suspend, bios?\n");
1733
1734         intel_display_power_resume(dev_priv);
1735
1736         ret = vlv_resume_prepare(dev_priv, true);
1737
1738         for_each_gt(gt, dev_priv, i)
1739                 intel_uncore_runtime_resume(gt->uncore);
1740
1741         intel_runtime_pm_enable_interrupts(dev_priv);
1742
1743         /*
1744          * No point of rolling back things in case of an error, as the best
1745          * we can do is to hope that things will still work (and disable RPM).
1746          */
1747         for_each_gt(gt, dev_priv, i)
1748                 intel_gt_runtime_resume(gt);
1749
1750         /*
1751          * On VLV/CHV display interrupts are part of the display
1752          * power well, so hpd is reinitialized from there. For
1753          * everyone else do it here.
1754          */
1755         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1756                 intel_hpd_init(dev_priv);
1757                 intel_hpd_poll_disable(dev_priv);
1758         }
1759
1760         skl_watermark_ipc_update(dev_priv);
1761
1762         enable_rpm_wakeref_asserts(rpm);
1763
1764         if (ret)
1765                 drm_err(&dev_priv->drm,
1766                         "Runtime resume failed, disabling it (%d)\n", ret);
1767         else
1768                 drm_dbg(&dev_priv->drm, "Device resumed\n");
1769
1770         return ret;
1771 }
1772
1773 const struct dev_pm_ops i915_pm_ops = {
1774         /*
1775          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1776          * PMSG_RESUME]
1777          */
1778         .prepare = i915_pm_prepare,
1779         .suspend = i915_pm_suspend,
1780         .suspend_late = i915_pm_suspend_late,
1781         .resume_early = i915_pm_resume_early,
1782         .resume = i915_pm_resume,
1783
1784         /*
1785          * S4 event handlers
1786          * @freeze, @freeze_late    : called (1) before creating the
1787          *                            hibernation image [PMSG_FREEZE] and
1788          *                            (2) after rebooting, before restoring
1789          *                            the image [PMSG_QUIESCE]
1790          * @thaw, @thaw_early       : called (1) after creating the hibernation
1791          *                            image, before writing it [PMSG_THAW]
1792          *                            and (2) after failing to create or
1793          *                            restore the image [PMSG_RECOVER]
1794          * @poweroff, @poweroff_late: called after writing the hibernation
1795          *                            image, before rebooting [PMSG_HIBERNATE]
1796          * @restore, @restore_early : called after rebooting and restoring the
1797          *                            hibernation image [PMSG_RESTORE]
1798          */
1799         .freeze = i915_pm_freeze,
1800         .freeze_late = i915_pm_freeze_late,
1801         .thaw_early = i915_pm_thaw_early,
1802         .thaw = i915_pm_thaw,
1803         .poweroff = i915_pm_suspend,
1804         .poweroff_late = i915_pm_poweroff_late,
1805         .restore_early = i915_pm_restore_early,
1806         .restore = i915_pm_restore,
1807
1808         /* S0ix (via runtime suspend) event handlers */
1809         .runtime_suspend = intel_runtime_suspend,
1810         .runtime_resume = intel_runtime_resume,
1811 };
1812
1813 static const struct file_operations i915_driver_fops = {
1814         .owner = THIS_MODULE,
1815         .open = drm_open,
1816         .release = drm_release_noglobal,
1817         .unlocked_ioctl = drm_ioctl,
1818         .mmap = i915_gem_mmap,
1819         .poll = drm_poll,
1820         .read = drm_read,
1821         .compat_ioctl = i915_ioc32_compat_ioctl,
1822         .llseek = noop_llseek,
1823 #ifdef CONFIG_PROC_FS
1824         .show_fdinfo = i915_drm_client_fdinfo,
1825 #endif
1826 };
1827
1828 static int
1829 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1830                           struct drm_file *file)
1831 {
1832         return -ENODEV;
1833 }
1834
1835 static const struct drm_ioctl_desc i915_ioctls[] = {
1836         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1837         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1838         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1839         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1840         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1841         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1842         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1843         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1844         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1845         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1846         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1847         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1848         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1849         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1850         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1851         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1852         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1853         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1854         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1855         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1856         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1857         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1858         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1859         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1860         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1861         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1862         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1863         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1864         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1865         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1866         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1867         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1868         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1869         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1870         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1871         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1872         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1873         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1874         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1875         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1876         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1877         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1878         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1879         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1880         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1881         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1882         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1883         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1884         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1885         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1886         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1887         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1888         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1889         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1890         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1891         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1892         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1893         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1894         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1895 };
1896
1897 /*
1898  * Interface history:
1899  *
1900  * 1.1: Original.
1901  * 1.2: Add Power Management
1902  * 1.3: Add vblank support
1903  * 1.4: Fix cmdbuffer path, add heap destroy
1904  * 1.5: Add vblank pipe configuration
1905  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1906  *      - Support vertical blank on secondary display pipe
1907  */
1908 #define DRIVER_MAJOR            1
1909 #define DRIVER_MINOR            6
1910 #define DRIVER_PATCHLEVEL       0
1911
1912 static const struct drm_driver i915_drm_driver = {
1913         /* Don't use MTRRs here; the Xserver or userspace app should
1914          * deal with them for Intel hardware.
1915          */
1916         .driver_features =
1917             DRIVER_GEM |
1918             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1919             DRIVER_SYNCOBJ_TIMELINE,
1920         .release = i915_driver_release,
1921         .open = i915_driver_open,
1922         .lastclose = i915_driver_lastclose,
1923         .postclose = i915_driver_postclose,
1924
1925         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1926         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1927         .gem_prime_import = i915_gem_prime_import,
1928
1929         .dumb_create = i915_gem_dumb_create,
1930         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1931
1932         .ioctls = i915_ioctls,
1933         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1934         .fops = &i915_driver_fops,
1935         .name = DRIVER_NAME,
1936         .desc = DRIVER_DESC,
1937         .date = DRIVER_DATE,
1938         .major = DRIVER_MAJOR,
1939         .minor = DRIVER_MINOR,
1940         .patchlevel = DRIVER_PATCHLEVEL,
1941 };