drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/string_helpers.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42
  43 #include <drm/drm_aperture.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_bw.h"
  51 #include "display/intel_cdclk.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dmc.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dpt.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pch_refclk.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64
  65 #include "gem/i915_gem_context.h"
  66 #include "gem/i915_gem_create.h"
  67 #include "gem/i915_gem_dmabuf.h"
  68 #include "gem/i915_gem_ioctls.h"
  69 #include "gem/i915_gem_mman.h"
  70 #include "gem/i915_gem_pm.h"
  71 #include "gt/intel_gt.h"
  72 #include "gt/intel_gt_pm.h"
  73 #include "gt/intel_rc6.h"
  74
  75 #include "pxp/intel_pxp_pm.h"
  76
  77 #include "i915_file_private.h"
  78 #include "i915_debugfs.h"
  79 #include "i915_driver.h"
  80 #include "i915_drm_client.h"
  81 #include "i915_drv.h"
  82 #include "i915_getparam.h"
  83 #include "i915_ioc32.h"
  84 #include "i915_ioctl.h"
  85 #include "i915_irq.h"
  86 #include "i915_memcpy.h"
  87 #include "i915_perf.h"
  88 #include "i915_query.h"
  89 #include "i915_suspend.h"
  90 #include "i915_switcheroo.h"
  91 #include "i915_sysfs.h"
  92 #include "i915_utils.h"
  93 #include "i915_vgpu.h"
  94 #include "intel_dram.h"
  95 #include "intel_gvt.h"
  96 #include "intel_memory_region.h"
  97 #include "intel_pci_config.h"
  98 #include "intel_pcode.h"
  99 #include "intel_pm.h"
 100 #include "intel_region_ttm.h"
 101 #include "vlv_suspend.h"
 102
 103 static const struct drm_driver i915_drm_driver;
 104
 105 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 106 {
 107         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
 108
 109         dev_priv->bridge_dev =
 110                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 111         if (!dev_priv->bridge_dev) {
 112                 drm_err(&dev_priv->drm, "bridge device not found\n");
 113                 return -EIO;
 114         }
 115         return 0;
 116 }
 117
 118 /* Allocate space for the MCH regs if needed, return nonzero on error */
 119 static int
 120 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 121 {
 122         int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 123         u32 temp_lo, temp_hi = 0;
 124         u64 mchbar_addr;
 125         int ret;
 126
 127         if (GRAPHICS_VER(dev_priv) >= 4)
 128                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 129         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 130         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 131
 132         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 133 #ifdef CONFIG_PNP
 134         if (mchbar_addr &&
 135             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 136                 return 0;
 137 #endif
 138
 139         /* Get some space for it */
 140         dev_priv->mch_res.name = "i915 MCHBAR";
 141         dev_priv->mch_res.flags = IORESOURCE_MEM;
 142         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 143                                      &dev_priv->mch_res,
 144                                      MCHBAR_SIZE, MCHBAR_SIZE,
 145                                      PCIBIOS_MIN_MEM,
 146                                      0, pcibios_align_resource,
 147                                      dev_priv->bridge_dev);
 148         if (ret) {
 149                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 150                 dev_priv->mch_res.start = 0;
 151                 return ret;
 152         }
 153
 154         if (GRAPHICS_VER(dev_priv) >= 4)
 155                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 156                                        upper_32_bits(dev_priv->mch_res.start));
 157
 158         pci_write_config_dword(dev_priv->bridge_dev, reg,
 159                                lower_32_bits(dev_priv->mch_res.start));
 160         return 0;
 161 }
 162
 163 /* Setup MCHBAR if possible, return true if we should disable it again */
 164 static void
 165 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 166 {
 167         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 168         u32 temp;
 169         bool enabled;
 170
 171         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 172                 return;
 173
 174         dev_priv->mchbar_need_disable = false;
 175
 176         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 177                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 178                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 179         } else {
 180                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 181                 enabled = temp & 1;
 182         }
 183
 184         /* If it's already enabled, don't have to do anything */
 185         if (enabled)
 186                 return;
 187
 188         if (intel_alloc_mchbar_resource(dev_priv))
 189                 return;
 190
 191         dev_priv->mchbar_need_disable = true;
 192
 193         /* Space is allocated or reserved, so enable it. */
 194         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 195                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 196                                        temp | DEVEN_MCHBAR_EN);
 197         } else {
 198                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 199                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 200         }
 201 }
 202
 203 static void
 204 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 205 {
 206         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 207
 208         if (dev_priv->mchbar_need_disable) {
 209                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 210                         u32 deven_val;
 211
 212                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 213                                               &deven_val);
 214                         deven_val &= ~DEVEN_MCHBAR_EN;
 215                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 216                                                deven_val);
 217                 } else {
 218                         u32 mchbar_val;
 219
 220                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 221                                               &mchbar_val);
 222                         mchbar_val &= ~1;
 223                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 224                                                mchbar_val);
 225                 }
 226         }
 227
 228         if (dev_priv->mch_res.start)
 229                 release_resource(&dev_priv->mch_res);
 230 }
 231
 232 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 233 {
 234         /*
 235          * The i915 workqueue is primarily used for batched retirement of
 236          * requests (and thus managing bo) once the task has been completed
 237          * by the GPU. i915_retire_requests() is called directly when we
 238          * need high-priority retirement, such as waiting for an explicit
 239          * bo.
 240          *
 241          * It is also used for periodic low-priority events, such as
 242          * idle-timers and recording error state.
 243          *
 244          * All tasks on the workqueue are expected to acquire the dev mutex
 245          * so there is no point in running more than one instance of the
 246          * workqueue at any time.  Use an ordered one.
 247          */
 248         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 249         if (dev_priv->wq == NULL)
 250                 goto out_err;
 251
 252         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 253         if (dev_priv->hotplug.dp_wq == NULL)
 254                 goto out_free_wq;
 255
 256         return 0;
 257
 258 out_free_wq:
 259         destroy_workqueue(dev_priv->wq);
 260 out_err:
 261         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 262
 263         return -ENOMEM;
 264 }
 265
 266 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 267 {
 268         destroy_workqueue(dev_priv->hotplug.dp_wq);
 269         destroy_workqueue(dev_priv->wq);
 270 }
 271
 272 /*
 273  * We don't keep the workarounds for pre-production hardware, so we expect our
 274  * driver to fail on these machines in one way or another. A little warning on
 275  * dmesg may help both the user and the bug triagers.
 276  *
 277  * Our policy for removing pre-production workarounds is to keep the
 278  * current gen workarounds as a guide to the bring-up of the next gen
 279  * (workarounds have a habit of persisting!). Anything older than that
 280  * should be removed along with the complications they introduce.
 281  */
 282 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 283 {
 284         bool pre = false;
 285
 286         pre |= IS_HSW_EARLY_SDV(dev_priv);
 287         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 288         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 289         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 290         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 291         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 292
 293         if (pre) {
 294                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 295                           "It may not be fully functional.\n");
 296                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 297         }
 298 }
 299
 300 static void sanitize_gpu(struct drm_i915_private *i915)
 301 {
 302         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 303                 __intel_gt_reset(to_gt(i915), ALL_ENGINES);
 304 }
 305
 306 /**
 307  * i915_driver_early_probe - setup state not requiring device access
 308  * @dev_priv: device private
 309  *
 310  * Initialize everything that is a "SW-only" state, that is state not
 311  * requiring accessing the device or exposing the driver via kernel internal
 312  * or userspace interfaces. Example steps belonging here: lock initialization,
 313  * system memory allocation, setting up device specific attributes and
 314  * function hooks not requiring accessing the device.
 315  */
 316 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 317 {
 318         int ret = 0;
 319
 320         if (i915_inject_probe_failure(dev_priv))
 321                 return -ENODEV;
 322
 323         intel_device_info_subplatform_init(dev_priv);
 324         intel_step_init(dev_priv);
 325
 326         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 327
 328         spin_lock_init(&dev_priv->irq_lock);
 329         spin_lock_init(&dev_priv->gpu_error.lock);
 330         mutex_init(&dev_priv->backlight_lock);
 331
 332         mutex_init(&dev_priv->sb_lock);
 333         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 334
 335         mutex_init(&dev_priv->audio.mutex);
 336         mutex_init(&dev_priv->wm.wm_mutex);
 337         mutex_init(&dev_priv->pps_mutex);
 338         mutex_init(&dev_priv->hdcp_comp_mutex);
 339
 340         i915_memcpy_init_early(dev_priv);
 341         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 342
 343         ret = i915_workqueues_init(dev_priv);
 344         if (ret < 0)
 345                 return ret;
 346
 347         ret = vlv_suspend_init(dev_priv);
 348         if (ret < 0)
 349                 goto err_workqueues;
 350
 351         ret = intel_region_ttm_device_init(dev_priv);
 352         if (ret)
 353                 goto err_ttm;
 354
 355         intel_wopcm_init_early(&dev_priv->wopcm);
 356
 357         intel_root_gt_init_early(dev_priv);
 358
 359         i915_drm_clients_init(&dev_priv->clients, dev_priv);
 360
 361         i915_gem_init_early(dev_priv);
 362
 363         /* This must be called before any calls to HAS_PCH_* */
 364         intel_detect_pch(dev_priv);
 365
 366         intel_pm_setup(dev_priv);
 367         ret = intel_power_domains_init(dev_priv);
 368         if (ret < 0)
 369                 goto err_gem;
 370         intel_irq_init(dev_priv);
 371         intel_init_display_hooks(dev_priv);
 372         intel_init_clock_gating_hooks(dev_priv);
 373
 374         intel_detect_preproduction_hw(dev_priv);
 375
 376         return 0;
 377
 378 err_gem:
 379         i915_gem_cleanup_early(dev_priv);
 380         intel_gt_driver_late_release_all(dev_priv);
 381         i915_drm_clients_fini(&dev_priv->clients);
 382         intel_region_ttm_device_fini(dev_priv);
 383 err_ttm:
 384         vlv_suspend_cleanup(dev_priv);
 385 err_workqueues:
 386         i915_workqueues_cleanup(dev_priv);
 387         return ret;
 388 }
 389
 390 /**
 391  * i915_driver_late_release - cleanup the setup done in
 392  *                             i915_driver_early_probe()
 393  * @dev_priv: device private
 394  */
 395 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 396 {
 397         intel_irq_fini(dev_priv);
 398         intel_power_domains_cleanup(dev_priv);
 399         i915_gem_cleanup_early(dev_priv);
 400         intel_gt_driver_late_release_all(dev_priv);
 401         i915_drm_clients_fini(&dev_priv->clients);
 402         intel_region_ttm_device_fini(dev_priv);
 403         vlv_suspend_cleanup(dev_priv);
 404         i915_workqueues_cleanup(dev_priv);
 405
 406         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 407         mutex_destroy(&dev_priv->sb_lock);
 408
 409         i915_params_free(&dev_priv->params);
 410 }
 411
 412 /**
 413  * i915_driver_mmio_probe - setup device MMIO
 414  * @dev_priv: device private
 415  *
 416  * Setup minimal device state necessary for MMIO accesses later in the
 417  * initialization sequence. The setup here should avoid any other device-wide
 418  * side effects or exposing the driver via kernel internal or user space
 419  * interfaces.
 420  */
 421 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 422 {
 423         int ret;
 424
 425         if (i915_inject_probe_failure(dev_priv))
 426                 return -ENODEV;
 427
 428         ret = i915_get_bridge_dev(dev_priv);
 429         if (ret < 0)
 430                 return ret;
 431
 432         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 433         if (ret)
 434                 return ret;
 435
 436         /* Try to make sure MCHBAR is enabled before poking at it */
 437         intel_setup_mchbar(dev_priv);
 438         intel_device_info_runtime_init(dev_priv);
 439
 440         ret = intel_gt_init_mmio(to_gt(dev_priv));
 441         if (ret)
 442                 goto err_uncore;
 443
 444         /* As early as possible, scrub existing GPU state before clobbering */
 445         sanitize_gpu(dev_priv);
 446
 447         return 0;
 448
 449 err_uncore:
 450         intel_teardown_mchbar(dev_priv);
 451         intel_uncore_fini_mmio(&dev_priv->uncore);
 452         pci_dev_put(dev_priv->bridge_dev);
 453
 454         return ret;
 455 }
 456
 457 /**
 458  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 459  * @dev_priv: device private
 460  */
 461 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 462 {
 463         intel_teardown_mchbar(dev_priv);
 464         intel_uncore_fini_mmio(&dev_priv->uncore);
 465         pci_dev_put(dev_priv->bridge_dev);
 466 }
 467
 468 /**
 469  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 470  * platform
 471  * @i915: valid i915 instance
 472  *
 473  * Set the dma max segment size, device and coherent masks.  The dma mask set
 474  * needs to occur before i915_ggtt_probe_hw.
 475  *
 476  * A couple of platforms have special needs.  Address them as well.
 477  *
 478  */
 479 static int i915_set_dma_info(struct drm_i915_private *i915)
 480 {
 481         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 482         int ret;
 483
 484         GEM_BUG_ON(!mask_size);
 485
 486         /*
 487          * We don't have a max segment size, so set it to the max so sg's
 488          * debugging layer doesn't complain
 489          */
 490         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 491
 492         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 493         if (ret)
 494                 goto mask_err;
 495
 496         /* overlay on gen2 is broken and can't address above 1G */
 497         if (GRAPHICS_VER(i915) == 2)
 498                 mask_size = 30;
 499
 500         /*
 501          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 502          * using 32bit addressing, overwriting memory if HWS is located
 503          * above 4GB.
 504          *
 505          * The documentation also mentions an issue with undefined
 506          * behaviour if any general state is accessed within a page above 4GB,
 507          * which also needs to be handled carefully.
 508          */
 509         if (IS_I965G(i915) || IS_I965GM(i915))
 510                 mask_size = 32;
 511
 512         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 513         if (ret)
 514                 goto mask_err;
 515
 516         return 0;
 517
 518 mask_err:
 519         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 520         return ret;
 521 }
 522
 523 /**
 524  * i915_driver_hw_probe - setup state requiring device access
 525  * @dev_priv: device private
 526  *
 527  * Setup state that requires accessing the device, but doesn't require
 528  * exposing the driver via kernel internal or userspace interfaces.
 529  */
 530 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 531 {
 532         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 533         int ret;
 534
 535         if (i915_inject_probe_failure(dev_priv))
 536                 return -ENODEV;
 537
 538         if (HAS_PPGTT(dev_priv)) {
 539                 if (intel_vgpu_active(dev_priv) &&
 540                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 541                         i915_report_error(dev_priv,
 542                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 543                         return -ENXIO;
 544                 }
 545         }
 546
 547         if (HAS_EXECLISTS(dev_priv)) {
 548                 /*
 549                  * Older GVT emulation depends upon intercepting CSB mmio,
 550                  * which we no longer use, preferring to use the HWSP cache
 551                  * instead.
 552                  */
 553                 if (intel_vgpu_active(dev_priv) &&
 554                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 555                         i915_report_error(dev_priv,
 556                                           "old vGPU host found, support for HWSP emulation required\n");
 557                         return -ENXIO;
 558                 }
 559         }
 560
 561         /* needs to be done before ggtt probe */
 562         intel_dram_edram_detect(dev_priv);
 563
 564         ret = i915_set_dma_info(dev_priv);
 565         if (ret)
 566                 return ret;
 567
 568         i915_perf_init(dev_priv);
 569
 570         ret = intel_gt_assign_ggtt(to_gt(dev_priv));
 571         if (ret)
 572                 goto err_perf;
 573
 574         ret = i915_ggtt_probe_hw(dev_priv);
 575         if (ret)
 576                 goto err_perf;
 577
 578         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 579         if (ret)
 580                 goto err_ggtt;
 581
 582         ret = i915_ggtt_init_hw(dev_priv);
 583         if (ret)
 584                 goto err_ggtt;
 585
 586         ret = intel_memory_regions_hw_probe(dev_priv);
 587         if (ret)
 588                 goto err_ggtt;
 589
 590         ret = intel_gt_tiles_init(dev_priv);
 591         if (ret)
 592                 goto err_mem_regions;
 593
 594         ret = i915_ggtt_enable_hw(dev_priv);
 595         if (ret) {
 596                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 597                 goto err_mem_regions;
 598         }
 599
 600         pci_set_master(pdev);
 601
 602         /* On the 945G/GM, the chipset reports the MSI capability on the
 603          * integrated graphics even though the support isn't actually there
 604          * according to the published specs.  It doesn't appear to function
 605          * correctly in testing on 945G.
 606          * This may be a side effect of MSI having been made available for PEG
 607          * and the registers being closely associated.
 608          *
 609          * According to chipset errata, on the 965GM, MSI interrupts may
 610          * be lost or delayed, and was defeatured. MSI interrupts seem to
 611          * get lost on g4x as well, and interrupt delivery seems to stay
 612          * properly dead afterwards. So we'll just disable them for all
 613          * pre-gen5 chipsets.
 614          *
 615          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 616          * interrupts even when in MSI mode. This results in spurious
 617          * interrupt warnings if the legacy irq no. is shared with another
 618          * device. The kernel then disables that interrupt source and so
 619          * prevents the other device from working properly.
 620          */
 621         if (GRAPHICS_VER(dev_priv) >= 5) {
 622                 if (pci_enable_msi(pdev) < 0)
 623                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 624         }
 625
 626         ret = intel_gvt_init(dev_priv);
 627         if (ret)
 628                 goto err_msi;
 629
 630         intel_opregion_setup(dev_priv);
 631
 632         ret = intel_pcode_init(&dev_priv->uncore);
 633         if (ret)
 634                 goto err_msi;
 635
 636         /*
 637          * Fill the dram structure to get the system dram info. This will be
 638          * used for memory latency calculation.
 639          */
 640         intel_dram_detect(dev_priv);
 641
 642         intel_bw_init_hw(dev_priv);
 643
 644         return 0;
 645
 646 err_msi:
 647         if (pdev->msi_enabled)
 648                 pci_disable_msi(pdev);
 649 err_mem_regions:
 650         intel_memory_regions_driver_release(dev_priv);
 651 err_ggtt:
 652         i915_ggtt_driver_release(dev_priv);
 653         i915_gem_drain_freed_objects(dev_priv);
 654         i915_ggtt_driver_late_release(dev_priv);
 655 err_perf:
 656         i915_perf_fini(dev_priv);
 657         return ret;
 658 }
 659
 660 /**
 661  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 662  * @dev_priv: device private
 663  */
 664 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 665 {
 666         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 667
 668         i915_perf_fini(dev_priv);
 669
 670         if (pdev->msi_enabled)
 671                 pci_disable_msi(pdev);
 672 }
 673
 674 /**
 675  * i915_driver_register - register the driver with the rest of the system
 676  * @dev_priv: device private
 677  *
 678  * Perform any steps necessary to make the driver available via kernel
 679  * internal or userspace interfaces.
 680  */
 681 static void i915_driver_register(struct drm_i915_private *dev_priv)
 682 {
 683         struct drm_device *dev = &dev_priv->drm;
 684
 685         i915_gem_driver_register(dev_priv);
 686         i915_pmu_register(dev_priv);
 687
 688         intel_vgpu_register(dev_priv);
 689
 690         /* Reveal our presence to userspace */
 691         if (drm_dev_register(dev, 0)) {
 692                 drm_err(&dev_priv->drm,
 693                         "Failed to register driver for userspace access!\n");
 694                 return;
 695         }
 696
 697         i915_debugfs_register(dev_priv);
 698         i915_setup_sysfs(dev_priv);
 699
 700         /* Depends on sysfs having been initialized */
 701         i915_perf_register(dev_priv);
 702
 703         intel_gt_driver_register(to_gt(dev_priv));
 704
 705         intel_display_driver_register(dev_priv);
 706
 707         intel_power_domains_enable(dev_priv);
 708         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 709
 710         intel_register_dsm_handler();
 711
 712         if (i915_switcheroo_register(dev_priv))
 713                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 714 }
 715
 716 /**
 717  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 718  * @dev_priv: device private
 719  */
 720 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 721 {
 722         i915_switcheroo_unregister(dev_priv);
 723
 724         intel_unregister_dsm_handler();
 725
 726         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 727         intel_power_domains_disable(dev_priv);
 728
 729         intel_display_driver_unregister(dev_priv);
 730
 731         intel_gt_driver_unregister(to_gt(dev_priv));
 732
 733         i915_perf_unregister(dev_priv);
 734         i915_pmu_unregister(dev_priv);
 735
 736         i915_teardown_sysfs(dev_priv);
 737         drm_dev_unplug(&dev_priv->drm);
 738
 739         i915_gem_driver_unregister(dev_priv);
 740 }
 741
 742 void
 743 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 744 {
 745         drm_printf(p, "iommu: %s\n",
 746                    str_enabled_disabled(i915_vtd_active(i915)));
 747 }
 748
 749 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 750 {
 751         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 752                 struct drm_printer p = drm_debug_printer("i915 device info:");
 753
 754                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 755                            INTEL_DEVID(dev_priv),
 756                            INTEL_REVID(dev_priv),
 757                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 758                            intel_subplatform(RUNTIME_INFO(dev_priv),
 759                                              INTEL_INFO(dev_priv)->platform),
 760                            GRAPHICS_VER(dev_priv));
 761
 762                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 763                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 764                 i915_print_iommu_status(dev_priv, &p);
 765                 intel_gt_info_print(&to_gt(dev_priv)->info, &p);
 766         }
 767
 768         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 769                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 770         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 771                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 772         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 773                 drm_info(&dev_priv->drm,
 774                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 775 }
 776
 777 static struct drm_i915_private *
 778 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 779 {
 780         const struct intel_device_info *match_info =
 781                 (struct intel_device_info *)ent->driver_data;
 782         struct intel_device_info *device_info;
 783         struct drm_i915_private *i915;
 784
 785         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 786                                   struct drm_i915_private, drm);
 787         if (IS_ERR(i915))
 788                 return i915;
 789
 790         pci_set_drvdata(pdev, i915);
 791
 792         /* Device parameters start as a copy of module parameters. */
 793         i915_params_copy(&i915->params, &i915_modparams);
 794
 795         /* Setup the write-once "constant" device info */
 796         device_info = mkwrite_device_info(i915);
 797         memcpy(device_info, match_info, sizeof(*device_info));
 798         RUNTIME_INFO(i915)->device_id = pdev->device;
 799
 800         return i915;
 801 }
 802
 803 /**
 804  * i915_driver_probe - setup chip and create an initial config
 805  * @pdev: PCI device
 806  * @ent: matching PCI ID entry
 807  *
 808  * The driver probe routine has to do several things:
 809  *   - drive output discovery via intel_modeset_init()
 810  *   - initialize the memory manager
 811  *   - allocate initial config memory
 812  *   - setup the DRM framebuffer with the allocated memory
 813  */
 814 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 815 {
 816         const struct intel_device_info *match_info =
 817                 (struct intel_device_info *)ent->driver_data;
 818         struct drm_i915_private *i915;
 819         int ret;
 820
 821         i915 = i915_driver_create(pdev, ent);
 822         if (IS_ERR(i915))
 823                 return PTR_ERR(i915);
 824
 825         /* Disable nuclear pageflip by default on pre-ILK */
 826         if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5)
 827                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 828
 829         ret = pci_enable_device(pdev);
 830         if (ret)
 831                 goto out_fini;
 832
 833         ret = i915_driver_early_probe(i915);
 834         if (ret < 0)
 835                 goto out_pci_disable;
 836
 837         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 838
 839         intel_vgpu_detect(i915);
 840
 841         ret = intel_gt_probe_all(i915);
 842         if (ret < 0)
 843                 goto out_runtime_pm_put;
 844
 845         ret = i915_driver_mmio_probe(i915);
 846         if (ret < 0)
 847                 goto out_tiles_cleanup;
 848
 849         ret = i915_driver_hw_probe(i915);
 850         if (ret < 0)
 851                 goto out_cleanup_mmio;
 852
 853         ret = intel_modeset_init_noirq(i915);
 854         if (ret < 0)
 855                 goto out_cleanup_hw;
 856
 857         ret = intel_irq_install(i915);
 858         if (ret)
 859                 goto out_cleanup_modeset;
 860
 861         ret = intel_modeset_init_nogem(i915);
 862         if (ret)
 863                 goto out_cleanup_irq;
 864
 865         ret = i915_gem_init(i915);
 866         if (ret)
 867                 goto out_cleanup_modeset2;
 868
 869         ret = intel_modeset_init(i915);
 870         if (ret)
 871                 goto out_cleanup_gem;
 872
 873         i915_driver_register(i915);
 874
 875         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 876
 877         i915_welcome_messages(i915);
 878
 879         i915->do_release = true;
 880
 881         return 0;
 882
 883 out_cleanup_gem:
 884         i915_gem_suspend(i915);
 885         i915_gem_driver_remove(i915);
 886         i915_gem_driver_release(i915);
 887 out_cleanup_modeset2:
 888         /* FIXME clean up the error path */
 889         intel_modeset_driver_remove(i915);
 890         intel_irq_uninstall(i915);
 891         intel_modeset_driver_remove_noirq(i915);
 892         goto out_cleanup_modeset;
 893 out_cleanup_irq:
 894         intel_irq_uninstall(i915);
 895 out_cleanup_modeset:
 896         intel_modeset_driver_remove_nogem(i915);
 897 out_cleanup_hw:
 898         i915_driver_hw_remove(i915);
 899         intel_memory_regions_driver_release(i915);
 900         i915_ggtt_driver_release(i915);
 901         i915_gem_drain_freed_objects(i915);
 902         i915_ggtt_driver_late_release(i915);
 903 out_cleanup_mmio:
 904         i915_driver_mmio_release(i915);
 905 out_tiles_cleanup:
 906         intel_gt_release_all(i915);
 907 out_runtime_pm_put:
 908         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 909         i915_driver_late_release(i915);
 910 out_pci_disable:
 911         pci_disable_device(pdev);
 912 out_fini:
 913         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 914         return ret;
 915 }
 916
 917 void i915_driver_remove(struct drm_i915_private *i915)
 918 {
 919         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 920
 921         i915_driver_unregister(i915);
 922
 923         /* Flush any external code that still may be under the RCU lock */
 924         synchronize_rcu();
 925
 926         i915_gem_suspend(i915);
 927
 928         intel_gvt_driver_remove(i915);
 929
 930         intel_modeset_driver_remove(i915);
 931
 932         intel_irq_uninstall(i915);
 933
 934         intel_modeset_driver_remove_noirq(i915);
 935
 936         i915_reset_error_state(i915);
 937         i915_gem_driver_remove(i915);
 938
 939         intel_modeset_driver_remove_nogem(i915);
 940
 941         i915_driver_hw_remove(i915);
 942
 943         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 944 }
 945
 946 static void i915_driver_release(struct drm_device *dev)
 947 {
 948         struct drm_i915_private *dev_priv = to_i915(dev);
 949         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 950
 951         if (!dev_priv->do_release)
 952                 return;
 953
 954         disable_rpm_wakeref_asserts(rpm);
 955
 956         i915_gem_driver_release(dev_priv);
 957
 958         intel_memory_regions_driver_release(dev_priv);
 959         i915_ggtt_driver_release(dev_priv);
 960         i915_gem_drain_freed_objects(dev_priv);
 961         i915_ggtt_driver_late_release(dev_priv);
 962
 963         i915_driver_mmio_release(dev_priv);
 964
 965         enable_rpm_wakeref_asserts(rpm);
 966         intel_runtime_pm_driver_release(rpm);
 967
 968         i915_driver_late_release(dev_priv);
 969 }
 970
 971 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 972 {
 973         struct drm_i915_private *i915 = to_i915(dev);
 974         int ret;
 975
 976         ret = i915_gem_open(i915, file);
 977         if (ret)
 978                 return ret;
 979
 980         return 0;
 981 }
 982
 983 /**
 984  * i915_driver_lastclose - clean up after all DRM clients have exited
 985  * @dev: DRM device
 986  *
 987  * Take care of cleaning up after all DRM clients have exited.  In the
 988  * mode setting case, we want to restore the kernel's initial mode (just
 989  * in case the last client left us in a bad state).
 990  *
 991  * Additionally, in the non-mode setting case, we'll tear down the GTT
 992  * and DMA structures, since the kernel won't be using them, and clea
 993  * up any GEM state.
 994  */
 995 static void i915_driver_lastclose(struct drm_device *dev)
 996 {
 997         struct drm_i915_private *i915 = to_i915(dev);
 998
 999         intel_fbdev_restore_mode(dev);
1000
1001         if (HAS_DISPLAY(i915))
1002                 vga_switcheroo_process_delayed_switch();
1003 }
1004
1005 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1006 {
1007         struct drm_i915_file_private *file_priv = file->driver_priv;
1008
1009         i915_gem_context_close(file);
1010         i915_drm_client_put(file_priv->client);
1011
1012         kfree_rcu(file_priv, rcu);
1013
1014         /* Catch up with all the deferred frees from "this" client */
1015         i915_gem_flush_free_objects(to_i915(dev));
1016 }
1017
1018 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1019 {
1020         struct drm_device *dev = &dev_priv->drm;
1021         struct intel_encoder *encoder;
1022
1023         if (!HAS_DISPLAY(dev_priv))
1024                 return;
1025
1026         drm_modeset_lock_all(dev);
1027         for_each_intel_encoder(dev, encoder)
1028                 if (encoder->suspend)
1029                         encoder->suspend(encoder);
1030         drm_modeset_unlock_all(dev);
1031 }
1032
1033 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1034 {
1035         struct drm_device *dev = &dev_priv->drm;
1036         struct intel_encoder *encoder;
1037
1038         if (!HAS_DISPLAY(dev_priv))
1039                 return;
1040
1041         drm_modeset_lock_all(dev);
1042         for_each_intel_encoder(dev, encoder)
1043                 if (encoder->shutdown)
1044                         encoder->shutdown(encoder);
1045         drm_modeset_unlock_all(dev);
1046 }
1047
1048 void i915_driver_shutdown(struct drm_i915_private *i915)
1049 {
1050         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1051         intel_runtime_pm_disable(&i915->runtime_pm);
1052         intel_power_domains_disable(i915);
1053
1054         i915_gem_suspend(i915);
1055
1056         if (HAS_DISPLAY(i915)) {
1057                 drm_kms_helper_poll_disable(&i915->drm);
1058
1059                 drm_atomic_helper_shutdown(&i915->drm);
1060         }
1061
1062         intel_dp_mst_suspend(i915);
1063
1064         intel_runtime_pm_disable_interrupts(i915);
1065         intel_hpd_cancel_work(i915);
1066
1067         intel_suspend_encoders(i915);
1068         intel_shutdown_encoders(i915);
1069
1070         intel_dmc_ucode_suspend(i915);
1071
1072         /*
1073          * The only requirement is to reboot with display DC states disabled,
1074          * for now leaving all display power wells in the INIT power domain
1075          * enabled.
1076          *
1077          * TODO:
1078          * - unify the pci_driver::shutdown sequence here with the
1079          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1080          * - unify the driver remove and system/runtime suspend sequences with
1081          *   the above unified shutdown/poweroff sequence.
1082          */
1083         intel_power_domains_driver_remove(i915);
1084         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1085
1086         intel_runtime_pm_driver_release(&i915->runtime_pm);
1087 }
1088
1089 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1090 {
1091 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1092         if (acpi_target_system_state() < ACPI_STATE_S3)
1093                 return true;
1094 #endif
1095         return false;
1096 }
1097
1098 static int i915_drm_prepare(struct drm_device *dev)
1099 {
1100         struct drm_i915_private *i915 = to_i915(dev);
1101
1102         /*
1103          * NB intel_display_suspend() may issue new requests after we've
1104          * ostensibly marked the GPU as ready-to-sleep here. We need to
1105          * split out that work and pull it forward so that after point,
1106          * the GPU is not woken again.
1107          */
1108         return i915_gem_backup_suspend(i915);
1109 }
1110
1111 static int i915_drm_suspend(struct drm_device *dev)
1112 {
1113         struct drm_i915_private *dev_priv = to_i915(dev);
1114         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1115         pci_power_t opregion_target_state;
1116
1117         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1118
1119         /* We do a lot of poking in a lot of registers, make sure they work
1120          * properly. */
1121         intel_power_domains_disable(dev_priv);
1122         if (HAS_DISPLAY(dev_priv))
1123                 drm_kms_helper_poll_disable(dev);
1124
1125         pci_save_state(pdev);
1126
1127         intel_display_suspend(dev);
1128
1129         intel_dp_mst_suspend(dev_priv);
1130
1131         intel_runtime_pm_disable_interrupts(dev_priv);
1132         intel_hpd_cancel_work(dev_priv);
1133
1134         intel_suspend_encoders(dev_priv);
1135
1136         intel_suspend_hw(dev_priv);
1137
1138         /* Must be called before GGTT is suspended. */
1139         intel_dpt_suspend(dev_priv);
1140         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1141
1142         i915_save_display(dev_priv);
1143
1144         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1145         intel_opregion_suspend(dev_priv, opregion_target_state);
1146
1147         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1148
1149         dev_priv->suspend_count++;
1150
1151         intel_dmc_ucode_suspend(dev_priv);
1152
1153         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1154
1155         return 0;
1156 }
1157
1158 static enum i915_drm_suspend_mode
1159 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1160 {
1161         if (hibernate)
1162                 return I915_DRM_SUSPEND_HIBERNATE;
1163
1164         if (suspend_to_idle(dev_priv))
1165                 return I915_DRM_SUSPEND_IDLE;
1166
1167         return I915_DRM_SUSPEND_MEM;
1168 }
1169
1170 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1171 {
1172         struct drm_i915_private *dev_priv = to_i915(dev);
1173         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1174         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1175         int ret;
1176
1177         disable_rpm_wakeref_asserts(rpm);
1178
1179         i915_gem_suspend_late(dev_priv);
1180
1181         intel_uncore_suspend(&dev_priv->uncore);
1182
1183         intel_power_domains_suspend(dev_priv,
1184                                     get_suspend_mode(dev_priv, hibernation));
1185
1186         intel_display_power_suspend_late(dev_priv);
1187
1188         ret = vlv_suspend_complete(dev_priv);
1189         if (ret) {
1190                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1191                 intel_power_domains_resume(dev_priv);
1192
1193                 goto out;
1194         }
1195
1196         /*
1197          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1198          * This should be totally removed when we handle the pci states properly
1199          * on runtime PM and on s2idle cases.
1200          */
1201         if (suspend_to_idle(dev_priv))
1202                 pci_d3cold_disable(pdev);
1203
1204         pci_disable_device(pdev);
1205         /*
1206          * During hibernation on some platforms the BIOS may try to access
1207          * the device even though it's already in D3 and hang the machine. So
1208          * leave the device in D0 on those platforms and hope the BIOS will
1209          * power down the device properly. The issue was seen on multiple old
1210          * GENs with different BIOS vendors, so having an explicit blacklist
1211          * is inpractical; apply the workaround on everything pre GEN6. The
1212          * platforms where the issue was seen:
1213          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1214          * Fujitsu FSC S7110
1215          * Acer Aspire 1830T
1216          */
1217         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1218                 pci_set_power_state(pdev, PCI_D3hot);
1219
1220 out:
1221         enable_rpm_wakeref_asserts(rpm);
1222         if (!dev_priv->uncore.user_forcewake_count)
1223                 intel_runtime_pm_driver_release(rpm);
1224
1225         return ret;
1226 }
1227
1228 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1229                                    pm_message_t state)
1230 {
1231         int error;
1232
1233         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1234                              state.event != PM_EVENT_FREEZE))
1235                 return -EINVAL;
1236
1237         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1238                 return 0;
1239
1240         error = i915_drm_suspend(&i915->drm);
1241         if (error)
1242                 return error;
1243
1244         return i915_drm_suspend_late(&i915->drm, false);
1245 }
1246
1247 static int i915_drm_resume(struct drm_device *dev)
1248 {
1249         struct drm_i915_private *dev_priv = to_i915(dev);
1250         int ret;
1251
1252         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1253
1254         ret = intel_pcode_init(&dev_priv->uncore);
1255         if (ret)
1256                 return ret;
1257
1258         sanitize_gpu(dev_priv);
1259
1260         ret = i915_ggtt_enable_hw(dev_priv);
1261         if (ret)
1262                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1263
1264         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1265         /* Must be called after GGTT is resumed. */
1266         intel_dpt_resume(dev_priv);
1267
1268         intel_dmc_ucode_resume(dev_priv);
1269
1270         i915_restore_display(dev_priv);
1271         intel_pps_unlock_regs_wa(dev_priv);
1272
1273         intel_init_pch_refclk(dev_priv);
1274
1275         /*
1276          * Interrupts have to be enabled before any batches are run. If not the
1277          * GPU will hang. i915_gem_init_hw() will initiate batches to
1278          * update/restore the context.
1279          *
1280          * drm_mode_config_reset() needs AUX interrupts.
1281          *
1282          * Modeset enabling in intel_modeset_init_hw() also needs working
1283          * interrupts.
1284          */
1285         intel_runtime_pm_enable_interrupts(dev_priv);
1286
1287         if (HAS_DISPLAY(dev_priv))
1288                 drm_mode_config_reset(dev);
1289
1290         i915_gem_resume(dev_priv);
1291
1292         intel_modeset_init_hw(dev_priv);
1293         intel_init_clock_gating(dev_priv);
1294         intel_hpd_init(dev_priv);
1295
1296         /* MST sideband requires HPD interrupts enabled */
1297         intel_dp_mst_resume(dev_priv);
1298         intel_display_resume(dev);
1299
1300         intel_hpd_poll_disable(dev_priv);
1301         if (HAS_DISPLAY(dev_priv))
1302                 drm_kms_helper_poll_enable(dev);
1303
1304         intel_opregion_resume(dev_priv);
1305
1306         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1307
1308         intel_power_domains_enable(dev_priv);
1309
1310         intel_gvt_resume(dev_priv);
1311
1312         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1313
1314         return 0;
1315 }
1316
1317 static int i915_drm_resume_early(struct drm_device *dev)
1318 {
1319         struct drm_i915_private *dev_priv = to_i915(dev);
1320         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1321         int ret;
1322
1323         /*
1324          * We have a resume ordering issue with the snd-hda driver also
1325          * requiring our device to be power up. Due to the lack of a
1326          * parent/child relationship we currently solve this with an early
1327          * resume hook.
1328          *
1329          * FIXME: This should be solved with a special hdmi sink device or
1330          * similar so that power domains can be employed.
1331          */
1332
1333         /*
1334          * Note that we need to set the power state explicitly, since we
1335          * powered off the device during freeze and the PCI core won't power
1336          * it back up for us during thaw. Powering off the device during
1337          * freeze is not a hard requirement though, and during the
1338          * suspend/resume phases the PCI core makes sure we get here with the
1339          * device powered on. So in case we change our freeze logic and keep
1340          * the device powered we can also remove the following set power state
1341          * call.
1342          */
1343         ret = pci_set_power_state(pdev, PCI_D0);
1344         if (ret) {
1345                 drm_err(&dev_priv->drm,
1346                         "failed to set PCI D0 power state (%d)\n", ret);
1347                 return ret;
1348         }
1349
1350         /*
1351          * Note that pci_enable_device() first enables any parent bridge
1352          * device and only then sets the power state for this device. The
1353          * bridge enabling is a nop though, since bridge devices are resumed
1354          * first. The order of enabling power and enabling the device is
1355          * imposed by the PCI core as described above, so here we preserve the
1356          * same order for the freeze/thaw phases.
1357          *
1358          * TODO: eventually we should remove pci_disable_device() /
1359          * pci_enable_enable_device() from suspend/resume. Due to how they
1360          * depend on the device enable refcount we can't anyway depend on them
1361          * disabling/enabling the device.
1362          */
1363         if (pci_enable_device(pdev))
1364                 return -EIO;
1365
1366         pci_set_master(pdev);
1367
1368         pci_d3cold_enable(pdev);
1369
1370         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1371
1372         ret = vlv_resume_prepare(dev_priv, false);
1373         if (ret)
1374                 drm_err(&dev_priv->drm,
1375                         "Resume prepare failed: %d, continuing anyway\n", ret);
1376
1377         intel_uncore_resume_early(&dev_priv->uncore);
1378
1379         intel_gt_check_and_clear_faults(to_gt(dev_priv));
1380
1381         intel_display_power_resume_early(dev_priv);
1382
1383         intel_power_domains_resume(dev_priv);
1384
1385         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1386
1387         return ret;
1388 }
1389
1390 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1391 {
1392         int ret;
1393
1394         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1395                 return 0;
1396
1397         ret = i915_drm_resume_early(&i915->drm);
1398         if (ret)
1399                 return ret;
1400
1401         return i915_drm_resume(&i915->drm);
1402 }
1403
1404 static int i915_pm_prepare(struct device *kdev)
1405 {
1406         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1407
1408         if (!i915) {
1409                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1410                 return -ENODEV;
1411         }
1412
1413         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1414                 return 0;
1415
1416         return i915_drm_prepare(&i915->drm);
1417 }
1418
1419 static int i915_pm_suspend(struct device *kdev)
1420 {
1421         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1422
1423         if (!i915) {
1424                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1425                 return -ENODEV;
1426         }
1427
1428         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1429                 return 0;
1430
1431         return i915_drm_suspend(&i915->drm);
1432 }
1433
1434 static int i915_pm_suspend_late(struct device *kdev)
1435 {
1436         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1437
1438         /*
1439          * We have a suspend ordering issue with the snd-hda driver also
1440          * requiring our device to be power up. Due to the lack of a
1441          * parent/child relationship we currently solve this with an late
1442          * suspend hook.
1443          *
1444          * FIXME: This should be solved with a special hdmi sink device or
1445          * similar so that power domains can be employed.
1446          */
1447         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1448                 return 0;
1449
1450         return i915_drm_suspend_late(&i915->drm, false);
1451 }
1452
1453 static int i915_pm_poweroff_late(struct device *kdev)
1454 {
1455         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1456
1457         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1458                 return 0;
1459
1460         return i915_drm_suspend_late(&i915->drm, true);
1461 }
1462
1463 static int i915_pm_resume_early(struct device *kdev)
1464 {
1465         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1466
1467         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1468                 return 0;
1469
1470         return i915_drm_resume_early(&i915->drm);
1471 }
1472
1473 static int i915_pm_resume(struct device *kdev)
1474 {
1475         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1476
1477         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1478                 return 0;
1479
1480         return i915_drm_resume(&i915->drm);
1481 }
1482
1483 /* freeze: before creating the hibernation_image */
1484 static int i915_pm_freeze(struct device *kdev)
1485 {
1486         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1487         int ret;
1488
1489         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1490                 ret = i915_drm_suspend(&i915->drm);
1491                 if (ret)
1492                         return ret;
1493         }
1494
1495         ret = i915_gem_freeze(i915);
1496         if (ret)
1497                 return ret;
1498
1499         return 0;
1500 }
1501
1502 static int i915_pm_freeze_late(struct device *kdev)
1503 {
1504         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1505         int ret;
1506
1507         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1508                 ret = i915_drm_suspend_late(&i915->drm, true);
1509                 if (ret)
1510                         return ret;
1511         }
1512
1513         ret = i915_gem_freeze_late(i915);
1514         if (ret)
1515                 return ret;
1516
1517         return 0;
1518 }
1519
1520 /* thaw: called after creating the hibernation image, but before turning off. */
1521 static int i915_pm_thaw_early(struct device *kdev)
1522 {
1523         return i915_pm_resume_early(kdev);
1524 }
1525
1526 static int i915_pm_thaw(struct device *kdev)
1527 {
1528         return i915_pm_resume(kdev);
1529 }
1530
1531 /* restore: called after loading the hibernation image. */
1532 static int i915_pm_restore_early(struct device *kdev)
1533 {
1534         return i915_pm_resume_early(kdev);
1535 }
1536
1537 static int i915_pm_restore(struct device *kdev)
1538 {
1539         return i915_pm_resume(kdev);
1540 }
1541
1542 static int intel_runtime_suspend(struct device *kdev)
1543 {
1544         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1545         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1546         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1547         int ret;
1548
1549         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1550                 return -ENODEV;
1551
1552         drm_dbg(&dev_priv->drm, "Suspending device\n");
1553
1554         disable_rpm_wakeref_asserts(rpm);
1555
1556         /*
1557          * We are safe here against re-faults, since the fault handler takes
1558          * an RPM reference.
1559          */
1560         i915_gem_runtime_suspend(dev_priv);
1561
1562         intel_gt_runtime_suspend(to_gt(dev_priv));
1563
1564         intel_runtime_pm_disable_interrupts(dev_priv);
1565
1566         intel_uncore_suspend(&dev_priv->uncore);
1567
1568         intel_display_power_suspend(dev_priv);
1569
1570         ret = vlv_suspend_complete(dev_priv);
1571         if (ret) {
1572                 drm_err(&dev_priv->drm,
1573                         "Runtime suspend failed, disabling it (%d)\n", ret);
1574                 intel_uncore_runtime_resume(&dev_priv->uncore);
1575
1576                 intel_runtime_pm_enable_interrupts(dev_priv);
1577
1578                 intel_gt_runtime_resume(to_gt(dev_priv));
1579
1580                 enable_rpm_wakeref_asserts(rpm);
1581
1582                 return ret;
1583         }
1584
1585         enable_rpm_wakeref_asserts(rpm);
1586         intel_runtime_pm_driver_release(rpm);
1587
1588         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1589                 drm_err(&dev_priv->drm,
1590                         "Unclaimed access detected prior to suspending\n");
1591
1592         /*
1593          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1594          * This should be totally removed when we handle the pci states properly
1595          * on runtime PM and on s2idle cases.
1596          */
1597         pci_d3cold_disable(pdev);
1598         rpm->suspended = true;
1599
1600         /*
1601          * FIXME: We really should find a document that references the arguments
1602          * used below!
1603          */
1604         if (IS_BROADWELL(dev_priv)) {
1605                 /*
1606                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1607                  * being detected, and the call we do at intel_runtime_resume()
1608                  * won't be able to restore them. Since PCI_D3hot matches the
1609                  * actual specification and appears to be working, use it.
1610                  */
1611                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1612         } else {
1613                 /*
1614                  * current versions of firmware which depend on this opregion
1615                  * notification have repurposed the D1 definition to mean
1616                  * "runtime suspended" vs. what you would normally expect (D3)
1617                  * to distinguish it from notifications that might be sent via
1618                  * the suspend path.
1619                  */
1620                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1621         }
1622
1623         assert_forcewakes_inactive(&dev_priv->uncore);
1624
1625         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1626                 intel_hpd_poll_enable(dev_priv);
1627
1628         drm_dbg(&dev_priv->drm, "Device suspended\n");
1629         return 0;
1630 }
1631
1632 static int intel_runtime_resume(struct device *kdev)
1633 {
1634         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1635         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1636         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1637         int ret;
1638
1639         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1640                 return -ENODEV;
1641
1642         drm_dbg(&dev_priv->drm, "Resuming device\n");
1643
1644         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1645         disable_rpm_wakeref_asserts(rpm);
1646
1647         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1648         rpm->suspended = false;
1649         pci_d3cold_enable(pdev);
1650         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1651                 drm_dbg(&dev_priv->drm,
1652                         "Unclaimed access during suspend, bios?\n");
1653
1654         intel_display_power_resume(dev_priv);
1655
1656         ret = vlv_resume_prepare(dev_priv, true);
1657
1658         intel_uncore_runtime_resume(&dev_priv->uncore);
1659
1660         intel_runtime_pm_enable_interrupts(dev_priv);
1661
1662         /*
1663          * No point of rolling back things in case of an error, as the best
1664          * we can do is to hope that things will still work (and disable RPM).
1665          */
1666         intel_gt_runtime_resume(to_gt(dev_priv));
1667
1668         /*
1669          * On VLV/CHV display interrupts are part of the display
1670          * power well, so hpd is reinitialized from there. For
1671          * everyone else do it here.
1672          */
1673         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1674                 intel_hpd_init(dev_priv);
1675                 intel_hpd_poll_disable(dev_priv);
1676         }
1677
1678         intel_enable_ipc(dev_priv);
1679
1680         enable_rpm_wakeref_asserts(rpm);
1681
1682         if (ret)
1683                 drm_err(&dev_priv->drm,
1684                         "Runtime resume failed, disabling it (%d)\n", ret);
1685         else
1686                 drm_dbg(&dev_priv->drm, "Device resumed\n");
1687
1688         return ret;
1689 }
1690
1691 const struct dev_pm_ops i915_pm_ops = {
1692         /*
1693          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1694          * PMSG_RESUME]
1695          */
1696         .prepare = i915_pm_prepare,
1697         .suspend = i915_pm_suspend,
1698         .suspend_late = i915_pm_suspend_late,
1699         .resume_early = i915_pm_resume_early,
1700         .resume = i915_pm_resume,
1701
1702         /*
1703          * S4 event handlers
1704          * @freeze, @freeze_late    : called (1) before creating the
1705          *                            hibernation image [PMSG_FREEZE] and
1706          *                            (2) after rebooting, before restoring
1707          *                            the image [PMSG_QUIESCE]
1708          * @thaw, @thaw_early       : called (1) after creating the hibernation
1709          *                            image, before writing it [PMSG_THAW]
1710          *                            and (2) after failing to create or
1711          *                            restore the image [PMSG_RECOVER]
1712          * @poweroff, @poweroff_late: called after writing the hibernation
1713          *                            image, before rebooting [PMSG_HIBERNATE]
1714          * @restore, @restore_early : called after rebooting and restoring the
1715          *                            hibernation image [PMSG_RESTORE]
1716          */
1717         .freeze = i915_pm_freeze,
1718         .freeze_late = i915_pm_freeze_late,
1719         .thaw_early = i915_pm_thaw_early,
1720         .thaw = i915_pm_thaw,
1721         .poweroff = i915_pm_suspend,
1722         .poweroff_late = i915_pm_poweroff_late,
1723         .restore_early = i915_pm_restore_early,
1724         .restore = i915_pm_restore,
1725
1726         /* S0ix (via runtime suspend) event handlers */
1727         .runtime_suspend = intel_runtime_suspend,
1728         .runtime_resume = intel_runtime_resume,
1729 };
1730
1731 static const struct file_operations i915_driver_fops = {
1732         .owner = THIS_MODULE,
1733         .open = drm_open,
1734         .release = drm_release_noglobal,
1735         .unlocked_ioctl = drm_ioctl,
1736         .mmap = i915_gem_mmap,
1737         .poll = drm_poll,
1738         .read = drm_read,
1739         .compat_ioctl = i915_ioc32_compat_ioctl,
1740         .llseek = noop_llseek,
1741 #ifdef CONFIG_PROC_FS
1742         .show_fdinfo = i915_drm_client_fdinfo,
1743 #endif
1744 };
1745
1746 static int
1747 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1748                           struct drm_file *file)
1749 {
1750         return -ENODEV;
1751 }
1752
1753 static const struct drm_ioctl_desc i915_ioctls[] = {
1754         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1755         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1756         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1757         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1758         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1759         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1760         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1761         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1762         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1763         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1764         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1765         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1766         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1767         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1768         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1769         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1770         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1771         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1772         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1773         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1774         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1775         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1778         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1779         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1780         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1781         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1782         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1783         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1784         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1785         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1786         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1787         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1788         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1789         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1790         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1791         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1792         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1793         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1794         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1795         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1796         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1797         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1798         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1799         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1800         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1801         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1802         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1803         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1804         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1805         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1806         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1807         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1808         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1809         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1810         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1811         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1812         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1813 };
1814
1815 /*
1816  * Interface history:
1817  *
1818  * 1.1: Original.
1819  * 1.2: Add Power Management
1820  * 1.3: Add vblank support
1821  * 1.4: Fix cmdbuffer path, add heap destroy
1822  * 1.5: Add vblank pipe configuration
1823  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1824  *      - Support vertical blank on secondary display pipe
1825  */
1826 #define DRIVER_MAJOR            1
1827 #define DRIVER_MINOR            6
1828 #define DRIVER_PATCHLEVEL       0
1829
1830 static const struct drm_driver i915_drm_driver = {
1831         /* Don't use MTRRs here; the Xserver or userspace app should
1832          * deal with them for Intel hardware.
1833          */
1834         .driver_features =
1835             DRIVER_GEM |
1836             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1837             DRIVER_SYNCOBJ_TIMELINE,
1838         .release = i915_driver_release,
1839         .open = i915_driver_open,
1840         .lastclose = i915_driver_lastclose,
1841         .postclose = i915_driver_postclose,
1842
1843         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1844         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1845         .gem_prime_import = i915_gem_prime_import,
1846
1847         .dumb_create = i915_gem_dumb_create,
1848         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1849
1850         .ioctls = i915_ioctls,
1851         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1852         .fops = &i915_driver_fops,
1853         .name = DRIVER_NAME,
1854         .desc = DRIVER_DESC,
1855         .date = DRIVER_DATE,
1856         .major = DRIVER_MAJOR,
1857         .minor = DRIVER_MINOR,
1858         .patchlevel = DRIVER_PATCHLEVEL,
1859 };