drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_display_types.h"
  52 #include "display/intel_dmc.h"
  53 #include "display/intel_dp.h"
  54 #include "display/intel_dpt.h"
  55 #include "display/intel_fbdev.h"
  56 #include "display/intel_hotplug.h"
  57 #include "display/intel_overlay.h"
  58 #include "display/intel_pch_refclk.h"
  59 #include "display/intel_pipe_crc.h"
  60 #include "display/intel_pps.h"
  61 #include "display/intel_sprite.h"
  62 #include "display/intel_vga.h"
  63
  64 #include "gem/i915_gem_context.h"
  65 #include "gem/i915_gem_create.h"
  66 #include "gem/i915_gem_dmabuf.h"
  67 #include "gem/i915_gem_ioctls.h"
  68 #include "gem/i915_gem_mman.h"
  69 #include "gem/i915_gem_pm.h"
  70 #include "gt/intel_gt.h"
  71 #include "gt/intel_gt_pm.h"
  72 #include "gt/intel_rc6.h"
  73
  74 #include "pxp/intel_pxp_pm.h"
  75
  76 #include "i915_file_private.h"
  77 #include "i915_debugfs.h"
  78 #include "i915_driver.h"
  79 #include "i915_drm_client.h"
  80 #include "i915_drv.h"
  81 #include "i915_getparam.h"
  82 #include "i915_ioc32.h"
  83 #include "i915_ioctl.h"
  84 #include "i915_irq.h"
  85 #include "i915_memcpy.h"
  86 #include "i915_perf.h"
  87 #include "i915_query.h"
  88 #include "i915_suspend.h"
  89 #include "i915_switcheroo.h"
  90 #include "i915_sysfs.h"
  91 #include "i915_vgpu.h"
  92 #include "intel_dram.h"
  93 #include "intel_gvt.h"
  94 #include "intel_memory_region.h"
  95 #include "intel_pci_config.h"
  96 #include "intel_pcode.h"
  97 #include "intel_pm.h"
  98 #include "intel_region_ttm.h"
  99 #include "vlv_suspend.h"
 100
 101 static const struct drm_driver i915_drm_driver;
 102
 103 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 104 {
 105         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
 106
 107         dev_priv->bridge_dev =
 108                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 109         if (!dev_priv->bridge_dev) {
 110                 drm_err(&dev_priv->drm, "bridge device not found\n");
 111                 return -EIO;
 112         }
 113         return 0;
 114 }
 115
 116 /* Allocate space for the MCH regs if needed, return nonzero on error */
 117 static int
 118 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 119 {
 120         int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 121         u32 temp_lo, temp_hi = 0;
 122         u64 mchbar_addr;
 123         int ret;
 124
 125         if (GRAPHICS_VER(dev_priv) >= 4)
 126                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 127         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 128         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 129
 130         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 131 #ifdef CONFIG_PNP
 132         if (mchbar_addr &&
 133             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 134                 return 0;
 135 #endif
 136
 137         /* Get some space for it */
 138         dev_priv->mch_res.name = "i915 MCHBAR";
 139         dev_priv->mch_res.flags = IORESOURCE_MEM;
 140         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 141                                      &dev_priv->mch_res,
 142                                      MCHBAR_SIZE, MCHBAR_SIZE,
 143                                      PCIBIOS_MIN_MEM,
 144                                      0, pcibios_align_resource,
 145                                      dev_priv->bridge_dev);
 146         if (ret) {
 147                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 148                 dev_priv->mch_res.start = 0;
 149                 return ret;
 150         }
 151
 152         if (GRAPHICS_VER(dev_priv) >= 4)
 153                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 154                                        upper_32_bits(dev_priv->mch_res.start));
 155
 156         pci_write_config_dword(dev_priv->bridge_dev, reg,
 157                                lower_32_bits(dev_priv->mch_res.start));
 158         return 0;
 159 }
 160
 161 /* Setup MCHBAR if possible, return true if we should disable it again */
 162 static void
 163 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 164 {
 165         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 166         u32 temp;
 167         bool enabled;
 168
 169         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 170                 return;
 171
 172         dev_priv->mchbar_need_disable = false;
 173
 174         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 175                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 176                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 177         } else {
 178                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 179                 enabled = temp & 1;
 180         }
 181
 182         /* If it's already enabled, don't have to do anything */
 183         if (enabled)
 184                 return;
 185
 186         if (intel_alloc_mchbar_resource(dev_priv))
 187                 return;
 188
 189         dev_priv->mchbar_need_disable = true;
 190
 191         /* Space is allocated or reserved, so enable it. */
 192         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 193                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 194                                        temp | DEVEN_MCHBAR_EN);
 195         } else {
 196                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 197                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 198         }
 199 }
 200
 201 static void
 202 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 203 {
 204         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 205
 206         if (dev_priv->mchbar_need_disable) {
 207                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 208                         u32 deven_val;
 209
 210                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 211                                               &deven_val);
 212                         deven_val &= ~DEVEN_MCHBAR_EN;
 213                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 214                                                deven_val);
 215                 } else {
 216                         u32 mchbar_val;
 217
 218                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 219                                               &mchbar_val);
 220                         mchbar_val &= ~1;
 221                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 222                                                mchbar_val);
 223                 }
 224         }
 225
 226         if (dev_priv->mch_res.start)
 227                 release_resource(&dev_priv->mch_res);
 228 }
 229
 230 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 231 {
 232         /*
 233          * The i915 workqueue is primarily used for batched retirement of
 234          * requests (and thus managing bo) once the task has been completed
 235          * by the GPU. i915_retire_requests() is called directly when we
 236          * need high-priority retirement, such as waiting for an explicit
 237          * bo.
 238          *
 239          * It is also used for periodic low-priority events, such as
 240          * idle-timers and recording error state.
 241          *
 242          * All tasks on the workqueue are expected to acquire the dev mutex
 243          * so there is no point in running more than one instance of the
 244          * workqueue at any time.  Use an ordered one.
 245          */
 246         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 247         if (dev_priv->wq == NULL)
 248                 goto out_err;
 249
 250         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 251         if (dev_priv->hotplug.dp_wq == NULL)
 252                 goto out_free_wq;
 253
 254         return 0;
 255
 256 out_free_wq:
 257         destroy_workqueue(dev_priv->wq);
 258 out_err:
 259         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 260
 261         return -ENOMEM;
 262 }
 263
 264 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 265 {
 266         destroy_workqueue(dev_priv->hotplug.dp_wq);
 267         destroy_workqueue(dev_priv->wq);
 268 }
 269
 270 /*
 271  * We don't keep the workarounds for pre-production hardware, so we expect our
 272  * driver to fail on these machines in one way or another. A little warning on
 273  * dmesg may help both the user and the bug triagers.
 274  *
 275  * Our policy for removing pre-production workarounds is to keep the
 276  * current gen workarounds as a guide to the bring-up of the next gen
 277  * (workarounds have a habit of persisting!). Anything older than that
 278  * should be removed along with the complications they introduce.
 279  */
 280 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 281 {
 282         bool pre = false;
 283
 284         pre |= IS_HSW_EARLY_SDV(dev_priv);
 285         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 286         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 287         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 288         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 289         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 290
 291         if (pre) {
 292                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 293                           "It may not be fully functional.\n");
 294                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 295         }
 296 }
 297
 298 static void sanitize_gpu(struct drm_i915_private *i915)
 299 {
 300         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 301                 __intel_gt_reset(to_gt(i915), ALL_ENGINES);
 302 }
 303
 304 /**
 305  * i915_driver_early_probe - setup state not requiring device access
 306  * @dev_priv: device private
 307  *
 308  * Initialize everything that is a "SW-only" state, that is state not
 309  * requiring accessing the device or exposing the driver via kernel internal
 310  * or userspace interfaces. Example steps belonging here: lock initialization,
 311  * system memory allocation, setting up device specific attributes and
 312  * function hooks not requiring accessing the device.
 313  */
 314 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 315 {
 316         int ret = 0;
 317
 318         if (i915_inject_probe_failure(dev_priv))
 319                 return -ENODEV;
 320
 321         intel_device_info_subplatform_init(dev_priv);
 322         intel_step_init(dev_priv);
 323
 324         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 325
 326         spin_lock_init(&dev_priv->irq_lock);
 327         spin_lock_init(&dev_priv->gpu_error.lock);
 328         mutex_init(&dev_priv->backlight_lock);
 329
 330         mutex_init(&dev_priv->sb_lock);
 331         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 332
 333         mutex_init(&dev_priv->audio.mutex);
 334         mutex_init(&dev_priv->wm.wm_mutex);
 335         mutex_init(&dev_priv->pps_mutex);
 336         mutex_init(&dev_priv->hdcp_comp_mutex);
 337
 338         i915_memcpy_init_early(dev_priv);
 339         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 340
 341         ret = i915_workqueues_init(dev_priv);
 342         if (ret < 0)
 343                 return ret;
 344
 345         ret = vlv_suspend_init(dev_priv);
 346         if (ret < 0)
 347                 goto err_workqueues;
 348
 349         ret = intel_region_ttm_device_init(dev_priv);
 350         if (ret)
 351                 goto err_ttm;
 352
 353         intel_wopcm_init_early(&dev_priv->wopcm);
 354
 355         intel_root_gt_init_early(dev_priv);
 356
 357         i915_drm_clients_init(&dev_priv->clients, dev_priv);
 358
 359         i915_gem_init_early(dev_priv);
 360
 361         /* This must be called before any calls to HAS_PCH_* */
 362         intel_detect_pch(dev_priv);
 363
 364         intel_pm_setup(dev_priv);
 365         ret = intel_power_domains_init(dev_priv);
 366         if (ret < 0)
 367                 goto err_gem;
 368         intel_irq_init(dev_priv);
 369         intel_init_display_hooks(dev_priv);
 370         intel_init_clock_gating_hooks(dev_priv);
 371
 372         intel_detect_preproduction_hw(dev_priv);
 373
 374         return 0;
 375
 376 err_gem:
 377         i915_gem_cleanup_early(dev_priv);
 378         intel_gt_driver_late_release_all(dev_priv);
 379         i915_drm_clients_fini(&dev_priv->clients);
 380         intel_region_ttm_device_fini(dev_priv);
 381 err_ttm:
 382         vlv_suspend_cleanup(dev_priv);
 383 err_workqueues:
 384         i915_workqueues_cleanup(dev_priv);
 385         return ret;
 386 }
 387
 388 /**
 389  * i915_driver_late_release - cleanup the setup done in
 390  *                             i915_driver_early_probe()
 391  * @dev_priv: device private
 392  */
 393 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 394 {
 395         intel_irq_fini(dev_priv);
 396         intel_power_domains_cleanup(dev_priv);
 397         i915_gem_cleanup_early(dev_priv);
 398         intel_gt_driver_late_release_all(dev_priv);
 399         i915_drm_clients_fini(&dev_priv->clients);
 400         intel_region_ttm_device_fini(dev_priv);
 401         vlv_suspend_cleanup(dev_priv);
 402         i915_workqueues_cleanup(dev_priv);
 403
 404         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 405         mutex_destroy(&dev_priv->sb_lock);
 406
 407         i915_params_free(&dev_priv->params);
 408 }
 409
 410 /**
 411  * i915_driver_mmio_probe - setup device MMIO
 412  * @dev_priv: device private
 413  *
 414  * Setup minimal device state necessary for MMIO accesses later in the
 415  * initialization sequence. The setup here should avoid any other device-wide
 416  * side effects or exposing the driver via kernel internal or user space
 417  * interfaces.
 418  */
 419 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 420 {
 421         int ret;
 422
 423         if (i915_inject_probe_failure(dev_priv))
 424                 return -ENODEV;
 425
 426         ret = i915_get_bridge_dev(dev_priv);
 427         if (ret < 0)
 428                 return ret;
 429
 430         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 431         if (ret)
 432                 return ret;
 433
 434         /* Try to make sure MCHBAR is enabled before poking at it */
 435         intel_setup_mchbar(dev_priv);
 436         intel_device_info_runtime_init(dev_priv);
 437
 438         ret = intel_gt_init_mmio(to_gt(dev_priv));
 439         if (ret)
 440                 goto err_uncore;
 441
 442         /* As early as possible, scrub existing GPU state before clobbering */
 443         sanitize_gpu(dev_priv);
 444
 445         return 0;
 446
 447 err_uncore:
 448         intel_teardown_mchbar(dev_priv);
 449         intel_uncore_fini_mmio(&dev_priv->uncore);
 450         pci_dev_put(dev_priv->bridge_dev);
 451
 452         return ret;
 453 }
 454
 455 /**
 456  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 457  * @dev_priv: device private
 458  */
 459 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 460 {
 461         intel_teardown_mchbar(dev_priv);
 462         intel_uncore_fini_mmio(&dev_priv->uncore);
 463         pci_dev_put(dev_priv->bridge_dev);
 464 }
 465
 466 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 467 {
 468         intel_gvt_sanitize_options(dev_priv);
 469 }
 470
 471 /**
 472  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 473  * platform
 474  * @i915: valid i915 instance
 475  *
 476  * Set the dma max segment size, device and coherent masks.  The dma mask set
 477  * needs to occur before i915_ggtt_probe_hw.
 478  *
 479  * A couple of platforms have special needs.  Address them as well.
 480  *
 481  */
 482 static int i915_set_dma_info(struct drm_i915_private *i915)
 483 {
 484         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 485         int ret;
 486
 487         GEM_BUG_ON(!mask_size);
 488
 489         /*
 490          * We don't have a max segment size, so set it to the max so sg's
 491          * debugging layer doesn't complain
 492          */
 493         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 494
 495         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 496         if (ret)
 497                 goto mask_err;
 498
 499         /* overlay on gen2 is broken and can't address above 1G */
 500         if (GRAPHICS_VER(i915) == 2)
 501                 mask_size = 30;
 502
 503         /*
 504          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 505          * using 32bit addressing, overwriting memory if HWS is located
 506          * above 4GB.
 507          *
 508          * The documentation also mentions an issue with undefined
 509          * behaviour if any general state is accessed within a page above 4GB,
 510          * which also needs to be handled carefully.
 511          */
 512         if (IS_I965G(i915) || IS_I965GM(i915))
 513                 mask_size = 32;
 514
 515         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 516         if (ret)
 517                 goto mask_err;
 518
 519         return 0;
 520
 521 mask_err:
 522         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 523         return ret;
 524 }
 525
 526 /**
 527  * i915_driver_hw_probe - setup state requiring device access
 528  * @dev_priv: device private
 529  *
 530  * Setup state that requires accessing the device, but doesn't require
 531  * exposing the driver via kernel internal or userspace interfaces.
 532  */
 533 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 534 {
 535         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 536         int ret;
 537
 538         if (i915_inject_probe_failure(dev_priv))
 539                 return -ENODEV;
 540
 541         if (HAS_PPGTT(dev_priv)) {
 542                 if (intel_vgpu_active(dev_priv) &&
 543                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 544                         i915_report_error(dev_priv,
 545                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 546                         return -ENXIO;
 547                 }
 548         }
 549
 550         if (HAS_EXECLISTS(dev_priv)) {
 551                 /*
 552                  * Older GVT emulation depends upon intercepting CSB mmio,
 553                  * which we no longer use, preferring to use the HWSP cache
 554                  * instead.
 555                  */
 556                 if (intel_vgpu_active(dev_priv) &&
 557                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 558                         i915_report_error(dev_priv,
 559                                           "old vGPU host found, support for HWSP emulation required\n");
 560                         return -ENXIO;
 561                 }
 562         }
 563
 564         intel_sanitize_options(dev_priv);
 565
 566         /* needs to be done before ggtt probe */
 567         intel_dram_edram_detect(dev_priv);
 568
 569         ret = i915_set_dma_info(dev_priv);
 570         if (ret)
 571                 return ret;
 572
 573         i915_perf_init(dev_priv);
 574
 575         ret = intel_gt_assign_ggtt(to_gt(dev_priv));
 576         if (ret)
 577                 goto err_perf;
 578
 579         ret = i915_ggtt_probe_hw(dev_priv);
 580         if (ret)
 581                 goto err_perf;
 582
 583         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 584         if (ret)
 585                 goto err_ggtt;
 586
 587         ret = i915_ggtt_init_hw(dev_priv);
 588         if (ret)
 589                 goto err_ggtt;
 590
 591         ret = intel_memory_regions_hw_probe(dev_priv);
 592         if (ret)
 593                 goto err_ggtt;
 594
 595         ret = intel_gt_tiles_init(dev_priv);
 596         if (ret)
 597                 goto err_mem_regions;
 598
 599         ret = i915_ggtt_enable_hw(dev_priv);
 600         if (ret) {
 601                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 602                 goto err_mem_regions;
 603         }
 604
 605         pci_set_master(pdev);
 606
 607         /* On the 945G/GM, the chipset reports the MSI capability on the
 608          * integrated graphics even though the support isn't actually there
 609          * according to the published specs.  It doesn't appear to function
 610          * correctly in testing on 945G.
 611          * This may be a side effect of MSI having been made available for PEG
 612          * and the registers being closely associated.
 613          *
 614          * According to chipset errata, on the 965GM, MSI interrupts may
 615          * be lost or delayed, and was defeatured. MSI interrupts seem to
 616          * get lost on g4x as well, and interrupt delivery seems to stay
 617          * properly dead afterwards. So we'll just disable them for all
 618          * pre-gen5 chipsets.
 619          *
 620          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 621          * interrupts even when in MSI mode. This results in spurious
 622          * interrupt warnings if the legacy irq no. is shared with another
 623          * device. The kernel then disables that interrupt source and so
 624          * prevents the other device from working properly.
 625          */
 626         if (GRAPHICS_VER(dev_priv) >= 5) {
 627                 if (pci_enable_msi(pdev) < 0)
 628                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 629         }
 630
 631         ret = intel_gvt_init(dev_priv);
 632         if (ret)
 633                 goto err_msi;
 634
 635         intel_opregion_setup(dev_priv);
 636
 637         ret = intel_pcode_init(dev_priv);
 638         if (ret)
 639                 goto err_msi;
 640
 641         /*
 642          * Fill the dram structure to get the system dram info. This will be
 643          * used for memory latency calculation.
 644          */
 645         intel_dram_detect(dev_priv);
 646
 647         intel_bw_init_hw(dev_priv);
 648
 649         return 0;
 650
 651 err_msi:
 652         if (pdev->msi_enabled)
 653                 pci_disable_msi(pdev);
 654 err_mem_regions:
 655         intel_memory_regions_driver_release(dev_priv);
 656 err_ggtt:
 657         i915_ggtt_driver_release(dev_priv);
 658         i915_gem_drain_freed_objects(dev_priv);
 659         i915_ggtt_driver_late_release(dev_priv);
 660 err_perf:
 661         i915_perf_fini(dev_priv);
 662         return ret;
 663 }
 664
 665 /**
 666  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 667  * @dev_priv: device private
 668  */
 669 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 670 {
 671         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 672
 673         i915_perf_fini(dev_priv);
 674
 675         if (pdev->msi_enabled)
 676                 pci_disable_msi(pdev);
 677 }
 678
 679 /**
 680  * i915_driver_register - register the driver with the rest of the system
 681  * @dev_priv: device private
 682  *
 683  * Perform any steps necessary to make the driver available via kernel
 684  * internal or userspace interfaces.
 685  */
 686 static void i915_driver_register(struct drm_i915_private *dev_priv)
 687 {
 688         struct drm_device *dev = &dev_priv->drm;
 689
 690         i915_gem_driver_register(dev_priv);
 691         i915_pmu_register(dev_priv);
 692
 693         intel_vgpu_register(dev_priv);
 694
 695         /* Reveal our presence to userspace */
 696         if (drm_dev_register(dev, 0)) {
 697                 drm_err(&dev_priv->drm,
 698                         "Failed to register driver for userspace access!\n");
 699                 return;
 700         }
 701
 702         i915_debugfs_register(dev_priv);
 703         i915_setup_sysfs(dev_priv);
 704
 705         /* Depends on sysfs having been initialized */
 706         i915_perf_register(dev_priv);
 707
 708         intel_gt_driver_register(to_gt(dev_priv));
 709
 710         intel_display_driver_register(dev_priv);
 711
 712         intel_power_domains_enable(dev_priv);
 713         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 714
 715         intel_register_dsm_handler();
 716
 717         if (i915_switcheroo_register(dev_priv))
 718                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 719 }
 720
 721 /**
 722  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 723  * @dev_priv: device private
 724  */
 725 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 726 {
 727         i915_switcheroo_unregister(dev_priv);
 728
 729         intel_unregister_dsm_handler();
 730
 731         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 732         intel_power_domains_disable(dev_priv);
 733
 734         intel_display_driver_unregister(dev_priv);
 735
 736         intel_gt_driver_unregister(to_gt(dev_priv));
 737
 738         i915_perf_unregister(dev_priv);
 739         i915_pmu_unregister(dev_priv);
 740
 741         i915_teardown_sysfs(dev_priv);
 742         drm_dev_unplug(&dev_priv->drm);
 743
 744         i915_gem_driver_unregister(dev_priv);
 745 }
 746
 747 void
 748 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 749 {
 750         drm_printf(p, "iommu: %s\n", enableddisabled(intel_vtd_active(i915)));
 751 }
 752
 753 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 754 {
 755         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 756                 struct drm_printer p = drm_debug_printer("i915 device info:");
 757
 758                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 759                            INTEL_DEVID(dev_priv),
 760                            INTEL_REVID(dev_priv),
 761                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 762                            intel_subplatform(RUNTIME_INFO(dev_priv),
 763                                              INTEL_INFO(dev_priv)->platform),
 764                            GRAPHICS_VER(dev_priv));
 765
 766                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 767                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 768                 i915_print_iommu_status(dev_priv, &p);
 769                 intel_gt_info_print(&to_gt(dev_priv)->info, &p);
 770         }
 771
 772         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 773                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 774         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 775                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 776         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 777                 drm_info(&dev_priv->drm,
 778                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 779 }
 780
 781 static struct drm_i915_private *
 782 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 783 {
 784         const struct intel_device_info *match_info =
 785                 (struct intel_device_info *)ent->driver_data;
 786         struct intel_device_info *device_info;
 787         struct drm_i915_private *i915;
 788
 789         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 790                                   struct drm_i915_private, drm);
 791         if (IS_ERR(i915))
 792                 return i915;
 793
 794         pci_set_drvdata(pdev, i915);
 795
 796         /* Device parameters start as a copy of module parameters. */
 797         i915_params_copy(&i915->params, &i915_modparams);
 798
 799         /* Setup the write-once "constant" device info */
 800         device_info = mkwrite_device_info(i915);
 801         memcpy(device_info, match_info, sizeof(*device_info));
 802         RUNTIME_INFO(i915)->device_id = pdev->device;
 803
 804         return i915;
 805 }
 806
 807 /**
 808  * i915_driver_probe - setup chip and create an initial config
 809  * @pdev: PCI device
 810  * @ent: matching PCI ID entry
 811  *
 812  * The driver probe routine has to do several things:
 813  *   - drive output discovery via intel_modeset_init()
 814  *   - initialize the memory manager
 815  *   - allocate initial config memory
 816  *   - setup the DRM framebuffer with the allocated memory
 817  */
 818 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 819 {
 820         const struct intel_device_info *match_info =
 821                 (struct intel_device_info *)ent->driver_data;
 822         struct drm_i915_private *i915;
 823         int ret;
 824
 825         i915 = i915_driver_create(pdev, ent);
 826         if (IS_ERR(i915))
 827                 return PTR_ERR(i915);
 828
 829         /* Disable nuclear pageflip by default on pre-ILK */
 830         if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5)
 831                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 832
 833         ret = pci_enable_device(pdev);
 834         if (ret)
 835                 goto out_fini;
 836
 837         ret = i915_driver_early_probe(i915);
 838         if (ret < 0)
 839                 goto out_pci_disable;
 840
 841         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 842
 843         intel_vgpu_detect(i915);
 844
 845         ret = intel_gt_probe_all(i915);
 846         if (ret < 0)
 847                 goto out_runtime_pm_put;
 848
 849         ret = i915_driver_mmio_probe(i915);
 850         if (ret < 0)
 851                 goto out_tiles_cleanup;
 852
 853         ret = i915_driver_hw_probe(i915);
 854         if (ret < 0)
 855                 goto out_cleanup_mmio;
 856
 857         ret = intel_modeset_init_noirq(i915);
 858         if (ret < 0)
 859                 goto out_cleanup_hw;
 860
 861         ret = intel_irq_install(i915);
 862         if (ret)
 863                 goto out_cleanup_modeset;
 864
 865         ret = intel_modeset_init_nogem(i915);
 866         if (ret)
 867                 goto out_cleanup_irq;
 868
 869         ret = i915_gem_init(i915);
 870         if (ret)
 871                 goto out_cleanup_modeset2;
 872
 873         ret = intel_modeset_init(i915);
 874         if (ret)
 875                 goto out_cleanup_gem;
 876
 877         i915_driver_register(i915);
 878
 879         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 880
 881         i915_welcome_messages(i915);
 882
 883         i915->do_release = true;
 884
 885         return 0;
 886
 887 out_cleanup_gem:
 888         i915_gem_suspend(i915);
 889         i915_gem_driver_remove(i915);
 890         i915_gem_driver_release(i915);
 891 out_cleanup_modeset2:
 892         /* FIXME clean up the error path */
 893         intel_modeset_driver_remove(i915);
 894         intel_irq_uninstall(i915);
 895         intel_modeset_driver_remove_noirq(i915);
 896         goto out_cleanup_modeset;
 897 out_cleanup_irq:
 898         intel_irq_uninstall(i915);
 899 out_cleanup_modeset:
 900         intel_modeset_driver_remove_nogem(i915);
 901 out_cleanup_hw:
 902         i915_driver_hw_remove(i915);
 903         intel_memory_regions_driver_release(i915);
 904         i915_ggtt_driver_release(i915);
 905         i915_gem_drain_freed_objects(i915);
 906         i915_ggtt_driver_late_release(i915);
 907 out_cleanup_mmio:
 908         i915_driver_mmio_release(i915);
 909 out_tiles_cleanup:
 910         intel_gt_release_all(i915);
 911 out_runtime_pm_put:
 912         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 913         i915_driver_late_release(i915);
 914 out_pci_disable:
 915         pci_disable_device(pdev);
 916 out_fini:
 917         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 918         return ret;
 919 }
 920
 921 void i915_driver_remove(struct drm_i915_private *i915)
 922 {
 923         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 924
 925         i915_driver_unregister(i915);
 926
 927         /* Flush any external code that still may be under the RCU lock */
 928         synchronize_rcu();
 929
 930         i915_gem_suspend(i915);
 931
 932         intel_gvt_driver_remove(i915);
 933
 934         intel_modeset_driver_remove(i915);
 935
 936         intel_irq_uninstall(i915);
 937
 938         intel_modeset_driver_remove_noirq(i915);
 939
 940         i915_reset_error_state(i915);
 941         i915_gem_driver_remove(i915);
 942
 943         intel_modeset_driver_remove_nogem(i915);
 944
 945         i915_driver_hw_remove(i915);
 946
 947         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 948 }
 949
 950 static void i915_driver_release(struct drm_device *dev)
 951 {
 952         struct drm_i915_private *dev_priv = to_i915(dev);
 953         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 954
 955         if (!dev_priv->do_release)
 956                 return;
 957
 958         disable_rpm_wakeref_asserts(rpm);
 959
 960         i915_gem_driver_release(dev_priv);
 961
 962         intel_memory_regions_driver_release(dev_priv);
 963         i915_ggtt_driver_release(dev_priv);
 964         i915_gem_drain_freed_objects(dev_priv);
 965         i915_ggtt_driver_late_release(dev_priv);
 966
 967         i915_driver_mmio_release(dev_priv);
 968
 969         enable_rpm_wakeref_asserts(rpm);
 970         intel_runtime_pm_driver_release(rpm);
 971
 972         i915_driver_late_release(dev_priv);
 973 }
 974
 975 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 976 {
 977         struct drm_i915_private *i915 = to_i915(dev);
 978         int ret;
 979
 980         ret = i915_gem_open(i915, file);
 981         if (ret)
 982                 return ret;
 983
 984         return 0;
 985 }
 986
 987 /**
 988  * i915_driver_lastclose - clean up after all DRM clients have exited
 989  * @dev: DRM device
 990  *
 991  * Take care of cleaning up after all DRM clients have exited.  In the
 992  * mode setting case, we want to restore the kernel's initial mode (just
 993  * in case the last client left us in a bad state).
 994  *
 995  * Additionally, in the non-mode setting case, we'll tear down the GTT
 996  * and DMA structures, since the kernel won't be using them, and clea
 997  * up any GEM state.
 998  */
 999 static void i915_driver_lastclose(struct drm_device *dev)
1000 {
1001         struct drm_i915_private *i915 = to_i915(dev);
1002
1003         intel_fbdev_restore_mode(dev);
1004
1005         if (HAS_DISPLAY(i915))
1006                 vga_switcheroo_process_delayed_switch();
1007 }
1008
1009 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1010 {
1011         struct drm_i915_file_private *file_priv = file->driver_priv;
1012
1013         i915_gem_context_close(file);
1014         i915_drm_client_put(file_priv->client);
1015
1016         kfree_rcu(file_priv, rcu);
1017
1018         /* Catch up with all the deferred frees from "this" client */
1019         i915_gem_flush_free_objects(to_i915(dev));
1020 }
1021
1022 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1023 {
1024         struct drm_device *dev = &dev_priv->drm;
1025         struct intel_encoder *encoder;
1026
1027         if (!HAS_DISPLAY(dev_priv))
1028                 return;
1029
1030         drm_modeset_lock_all(dev);
1031         for_each_intel_encoder(dev, encoder)
1032                 if (encoder->suspend)
1033                         encoder->suspend(encoder);
1034         drm_modeset_unlock_all(dev);
1035 }
1036
1037 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1038 {
1039         struct drm_device *dev = &dev_priv->drm;
1040         struct intel_encoder *encoder;
1041
1042         if (!HAS_DISPLAY(dev_priv))
1043                 return;
1044
1045         drm_modeset_lock_all(dev);
1046         for_each_intel_encoder(dev, encoder)
1047                 if (encoder->shutdown)
1048                         encoder->shutdown(encoder);
1049         drm_modeset_unlock_all(dev);
1050 }
1051
1052 void i915_driver_shutdown(struct drm_i915_private *i915)
1053 {
1054         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1055         intel_runtime_pm_disable(&i915->runtime_pm);
1056         intel_power_domains_disable(i915);
1057
1058         i915_gem_suspend(i915);
1059
1060         if (HAS_DISPLAY(i915)) {
1061                 drm_kms_helper_poll_disable(&i915->drm);
1062
1063                 drm_atomic_helper_shutdown(&i915->drm);
1064         }
1065
1066         intel_dp_mst_suspend(i915);
1067
1068         intel_runtime_pm_disable_interrupts(i915);
1069         intel_hpd_cancel_work(i915);
1070
1071         intel_suspend_encoders(i915);
1072         intel_shutdown_encoders(i915);
1073
1074         intel_dmc_ucode_suspend(i915);
1075
1076         /*
1077          * The only requirement is to reboot with display DC states disabled,
1078          * for now leaving all display power wells in the INIT power domain
1079          * enabled.
1080          *
1081          * TODO:
1082          * - unify the pci_driver::shutdown sequence here with the
1083          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1084          * - unify the driver remove and system/runtime suspend sequences with
1085          *   the above unified shutdown/poweroff sequence.
1086          */
1087         intel_power_domains_driver_remove(i915);
1088         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1089
1090         intel_runtime_pm_driver_release(&i915->runtime_pm);
1091 }
1092
1093 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1094 {
1095 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1096         if (acpi_target_system_state() < ACPI_STATE_S3)
1097                 return true;
1098 #endif
1099         return false;
1100 }
1101
1102 static int i915_drm_prepare(struct drm_device *dev)
1103 {
1104         struct drm_i915_private *i915 = to_i915(dev);
1105
1106         /*
1107          * NB intel_display_suspend() may issue new requests after we've
1108          * ostensibly marked the GPU as ready-to-sleep here. We need to
1109          * split out that work and pull it forward so that after point,
1110          * the GPU is not woken again.
1111          */
1112         return i915_gem_backup_suspend(i915);
1113 }
1114
1115 static int i915_drm_suspend(struct drm_device *dev)
1116 {
1117         struct drm_i915_private *dev_priv = to_i915(dev);
1118         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1119         pci_power_t opregion_target_state;
1120
1121         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1122
1123         /* We do a lot of poking in a lot of registers, make sure they work
1124          * properly. */
1125         intel_power_domains_disable(dev_priv);
1126         if (HAS_DISPLAY(dev_priv))
1127                 drm_kms_helper_poll_disable(dev);
1128
1129         pci_save_state(pdev);
1130
1131         intel_display_suspend(dev);
1132
1133         intel_dp_mst_suspend(dev_priv);
1134
1135         intel_runtime_pm_disable_interrupts(dev_priv);
1136         intel_hpd_cancel_work(dev_priv);
1137
1138         intel_suspend_encoders(dev_priv);
1139
1140         intel_suspend_hw(dev_priv);
1141
1142         /* Must be called before GGTT is suspended. */
1143         intel_dpt_suspend(dev_priv);
1144         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1145
1146         i915_save_display(dev_priv);
1147
1148         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1149         intel_opregion_suspend(dev_priv, opregion_target_state);
1150
1151         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1152
1153         dev_priv->suspend_count++;
1154
1155         intel_dmc_ucode_suspend(dev_priv);
1156
1157         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1158
1159         return 0;
1160 }
1161
1162 static enum i915_drm_suspend_mode
1163 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1164 {
1165         if (hibernate)
1166                 return I915_DRM_SUSPEND_HIBERNATE;
1167
1168         if (suspend_to_idle(dev_priv))
1169                 return I915_DRM_SUSPEND_IDLE;
1170
1171         return I915_DRM_SUSPEND_MEM;
1172 }
1173
1174 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1175 {
1176         struct drm_i915_private *dev_priv = to_i915(dev);
1177         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1178         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1179         int ret;
1180
1181         disable_rpm_wakeref_asserts(rpm);
1182
1183         i915_gem_suspend_late(dev_priv);
1184
1185         intel_uncore_suspend(&dev_priv->uncore);
1186
1187         intel_power_domains_suspend(dev_priv,
1188                                     get_suspend_mode(dev_priv, hibernation));
1189
1190         intel_display_power_suspend_late(dev_priv);
1191
1192         ret = vlv_suspend_complete(dev_priv);
1193         if (ret) {
1194                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1195                 intel_power_domains_resume(dev_priv);
1196
1197                 goto out;
1198         }
1199
1200         /*
1201          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1202          * This should be totally removed when we handle the pci states properly
1203          * on runtime PM and on s2idle cases.
1204          */
1205         if (suspend_to_idle(dev_priv))
1206                 pci_d3cold_disable(pdev);
1207
1208         pci_disable_device(pdev);
1209         /*
1210          * During hibernation on some platforms the BIOS may try to access
1211          * the device even though it's already in D3 and hang the machine. So
1212          * leave the device in D0 on those platforms and hope the BIOS will
1213          * power down the device properly. The issue was seen on multiple old
1214          * GENs with different BIOS vendors, so having an explicit blacklist
1215          * is inpractical; apply the workaround on everything pre GEN6. The
1216          * platforms where the issue was seen:
1217          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1218          * Fujitsu FSC S7110
1219          * Acer Aspire 1830T
1220          */
1221         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1222                 pci_set_power_state(pdev, PCI_D3hot);
1223
1224 out:
1225         enable_rpm_wakeref_asserts(rpm);
1226         if (!dev_priv->uncore.user_forcewake_count)
1227                 intel_runtime_pm_driver_release(rpm);
1228
1229         return ret;
1230 }
1231
1232 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1233                                    pm_message_t state)
1234 {
1235         int error;
1236
1237         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1238                              state.event != PM_EVENT_FREEZE))
1239                 return -EINVAL;
1240
1241         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1242                 return 0;
1243
1244         error = i915_drm_suspend(&i915->drm);
1245         if (error)
1246                 return error;
1247
1248         return i915_drm_suspend_late(&i915->drm, false);
1249 }
1250
1251 static int i915_drm_resume(struct drm_device *dev)
1252 {
1253         struct drm_i915_private *dev_priv = to_i915(dev);
1254         int ret;
1255
1256         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1257
1258         ret = intel_pcode_init(dev_priv);
1259         if (ret)
1260                 return ret;
1261
1262         sanitize_gpu(dev_priv);
1263
1264         ret = i915_ggtt_enable_hw(dev_priv);
1265         if (ret)
1266                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1267
1268         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1269         /* Must be called after GGTT is resumed. */
1270         intel_dpt_resume(dev_priv);
1271
1272         intel_dmc_ucode_resume(dev_priv);
1273
1274         i915_restore_display(dev_priv);
1275         intel_pps_unlock_regs_wa(dev_priv);
1276
1277         intel_init_pch_refclk(dev_priv);
1278
1279         /*
1280          * Interrupts have to be enabled before any batches are run. If not the
1281          * GPU will hang. i915_gem_init_hw() will initiate batches to
1282          * update/restore the context.
1283          *
1284          * drm_mode_config_reset() needs AUX interrupts.
1285          *
1286          * Modeset enabling in intel_modeset_init_hw() also needs working
1287          * interrupts.
1288          */
1289         intel_runtime_pm_enable_interrupts(dev_priv);
1290
1291         if (HAS_DISPLAY(dev_priv))
1292                 drm_mode_config_reset(dev);
1293
1294         i915_gem_resume(dev_priv);
1295
1296         intel_modeset_init_hw(dev_priv);
1297         intel_init_clock_gating(dev_priv);
1298         intel_hpd_init(dev_priv);
1299
1300         /* MST sideband requires HPD interrupts enabled */
1301         intel_dp_mst_resume(dev_priv);
1302         intel_display_resume(dev);
1303
1304         intel_hpd_poll_disable(dev_priv);
1305         if (HAS_DISPLAY(dev_priv))
1306                 drm_kms_helper_poll_enable(dev);
1307
1308         intel_opregion_resume(dev_priv);
1309
1310         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1311
1312         intel_power_domains_enable(dev_priv);
1313
1314         intel_gvt_resume(dev_priv);
1315
1316         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1317
1318         return 0;
1319 }
1320
1321 static int i915_drm_resume_early(struct drm_device *dev)
1322 {
1323         struct drm_i915_private *dev_priv = to_i915(dev);
1324         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1325         int ret;
1326
1327         /*
1328          * We have a resume ordering issue with the snd-hda driver also
1329          * requiring our device to be power up. Due to the lack of a
1330          * parent/child relationship we currently solve this with an early
1331          * resume hook.
1332          *
1333          * FIXME: This should be solved with a special hdmi sink device or
1334          * similar so that power domains can be employed.
1335          */
1336
1337         /*
1338          * Note that we need to set the power state explicitly, since we
1339          * powered off the device during freeze and the PCI core won't power
1340          * it back up for us during thaw. Powering off the device during
1341          * freeze is not a hard requirement though, and during the
1342          * suspend/resume phases the PCI core makes sure we get here with the
1343          * device powered on. So in case we change our freeze logic and keep
1344          * the device powered we can also remove the following set power state
1345          * call.
1346          */
1347         ret = pci_set_power_state(pdev, PCI_D0);
1348         if (ret) {
1349                 drm_err(&dev_priv->drm,
1350                         "failed to set PCI D0 power state (%d)\n", ret);
1351                 return ret;
1352         }
1353
1354         /*
1355          * Note that pci_enable_device() first enables any parent bridge
1356          * device and only then sets the power state for this device. The
1357          * bridge enabling is a nop though, since bridge devices are resumed
1358          * first. The order of enabling power and enabling the device is
1359          * imposed by the PCI core as described above, so here we preserve the
1360          * same order for the freeze/thaw phases.
1361          *
1362          * TODO: eventually we should remove pci_disable_device() /
1363          * pci_enable_enable_device() from suspend/resume. Due to how they
1364          * depend on the device enable refcount we can't anyway depend on them
1365          * disabling/enabling the device.
1366          */
1367         if (pci_enable_device(pdev))
1368                 return -EIO;
1369
1370         pci_set_master(pdev);
1371
1372         pci_d3cold_enable(pdev);
1373
1374         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1375
1376         ret = vlv_resume_prepare(dev_priv, false);
1377         if (ret)
1378                 drm_err(&dev_priv->drm,
1379                         "Resume prepare failed: %d, continuing anyway\n", ret);
1380
1381         intel_uncore_resume_early(&dev_priv->uncore);
1382
1383         intel_gt_check_and_clear_faults(to_gt(dev_priv));
1384
1385         intel_display_power_resume_early(dev_priv);
1386
1387         intel_power_domains_resume(dev_priv);
1388
1389         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1390
1391         return ret;
1392 }
1393
1394 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1395 {
1396         int ret;
1397
1398         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1399                 return 0;
1400
1401         ret = i915_drm_resume_early(&i915->drm);
1402         if (ret)
1403                 return ret;
1404
1405         return i915_drm_resume(&i915->drm);
1406 }
1407
1408 static int i915_pm_prepare(struct device *kdev)
1409 {
1410         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1411
1412         if (!i915) {
1413                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1414                 return -ENODEV;
1415         }
1416
1417         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1418                 return 0;
1419
1420         return i915_drm_prepare(&i915->drm);
1421 }
1422
1423 static int i915_pm_suspend(struct device *kdev)
1424 {
1425         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1426
1427         if (!i915) {
1428                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1429                 return -ENODEV;
1430         }
1431
1432         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1433                 return 0;
1434
1435         return i915_drm_suspend(&i915->drm);
1436 }
1437
1438 static int i915_pm_suspend_late(struct device *kdev)
1439 {
1440         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1441
1442         /*
1443          * We have a suspend ordering issue with the snd-hda driver also
1444          * requiring our device to be power up. Due to the lack of a
1445          * parent/child relationship we currently solve this with an late
1446          * suspend hook.
1447          *
1448          * FIXME: This should be solved with a special hdmi sink device or
1449          * similar so that power domains can be employed.
1450          */
1451         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1452                 return 0;
1453
1454         return i915_drm_suspend_late(&i915->drm, false);
1455 }
1456
1457 static int i915_pm_poweroff_late(struct device *kdev)
1458 {
1459         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1460
1461         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1462                 return 0;
1463
1464         return i915_drm_suspend_late(&i915->drm, true);
1465 }
1466
1467 static int i915_pm_resume_early(struct device *kdev)
1468 {
1469         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1470
1471         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1472                 return 0;
1473
1474         return i915_drm_resume_early(&i915->drm);
1475 }
1476
1477 static int i915_pm_resume(struct device *kdev)
1478 {
1479         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1480
1481         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1482                 return 0;
1483
1484         return i915_drm_resume(&i915->drm);
1485 }
1486
1487 /* freeze: before creating the hibernation_image */
1488 static int i915_pm_freeze(struct device *kdev)
1489 {
1490         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1491         int ret;
1492
1493         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1494                 ret = i915_drm_suspend(&i915->drm);
1495                 if (ret)
1496                         return ret;
1497         }
1498
1499         ret = i915_gem_freeze(i915);
1500         if (ret)
1501                 return ret;
1502
1503         return 0;
1504 }
1505
1506 static int i915_pm_freeze_late(struct device *kdev)
1507 {
1508         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1509         int ret;
1510
1511         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1512                 ret = i915_drm_suspend_late(&i915->drm, true);
1513                 if (ret)
1514                         return ret;
1515         }
1516
1517         ret = i915_gem_freeze_late(i915);
1518         if (ret)
1519                 return ret;
1520
1521         return 0;
1522 }
1523
1524 /* thaw: called after creating the hibernation image, but before turning off. */
1525 static int i915_pm_thaw_early(struct device *kdev)
1526 {
1527         return i915_pm_resume_early(kdev);
1528 }
1529
1530 static int i915_pm_thaw(struct device *kdev)
1531 {
1532         return i915_pm_resume(kdev);
1533 }
1534
1535 /* restore: called after loading the hibernation image. */
1536 static int i915_pm_restore_early(struct device *kdev)
1537 {
1538         return i915_pm_resume_early(kdev);
1539 }
1540
1541 static int i915_pm_restore(struct device *kdev)
1542 {
1543         return i915_pm_resume(kdev);
1544 }
1545
1546 static int intel_runtime_suspend(struct device *kdev)
1547 {
1548         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1549         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1550         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1551         int ret;
1552
1553         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1554                 return -ENODEV;
1555
1556         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1557
1558         disable_rpm_wakeref_asserts(rpm);
1559
1560         /*
1561          * We are safe here against re-faults, since the fault handler takes
1562          * an RPM reference.
1563          */
1564         i915_gem_runtime_suspend(dev_priv);
1565
1566         intel_gt_runtime_suspend(to_gt(dev_priv));
1567
1568         intel_runtime_pm_disable_interrupts(dev_priv);
1569
1570         intel_uncore_suspend(&dev_priv->uncore);
1571
1572         intel_display_power_suspend(dev_priv);
1573
1574         ret = vlv_suspend_complete(dev_priv);
1575         if (ret) {
1576                 drm_err(&dev_priv->drm,
1577                         "Runtime suspend failed, disabling it (%d)\n", ret);
1578                 intel_uncore_runtime_resume(&dev_priv->uncore);
1579
1580                 intel_runtime_pm_enable_interrupts(dev_priv);
1581
1582                 intel_gt_runtime_resume(to_gt(dev_priv));
1583
1584                 enable_rpm_wakeref_asserts(rpm);
1585
1586                 return ret;
1587         }
1588
1589         enable_rpm_wakeref_asserts(rpm);
1590         intel_runtime_pm_driver_release(rpm);
1591
1592         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1593                 drm_err(&dev_priv->drm,
1594                         "Unclaimed access detected prior to suspending\n");
1595
1596         /*
1597          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1598          * This should be totally removed when we handle the pci states properly
1599          * on runtime PM and on s2idle cases.
1600          */
1601         pci_d3cold_disable(pdev);
1602         rpm->suspended = true;
1603
1604         /*
1605          * FIXME: We really should find a document that references the arguments
1606          * used below!
1607          */
1608         if (IS_BROADWELL(dev_priv)) {
1609                 /*
1610                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1611                  * being detected, and the call we do at intel_runtime_resume()
1612                  * won't be able to restore them. Since PCI_D3hot matches the
1613                  * actual specification and appears to be working, use it.
1614                  */
1615                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1616         } else {
1617                 /*
1618                  * current versions of firmware which depend on this opregion
1619                  * notification have repurposed the D1 definition to mean
1620                  * "runtime suspended" vs. what you would normally expect (D3)
1621                  * to distinguish it from notifications that might be sent via
1622                  * the suspend path.
1623                  */
1624                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1625         }
1626
1627         assert_forcewakes_inactive(&dev_priv->uncore);
1628
1629         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1630                 intel_hpd_poll_enable(dev_priv);
1631
1632         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1633         return 0;
1634 }
1635
1636 static int intel_runtime_resume(struct device *kdev)
1637 {
1638         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1639         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1640         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1641         int ret;
1642
1643         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1644                 return -ENODEV;
1645
1646         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1647
1648         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1649         disable_rpm_wakeref_asserts(rpm);
1650
1651         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1652         rpm->suspended = false;
1653         pci_d3cold_enable(pdev);
1654         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1655                 drm_dbg(&dev_priv->drm,
1656                         "Unclaimed access during suspend, bios?\n");
1657
1658         intel_display_power_resume(dev_priv);
1659
1660         ret = vlv_resume_prepare(dev_priv, true);
1661
1662         intel_uncore_runtime_resume(&dev_priv->uncore);
1663
1664         intel_runtime_pm_enable_interrupts(dev_priv);
1665
1666         /*
1667          * No point of rolling back things in case of an error, as the best
1668          * we can do is to hope that things will still work (and disable RPM).
1669          */
1670         intel_gt_runtime_resume(to_gt(dev_priv));
1671
1672         /*
1673          * On VLV/CHV display interrupts are part of the display
1674          * power well, so hpd is reinitialized from there. For
1675          * everyone else do it here.
1676          */
1677         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1678                 intel_hpd_init(dev_priv);
1679                 intel_hpd_poll_disable(dev_priv);
1680         }
1681
1682         intel_enable_ipc(dev_priv);
1683
1684         enable_rpm_wakeref_asserts(rpm);
1685
1686         if (ret)
1687                 drm_err(&dev_priv->drm,
1688                         "Runtime resume failed, disabling it (%d)\n", ret);
1689         else
1690                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1691
1692         return ret;
1693 }
1694
1695 const struct dev_pm_ops i915_pm_ops = {
1696         /*
1697          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1698          * PMSG_RESUME]
1699          */
1700         .prepare = i915_pm_prepare,
1701         .suspend = i915_pm_suspend,
1702         .suspend_late = i915_pm_suspend_late,
1703         .resume_early = i915_pm_resume_early,
1704         .resume = i915_pm_resume,
1705
1706         /*
1707          * S4 event handlers
1708          * @freeze, @freeze_late    : called (1) before creating the
1709          *                            hibernation image [PMSG_FREEZE] and
1710          *                            (2) after rebooting, before restoring
1711          *                            the image [PMSG_QUIESCE]
1712          * @thaw, @thaw_early       : called (1) after creating the hibernation
1713          *                            image, before writing it [PMSG_THAW]
1714          *                            and (2) after failing to create or
1715          *                            restore the image [PMSG_RECOVER]
1716          * @poweroff, @poweroff_late: called after writing the hibernation
1717          *                            image, before rebooting [PMSG_HIBERNATE]
1718          * @restore, @restore_early : called after rebooting and restoring the
1719          *                            hibernation image [PMSG_RESTORE]
1720          */
1721         .freeze = i915_pm_freeze,
1722         .freeze_late = i915_pm_freeze_late,
1723         .thaw_early = i915_pm_thaw_early,
1724         .thaw = i915_pm_thaw,
1725         .poweroff = i915_pm_suspend,
1726         .poweroff_late = i915_pm_poweroff_late,
1727         .restore_early = i915_pm_restore_early,
1728         .restore = i915_pm_restore,
1729
1730         /* S0ix (via runtime suspend) event handlers */
1731         .runtime_suspend = intel_runtime_suspend,
1732         .runtime_resume = intel_runtime_resume,
1733 };
1734
1735 static const struct file_operations i915_driver_fops = {
1736         .owner = THIS_MODULE,
1737         .open = drm_open,
1738         .release = drm_release_noglobal,
1739         .unlocked_ioctl = drm_ioctl,
1740         .mmap = i915_gem_mmap,
1741         .poll = drm_poll,
1742         .read = drm_read,
1743         .compat_ioctl = i915_ioc32_compat_ioctl,
1744         .llseek = noop_llseek,
1745 };
1746
1747 static int
1748 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1749                           struct drm_file *file)
1750 {
1751         return -ENODEV;
1752 }
1753
1754 static const struct drm_ioctl_desc i915_ioctls[] = {
1755         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1756         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1757         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1758         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1759         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1760         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1761         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1762         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1763         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1764         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1765         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1766         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1767         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1768         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1769         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1770         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1771         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1772         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1773         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1774         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1775         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1778         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1779         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1780         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1781         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1782         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1783         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1784         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1785         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1786         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1787         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1788         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1789         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1790         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1791         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1792         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1793         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1794         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1795         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1796         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1797         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1798         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1799         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1800         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1801         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1802         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1803         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1804         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1805         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1806         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1807         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1808         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1809         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1810         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1811         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1812         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1813         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1814 };
1815
1816 /*
1817  * Interface history:
1818  *
1819  * 1.1: Original.
1820  * 1.2: Add Power Management
1821  * 1.3: Add vblank support
1822  * 1.4: Fix cmdbuffer path, add heap destroy
1823  * 1.5: Add vblank pipe configuration
1824  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1825  *      - Support vertical blank on secondary display pipe
1826  */
1827 #define DRIVER_MAJOR            1
1828 #define DRIVER_MINOR            6
1829 #define DRIVER_PATCHLEVEL       0
1830
1831 static const struct drm_driver i915_drm_driver = {
1832         /* Don't use MTRRs here; the Xserver or userspace app should
1833          * deal with them for Intel hardware.
1834          */
1835         .driver_features =
1836             DRIVER_GEM |
1837             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1838             DRIVER_SYNCOBJ_TIMELINE,
1839         .release = i915_driver_release,
1840         .open = i915_driver_open,
1841         .lastclose = i915_driver_lastclose,
1842         .postclose = i915_driver_postclose,
1843
1844         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1845         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1846         .gem_prime_import = i915_gem_prime_import,
1847
1848         .dumb_create = i915_gem_dumb_create,
1849         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1850
1851         .ioctls = i915_ioctls,
1852         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1853         .fops = &i915_driver_fops,
1854         .name = DRIVER_NAME,
1855         .desc = DRIVER_DESC,
1856         .date = DRIVER_DATE,
1857         .major = DRIVER_MAJOR,
1858         .minor = DRIVER_MINOR,
1859         .patchlevel = DRIVER_PATCHLEVEL,
1860 };