drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/async.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_legacy.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_vgpu.h"
  40 #include "i915_trace.h"
  41 #include <linux/pci.h>
  42 #include <linux/console.h>
  43 #include <linux/vt.h>
  44 #include <linux/vgaarb.h>
  45 #include <linux/acpi.h>
  46 #include <linux/pnp.h>
  47 #include <linux/vga_switcheroo.h>
  48 #include <linux/slab.h>
  49 #include <acpi/video.h>
  50 #include <linux/pm.h>
  51 #include <linux/pm_runtime.h>
  52 #include <linux/oom.h>
  53
  54
  55 static int i915_getparam(struct drm_device *dev, void *data,
  56                          struct drm_file *file_priv)
  57 {
  58         struct drm_i915_private *dev_priv = dev->dev_private;
  59         drm_i915_getparam_t *param = data;
  60         int value;
  61
  62         switch (param->param) {
  63         case I915_PARAM_IRQ_ACTIVE:
  64         case I915_PARAM_ALLOW_BATCHBUFFER:
  65         case I915_PARAM_LAST_DISPATCH:
  66                 /* Reject all old ums/dri params. */
  67                 return -ENODEV;
  68         case I915_PARAM_CHIPSET_ID:
  69                 value = dev->pdev->device;
  70                 break;
  71         case I915_PARAM_REVISION:
  72                 value = dev->pdev->revision;
  73                 break;
  74         case I915_PARAM_HAS_GEM:
  75                 value = 1;
  76                 break;
  77         case I915_PARAM_NUM_FENCES_AVAIL:
  78                 value = dev_priv->num_fence_regs;
  79                 break;
  80         case I915_PARAM_HAS_OVERLAY:
  81                 value = dev_priv->overlay ? 1 : 0;
  82                 break;
  83         case I915_PARAM_HAS_PAGEFLIPPING:
  84                 value = 1;
  85                 break;
  86         case I915_PARAM_HAS_EXECBUF2:
  87                 /* depends on GEM */
  88                 value = 1;
  89                 break;
  90         case I915_PARAM_HAS_BSD:
  91                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  92                 break;
  93         case I915_PARAM_HAS_BLT:
  94                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  95                 break;
  96         case I915_PARAM_HAS_VEBOX:
  97                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  98                 break;
  99         case I915_PARAM_HAS_BSD2:
 100                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
 101                 break;
 102         case I915_PARAM_HAS_RELAXED_FENCING:
 103                 value = 1;
 104                 break;
 105         case I915_PARAM_HAS_COHERENT_RINGS:
 106                 value = 1;
 107                 break;
 108         case I915_PARAM_HAS_EXEC_CONSTANTS:
 109                 value = INTEL_INFO(dev)->gen >= 4;
 110                 break;
 111         case I915_PARAM_HAS_RELAXED_DELTA:
 112                 value = 1;
 113                 break;
 114         case I915_PARAM_HAS_GEN7_SOL_RESET:
 115                 value = 1;
 116                 break;
 117         case I915_PARAM_HAS_LLC:
 118                 value = HAS_LLC(dev);
 119                 break;
 120         case I915_PARAM_HAS_WT:
 121                 value = HAS_WT(dev);
 122                 break;
 123         case I915_PARAM_HAS_ALIASING_PPGTT:
 124                 value = USES_PPGTT(dev);
 125                 break;
 126         case I915_PARAM_HAS_WAIT_TIMEOUT:
 127                 value = 1;
 128                 break;
 129         case I915_PARAM_HAS_SEMAPHORES:
 130                 value = i915_semaphore_is_enabled(dev);
 131                 break;
 132         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 133                 value = 1;
 134                 break;
 135         case I915_PARAM_HAS_SECURE_BATCHES:
 136                 value = capable(CAP_SYS_ADMIN);
 137                 break;
 138         case I915_PARAM_HAS_PINNED_BATCHES:
 139                 value = 1;
 140                 break;
 141         case I915_PARAM_HAS_EXEC_NO_RELOC:
 142                 value = 1;
 143                 break;
 144         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 145                 value = 1;
 146                 break;
 147         case I915_PARAM_CMD_PARSER_VERSION:
 148                 value = i915_cmd_parser_get_version();
 149                 break;
 150         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 151                 value = 1;
 152                 break;
 153         case I915_PARAM_MMAP_VERSION:
 154                 value = 1;
 155                 break;
 156         case I915_PARAM_SUBSLICE_TOTAL:
 157                 value = INTEL_INFO(dev)->subslice_total;
 158                 if (!value)
 159                         return -ENODEV;
 160                 break;
 161         case I915_PARAM_EU_TOTAL:
 162                 value = INTEL_INFO(dev)->eu_total;
 163                 if (!value)
 164                         return -ENODEV;
 165                 break;
 166         case I915_PARAM_HAS_GPU_RESET:
 167                 value = i915.enable_hangcheck &&
 168                         intel_has_gpu_reset(dev);
 169                 break;
 170         case I915_PARAM_HAS_RESOURCE_STREAMER:
 171                 value = HAS_RESOURCE_STREAMER(dev);
 172                 break;
 173         default:
 174                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 175                 return -EINVAL;
 176         }
 177
 178         if (copy_to_user(param->value, &value, sizeof(int))) {
 179                 DRM_ERROR("copy_to_user failed\n");
 180                 return -EFAULT;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static int i915_get_bridge_dev(struct drm_device *dev)
 187 {
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189
 190         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 191         if (!dev_priv->bridge_dev) {
 192                 DRM_ERROR("bridge device not found\n");
 193                 return -1;
 194         }
 195         return 0;
 196 }
 197
 198 #define MCHBAR_I915 0x44
 199 #define MCHBAR_I965 0x48
 200 #define MCHBAR_SIZE (4*4096)
 201
 202 #define DEVEN_REG 0x54
 203 #define   DEVEN_MCHBAR_EN (1 << 28)
 204
 205 /* Allocate space for the MCH regs if needed, return nonzero on error */
 206 static int
 207 intel_alloc_mchbar_resource(struct drm_device *dev)
 208 {
 209         struct drm_i915_private *dev_priv = dev->dev_private;
 210         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 211         u32 temp_lo, temp_hi = 0;
 212         u64 mchbar_addr;
 213         int ret;
 214
 215         if (INTEL_INFO(dev)->gen >= 4)
 216                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 217         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 218         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 219
 220         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 221 #ifdef CONFIG_PNP
 222         if (mchbar_addr &&
 223             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 224                 return 0;
 225 #endif
 226
 227         /* Get some space for it */
 228         dev_priv->mch_res.name = "i915 MCHBAR";
 229         dev_priv->mch_res.flags = IORESOURCE_MEM;
 230         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 231                                      &dev_priv->mch_res,
 232                                      MCHBAR_SIZE, MCHBAR_SIZE,
 233                                      PCIBIOS_MIN_MEM,
 234                                      0, pcibios_align_resource,
 235                                      dev_priv->bridge_dev);
 236         if (ret) {
 237                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 238                 dev_priv->mch_res.start = 0;
 239                 return ret;
 240         }
 241
 242         if (INTEL_INFO(dev)->gen >= 4)
 243                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 244                                        upper_32_bits(dev_priv->mch_res.start));
 245
 246         pci_write_config_dword(dev_priv->bridge_dev, reg,
 247                                lower_32_bits(dev_priv->mch_res.start));
 248         return 0;
 249 }
 250
 251 /* Setup MCHBAR if possible, return true if we should disable it again */
 252 static void
 253 intel_setup_mchbar(struct drm_device *dev)
 254 {
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 257         u32 temp;
 258         bool enabled;
 259
 260         if (IS_VALLEYVIEW(dev))
 261                 return;
 262
 263         dev_priv->mchbar_need_disable = false;
 264
 265         if (IS_I915G(dev) || IS_I915GM(dev)) {
 266                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 267                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 268         } else {
 269                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 270                 enabled = temp & 1;
 271         }
 272
 273         /* If it's already enabled, don't have to do anything */
 274         if (enabled)
 275                 return;
 276
 277         if (intel_alloc_mchbar_resource(dev))
 278                 return;
 279
 280         dev_priv->mchbar_need_disable = true;
 281
 282         /* Space is allocated or reserved, so enable it. */
 283         if (IS_I915G(dev) || IS_I915GM(dev)) {
 284                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 285                                        temp | DEVEN_MCHBAR_EN);
 286         } else {
 287                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 288                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 289         }
 290 }
 291
 292 static void
 293 intel_teardown_mchbar(struct drm_device *dev)
 294 {
 295         struct drm_i915_private *dev_priv = dev->dev_private;
 296         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 297         u32 temp;
 298
 299         if (dev_priv->mchbar_need_disable) {
 300                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 301                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 302                         temp &= ~DEVEN_MCHBAR_EN;
 303                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 304                 } else {
 305                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 306                         temp &= ~1;
 307                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 308                 }
 309         }
 310
 311         if (dev_priv->mch_res.start)
 312                 release_resource(&dev_priv->mch_res);
 313 }
 314
 315 /* true = enable decode, false = disable decoder */
 316 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 317 {
 318         struct drm_device *dev = cookie;
 319
 320         intel_modeset_vga_set_state(dev, state);
 321         if (state)
 322                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 323                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 324         else
 325                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 326 }
 327
 328 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 329 {
 330         struct drm_device *dev = pci_get_drvdata(pdev);
 331         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 332
 333         if (state == VGA_SWITCHEROO_ON) {
 334                 pr_info("switched on\n");
 335                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 336                 /* i915 resume handler doesn't set to D0 */
 337                 pci_set_power_state(dev->pdev, PCI_D0);
 338                 i915_resume_legacy(dev);
 339                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 340         } else {
 341                 pr_err("switched off\n");
 342                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 343                 i915_suspend_legacy(dev, pmm);
 344                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 345         }
 346 }
 347
 348 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 349 {
 350         struct drm_device *dev = pci_get_drvdata(pdev);
 351
 352         /*
 353          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 354          * locking inversion with the driver load path. And the access here is
 355          * completely racy anyway. So don't bother with locking for now.
 356          */
 357         return dev->open_count == 0;
 358 }
 359
 360 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 361         .set_gpu_state = i915_switcheroo_set_state,
 362         .reprobe = NULL,
 363         .can_switch = i915_switcheroo_can_switch,
 364 };
 365
 366 static int i915_load_modeset_init(struct drm_device *dev)
 367 {
 368         struct drm_i915_private *dev_priv = dev->dev_private;
 369         int ret;
 370
 371         ret = intel_parse_bios(dev);
 372         if (ret)
 373                 DRM_INFO("failed to find VBIOS tables\n");
 374
 375         /* If we have > 1 VGA cards, then we need to arbitrate access
 376          * to the common VGA resources.
 377          *
 378          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 379          * then we do not take part in VGA arbitration and the
 380          * vga_client_register() fails with -ENODEV.
 381          */
 382         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 383         if (ret && ret != -ENODEV)
 384                 goto out;
 385
 386         intel_register_dsm_handler();
 387
 388         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 389         if (ret)
 390                 goto cleanup_vga_client;
 391
 392         /* Initialise stolen first so that we may reserve preallocated
 393          * objects for the BIOS to KMS transition.
 394          */
 395         ret = i915_gem_init_stolen(dev);
 396         if (ret)
 397                 goto cleanup_vga_switcheroo;
 398
 399         intel_power_domains_init_hw(dev_priv);
 400
 401         ret = intel_irq_install(dev_priv);
 402         if (ret)
 403                 goto cleanup_gem_stolen;
 404
 405         /* Important: The output setup functions called by modeset_init need
 406          * working irqs for e.g. gmbus and dp aux transfers. */
 407         intel_modeset_init(dev);
 408
 409         ret = i915_gem_init(dev);
 410         if (ret)
 411                 goto cleanup_irq;
 412
 413         intel_modeset_gem_init(dev);
 414
 415         /* Always safe in the mode setting case. */
 416         /* FIXME: do pre/post-mode set stuff in core KMS code */
 417         dev->vblank_disable_allowed = true;
 418         if (INTEL_INFO(dev)->num_pipes == 0)
 419                 return 0;
 420
 421         ret = intel_fbdev_init(dev);
 422         if (ret)
 423                 goto cleanup_gem;
 424
 425         /* Only enable hotplug handling once the fbdev is fully set up. */
 426         intel_hpd_init(dev_priv);
 427
 428         /*
 429          * Some ports require correctly set-up hpd registers for detection to
 430          * work properly (leading to ghost connected connector status), e.g. VGA
 431          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 432          * irqs are fully enabled. Now we should scan for the initial config
 433          * only once hotplug handling is enabled, but due to screwed-up locking
 434          * around kms/fbdev init we can't protect the fdbev initial config
 435          * scanning against hotplug events. Hence do this first and ignore the
 436          * tiny window where we will loose hotplug notifactions.
 437          */
 438         async_schedule(intel_fbdev_initial_config, dev_priv);
 439
 440         drm_kms_helper_poll_init(dev);
 441
 442         return 0;
 443
 444 cleanup_gem:
 445         mutex_lock(&dev->struct_mutex);
 446         i915_gem_cleanup_ringbuffer(dev);
 447         i915_gem_context_fini(dev);
 448         mutex_unlock(&dev->struct_mutex);
 449 cleanup_irq:
 450         drm_irq_uninstall(dev);
 451 cleanup_gem_stolen:
 452         i915_gem_cleanup_stolen(dev);
 453 cleanup_vga_switcheroo:
 454         vga_switcheroo_unregister_client(dev->pdev);
 455 cleanup_vga_client:
 456         vga_client_register(dev->pdev, NULL, NULL, NULL);
 457 out:
 458         return ret;
 459 }
 460
 461 #if IS_ENABLED(CONFIG_FB)
 462 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 463 {
 464         struct apertures_struct *ap;
 465         struct pci_dev *pdev = dev_priv->dev->pdev;
 466         bool primary;
 467         int ret;
 468
 469         ap = alloc_apertures(1);
 470         if (!ap)
 471                 return -ENOMEM;
 472
 473         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 474         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 475
 476         primary =
 477                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 478
 479         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 480
 481         kfree(ap);
 482
 483         return ret;
 484 }
 485 #else
 486 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 487 {
 488         return 0;
 489 }
 490 #endif
 491
 492 #if !defined(CONFIG_VGA_CONSOLE)
 493 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 494 {
 495         return 0;
 496 }
 497 #elif !defined(CONFIG_DUMMY_CONSOLE)
 498 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 499 {
 500         return -ENODEV;
 501 }
 502 #else
 503 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 504 {
 505         int ret = 0;
 506
 507         DRM_INFO("Replacing VGA console driver\n");
 508
 509         console_lock();
 510         if (con_is_bound(&vga_con))
 511                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 512         if (ret == 0) {
 513                 ret = do_unregister_con_driver(&vga_con);
 514
 515                 /* Ignore "already unregistered". */
 516                 if (ret == -ENODEV)
 517                         ret = 0;
 518         }
 519         console_unlock();
 520
 521         return ret;
 522 }
 523 #endif
 524
 525 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 526 {
 527         const struct intel_device_info *info = &dev_priv->info;
 528
 529 #define PRINT_S(name) "%s"
 530 #define SEP_EMPTY
 531 #define PRINT_FLAG(name) info->name ? #name "," : ""
 532 #define SEP_COMMA ,
 533         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 534                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 535                          info->gen,
 536                          dev_priv->dev->pdev->device,
 537                          dev_priv->dev->pdev->revision,
 538                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 539 #undef PRINT_S
 540 #undef SEP_EMPTY
 541 #undef PRINT_FLAG
 542 #undef SEP_COMMA
 543 }
 544
 545 static void cherryview_sseu_info_init(struct drm_device *dev)
 546 {
 547         struct drm_i915_private *dev_priv = dev->dev_private;
 548         struct intel_device_info *info;
 549         u32 fuse, eu_dis;
 550
 551         info = (struct intel_device_info *)&dev_priv->info;
 552         fuse = I915_READ(CHV_FUSE_GT);
 553
 554         info->slice_total = 1;
 555
 556         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 557                 info->subslice_per_slice++;
 558                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 559                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 560                 info->eu_total += 8 - hweight32(eu_dis);
 561         }
 562
 563         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 564                 info->subslice_per_slice++;
 565                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 566                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 567                 info->eu_total += 8 - hweight32(eu_dis);
 568         }
 569
 570         info->subslice_total = info->subslice_per_slice;
 571         /*
 572          * CHV expected to always have a uniform distribution of EU
 573          * across subslices.
 574         */
 575         info->eu_per_subslice = info->subslice_total ?
 576                                 info->eu_total / info->subslice_total :
 577                                 0;
 578         /*
 579          * CHV supports subslice power gating on devices with more than
 580          * one subslice, and supports EU power gating on devices with
 581          * more than one EU pair per subslice.
 582         */
 583         info->has_slice_pg = 0;
 584         info->has_subslice_pg = (info->subslice_total > 1);
 585         info->has_eu_pg = (info->eu_per_subslice > 2);
 586 }
 587
 588 static void gen9_sseu_info_init(struct drm_device *dev)
 589 {
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591         struct intel_device_info *info;
 592         int s_max = 3, ss_max = 4, eu_max = 8;
 593         int s, ss;
 594         u32 fuse2, s_enable, ss_disable, eu_disable;
 595         u8 eu_mask = 0xff;
 596
 597         /*
 598          * BXT has a single slice. BXT also has at most 6 EU per subslice,
 599          * and therefore only the lowest 6 bits of the 8-bit EU disable
 600          * fields are valid.
 601         */
 602         if (IS_BROXTON(dev)) {
 603                 s_max = 1;
 604                 eu_max = 6;
 605                 eu_mask = 0x3f;
 606         }
 607
 608         info = (struct intel_device_info *)&dev_priv->info;
 609         fuse2 = I915_READ(GEN8_FUSE2);
 610         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 611                    GEN8_F2_S_ENA_SHIFT;
 612         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 613                      GEN9_F2_SS_DIS_SHIFT;
 614
 615         info->slice_total = hweight32(s_enable);
 616         /*
 617          * The subslice disable field is global, i.e. it applies
 618          * to each of the enabled slices.
 619         */
 620         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 621         info->subslice_total = info->slice_total *
 622                                info->subslice_per_slice;
 623
 624         /*
 625          * Iterate through enabled slices and subslices to
 626          * count the total enabled EU.
 627         */
 628         for (s = 0; s < s_max; s++) {
 629                 if (!(s_enable & (0x1 << s)))
 630                         /* skip disabled slice */
 631                         continue;
 632
 633                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 634                 for (ss = 0; ss < ss_max; ss++) {
 635                         int eu_per_ss;
 636
 637                         if (ss_disable & (0x1 << ss))
 638                                 /* skip disabled subslice */
 639                                 continue;
 640
 641                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 642                                                       eu_mask);
 643
 644                         /*
 645                          * Record which subslice(s) has(have) 7 EUs. we
 646                          * can tune the hash used to spread work among
 647                          * subslices if they are unbalanced.
 648                          */
 649                         if (eu_per_ss == 7)
 650                                 info->subslice_7eu[s] |= 1 << ss;
 651
 652                         info->eu_total += eu_per_ss;
 653                 }
 654         }
 655
 656         /*
 657          * SKL is expected to always have a uniform distribution
 658          * of EU across subslices with the exception that any one
 659          * EU in any one subslice may be fused off for die
 660          * recovery. BXT is expected to be perfectly uniform in EU
 661          * distribution.
 662         */
 663         info->eu_per_subslice = info->subslice_total ?
 664                                 DIV_ROUND_UP(info->eu_total,
 665                                              info->subslice_total) : 0;
 666         /*
 667          * SKL supports slice power gating on devices with more than
 668          * one slice, and supports EU power gating on devices with
 669          * more than one EU pair per subslice. BXT supports subslice
 670          * power gating on devices with more than one subslice, and
 671          * supports EU power gating on devices with more than one EU
 672          * pair per subslice.
 673         */
 674         info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
 675         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 676         info->has_eu_pg = (info->eu_per_subslice > 2);
 677 }
 678
 679 /*
 680  * Determine various intel_device_info fields at runtime.
 681  *
 682  * Use it when either:
 683  *   - it's judged too laborious to fill n static structures with the limit
 684  *     when a simple if statement does the job,
 685  *   - run-time checks (eg read fuse/strap registers) are needed.
 686  *
 687  * This function needs to be called:
 688  *   - after the MMIO has been setup as we are reading registers,
 689  *   - after the PCH has been detected,
 690  *   - before the first usage of the fields it can tweak.
 691  */
 692 static void intel_device_info_runtime_init(struct drm_device *dev)
 693 {
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695         struct intel_device_info *info;
 696         enum pipe pipe;
 697
 698         info = (struct intel_device_info *)&dev_priv->info;
 699
 700         /*
 701          * Skylake and Broxton currently don't expose the topmost plane as its
 702          * use is exclusive with the legacy cursor and we only want to expose
 703          * one of those, not both. Until we can safely expose the topmost plane
 704          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 705          * we don't expose the topmost plane at all to prevent ABI breakage
 706          * down the line.
 707          */
 708         if (IS_BROXTON(dev)) {
 709                 info->num_sprites[PIPE_A] = 2;
 710                 info->num_sprites[PIPE_B] = 2;
 711                 info->num_sprites[PIPE_C] = 1;
 712         } else if (IS_VALLEYVIEW(dev))
 713                 for_each_pipe(dev_priv, pipe)
 714                         info->num_sprites[pipe] = 2;
 715         else
 716                 for_each_pipe(dev_priv, pipe)
 717                         info->num_sprites[pipe] = 1;
 718
 719         if (i915.disable_display) {
 720                 DRM_INFO("Display disabled (module parameter)\n");
 721                 info->num_pipes = 0;
 722         } else if (info->num_pipes > 0 &&
 723                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 724                    !IS_VALLEYVIEW(dev)) {
 725                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 726                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 727
 728                 /*
 729                  * SFUSE_STRAP is supposed to have a bit signalling the display
 730                  * is fused off. Unfortunately it seems that, at least in
 731                  * certain cases, fused off display means that PCH display
 732                  * reads don't land anywhere. In that case, we read 0s.
 733                  *
 734                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 735                  * should be set when taking over after the firmware.
 736                  */
 737                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 738                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 739                     (dev_priv->pch_type == PCH_CPT &&
 740                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 741                         DRM_INFO("Display fused off, disabling\n");
 742                         info->num_pipes = 0;
 743                 }
 744         }
 745
 746         /* Initialize slice/subslice/EU info */
 747         if (IS_CHERRYVIEW(dev))
 748                 cherryview_sseu_info_init(dev);
 749         else if (INTEL_INFO(dev)->gen >= 9)
 750                 gen9_sseu_info_init(dev);
 751
 752         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 753         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 754         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 755         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 756         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 757         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 758                          info->has_slice_pg ? "y" : "n");
 759         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 760                          info->has_subslice_pg ? "y" : "n");
 761         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 762                          info->has_eu_pg ? "y" : "n");
 763 }
 764
 765 /**
 766  * i915_driver_load - setup chip and create an initial config
 767  * @dev: DRM device
 768  * @flags: startup flags
 769  *
 770  * The driver load routine has to do several things:
 771  *   - drive output discovery via intel_modeset_init()
 772  *   - initialize the memory manager
 773  *   - allocate initial config memory
 774  *   - setup the DRM framebuffer with the allocated memory
 775  */
 776 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 777 {
 778         struct drm_i915_private *dev_priv;
 779         struct intel_device_info *info, *device_info;
 780         int ret = 0, mmio_bar, mmio_size;
 781         uint32_t aperture_size;
 782
 783         info = (struct intel_device_info *) flags;
 784
 785         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 786         if (dev_priv == NULL)
 787                 return -ENOMEM;
 788
 789         dev->dev_private = dev_priv;
 790         dev_priv->dev = dev;
 791
 792         /* Setup the write-once "constant" device info */
 793         device_info = (struct intel_device_info *)&dev_priv->info;
 794         memcpy(device_info, info, sizeof(dev_priv->info));
 795         device_info->device_id = dev->pdev->device;
 796
 797         spin_lock_init(&dev_priv->irq_lock);
 798         spin_lock_init(&dev_priv->gpu_error.lock);
 799         mutex_init(&dev_priv->backlight_lock);
 800         spin_lock_init(&dev_priv->uncore.lock);
 801         spin_lock_init(&dev_priv->mm.object_stat_lock);
 802         spin_lock_init(&dev_priv->mmio_flip_lock);
 803         mutex_init(&dev_priv->sb_lock);
 804         mutex_init(&dev_priv->modeset_restore_lock);
 805         mutex_init(&dev_priv->csr_lock);
 806
 807         intel_pm_setup(dev);
 808
 809         intel_display_crc_init(dev);
 810
 811         i915_dump_device_info(dev_priv);
 812
 813         /* Not all pre-production machines fall into this category, only the
 814          * very first ones. Almost everything should work, except for maybe
 815          * suspend/resume. And we don't implement workarounds that affect only
 816          * pre-production machines. */
 817         if (IS_HSW_EARLY_SDV(dev))
 818                 DRM_INFO("This is an early pre-production Haswell machine. "
 819                          "It may not be fully functional.\n");
 820
 821         if (i915_get_bridge_dev(dev)) {
 822                 ret = -EIO;
 823                 goto free_priv;
 824         }
 825
 826         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 827         /* Before gen4, the registers and the GTT are behind different BARs.
 828          * However, from gen4 onwards, the registers and the GTT are shared
 829          * in the same BAR, so we want to restrict this ioremap from
 830          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 831          * the register BAR remains the same size for all the earlier
 832          * generations up to Ironlake.
 833          */
 834         if (info->gen < 5)
 835                 mmio_size = 512*1024;
 836         else
 837                 mmio_size = 2*1024*1024;
 838
 839         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 840         if (!dev_priv->regs) {
 841                 DRM_ERROR("failed to map registers\n");
 842                 ret = -EIO;
 843                 goto put_bridge;
 844         }
 845
 846         /* This must be called before any calls to HAS_PCH_* */
 847         intel_detect_pch(dev);
 848
 849         intel_uncore_init(dev);
 850
 851         /* Load CSR Firmware for SKL */
 852         intel_csr_ucode_init(dev);
 853
 854         ret = i915_gem_gtt_init(dev);
 855         if (ret)
 856                 goto out_freecsr;
 857
 858         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 859          * otherwise the vga fbdev driver falls over. */
 860         ret = i915_kick_out_firmware_fb(dev_priv);
 861         if (ret) {
 862                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 863                 goto out_gtt;
 864         }
 865
 866         ret = i915_kick_out_vgacon(dev_priv);
 867         if (ret) {
 868                 DRM_ERROR("failed to remove conflicting VGA console\n");
 869                 goto out_gtt;
 870         }
 871
 872         pci_set_master(dev->pdev);
 873
 874         /* overlay on gen2 is broken and can't address above 1G */
 875         if (IS_GEN2(dev))
 876                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 877
 878         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 879          * using 32bit addressing, overwriting memory if HWS is located
 880          * above 4GB.
 881          *
 882          * The documentation also mentions an issue with undefined
 883          * behaviour if any general state is accessed within a page above 4GB,
 884          * which also needs to be handled carefully.
 885          */
 886         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 887                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 888
 889         aperture_size = dev_priv->gtt.mappable_end;
 890
 891         dev_priv->gtt.mappable =
 892                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 893                                      aperture_size);
 894         if (dev_priv->gtt.mappable == NULL) {
 895                 ret = -EIO;
 896                 goto out_gtt;
 897         }
 898
 899         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 900                                               aperture_size);
 901
 902         /* The i915 workqueue is primarily used for batched retirement of
 903          * requests (and thus managing bo) once the task has been completed
 904          * by the GPU. i915_gem_retire_requests() is called directly when we
 905          * need high-priority retirement, such as waiting for an explicit
 906          * bo.
 907          *
 908          * It is also used for periodic low-priority events, such as
 909          * idle-timers and recording error state.
 910          *
 911          * All tasks on the workqueue are expected to acquire the dev mutex
 912          * so there is no point in running more than one instance of the
 913          * workqueue at any time.  Use an ordered one.
 914          */
 915         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 916         if (dev_priv->wq == NULL) {
 917                 DRM_ERROR("Failed to create our workqueue.\n");
 918                 ret = -ENOMEM;
 919                 goto out_mtrrfree;
 920         }
 921
 922         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 923         if (dev_priv->hotplug.dp_wq == NULL) {
 924                 DRM_ERROR("Failed to create our dp workqueue.\n");
 925                 ret = -ENOMEM;
 926                 goto out_freewq;
 927         }
 928
 929         dev_priv->gpu_error.hangcheck_wq =
 930                 alloc_ordered_workqueue("i915-hangcheck", 0);
 931         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
 932                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
 933                 ret = -ENOMEM;
 934                 goto out_freedpwq;
 935         }
 936
 937         intel_irq_init(dev_priv);
 938         intel_uncore_sanitize(dev);
 939
 940         /* Try to make sure MCHBAR is enabled before poking at it */
 941         intel_setup_mchbar(dev);
 942         intel_setup_gmbus(dev);
 943         intel_opregion_setup(dev);
 944
 945         intel_setup_bios(dev);
 946
 947         i915_gem_load(dev);
 948
 949         /* On the 945G/GM, the chipset reports the MSI capability on the
 950          * integrated graphics even though the support isn't actually there
 951          * according to the published specs.  It doesn't appear to function
 952          * correctly in testing on 945G.
 953          * This may be a side effect of MSI having been made available for PEG
 954          * and the registers being closely associated.
 955          *
 956          * According to chipset errata, on the 965GM, MSI interrupts may
 957          * be lost or delayed, but we use them anyways to avoid
 958          * stuck interrupts on some machines.
 959          */
 960         if (!IS_I945G(dev) && !IS_I945GM(dev))
 961                 pci_enable_msi(dev->pdev);
 962
 963         intel_device_info_runtime_init(dev);
 964
 965         if (INTEL_INFO(dev)->num_pipes) {
 966                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 967                 if (ret)
 968                         goto out_gem_unload;
 969         }
 970
 971         intel_power_domains_init(dev_priv);
 972
 973         ret = i915_load_modeset_init(dev);
 974         if (ret < 0) {
 975                 DRM_ERROR("failed to init modeset\n");
 976                 goto out_power_well;
 977         }
 978
 979         /*
 980          * Notify a valid surface after modesetting,
 981          * when running inside a VM.
 982          */
 983         if (intel_vgpu_active(dev))
 984                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
 985
 986         i915_setup_sysfs(dev);
 987
 988         if (INTEL_INFO(dev)->num_pipes) {
 989                 /* Must be done after probing outputs */
 990                 intel_opregion_init(dev);
 991                 acpi_video_register();
 992         }
 993
 994         if (IS_GEN5(dev))
 995                 intel_gpu_ips_init(dev_priv);
 996
 997         intel_runtime_pm_enable(dev_priv);
 998
 999         i915_audio_component_init(dev_priv);
1000
1001         return 0;
1002
1003 out_power_well:
1004         intel_power_domains_fini(dev_priv);
1005         drm_vblank_cleanup(dev);
1006 out_gem_unload:
1007         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1008         unregister_shrinker(&dev_priv->mm.shrinker);
1009
1010         if (dev->pdev->msi_enabled)
1011                 pci_disable_msi(dev->pdev);
1012
1013         intel_teardown_gmbus(dev);
1014         intel_teardown_mchbar(dev);
1015         pm_qos_remove_request(&dev_priv->pm_qos);
1016         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1017 out_freedpwq:
1018         destroy_workqueue(dev_priv->hotplug.dp_wq);
1019 out_freewq:
1020         destroy_workqueue(dev_priv->wq);
1021 out_mtrrfree:
1022         arch_phys_wc_del(dev_priv->gtt.mtrr);
1023         io_mapping_free(dev_priv->gtt.mappable);
1024 out_gtt:
1025         i915_global_gtt_cleanup(dev);
1026 out_freecsr:
1027         intel_csr_ucode_fini(dev);
1028         intel_uncore_fini(dev);
1029         pci_iounmap(dev->pdev, dev_priv->regs);
1030 put_bridge:
1031         pci_dev_put(dev_priv->bridge_dev);
1032 free_priv:
1033         if (dev_priv->requests)
1034                 kmem_cache_destroy(dev_priv->requests);
1035         if (dev_priv->vmas)
1036                 kmem_cache_destroy(dev_priv->vmas);
1037         if (dev_priv->objects)
1038                 kmem_cache_destroy(dev_priv->objects);
1039         kfree(dev_priv);
1040         return ret;
1041 }
1042
1043 int i915_driver_unload(struct drm_device *dev)
1044 {
1045         struct drm_i915_private *dev_priv = dev->dev_private;
1046         int ret;
1047
1048         i915_audio_component_cleanup(dev_priv);
1049
1050         ret = i915_gem_suspend(dev);
1051         if (ret) {
1052                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1053                 return ret;
1054         }
1055
1056         intel_power_domains_fini(dev_priv);
1057
1058         intel_gpu_ips_teardown();
1059
1060         i915_teardown_sysfs(dev);
1061
1062         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1063         unregister_shrinker(&dev_priv->mm.shrinker);
1064
1065         io_mapping_free(dev_priv->gtt.mappable);
1066         arch_phys_wc_del(dev_priv->gtt.mtrr);
1067
1068         acpi_video_unregister();
1069
1070         intel_fbdev_fini(dev);
1071
1072         drm_vblank_cleanup(dev);
1073
1074         intel_modeset_cleanup(dev);
1075
1076         /*
1077          * free the memory space allocated for the child device
1078          * config parsed from VBT
1079          */
1080         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1081                 kfree(dev_priv->vbt.child_dev);
1082                 dev_priv->vbt.child_dev = NULL;
1083                 dev_priv->vbt.child_dev_num = 0;
1084         }
1085
1086         vga_switcheroo_unregister_client(dev->pdev);
1087         vga_client_register(dev->pdev, NULL, NULL, NULL);
1088
1089         /* Free error state after interrupts are fully disabled. */
1090         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1091         i915_destroy_error_state(dev);
1092
1093         if (dev->pdev->msi_enabled)
1094                 pci_disable_msi(dev->pdev);
1095
1096         intel_opregion_fini(dev);
1097
1098         /* Flush any outstanding unpin_work. */
1099         flush_workqueue(dev_priv->wq);
1100
1101         mutex_lock(&dev->struct_mutex);
1102         i915_gem_cleanup_ringbuffer(dev);
1103         i915_gem_context_fini(dev);
1104         mutex_unlock(&dev->struct_mutex);
1105         intel_fbc_cleanup_cfb(dev_priv);
1106         i915_gem_cleanup_stolen(dev);
1107
1108         intel_csr_ucode_fini(dev);
1109
1110         intel_teardown_gmbus(dev);
1111         intel_teardown_mchbar(dev);
1112
1113         destroy_workqueue(dev_priv->hotplug.dp_wq);
1114         destroy_workqueue(dev_priv->wq);
1115         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1116         pm_qos_remove_request(&dev_priv->pm_qos);
1117
1118         i915_global_gtt_cleanup(dev);
1119
1120         intel_uncore_fini(dev);
1121         if (dev_priv->regs != NULL)
1122                 pci_iounmap(dev->pdev, dev_priv->regs);
1123
1124         if (dev_priv->requests)
1125                 kmem_cache_destroy(dev_priv->requests);
1126         if (dev_priv->vmas)
1127                 kmem_cache_destroy(dev_priv->vmas);
1128         if (dev_priv->objects)
1129                 kmem_cache_destroy(dev_priv->objects);
1130
1131         pci_dev_put(dev_priv->bridge_dev);
1132         kfree(dev_priv);
1133
1134         return 0;
1135 }
1136
1137 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1138 {
1139         int ret;
1140
1141         ret = i915_gem_open(dev, file);
1142         if (ret)
1143                 return ret;
1144
1145         return 0;
1146 }
1147
1148 /**
1149  * i915_driver_lastclose - clean up after all DRM clients have exited
1150  * @dev: DRM device
1151  *
1152  * Take care of cleaning up after all DRM clients have exited.  In the
1153  * mode setting case, we want to restore the kernel's initial mode (just
1154  * in case the last client left us in a bad state).
1155  *
1156  * Additionally, in the non-mode setting case, we'll tear down the GTT
1157  * and DMA structures, since the kernel won't be using them, and clea
1158  * up any GEM state.
1159  */
1160 void i915_driver_lastclose(struct drm_device *dev)
1161 {
1162         intel_fbdev_restore_mode(dev);
1163         vga_switcheroo_process_delayed_switch();
1164 }
1165
1166 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1167 {
1168         mutex_lock(&dev->struct_mutex);
1169         i915_gem_context_close(dev, file);
1170         i915_gem_release(dev, file);
1171         mutex_unlock(&dev->struct_mutex);
1172
1173         intel_modeset_preclose(dev, file);
1174 }
1175
1176 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1177 {
1178         struct drm_i915_file_private *file_priv = file->driver_priv;
1179
1180         if (file_priv && file_priv->bsd_ring)
1181                 file_priv->bsd_ring = NULL;
1182         kfree(file_priv);
1183 }
1184
1185 static int
1186 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1187                           struct drm_file *file)
1188 {
1189         return -ENODEV;
1190 }
1191
1192 const struct drm_ioctl_desc i915_ioctls[] = {
1193         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1194         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1195         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1196         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1197         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1198         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1199         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1200         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1201         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1202         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1203         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1204         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1205         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1206         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1207         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1208         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1209         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1210         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1211         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1212         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1213         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1214         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1215         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1216         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1217         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1218         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1219         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1220         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1221         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1222         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1223         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1224         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1225         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1226         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1227         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1228         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1229         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1230         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1231         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1232         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1233         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1234         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1235         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1236         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1237         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1238         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1239         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1240         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1241         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1242         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1243         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1244         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1245 };
1246
1247 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);