1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_legacy.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
38 #include "i915_vgpu.h"
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
54 static int i915_getparam(struct drm_device *dev, void *data,
55 struct drm_file *file_priv)
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 drm_i915_getparam_t *param = data;
61 switch (param->param) {
62 case I915_PARAM_IRQ_ACTIVE:
63 case I915_PARAM_ALLOW_BATCHBUFFER:
64 case I915_PARAM_LAST_DISPATCH:
65 /* Reject all old ums/dri params. */
67 case I915_PARAM_CHIPSET_ID:
68 value = dev->pdev->device;
70 case I915_PARAM_REVISION:
71 value = dev->pdev->revision;
73 case I915_PARAM_HAS_GEM:
76 case I915_PARAM_NUM_FENCES_AVAIL:
77 value = dev_priv->num_fence_regs;
79 case I915_PARAM_HAS_OVERLAY:
80 value = dev_priv->overlay ? 1 : 0;
82 case I915_PARAM_HAS_PAGEFLIPPING:
85 case I915_PARAM_HAS_EXECBUF2:
89 case I915_PARAM_HAS_BSD:
90 value = intel_ring_initialized(&dev_priv->ring[VCS]);
92 case I915_PARAM_HAS_BLT:
93 value = intel_ring_initialized(&dev_priv->ring[BCS]);
95 case I915_PARAM_HAS_VEBOX:
96 value = intel_ring_initialized(&dev_priv->ring[VECS]);
98 case I915_PARAM_HAS_BSD2:
99 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
101 case I915_PARAM_HAS_RELAXED_FENCING:
104 case I915_PARAM_HAS_COHERENT_RINGS:
107 case I915_PARAM_HAS_EXEC_CONSTANTS:
108 value = INTEL_INFO(dev)->gen >= 4;
110 case I915_PARAM_HAS_RELAXED_DELTA:
113 case I915_PARAM_HAS_GEN7_SOL_RESET:
116 case I915_PARAM_HAS_LLC:
117 value = HAS_LLC(dev);
119 case I915_PARAM_HAS_WT:
122 case I915_PARAM_HAS_ALIASING_PPGTT:
123 value = USES_PPGTT(dev);
125 case I915_PARAM_HAS_WAIT_TIMEOUT:
128 case I915_PARAM_HAS_SEMAPHORES:
129 value = i915_semaphore_is_enabled(dev);
131 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
134 case I915_PARAM_HAS_SECURE_BATCHES:
135 value = capable(CAP_SYS_ADMIN);
137 case I915_PARAM_HAS_PINNED_BATCHES:
140 case I915_PARAM_HAS_EXEC_NO_RELOC:
143 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
146 case I915_PARAM_CMD_PARSER_VERSION:
147 value = i915_cmd_parser_get_version();
149 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
152 case I915_PARAM_MMAP_VERSION:
155 case I915_PARAM_SUBSLICE_TOTAL:
156 value = INTEL_INFO(dev)->subslice_total;
160 case I915_PARAM_EU_TOTAL:
161 value = INTEL_INFO(dev)->eu_total;
165 case I915_PARAM_HAS_GPU_RESET:
166 value = i915.enable_hangcheck &&
167 intel_has_gpu_reset(dev);
169 case I915_PARAM_HAS_RESOURCE_STREAMER:
170 value = HAS_RESOURCE_STREAMER(dev);
173 DRM_DEBUG("Unknown parameter %d\n", param->param);
177 if (copy_to_user(param->value, &value, sizeof(int))) {
178 DRM_ERROR("copy_to_user failed\n");
185 static int i915_get_bridge_dev(struct drm_device *dev)
187 struct drm_i915_private *dev_priv = dev->dev_private;
189 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
190 if (!dev_priv->bridge_dev) {
191 DRM_ERROR("bridge device not found\n");
197 #define MCHBAR_I915 0x44
198 #define MCHBAR_I965 0x48
199 #define MCHBAR_SIZE (4*4096)
201 #define DEVEN_REG 0x54
202 #define DEVEN_MCHBAR_EN (1 << 28)
204 /* Allocate space for the MCH regs if needed, return nonzero on error */
206 intel_alloc_mchbar_resource(struct drm_device *dev)
208 struct drm_i915_private *dev_priv = dev->dev_private;
209 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
210 u32 temp_lo, temp_hi = 0;
214 if (INTEL_INFO(dev)->gen >= 4)
215 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
216 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
217 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
219 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
222 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
226 /* Get some space for it */
227 dev_priv->mch_res.name = "i915 MCHBAR";
228 dev_priv->mch_res.flags = IORESOURCE_MEM;
229 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
231 MCHBAR_SIZE, MCHBAR_SIZE,
233 0, pcibios_align_resource,
234 dev_priv->bridge_dev);
236 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
237 dev_priv->mch_res.start = 0;
241 if (INTEL_INFO(dev)->gen >= 4)
242 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
243 upper_32_bits(dev_priv->mch_res.start));
245 pci_write_config_dword(dev_priv->bridge_dev, reg,
246 lower_32_bits(dev_priv->mch_res.start));
250 /* Setup MCHBAR if possible, return true if we should disable it again */
252 intel_setup_mchbar(struct drm_device *dev)
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
259 if (IS_VALLEYVIEW(dev))
262 dev_priv->mchbar_need_disable = false;
264 if (IS_I915G(dev) || IS_I915GM(dev)) {
265 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
266 enabled = !!(temp & DEVEN_MCHBAR_EN);
268 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
272 /* If it's already enabled, don't have to do anything */
276 if (intel_alloc_mchbar_resource(dev))
279 dev_priv->mchbar_need_disable = true;
281 /* Space is allocated or reserved, so enable it. */
282 if (IS_I915G(dev) || IS_I915GM(dev)) {
283 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
284 temp | DEVEN_MCHBAR_EN);
286 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
287 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
292 intel_teardown_mchbar(struct drm_device *dev)
294 struct drm_i915_private *dev_priv = dev->dev_private;
295 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
298 if (dev_priv->mchbar_need_disable) {
299 if (IS_I915G(dev) || IS_I915GM(dev)) {
300 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
301 temp &= ~DEVEN_MCHBAR_EN;
302 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
304 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
306 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
310 if (dev_priv->mch_res.start)
311 release_resource(&dev_priv->mch_res);
314 /* true = enable decode, false = disable decoder */
315 static unsigned int i915_vga_set_decode(void *cookie, bool state)
317 struct drm_device *dev = cookie;
319 intel_modeset_vga_set_state(dev, state);
321 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
322 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
324 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
327 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
329 struct drm_device *dev = pci_get_drvdata(pdev);
330 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
332 if (state == VGA_SWITCHEROO_ON) {
333 pr_info("switched on\n");
334 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
335 /* i915 resume handler doesn't set to D0 */
336 pci_set_power_state(dev->pdev, PCI_D0);
337 i915_resume_switcheroo(dev);
338 dev->switch_power_state = DRM_SWITCH_POWER_ON;
340 pr_info("switched off\n");
341 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
342 i915_suspend_switcheroo(dev, pmm);
343 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
347 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
349 struct drm_device *dev = pci_get_drvdata(pdev);
352 * FIXME: open_count is protected by drm_global_mutex but that would lead to
353 * locking inversion with the driver load path. And the access here is
354 * completely racy anyway. So don't bother with locking for now.
356 return dev->open_count == 0;
359 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
360 .set_gpu_state = i915_switcheroo_set_state,
362 .can_switch = i915_switcheroo_can_switch,
365 static int i915_load_modeset_init(struct drm_device *dev)
367 struct drm_i915_private *dev_priv = dev->dev_private;
370 ret = intel_parse_bios(dev);
372 DRM_INFO("failed to find VBIOS tables\n");
374 /* If we have > 1 VGA cards, then we need to arbitrate access
375 * to the common VGA resources.
377 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
378 * then we do not take part in VGA arbitration and the
379 * vga_client_register() fails with -ENODEV.
381 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
382 if (ret && ret != -ENODEV)
385 intel_register_dsm_handler();
387 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
389 goto cleanup_vga_client;
391 /* Initialise stolen first so that we may reserve preallocated
392 * objects for the BIOS to KMS transition.
394 ret = i915_gem_init_stolen(dev);
396 goto cleanup_vga_switcheroo;
398 intel_power_domains_init_hw(dev_priv, false);
400 intel_csr_ucode_init(dev_priv);
402 ret = intel_irq_install(dev_priv);
404 goto cleanup_gem_stolen;
406 /* Important: The output setup functions called by modeset_init need
407 * working irqs for e.g. gmbus and dp aux transfers. */
408 intel_modeset_init(dev);
410 intel_guc_ucode_init(dev);
412 ret = i915_gem_init(dev);
416 intel_modeset_gem_init(dev);
418 /* Always safe in the mode setting case. */
419 /* FIXME: do pre/post-mode set stuff in core KMS code */
420 dev->vblank_disable_allowed = true;
421 if (INTEL_INFO(dev)->num_pipes == 0)
424 ret = intel_fbdev_init(dev);
428 /* Only enable hotplug handling once the fbdev is fully set up. */
429 intel_hpd_init(dev_priv);
432 * Some ports require correctly set-up hpd registers for detection to
433 * work properly (leading to ghost connected connector status), e.g. VGA
434 * on gm45. Hence we can only set up the initial fbdev config after hpd
435 * irqs are fully enabled. Now we should scan for the initial config
436 * only once hotplug handling is enabled, but due to screwed-up locking
437 * around kms/fbdev init we can't protect the fdbev initial config
438 * scanning against hotplug events. Hence do this first and ignore the
439 * tiny window where we will loose hotplug notifactions.
441 intel_fbdev_initial_config_async(dev);
443 drm_kms_helper_poll_init(dev);
448 mutex_lock(&dev->struct_mutex);
449 i915_gem_cleanup_ringbuffer(dev);
450 i915_gem_context_fini(dev);
451 mutex_unlock(&dev->struct_mutex);
453 intel_guc_ucode_fini(dev);
454 drm_irq_uninstall(dev);
456 i915_gem_cleanup_stolen(dev);
457 cleanup_vga_switcheroo:
458 vga_switcheroo_unregister_client(dev->pdev);
460 vga_client_register(dev->pdev, NULL, NULL, NULL);
465 #if IS_ENABLED(CONFIG_FB)
466 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
468 struct apertures_struct *ap;
469 struct pci_dev *pdev = dev_priv->dev->pdev;
473 ap = alloc_apertures(1);
477 ap->ranges[0].base = dev_priv->gtt.mappable_base;
478 ap->ranges[0].size = dev_priv->gtt.mappable_end;
481 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
483 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
490 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
496 #if !defined(CONFIG_VGA_CONSOLE)
497 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
501 #elif !defined(CONFIG_DUMMY_CONSOLE)
502 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
507 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
511 DRM_INFO("Replacing VGA console driver\n");
514 if (con_is_bound(&vga_con))
515 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
517 ret = do_unregister_con_driver(&vga_con);
519 /* Ignore "already unregistered". */
529 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
531 const struct intel_device_info *info = &dev_priv->info;
533 #define PRINT_S(name) "%s"
535 #define PRINT_FLAG(name) info->name ? #name "," : ""
537 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
538 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
540 dev_priv->dev->pdev->device,
541 dev_priv->dev->pdev->revision,
542 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
549 static void cherryview_sseu_info_init(struct drm_device *dev)
551 struct drm_i915_private *dev_priv = dev->dev_private;
552 struct intel_device_info *info;
555 info = (struct intel_device_info *)&dev_priv->info;
556 fuse = I915_READ(CHV_FUSE_GT);
558 info->slice_total = 1;
560 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
561 info->subslice_per_slice++;
562 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
563 CHV_FGT_EU_DIS_SS0_R1_MASK);
564 info->eu_total += 8 - hweight32(eu_dis);
567 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
568 info->subslice_per_slice++;
569 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
570 CHV_FGT_EU_DIS_SS1_R1_MASK);
571 info->eu_total += 8 - hweight32(eu_dis);
574 info->subslice_total = info->subslice_per_slice;
576 * CHV expected to always have a uniform distribution of EU
579 info->eu_per_subslice = info->subslice_total ?
580 info->eu_total / info->subslice_total :
583 * CHV supports subslice power gating on devices with more than
584 * one subslice, and supports EU power gating on devices with
585 * more than one EU pair per subslice.
587 info->has_slice_pg = 0;
588 info->has_subslice_pg = (info->subslice_total > 1);
589 info->has_eu_pg = (info->eu_per_subslice > 2);
592 static void gen9_sseu_info_init(struct drm_device *dev)
594 struct drm_i915_private *dev_priv = dev->dev_private;
595 struct intel_device_info *info;
596 int s_max = 3, ss_max = 4, eu_max = 8;
598 u32 fuse2, s_enable, ss_disable, eu_disable;
601 info = (struct intel_device_info *)&dev_priv->info;
602 fuse2 = I915_READ(GEN8_FUSE2);
603 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
605 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
606 GEN9_F2_SS_DIS_SHIFT;
608 info->slice_total = hweight32(s_enable);
610 * The subslice disable field is global, i.e. it applies
611 * to each of the enabled slices.
613 info->subslice_per_slice = ss_max - hweight32(ss_disable);
614 info->subslice_total = info->slice_total *
615 info->subslice_per_slice;
618 * Iterate through enabled slices and subslices to
619 * count the total enabled EU.
621 for (s = 0; s < s_max; s++) {
622 if (!(s_enable & (0x1 << s)))
623 /* skip disabled slice */
626 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
627 for (ss = 0; ss < ss_max; ss++) {
630 if (ss_disable & (0x1 << ss))
631 /* skip disabled subslice */
634 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
638 * Record which subslice(s) has(have) 7 EUs. we
639 * can tune the hash used to spread work among
640 * subslices if they are unbalanced.
643 info->subslice_7eu[s] |= 1 << ss;
645 info->eu_total += eu_per_ss;
650 * SKL is expected to always have a uniform distribution
651 * of EU across subslices with the exception that any one
652 * EU in any one subslice may be fused off for die
653 * recovery. BXT is expected to be perfectly uniform in EU
656 info->eu_per_subslice = info->subslice_total ?
657 DIV_ROUND_UP(info->eu_total,
658 info->subslice_total) : 0;
660 * SKL supports slice power gating on devices with more than
661 * one slice, and supports EU power gating on devices with
662 * more than one EU pair per subslice. BXT supports subslice
663 * power gating on devices with more than one subslice, and
664 * supports EU power gating on devices with more than one EU
667 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
668 (info->slice_total > 1));
669 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
670 info->has_eu_pg = (info->eu_per_subslice > 2);
673 static void broadwell_sseu_info_init(struct drm_device *dev)
675 struct drm_i915_private *dev_priv = dev->dev_private;
676 struct intel_device_info *info;
677 const int s_max = 3, ss_max = 3, eu_max = 8;
679 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
681 fuse2 = I915_READ(GEN8_FUSE2);
682 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
683 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
685 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
686 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
687 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
688 (32 - GEN8_EU_DIS0_S1_SHIFT));
689 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
690 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
691 (32 - GEN8_EU_DIS1_S2_SHIFT));
694 info = (struct intel_device_info *)&dev_priv->info;
695 info->slice_total = hweight32(s_enable);
698 * The subslice disable field is global, i.e. it applies
699 * to each of the enabled slices.
701 info->subslice_per_slice = ss_max - hweight32(ss_disable);
702 info->subslice_total = info->slice_total * info->subslice_per_slice;
705 * Iterate through enabled slices and subslices to
706 * count the total enabled EU.
708 for (s = 0; s < s_max; s++) {
709 if (!(s_enable & (0x1 << s)))
710 /* skip disabled slice */
713 for (ss = 0; ss < ss_max; ss++) {
716 if (ss_disable & (0x1 << ss))
717 /* skip disabled subslice */
720 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
723 * Record which subslices have 7 EUs.
725 if (eu_max - n_disabled == 7)
726 info->subslice_7eu[s] |= 1 << ss;
728 info->eu_total += eu_max - n_disabled;
733 * BDW is expected to always have a uniform distribution of EU across
734 * subslices with the exception that any one EU in any one subslice may
735 * be fused off for die recovery.
737 info->eu_per_subslice = info->subslice_total ?
738 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
741 * BDW supports slice power gating on devices with more than
744 info->has_slice_pg = (info->slice_total > 1);
745 info->has_subslice_pg = 0;
750 * Determine various intel_device_info fields at runtime.
752 * Use it when either:
753 * - it's judged too laborious to fill n static structures with the limit
754 * when a simple if statement does the job,
755 * - run-time checks (eg read fuse/strap registers) are needed.
757 * This function needs to be called:
758 * - after the MMIO has been setup as we are reading registers,
759 * - after the PCH has been detected,
760 * - before the first usage of the fields it can tweak.
762 static void intel_device_info_runtime_init(struct drm_device *dev)
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 struct intel_device_info *info;
768 info = (struct intel_device_info *)&dev_priv->info;
771 * Skylake and Broxton currently don't expose the topmost plane as its
772 * use is exclusive with the legacy cursor and we only want to expose
773 * one of those, not both. Until we can safely expose the topmost plane
774 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
775 * we don't expose the topmost plane at all to prevent ABI breakage
778 if (IS_BROXTON(dev)) {
779 info->num_sprites[PIPE_A] = 2;
780 info->num_sprites[PIPE_B] = 2;
781 info->num_sprites[PIPE_C] = 1;
782 } else if (IS_VALLEYVIEW(dev))
783 for_each_pipe(dev_priv, pipe)
784 info->num_sprites[pipe] = 2;
786 for_each_pipe(dev_priv, pipe)
787 info->num_sprites[pipe] = 1;
789 if (i915.disable_display) {
790 DRM_INFO("Display disabled (module parameter)\n");
792 } else if (info->num_pipes > 0 &&
793 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
794 !IS_VALLEYVIEW(dev)) {
795 u32 fuse_strap = I915_READ(FUSE_STRAP);
796 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
799 * SFUSE_STRAP is supposed to have a bit signalling the display
800 * is fused off. Unfortunately it seems that, at least in
801 * certain cases, fused off display means that PCH display
802 * reads don't land anywhere. In that case, we read 0s.
804 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
805 * should be set when taking over after the firmware.
807 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
808 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
809 (dev_priv->pch_type == PCH_CPT &&
810 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
811 DRM_INFO("Display fused off, disabling\n");
816 /* Initialize slice/subslice/EU info */
817 if (IS_CHERRYVIEW(dev))
818 cherryview_sseu_info_init(dev);
819 else if (IS_BROADWELL(dev))
820 broadwell_sseu_info_init(dev);
821 else if (INTEL_INFO(dev)->gen >= 9)
822 gen9_sseu_info_init(dev);
824 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
825 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
826 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
827 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
828 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
829 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
830 info->has_slice_pg ? "y" : "n");
831 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
832 info->has_subslice_pg ? "y" : "n");
833 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
834 info->has_eu_pg ? "y" : "n");
837 static void intel_init_dpio(struct drm_i915_private *dev_priv)
839 if (!IS_VALLEYVIEW(dev_priv))
843 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
844 * CHV x1 PHY (DP/HDMI D)
845 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
847 if (IS_CHERRYVIEW(dev_priv)) {
848 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
849 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
851 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
856 * i915_driver_load - setup chip and create an initial config
858 * @flags: startup flags
860 * The driver load routine has to do several things:
861 * - drive output discovery via intel_modeset_init()
862 * - initialize the memory manager
863 * - allocate initial config memory
864 * - setup the DRM framebuffer with the allocated memory
866 int i915_driver_load(struct drm_device *dev, unsigned long flags)
868 struct drm_i915_private *dev_priv;
869 struct intel_device_info *info, *device_info;
870 int ret = 0, mmio_bar, mmio_size;
871 uint32_t aperture_size;
873 info = (struct intel_device_info *) flags;
875 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
876 if (dev_priv == NULL)
879 dev->dev_private = dev_priv;
882 /* Setup the write-once "constant" device info */
883 device_info = (struct intel_device_info *)&dev_priv->info;
884 memcpy(device_info, info, sizeof(dev_priv->info));
885 device_info->device_id = dev->pdev->device;
887 spin_lock_init(&dev_priv->irq_lock);
888 spin_lock_init(&dev_priv->gpu_error.lock);
889 mutex_init(&dev_priv->backlight_lock);
890 spin_lock_init(&dev_priv->uncore.lock);
891 spin_lock_init(&dev_priv->mm.object_stat_lock);
892 spin_lock_init(&dev_priv->mmio_flip_lock);
893 mutex_init(&dev_priv->sb_lock);
894 mutex_init(&dev_priv->modeset_restore_lock);
895 mutex_init(&dev_priv->av_mutex);
899 intel_display_crc_init(dev);
901 i915_dump_device_info(dev_priv);
903 /* Not all pre-production machines fall into this category, only the
904 * very first ones. Almost everything should work, except for maybe
905 * suspend/resume. And we don't implement workarounds that affect only
906 * pre-production machines. */
907 if (IS_HSW_EARLY_SDV(dev))
908 DRM_INFO("This is an early pre-production Haswell machine. "
909 "It may not be fully functional.\n");
911 if (i915_get_bridge_dev(dev)) {
916 mmio_bar = IS_GEN2(dev) ? 1 : 0;
917 /* Before gen4, the registers and the GTT are behind different BARs.
918 * However, from gen4 onwards, the registers and the GTT are shared
919 * in the same BAR, so we want to restrict this ioremap from
920 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
921 * the register BAR remains the same size for all the earlier
922 * generations up to Ironlake.
925 mmio_size = 512*1024;
927 mmio_size = 2*1024*1024;
929 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
930 if (!dev_priv->regs) {
931 DRM_ERROR("failed to map registers\n");
936 /* This must be called before any calls to HAS_PCH_* */
937 intel_detect_pch(dev);
939 intel_uncore_init(dev);
941 ret = i915_gem_gtt_init(dev);
945 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
946 * otherwise the vga fbdev driver falls over. */
947 ret = i915_kick_out_firmware_fb(dev_priv);
949 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
953 ret = i915_kick_out_vgacon(dev_priv);
955 DRM_ERROR("failed to remove conflicting VGA console\n");
959 pci_set_master(dev->pdev);
961 /* overlay on gen2 is broken and can't address above 1G */
963 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
965 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
966 * using 32bit addressing, overwriting memory if HWS is located
969 * The documentation also mentions an issue with undefined
970 * behaviour if any general state is accessed within a page above 4GB,
971 * which also needs to be handled carefully.
973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
974 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
976 aperture_size = dev_priv->gtt.mappable_end;
978 dev_priv->gtt.mappable =
979 io_mapping_create_wc(dev_priv->gtt.mappable_base,
981 if (dev_priv->gtt.mappable == NULL) {
986 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
989 /* The i915 workqueue is primarily used for batched retirement of
990 * requests (and thus managing bo) once the task has been completed
991 * by the GPU. i915_gem_retire_requests() is called directly when we
992 * need high-priority retirement, such as waiting for an explicit
995 * It is also used for periodic low-priority events, such as
996 * idle-timers and recording error state.
998 * All tasks on the workqueue are expected to acquire the dev mutex
999 * so there is no point in running more than one instance of the
1000 * workqueue at any time. Use an ordered one.
1002 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1003 if (dev_priv->wq == NULL) {
1004 DRM_ERROR("Failed to create our workqueue.\n");
1009 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1010 if (dev_priv->hotplug.dp_wq == NULL) {
1011 DRM_ERROR("Failed to create our dp workqueue.\n");
1016 dev_priv->gpu_error.hangcheck_wq =
1017 alloc_ordered_workqueue("i915-hangcheck", 0);
1018 if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1019 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1024 intel_irq_init(dev_priv);
1025 intel_uncore_sanitize(dev);
1027 /* Try to make sure MCHBAR is enabled before poking at it */
1028 intel_setup_mchbar(dev);
1029 intel_setup_gmbus(dev);
1030 intel_opregion_setup(dev);
1034 /* On the 945G/GM, the chipset reports the MSI capability on the
1035 * integrated graphics even though the support isn't actually there
1036 * according to the published specs. It doesn't appear to function
1037 * correctly in testing on 945G.
1038 * This may be a side effect of MSI having been made available for PEG
1039 * and the registers being closely associated.
1041 * According to chipset errata, on the 965GM, MSI interrupts may
1042 * be lost or delayed, but we use them anyways to avoid
1043 * stuck interrupts on some machines.
1045 if (!IS_I945G(dev) && !IS_I945GM(dev))
1046 pci_enable_msi(dev->pdev);
1048 intel_device_info_runtime_init(dev);
1050 intel_init_dpio(dev_priv);
1052 if (INTEL_INFO(dev)->num_pipes) {
1053 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1055 goto out_gem_unload;
1058 intel_power_domains_init(dev_priv);
1060 ret = i915_load_modeset_init(dev);
1062 DRM_ERROR("failed to init modeset\n");
1063 goto out_power_well;
1067 * Notify a valid surface after modesetting,
1068 * when running inside a VM.
1070 if (intel_vgpu_active(dev))
1071 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1073 i915_setup_sysfs(dev);
1075 if (INTEL_INFO(dev)->num_pipes) {
1076 /* Must be done after probing outputs */
1077 intel_opregion_init(dev);
1078 acpi_video_register();
1082 intel_gpu_ips_init(dev_priv);
1084 intel_runtime_pm_enable(dev_priv);
1086 i915_audio_component_init(dev_priv);
1091 intel_power_domains_fini(dev_priv);
1092 drm_vblank_cleanup(dev);
1094 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1095 unregister_shrinker(&dev_priv->mm.shrinker);
1097 if (dev->pdev->msi_enabled)
1098 pci_disable_msi(dev->pdev);
1100 intel_teardown_gmbus(dev);
1101 intel_teardown_mchbar(dev);
1102 pm_qos_remove_request(&dev_priv->pm_qos);
1103 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1105 destroy_workqueue(dev_priv->hotplug.dp_wq);
1107 destroy_workqueue(dev_priv->wq);
1109 arch_phys_wc_del(dev_priv->gtt.mtrr);
1110 io_mapping_free(dev_priv->gtt.mappable);
1112 i915_global_gtt_cleanup(dev);
1114 intel_csr_ucode_fini(dev_priv);
1115 intel_uncore_fini(dev);
1116 pci_iounmap(dev->pdev, dev_priv->regs);
1118 pci_dev_put(dev_priv->bridge_dev);
1120 kmem_cache_destroy(dev_priv->requests);
1121 kmem_cache_destroy(dev_priv->vmas);
1122 kmem_cache_destroy(dev_priv->objects);
1127 int i915_driver_unload(struct drm_device *dev)
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1132 intel_fbdev_fini(dev);
1134 i915_audio_component_cleanup(dev_priv);
1136 ret = i915_gem_suspend(dev);
1138 DRM_ERROR("failed to idle hardware: %d\n", ret);
1142 intel_power_domains_fini(dev_priv);
1144 intel_gpu_ips_teardown();
1146 i915_teardown_sysfs(dev);
1148 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1149 unregister_shrinker(&dev_priv->mm.shrinker);
1151 io_mapping_free(dev_priv->gtt.mappable);
1152 arch_phys_wc_del(dev_priv->gtt.mtrr);
1154 acpi_video_unregister();
1156 drm_vblank_cleanup(dev);
1158 intel_modeset_cleanup(dev);
1161 * free the memory space allocated for the child device
1162 * config parsed from VBT
1164 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1165 kfree(dev_priv->vbt.child_dev);
1166 dev_priv->vbt.child_dev = NULL;
1167 dev_priv->vbt.child_dev_num = 0;
1169 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1170 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1171 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1172 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1174 vga_switcheroo_unregister_client(dev->pdev);
1175 vga_client_register(dev->pdev, NULL, NULL, NULL);
1177 /* Free error state after interrupts are fully disabled. */
1178 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1179 i915_destroy_error_state(dev);
1181 if (dev->pdev->msi_enabled)
1182 pci_disable_msi(dev->pdev);
1184 intel_opregion_fini(dev);
1186 /* Flush any outstanding unpin_work. */
1187 flush_workqueue(dev_priv->wq);
1189 intel_guc_ucode_fini(dev);
1190 mutex_lock(&dev->struct_mutex);
1191 i915_gem_cleanup_ringbuffer(dev);
1192 i915_gem_context_fini(dev);
1193 mutex_unlock(&dev->struct_mutex);
1194 intel_fbc_cleanup_cfb(dev_priv);
1195 i915_gem_cleanup_stolen(dev);
1197 intel_csr_ucode_fini(dev_priv);
1199 intel_teardown_gmbus(dev);
1200 intel_teardown_mchbar(dev);
1202 destroy_workqueue(dev_priv->hotplug.dp_wq);
1203 destroy_workqueue(dev_priv->wq);
1204 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1205 pm_qos_remove_request(&dev_priv->pm_qos);
1207 i915_global_gtt_cleanup(dev);
1209 intel_uncore_fini(dev);
1210 if (dev_priv->regs != NULL)
1211 pci_iounmap(dev->pdev, dev_priv->regs);
1213 kmem_cache_destroy(dev_priv->requests);
1214 kmem_cache_destroy(dev_priv->vmas);
1215 kmem_cache_destroy(dev_priv->objects);
1216 pci_dev_put(dev_priv->bridge_dev);
1222 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1226 ret = i915_gem_open(dev, file);
1234 * i915_driver_lastclose - clean up after all DRM clients have exited
1237 * Take care of cleaning up after all DRM clients have exited. In the
1238 * mode setting case, we want to restore the kernel's initial mode (just
1239 * in case the last client left us in a bad state).
1241 * Additionally, in the non-mode setting case, we'll tear down the GTT
1242 * and DMA structures, since the kernel won't be using them, and clea
1245 void i915_driver_lastclose(struct drm_device *dev)
1247 intel_fbdev_restore_mode(dev);
1248 vga_switcheroo_process_delayed_switch();
1251 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1253 mutex_lock(&dev->struct_mutex);
1254 i915_gem_context_close(dev, file);
1255 i915_gem_release(dev, file);
1256 mutex_unlock(&dev->struct_mutex);
1258 intel_modeset_preclose(dev, file);
1261 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1263 struct drm_i915_file_private *file_priv = file->driver_priv;
1269 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1270 struct drm_file *file)
1275 const struct drm_ioctl_desc i915_ioctls[] = {
1276 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1277 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1278 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1279 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1280 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1281 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1282 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1283 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1284 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1285 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1286 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1287 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1288 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1289 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1290 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1291 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1292 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1293 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1294 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1295 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1296 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1297 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1298 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1299 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1300 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1301 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1302 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1303 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1304 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1305 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1306 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1307 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1308 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1309 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1310 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1311 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1312 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1313 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1314 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1315 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1316 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1317 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1318 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1319 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1320 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1321 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1322 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1323 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1324 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1325 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1326 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1327 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1330 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);