1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
36 #include "i915_trace.h"
37 #include "../../../platform/x86/intel_ips.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <linux/module.h>
45 #include <acpi/video.h>
47 static void i915_write_hws_pga(struct drm_device *dev)
49 drm_i915_private_t *dev_priv = dev->dev_private;
52 addr = dev_priv->status_page_dmah->busaddr;
53 if (INTEL_INFO(dev)->gen >= 4)
54 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
55 I915_WRITE(HWS_PGA, addr);
59 * Sets up the hardware status page for devices that need a physical address
62 static int i915_init_phys_hws(struct drm_device *dev)
64 drm_i915_private_t *dev_priv = dev->dev_private;
66 /* Program Hardware Status Page */
67 dev_priv->status_page_dmah =
68 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
70 if (!dev_priv->status_page_dmah) {
71 DRM_ERROR("Can not allocate hardware status page\n");
75 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
78 i915_write_hws_pga(dev);
80 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
85 * Frees the hardware status page, whether it's a physical address or a virtual
86 * address set up by the X Server.
88 static void i915_free_hws(struct drm_device *dev)
90 drm_i915_private_t *dev_priv = dev->dev_private;
91 struct intel_ring_buffer *ring = LP_RING(dev_priv);
93 if (dev_priv->status_page_dmah) {
94 drm_pci_free(dev, dev_priv->status_page_dmah);
95 dev_priv->status_page_dmah = NULL;
98 if (ring->status_page.gfx_addr) {
99 ring->status_page.gfx_addr = 0;
100 drm_core_ioremapfree(&dev_priv->hws_map, dev);
103 /* Need to rewrite hardware status page */
104 I915_WRITE(HWS_PGA, 0x1ffff000);
107 void i915_kernel_lost_context(struct drm_device * dev)
109 drm_i915_private_t *dev_priv = dev->dev_private;
110 struct drm_i915_master_private *master_priv;
111 struct intel_ring_buffer *ring = LP_RING(dev_priv);
114 * We should never lose context on the ring with modesetting
115 * as we don't expose it to userspace
117 if (drm_core_check_feature(dev, DRIVER_MODESET))
120 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
121 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
122 ring->space = ring->head - (ring->tail + 8);
124 ring->space += ring->size;
126 if (!dev->primary->master)
129 master_priv = dev->primary->master->driver_priv;
130 if (ring->head == ring->tail && master_priv->sarea_priv)
131 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
134 static int i915_dma_cleanup(struct drm_device * dev)
136 drm_i915_private_t *dev_priv = dev->dev_private;
139 /* Make sure interrupts are disabled here because the uninstall ioctl
140 * may not have been called from userspace and after dev_private
141 * is freed, it's too late.
143 if (dev->irq_enabled)
144 drm_irq_uninstall(dev);
146 mutex_lock(&dev->struct_mutex);
147 for (i = 0; i < I915_NUM_RINGS; i++)
148 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
149 mutex_unlock(&dev->struct_mutex);
151 /* Clear the HWS virtual address at teardown */
152 if (I915_NEED_GFX_HWS(dev))
158 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
160 drm_i915_private_t *dev_priv = dev->dev_private;
161 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
164 master_priv->sarea = drm_getsarea(dev);
165 if (master_priv->sarea) {
166 master_priv->sarea_priv = (drm_i915_sarea_t *)
167 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
169 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
172 if (init->ring_size != 0) {
173 if (LP_RING(dev_priv)->obj != NULL) {
174 i915_dma_cleanup(dev);
175 DRM_ERROR("Client tried to initialize ringbuffer in "
180 ret = intel_render_ring_init_dri(dev,
184 i915_dma_cleanup(dev);
189 dev_priv->cpp = init->cpp;
190 dev_priv->back_offset = init->back_offset;
191 dev_priv->front_offset = init->front_offset;
192 dev_priv->current_page = 0;
193 if (master_priv->sarea_priv)
194 master_priv->sarea_priv->pf_current_page = 0;
196 /* Allow hardware batchbuffers unless told otherwise.
198 dev_priv->allow_batchbuffer = 1;
203 static int i915_dma_resume(struct drm_device * dev)
205 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
206 struct intel_ring_buffer *ring = LP_RING(dev_priv);
208 DRM_DEBUG_DRIVER("%s\n", __func__);
210 if (ring->map.handle == NULL) {
211 DRM_ERROR("can not ioremap virtual address for"
216 /* Program Hardware Status Page */
217 if (!ring->status_page.page_addr) {
218 DRM_ERROR("Can not find hardware status page\n");
221 DRM_DEBUG_DRIVER("hw status page @ %p\n",
222 ring->status_page.page_addr);
223 if (ring->status_page.gfx_addr != 0)
224 intel_ring_setup_status_page(ring);
226 i915_write_hws_pga(dev);
228 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
233 static int i915_dma_init(struct drm_device *dev, void *data,
234 struct drm_file *file_priv)
236 drm_i915_init_t *init = data;
239 switch (init->func) {
241 retcode = i915_initialize(dev, init);
243 case I915_CLEANUP_DMA:
244 retcode = i915_dma_cleanup(dev);
246 case I915_RESUME_DMA:
247 retcode = i915_dma_resume(dev);
257 /* Implement basically the same security restrictions as hardware does
258 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
260 * Most of the calculations below involve calculating the size of a
261 * particular instruction. It's important to get the size right as
262 * that tells us where the next instruction to check is. Any illegal
263 * instruction detected will be given a size of zero, which is a
264 * signal to abort the rest of the buffer.
266 static int validate_cmd(int cmd)
268 switch (((cmd >> 29) & 0x7)) {
270 switch ((cmd >> 23) & 0x3f) {
272 return 1; /* MI_NOOP */
274 return 1; /* MI_FLUSH */
276 return 0; /* disallow everything else */
280 return 0; /* reserved */
282 return (cmd & 0xff) + 2; /* 2d commands */
284 if (((cmd >> 24) & 0x1f) <= 0x18)
287 switch ((cmd >> 24) & 0x1f) {
291 switch ((cmd >> 16) & 0xff) {
293 return (cmd & 0x1f) + 2;
295 return (cmd & 0xf) + 2;
297 return (cmd & 0xffff) + 2;
301 return (cmd & 0xffff) + 1;
305 if ((cmd & (1 << 23)) == 0) /* inline vertices */
306 return (cmd & 0x1ffff) + 2;
307 else if (cmd & (1 << 17)) /* indirect random */
308 if ((cmd & 0xffff) == 0)
309 return 0; /* unknown length, too hard */
311 return (((cmd & 0xffff) + 1) / 2) + 1;
313 return 2; /* indirect sequential */
324 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
326 drm_i915_private_t *dev_priv = dev->dev_private;
329 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
332 for (i = 0; i < dwords;) {
333 int sz = validate_cmd(buffer[i]);
334 if (sz == 0 || i + sz > dwords)
339 ret = BEGIN_LP_RING((dwords+1)&~1);
343 for (i = 0; i < dwords; i++)
354 i915_emit_box(struct drm_device *dev,
355 struct drm_clip_rect *box,
358 struct drm_i915_private *dev_priv = dev->dev_private;
361 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
362 box->y2 <= 0 || box->x2 <= 0) {
363 DRM_ERROR("Bad box %d,%d..%d,%d\n",
364 box->x1, box->y1, box->x2, box->y2);
368 if (INTEL_INFO(dev)->gen >= 4) {
369 ret = BEGIN_LP_RING(4);
373 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
374 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
375 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
378 ret = BEGIN_LP_RING(6);
382 OUT_RING(GFX_OP_DRAWRECT_INFO);
384 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
385 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
394 /* XXX: Emitting the counter should really be moved to part of the IRQ
395 * emit. For now, do it in both places:
398 static void i915_emit_breadcrumb(struct drm_device *dev)
400 drm_i915_private_t *dev_priv = dev->dev_private;
401 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
404 if (dev_priv->counter > 0x7FFFFFFFUL)
405 dev_priv->counter = 0;
406 if (master_priv->sarea_priv)
407 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
409 if (BEGIN_LP_RING(4) == 0) {
410 OUT_RING(MI_STORE_DWORD_INDEX);
411 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
412 OUT_RING(dev_priv->counter);
418 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
419 drm_i915_cmdbuffer_t *cmd,
420 struct drm_clip_rect *cliprects,
423 int nbox = cmd->num_cliprects;
424 int i = 0, count, ret;
427 DRM_ERROR("alignment");
431 i915_kernel_lost_context(dev);
433 count = nbox ? nbox : 1;
435 for (i = 0; i < count; i++) {
437 ret = i915_emit_box(dev, &cliprects[i],
443 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
448 i915_emit_breadcrumb(dev);
452 static int i915_dispatch_batchbuffer(struct drm_device * dev,
453 drm_i915_batchbuffer_t * batch,
454 struct drm_clip_rect *cliprects)
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 int nbox = batch->num_cliprects;
460 if ((batch->start | batch->used) & 0x7) {
461 DRM_ERROR("alignment");
465 i915_kernel_lost_context(dev);
467 count = nbox ? nbox : 1;
468 for (i = 0; i < count; i++) {
470 ret = i915_emit_box(dev, &cliprects[i],
471 batch->DR1, batch->DR4);
476 if (!IS_I830(dev) && !IS_845G(dev)) {
477 ret = BEGIN_LP_RING(2);
481 if (INTEL_INFO(dev)->gen >= 4) {
482 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
483 OUT_RING(batch->start);
485 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
486 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
489 ret = BEGIN_LP_RING(4);
493 OUT_RING(MI_BATCH_BUFFER);
494 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
495 OUT_RING(batch->start + batch->used - 4);
502 if (IS_G4X(dev) || IS_GEN5(dev)) {
503 if (BEGIN_LP_RING(2) == 0) {
504 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
510 i915_emit_breadcrumb(dev);
514 static int i915_dispatch_flip(struct drm_device * dev)
516 drm_i915_private_t *dev_priv = dev->dev_private;
517 struct drm_i915_master_private *master_priv =
518 dev->primary->master->driver_priv;
521 if (!master_priv->sarea_priv)
524 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
526 dev_priv->current_page,
527 master_priv->sarea_priv->pf_current_page);
529 i915_kernel_lost_context(dev);
531 ret = BEGIN_LP_RING(10);
535 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
538 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
540 if (dev_priv->current_page == 0) {
541 OUT_RING(dev_priv->back_offset);
542 dev_priv->current_page = 1;
544 OUT_RING(dev_priv->front_offset);
545 dev_priv->current_page = 0;
549 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
554 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
556 if (BEGIN_LP_RING(4) == 0) {
557 OUT_RING(MI_STORE_DWORD_INDEX);
558 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
559 OUT_RING(dev_priv->counter);
564 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
568 static int i915_quiescent(struct drm_device *dev)
570 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
572 i915_kernel_lost_context(dev);
573 return intel_wait_ring_idle(ring);
576 static int i915_flush_ioctl(struct drm_device *dev, void *data,
577 struct drm_file *file_priv)
581 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
583 mutex_lock(&dev->struct_mutex);
584 ret = i915_quiescent(dev);
585 mutex_unlock(&dev->struct_mutex);
590 static int i915_batchbuffer(struct drm_device *dev, void *data,
591 struct drm_file *file_priv)
593 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
594 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
595 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
596 master_priv->sarea_priv;
597 drm_i915_batchbuffer_t *batch = data;
599 struct drm_clip_rect *cliprects = NULL;
601 if (!dev_priv->allow_batchbuffer) {
602 DRM_ERROR("Batchbuffer ioctl disabled\n");
606 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
607 batch->start, batch->used, batch->num_cliprects);
609 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
611 if (batch->num_cliprects < 0)
614 if (batch->num_cliprects) {
615 cliprects = kcalloc(batch->num_cliprects,
616 sizeof(struct drm_clip_rect),
618 if (cliprects == NULL)
621 ret = copy_from_user(cliprects, batch->cliprects,
622 batch->num_cliprects *
623 sizeof(struct drm_clip_rect));
630 mutex_lock(&dev->struct_mutex);
631 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
632 mutex_unlock(&dev->struct_mutex);
635 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
643 static int i915_cmdbuffer(struct drm_device *dev, void *data,
644 struct drm_file *file_priv)
646 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
647 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
648 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
649 master_priv->sarea_priv;
650 drm_i915_cmdbuffer_t *cmdbuf = data;
651 struct drm_clip_rect *cliprects = NULL;
655 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
656 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
658 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
660 if (cmdbuf->num_cliprects < 0)
663 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
664 if (batch_data == NULL)
667 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
670 goto fail_batch_free;
673 if (cmdbuf->num_cliprects) {
674 cliprects = kcalloc(cmdbuf->num_cliprects,
675 sizeof(struct drm_clip_rect), GFP_KERNEL);
676 if (cliprects == NULL) {
678 goto fail_batch_free;
681 ret = copy_from_user(cliprects, cmdbuf->cliprects,
682 cmdbuf->num_cliprects *
683 sizeof(struct drm_clip_rect));
690 mutex_lock(&dev->struct_mutex);
691 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
692 mutex_unlock(&dev->struct_mutex);
694 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
699 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
709 static int i915_flip_bufs(struct drm_device *dev, void *data,
710 struct drm_file *file_priv)
714 DRM_DEBUG_DRIVER("%s\n", __func__);
716 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
718 mutex_lock(&dev->struct_mutex);
719 ret = i915_dispatch_flip(dev);
720 mutex_unlock(&dev->struct_mutex);
725 static int i915_getparam(struct drm_device *dev, void *data,
726 struct drm_file *file_priv)
728 drm_i915_private_t *dev_priv = dev->dev_private;
729 drm_i915_getparam_t *param = data;
733 DRM_ERROR("called with no initialization\n");
737 switch (param->param) {
738 case I915_PARAM_IRQ_ACTIVE:
739 value = dev->pdev->irq ? 1 : 0;
741 case I915_PARAM_ALLOW_BATCHBUFFER:
742 value = dev_priv->allow_batchbuffer ? 1 : 0;
744 case I915_PARAM_LAST_DISPATCH:
745 value = READ_BREADCRUMB(dev_priv);
747 case I915_PARAM_CHIPSET_ID:
748 value = dev->pci_device;
750 case I915_PARAM_HAS_GEM:
751 value = dev_priv->has_gem;
753 case I915_PARAM_NUM_FENCES_AVAIL:
754 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
756 case I915_PARAM_HAS_OVERLAY:
757 value = dev_priv->overlay ? 1 : 0;
759 case I915_PARAM_HAS_PAGEFLIPPING:
762 case I915_PARAM_HAS_EXECBUF2:
764 value = dev_priv->has_gem;
766 case I915_PARAM_HAS_BSD:
767 value = HAS_BSD(dev);
769 case I915_PARAM_HAS_BLT:
770 value = HAS_BLT(dev);
772 case I915_PARAM_HAS_RELAXED_FENCING:
775 case I915_PARAM_HAS_COHERENT_RINGS:
778 case I915_PARAM_HAS_EXEC_CONSTANTS:
779 value = INTEL_INFO(dev)->gen >= 4;
781 case I915_PARAM_HAS_RELAXED_DELTA:
784 case I915_PARAM_HAS_GEN7_SOL_RESET:
787 case I915_PARAM_HAS_LLC:
788 value = HAS_LLC(dev);
791 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
796 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
797 DRM_ERROR("DRM_COPY_TO_USER failed\n");
804 static int i915_setparam(struct drm_device *dev, void *data,
805 struct drm_file *file_priv)
807 drm_i915_private_t *dev_priv = dev->dev_private;
808 drm_i915_setparam_t *param = data;
811 DRM_ERROR("called with no initialization\n");
815 switch (param->param) {
816 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
818 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
819 dev_priv->tex_lru_log_granularity = param->value;
821 case I915_SETPARAM_ALLOW_BATCHBUFFER:
822 dev_priv->allow_batchbuffer = param->value;
824 case I915_SETPARAM_NUM_USED_FENCES:
825 if (param->value > dev_priv->num_fence_regs ||
828 /* Userspace can use first N regs */
829 dev_priv->fence_reg_start = param->value;
832 DRM_DEBUG_DRIVER("unknown parameter %d\n",
840 static int i915_set_status_page(struct drm_device *dev, void *data,
841 struct drm_file *file_priv)
843 drm_i915_private_t *dev_priv = dev->dev_private;
844 drm_i915_hws_addr_t *hws = data;
845 struct intel_ring_buffer *ring = LP_RING(dev_priv);
847 if (!I915_NEED_GFX_HWS(dev))
851 DRM_ERROR("called with no initialization\n");
855 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
856 WARN(1, "tried to set status page when mode setting active\n");
860 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
862 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
864 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
865 dev_priv->hws_map.size = 4*1024;
866 dev_priv->hws_map.type = 0;
867 dev_priv->hws_map.flags = 0;
868 dev_priv->hws_map.mtrr = 0;
870 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
871 if (dev_priv->hws_map.handle == NULL) {
872 i915_dma_cleanup(dev);
873 ring->status_page.gfx_addr = 0;
874 DRM_ERROR("can not ioremap virtual address for"
875 " G33 hw status page\n");
878 ring->status_page.page_addr =
879 (void __force __iomem *)dev_priv->hws_map.handle;
880 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
881 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
883 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
884 ring->status_page.gfx_addr);
885 DRM_DEBUG_DRIVER("load hws at %p\n",
886 ring->status_page.page_addr);
890 static int i915_get_bridge_dev(struct drm_device *dev)
892 struct drm_i915_private *dev_priv = dev->dev_private;
894 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
895 if (!dev_priv->bridge_dev) {
896 DRM_ERROR("bridge device not found\n");
902 #define MCHBAR_I915 0x44
903 #define MCHBAR_I965 0x48
904 #define MCHBAR_SIZE (4*4096)
906 #define DEVEN_REG 0x54
907 #define DEVEN_MCHBAR_EN (1 << 28)
909 /* Allocate space for the MCH regs if needed, return nonzero on error */
911 intel_alloc_mchbar_resource(struct drm_device *dev)
913 drm_i915_private_t *dev_priv = dev->dev_private;
914 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
915 u32 temp_lo, temp_hi = 0;
919 if (INTEL_INFO(dev)->gen >= 4)
920 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
921 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
922 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
924 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
927 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
931 /* Get some space for it */
932 dev_priv->mch_res.name = "i915 MCHBAR";
933 dev_priv->mch_res.flags = IORESOURCE_MEM;
934 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
936 MCHBAR_SIZE, MCHBAR_SIZE,
938 0, pcibios_align_resource,
939 dev_priv->bridge_dev);
941 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
942 dev_priv->mch_res.start = 0;
946 if (INTEL_INFO(dev)->gen >= 4)
947 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
948 upper_32_bits(dev_priv->mch_res.start));
950 pci_write_config_dword(dev_priv->bridge_dev, reg,
951 lower_32_bits(dev_priv->mch_res.start));
955 /* Setup MCHBAR if possible, return true if we should disable it again */
957 intel_setup_mchbar(struct drm_device *dev)
959 drm_i915_private_t *dev_priv = dev->dev_private;
960 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
964 dev_priv->mchbar_need_disable = false;
966 if (IS_I915G(dev) || IS_I915GM(dev)) {
967 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
968 enabled = !!(temp & DEVEN_MCHBAR_EN);
970 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
974 /* If it's already enabled, don't have to do anything */
978 if (intel_alloc_mchbar_resource(dev))
981 dev_priv->mchbar_need_disable = true;
983 /* Space is allocated or reserved, so enable it. */
984 if (IS_I915G(dev) || IS_I915GM(dev)) {
985 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
986 temp | DEVEN_MCHBAR_EN);
988 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
989 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
994 intel_teardown_mchbar(struct drm_device *dev)
996 drm_i915_private_t *dev_priv = dev->dev_private;
997 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1000 if (dev_priv->mchbar_need_disable) {
1001 if (IS_I915G(dev) || IS_I915GM(dev)) {
1002 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1003 temp &= ~DEVEN_MCHBAR_EN;
1004 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1006 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1008 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1012 if (dev_priv->mch_res.start)
1013 release_resource(&dev_priv->mch_res);
1016 #define PTE_ADDRESS_MASK 0xfffff000
1017 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1018 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1019 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1020 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1021 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1022 #define PTE_VALID (1 << 0)
1025 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1028 * @offset: address to translate
1030 * Some chip functions require allocations from stolen space and need the
1031 * physical address of the memory in question.
1033 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036 struct pci_dev *pdev = dev_priv->bridge_dev;
1040 /* On the machines I have tested the Graphics Base of Stolen Memory
1041 * is unreliable, so compute the base by subtracting the stolen memory
1042 * from the Top of Low Usable DRAM which is where the BIOS places
1043 * the graphics stolen memory.
1045 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1046 /* top 32bits are reserved = 0 */
1047 pci_read_config_dword(pdev, 0xA4, &base);
1049 /* XXX presume 8xx is the same as i915 */
1050 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1053 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1055 pci_read_config_word(pdev, 0xb0, &val);
1056 base = val >> 4 << 20;
1059 pci_read_config_byte(pdev, 0x9c, &val);
1060 base = val >> 3 << 27;
1062 base -= dev_priv->mm.gtt->stolen_size;
1065 return base + offset;
1068 static void i915_warn_stolen(struct drm_device *dev)
1070 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1071 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1074 static void i915_setup_compression(struct drm_device *dev, int size)
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1078 unsigned long cfb_base;
1079 unsigned long ll_base = 0;
1081 /* Just in case the BIOS is doing something questionable. */
1082 intel_disable_fbc(dev);
1084 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1086 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1090 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1094 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1095 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1098 compressed_llb = drm_mm_get_block(compressed_llb,
1100 if (!compressed_llb)
1103 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1108 dev_priv->cfb_size = size;
1110 dev_priv->compressed_fb = compressed_fb;
1111 if (HAS_PCH_SPLIT(dev))
1112 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1113 else if (IS_GM45(dev)) {
1114 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1116 I915_WRITE(FBC_CFB_BASE, cfb_base);
1117 I915_WRITE(FBC_LL_BASE, ll_base);
1118 dev_priv->compressed_llb = compressed_llb;
1121 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1122 cfb_base, ll_base, size >> 20);
1126 drm_mm_put_block(compressed_llb);
1128 drm_mm_put_block(compressed_fb);
1130 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1131 i915_warn_stolen(dev);
1134 static void i915_cleanup_compression(struct drm_device *dev)
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1138 drm_mm_put_block(dev_priv->compressed_fb);
1139 if (dev_priv->compressed_llb)
1140 drm_mm_put_block(dev_priv->compressed_llb);
1143 /* true = enable decode, false = disable decoder */
1144 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1146 struct drm_device *dev = cookie;
1148 intel_modeset_vga_set_state(dev, state);
1150 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1151 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1153 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1156 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1158 struct drm_device *dev = pci_get_drvdata(pdev);
1159 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1160 if (state == VGA_SWITCHEROO_ON) {
1161 printk(KERN_INFO "i915: switched on\n");
1162 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1163 /* i915 resume handler doesn't set to D0 */
1164 pci_set_power_state(dev->pdev, PCI_D0);
1166 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1168 printk(KERN_ERR "i915: switched off\n");
1169 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1170 i915_suspend(dev, pmm);
1171 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1175 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1177 struct drm_device *dev = pci_get_drvdata(pdev);
1180 spin_lock(&dev->count_lock);
1181 can_switch = (dev->open_count == 0);
1182 spin_unlock(&dev->count_lock);
1187 intel_enable_ppgtt(struct drm_device *dev)
1189 if (i915_enable_ppgtt >= 0)
1190 return i915_enable_ppgtt;
1192 #ifdef CONFIG_INTEL_IOMMU
1193 /* Disable ppgtt on SNB if VT-d is on. */
1194 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
1201 static int i915_load_gem_init(struct drm_device *dev)
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 unsigned long prealloc_size, gtt_size, mappable_size;
1207 prealloc_size = dev_priv->mm.gtt->stolen_size;
1208 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1209 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1211 /* Basic memrange allocator for stolen space */
1212 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1214 mutex_lock(&dev->struct_mutex);
1215 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1216 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1217 * aperture accordingly when using aliasing ppgtt. */
1218 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
1219 /* For paranoia keep the guard page in between. */
1220 gtt_size -= PAGE_SIZE;
1222 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
1224 ret = i915_gem_init_aliasing_ppgtt(dev);
1228 /* Let GEM Manage all of the aperture.
1230 * However, leave one page at the end still bound to the scratch
1231 * page. There are a number of places where the hardware
1232 * apparently prefetches past the end of the object, and we've
1233 * seen multiple hangs with the GPU head pointer stuck in a
1234 * batchbuffer bound at the last page of the aperture. One page
1235 * should be enough to keep any prefetching inside of the
1238 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1241 ret = i915_gem_init_hw(dev);
1242 mutex_unlock(&dev->struct_mutex);
1244 i915_gem_cleanup_aliasing_ppgtt(dev);
1248 /* Try to set up FBC with a reasonable compressed buffer size */
1249 if (I915_HAS_FBC(dev) && i915_powersave) {
1252 /* Leave 1M for line length buffer & misc. */
1254 /* Try to get a 32M buffer... */
1255 if (prealloc_size > (36*1024*1024))
1256 cfb_size = 32*1024*1024;
1257 else /* fall back to 7/8 of the stolen space */
1258 cfb_size = prealloc_size * 7 / 8;
1259 i915_setup_compression(dev, cfb_size);
1262 /* Allow hardware batchbuffers unless told otherwise. */
1263 dev_priv->allow_batchbuffer = 1;
1267 static int i915_load_modeset_init(struct drm_device *dev)
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1272 ret = intel_parse_bios(dev);
1274 DRM_INFO("failed to find VBIOS tables\n");
1276 /* If we have > 1 VGA cards, then we need to arbitrate access
1277 * to the common VGA resources.
1279 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1280 * then we do not take part in VGA arbitration and the
1281 * vga_client_register() fails with -ENODEV.
1283 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1284 if (ret && ret != -ENODEV)
1287 intel_register_dsm_handler();
1289 ret = vga_switcheroo_register_client(dev->pdev,
1290 i915_switcheroo_set_state,
1292 i915_switcheroo_can_switch);
1294 goto cleanup_vga_client;
1296 /* IIR "flip pending" bit means done if this bit is set */
1297 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1298 dev_priv->flip_pending_is_done = true;
1300 intel_modeset_init(dev);
1302 ret = i915_load_gem_init(dev);
1304 goto cleanup_vga_switcheroo;
1306 intel_modeset_gem_init(dev);
1308 ret = drm_irq_install(dev);
1312 /* Always safe in the mode setting case. */
1313 /* FIXME: do pre/post-mode set stuff in core KMS code */
1314 dev->vblank_disable_allowed = 1;
1316 ret = intel_fbdev_init(dev);
1320 drm_kms_helper_poll_init(dev);
1322 /* We're off and running w/KMS */
1323 dev_priv->mm.suspended = 0;
1328 drm_irq_uninstall(dev);
1330 mutex_lock(&dev->struct_mutex);
1331 i915_gem_cleanup_ringbuffer(dev);
1332 mutex_unlock(&dev->struct_mutex);
1333 i915_gem_cleanup_aliasing_ppgtt(dev);
1334 cleanup_vga_switcheroo:
1335 vga_switcheroo_unregister_client(dev->pdev);
1337 vga_client_register(dev->pdev, NULL, NULL, NULL);
1342 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1344 struct drm_i915_master_private *master_priv;
1346 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1350 master->driver_priv = master_priv;
1354 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1356 struct drm_i915_master_private *master_priv = master->driver_priv;
1363 master->driver_priv = NULL;
1366 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1368 drm_i915_private_t *dev_priv = dev->dev_private;
1371 tmp = I915_READ(CLKCFG);
1373 switch (tmp & CLKCFG_FSB_MASK) {
1374 case CLKCFG_FSB_533:
1375 dev_priv->fsb_freq = 533; /* 133*4 */
1377 case CLKCFG_FSB_800:
1378 dev_priv->fsb_freq = 800; /* 200*4 */
1380 case CLKCFG_FSB_667:
1381 dev_priv->fsb_freq = 667; /* 167*4 */
1383 case CLKCFG_FSB_400:
1384 dev_priv->fsb_freq = 400; /* 100*4 */
1388 switch (tmp & CLKCFG_MEM_MASK) {
1389 case CLKCFG_MEM_533:
1390 dev_priv->mem_freq = 533;
1392 case CLKCFG_MEM_667:
1393 dev_priv->mem_freq = 667;
1395 case CLKCFG_MEM_800:
1396 dev_priv->mem_freq = 800;
1400 /* detect pineview DDR3 setting */
1401 tmp = I915_READ(CSHRDDR3CTL);
1402 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1405 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1407 drm_i915_private_t *dev_priv = dev->dev_private;
1410 ddrpll = I915_READ16(DDRMPLL1);
1411 csipll = I915_READ16(CSIPLL0);
1413 switch (ddrpll & 0xff) {
1415 dev_priv->mem_freq = 800;
1418 dev_priv->mem_freq = 1066;
1421 dev_priv->mem_freq = 1333;
1424 dev_priv->mem_freq = 1600;
1427 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1429 dev_priv->mem_freq = 0;
1433 dev_priv->r_t = dev_priv->mem_freq;
1435 switch (csipll & 0x3ff) {
1437 dev_priv->fsb_freq = 3200;
1440 dev_priv->fsb_freq = 3733;
1443 dev_priv->fsb_freq = 4266;
1446 dev_priv->fsb_freq = 4800;
1449 dev_priv->fsb_freq = 5333;
1452 dev_priv->fsb_freq = 5866;
1455 dev_priv->fsb_freq = 6400;
1458 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1460 dev_priv->fsb_freq = 0;
1464 if (dev_priv->fsb_freq == 3200) {
1466 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1473 static const struct cparams {
1479 { 1, 1333, 301, 28664 },
1480 { 1, 1066, 294, 24460 },
1481 { 1, 800, 294, 25192 },
1482 { 0, 1333, 276, 27605 },
1483 { 0, 1066, 276, 27605 },
1484 { 0, 800, 231, 23784 },
1487 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1489 u64 total_count, diff, ret;
1490 u32 count1, count2, count3, m = 0, c = 0;
1491 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1494 diff1 = now - dev_priv->last_time1;
1496 /* Prevent division-by-zero if we are asking too fast.
1497 * Also, we don't get interesting results if we are polling
1498 * faster than once in 10ms, so just return the saved value
1502 return dev_priv->chipset_power;
1504 count1 = I915_READ(DMIEC);
1505 count2 = I915_READ(DDREC);
1506 count3 = I915_READ(CSIEC);
1508 total_count = count1 + count2 + count3;
1510 /* FIXME: handle per-counter overflow */
1511 if (total_count < dev_priv->last_count1) {
1512 diff = ~0UL - dev_priv->last_count1;
1513 diff += total_count;
1515 diff = total_count - dev_priv->last_count1;
1518 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1519 if (cparams[i].i == dev_priv->c_m &&
1520 cparams[i].t == dev_priv->r_t) {
1527 diff = div_u64(diff, diff1);
1528 ret = ((m * diff) + c);
1529 ret = div_u64(ret, 10);
1531 dev_priv->last_count1 = total_count;
1532 dev_priv->last_time1 = now;
1534 dev_priv->chipset_power = ret;
1539 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1541 unsigned long m, x, b;
1544 tsfs = I915_READ(TSFS);
1546 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1547 x = I915_READ8(TR1);
1549 b = tsfs & TSFS_INTR_MASK;
1551 return ((m * x) / 127) - b;
1554 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1556 static const struct v_table {
1557 u16 vd; /* in .1 mil */
1558 u16 vm; /* in .1 mil */
1689 if (dev_priv->info->is_mobile)
1690 return v_table[pxvid].vm;
1692 return v_table[pxvid].vd;
1695 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1697 struct timespec now, diff1;
1699 unsigned long diffms;
1702 getrawmonotonic(&now);
1703 diff1 = timespec_sub(now, dev_priv->last_time2);
1705 /* Don't divide by 0 */
1706 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1710 count = I915_READ(GFXEC);
1712 if (count < dev_priv->last_count2) {
1713 diff = ~0UL - dev_priv->last_count2;
1716 diff = count - dev_priv->last_count2;
1719 dev_priv->last_count2 = count;
1720 dev_priv->last_time2 = now;
1722 /* More magic constants... */
1724 diff = div_u64(diff, diffms * 10);
1725 dev_priv->gfx_power = diff;
1728 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1730 unsigned long t, corr, state1, corr2, state2;
1733 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1734 pxvid = (pxvid >> 24) & 0x7f;
1735 ext_v = pvid_to_extvid(dev_priv, pxvid);
1739 t = i915_mch_val(dev_priv);
1741 /* Revel in the empirically derived constants */
1743 /* Correction factor in 1/100000 units */
1745 corr = ((t * 2349) + 135940);
1747 corr = ((t * 964) + 29317);
1749 corr = ((t * 301) + 1004);
1751 corr = corr * ((150142 * state1) / 10000 - 78642);
1753 corr2 = (corr * dev_priv->corr);
1755 state2 = (corr2 * state1) / 10000;
1756 state2 /= 100; /* convert to mW */
1758 i915_update_gfx_val(dev_priv);
1760 return dev_priv->gfx_power + state2;
1763 /* Global for IPS driver to get at the current i915 device */
1764 static struct drm_i915_private *i915_mch_dev;
1766 * Lock protecting IPS related data structures
1768 * - dev_priv->max_delay
1769 * - dev_priv->min_delay
1771 * - dev_priv->gpu_busy
1773 static DEFINE_SPINLOCK(mchdev_lock);
1776 * i915_read_mch_val - return value for IPS use
1778 * Calculate and return a value for the IPS driver to use when deciding whether
1779 * we have thermal and power headroom to increase CPU or GPU power budget.
1781 unsigned long i915_read_mch_val(void)
1783 struct drm_i915_private *dev_priv;
1784 unsigned long chipset_val, graphics_val, ret = 0;
1786 spin_lock(&mchdev_lock);
1789 dev_priv = i915_mch_dev;
1791 chipset_val = i915_chipset_val(dev_priv);
1792 graphics_val = i915_gfx_val(dev_priv);
1794 ret = chipset_val + graphics_val;
1797 spin_unlock(&mchdev_lock);
1801 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1804 * i915_gpu_raise - raise GPU frequency limit
1806 * Raise the limit; IPS indicates we have thermal headroom.
1808 bool i915_gpu_raise(void)
1810 struct drm_i915_private *dev_priv;
1813 spin_lock(&mchdev_lock);
1814 if (!i915_mch_dev) {
1818 dev_priv = i915_mch_dev;
1820 if (dev_priv->max_delay > dev_priv->fmax)
1821 dev_priv->max_delay--;
1824 spin_unlock(&mchdev_lock);
1828 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1831 * i915_gpu_lower - lower GPU frequency limit
1833 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1834 * frequency maximum.
1836 bool i915_gpu_lower(void)
1838 struct drm_i915_private *dev_priv;
1841 spin_lock(&mchdev_lock);
1842 if (!i915_mch_dev) {
1846 dev_priv = i915_mch_dev;
1848 if (dev_priv->max_delay < dev_priv->min_delay)
1849 dev_priv->max_delay++;
1852 spin_unlock(&mchdev_lock);
1856 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1859 * i915_gpu_busy - indicate GPU business to IPS
1861 * Tell the IPS driver whether or not the GPU is busy.
1863 bool i915_gpu_busy(void)
1865 struct drm_i915_private *dev_priv;
1868 spin_lock(&mchdev_lock);
1871 dev_priv = i915_mch_dev;
1873 ret = dev_priv->busy;
1876 spin_unlock(&mchdev_lock);
1880 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1883 * i915_gpu_turbo_disable - disable graphics turbo
1885 * Disable graphics turbo by resetting the max frequency and setting the
1886 * current frequency to the default.
1888 bool i915_gpu_turbo_disable(void)
1890 struct drm_i915_private *dev_priv;
1893 spin_lock(&mchdev_lock);
1894 if (!i915_mch_dev) {
1898 dev_priv = i915_mch_dev;
1900 dev_priv->max_delay = dev_priv->fstart;
1902 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1906 spin_unlock(&mchdev_lock);
1910 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1913 * Tells the intel_ips driver that the i915 driver is now loaded, if
1914 * IPS got loaded first.
1916 * This awkward dance is so that neither module has to depend on the
1917 * other in order for IPS to do the appropriate communication of
1918 * GPU turbo limits to i915.
1921 ips_ping_for_i915_load(void)
1925 link = symbol_get(ips_link_to_i915_driver);
1928 symbol_put(ips_link_to_i915_driver);
1933 * i915_driver_load - setup chip and create an initial config
1935 * @flags: startup flags
1937 * The driver load routine has to do several things:
1938 * - drive output discovery via intel_modeset_init()
1939 * - initialize the memory manager
1940 * - allocate initial config memory
1941 * - setup the DRM framebuffer with the allocated memory
1943 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1945 struct drm_i915_private *dev_priv;
1946 int ret = 0, mmio_bar;
1949 /* i915 has 4 more counters */
1951 dev->types[6] = _DRM_STAT_IRQ;
1952 dev->types[7] = _DRM_STAT_PRIMARY;
1953 dev->types[8] = _DRM_STAT_SECONDARY;
1954 dev->types[9] = _DRM_STAT_DMA;
1956 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1957 if (dev_priv == NULL)
1960 dev->dev_private = (void *)dev_priv;
1961 dev_priv->dev = dev;
1962 dev_priv->info = (struct intel_device_info *) flags;
1964 if (i915_get_bridge_dev(dev)) {
1969 pci_set_master(dev->pdev);
1971 /* overlay on gen2 is broken and can't address above 1G */
1973 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1975 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1976 * using 32bit addressing, overwriting memory if HWS is located
1979 * The documentation also mentions an issue with undefined
1980 * behaviour if any general state is accessed within a page above 4GB,
1981 * which also needs to be handled carefully.
1983 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1984 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1986 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1987 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1988 if (!dev_priv->regs) {
1989 DRM_ERROR("failed to map registers\n");
1994 dev_priv->mm.gtt = intel_gtt_get();
1995 if (!dev_priv->mm.gtt) {
1996 DRM_ERROR("Failed to initialize GTT\n");
2001 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
2003 dev_priv->mm.gtt_mapping =
2004 io_mapping_create_wc(dev->agp->base, agp_size);
2005 if (dev_priv->mm.gtt_mapping == NULL) {
2010 /* Set up a WC MTRR for non-PAT systems. This is more common than
2011 * one would think, because the kernel disables PAT on first
2012 * generation Core chips because WC PAT gets overridden by a UC
2013 * MTRR if present. Even if a UC MTRR isn't present.
2015 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2017 MTRR_TYPE_WRCOMB, 1);
2018 if (dev_priv->mm.gtt_mtrr < 0) {
2019 DRM_INFO("MTRR allocation failed. Graphics "
2020 "performance may suffer.\n");
2023 /* The i915 workqueue is primarily used for batched retirement of
2024 * requests (and thus managing bo) once the task has been completed
2025 * by the GPU. i915_gem_retire_requests() is called directly when we
2026 * need high-priority retirement, such as waiting for an explicit
2029 * It is also used for periodic low-priority events, such as
2030 * idle-timers and recording error state.
2032 * All tasks on the workqueue are expected to acquire the dev mutex
2033 * so there is no point in running more than one instance of the
2034 * workqueue at any time: max_active = 1 and NON_REENTRANT.
2036 dev_priv->wq = alloc_workqueue("i915",
2037 WQ_UNBOUND | WQ_NON_REENTRANT,
2039 if (dev_priv->wq == NULL) {
2040 DRM_ERROR("Failed to create our workqueue.\n");
2045 /* enable GEM by default */
2046 dev_priv->has_gem = 1;
2048 intel_irq_init(dev);
2050 /* Try to make sure MCHBAR is enabled before poking at it */
2051 intel_setup_mchbar(dev);
2052 intel_setup_gmbus(dev);
2053 intel_opregion_setup(dev);
2055 /* Make sure the bios did its job and set up vital registers */
2056 intel_setup_bios(dev);
2061 if (!I915_NEED_GFX_HWS(dev)) {
2062 ret = i915_init_phys_hws(dev);
2064 goto out_gem_unload;
2067 if (IS_PINEVIEW(dev))
2068 i915_pineview_get_mem_freq(dev);
2069 else if (IS_GEN5(dev))
2070 i915_ironlake_get_mem_freq(dev);
2072 /* On the 945G/GM, the chipset reports the MSI capability on the
2073 * integrated graphics even though the support isn't actually there
2074 * according to the published specs. It doesn't appear to function
2075 * correctly in testing on 945G.
2076 * This may be a side effect of MSI having been made available for PEG
2077 * and the registers being closely associated.
2079 * According to chipset errata, on the 965GM, MSI interrupts may
2080 * be lost or delayed, but we use them anyways to avoid
2081 * stuck interrupts on some machines.
2083 if (!IS_I945G(dev) && !IS_I945GM(dev))
2084 pci_enable_msi(dev->pdev);
2086 spin_lock_init(&dev_priv->gt_lock);
2087 spin_lock_init(&dev_priv->irq_lock);
2088 spin_lock_init(&dev_priv->error_lock);
2089 spin_lock_init(&dev_priv->rps_lock);
2091 if (IS_IVYBRIDGE(dev))
2092 dev_priv->num_pipe = 3;
2093 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
2094 dev_priv->num_pipe = 2;
2096 dev_priv->num_pipe = 1;
2098 ret = drm_vblank_init(dev, dev_priv->num_pipe);
2100 goto out_gem_unload;
2102 /* Start out suspended */
2103 dev_priv->mm.suspended = 1;
2105 intel_detect_pch(dev);
2107 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2108 ret = i915_load_modeset_init(dev);
2110 DRM_ERROR("failed to init modeset\n");
2111 goto out_gem_unload;
2115 /* Must be done after probing outputs */
2116 intel_opregion_init(dev);
2117 acpi_video_register();
2119 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2120 (unsigned long) dev);
2122 spin_lock(&mchdev_lock);
2123 i915_mch_dev = dev_priv;
2124 dev_priv->mchdev_lock = &mchdev_lock;
2125 spin_unlock(&mchdev_lock);
2127 ips_ping_for_i915_load();
2132 if (dev_priv->mm.inactive_shrinker.shrink)
2133 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2135 if (dev->pdev->msi_enabled)
2136 pci_disable_msi(dev->pdev);
2138 intel_teardown_gmbus(dev);
2139 intel_teardown_mchbar(dev);
2140 destroy_workqueue(dev_priv->wq);
2142 if (dev_priv->mm.gtt_mtrr >= 0) {
2143 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2144 dev->agp->agp_info.aper_size * 1024 * 1024);
2145 dev_priv->mm.gtt_mtrr = -1;
2147 io_mapping_free(dev_priv->mm.gtt_mapping);
2149 pci_iounmap(dev->pdev, dev_priv->regs);
2151 pci_dev_put(dev_priv->bridge_dev);
2157 int i915_driver_unload(struct drm_device *dev)
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2162 spin_lock(&mchdev_lock);
2163 i915_mch_dev = NULL;
2164 spin_unlock(&mchdev_lock);
2166 if (dev_priv->mm.inactive_shrinker.shrink)
2167 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2169 mutex_lock(&dev->struct_mutex);
2170 ret = i915_gpu_idle(dev, true);
2172 DRM_ERROR("failed to idle hardware: %d\n", ret);
2173 mutex_unlock(&dev->struct_mutex);
2175 /* Cancel the retire work handler, which should be idle now. */
2176 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2178 io_mapping_free(dev_priv->mm.gtt_mapping);
2179 if (dev_priv->mm.gtt_mtrr >= 0) {
2180 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2181 dev->agp->agp_info.aper_size * 1024 * 1024);
2182 dev_priv->mm.gtt_mtrr = -1;
2185 acpi_video_unregister();
2187 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2188 intel_fbdev_fini(dev);
2189 intel_modeset_cleanup(dev);
2192 * free the memory space allocated for the child device
2193 * config parsed from VBT
2195 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2196 kfree(dev_priv->child_dev);
2197 dev_priv->child_dev = NULL;
2198 dev_priv->child_dev_num = 0;
2201 vga_switcheroo_unregister_client(dev->pdev);
2202 vga_client_register(dev->pdev, NULL, NULL, NULL);
2205 /* Free error state after interrupts are fully disabled. */
2206 del_timer_sync(&dev_priv->hangcheck_timer);
2207 cancel_work_sync(&dev_priv->error_work);
2208 i915_destroy_error_state(dev);
2210 if (dev->pdev->msi_enabled)
2211 pci_disable_msi(dev->pdev);
2213 intel_opregion_fini(dev);
2215 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2216 /* Flush any outstanding unpin_work. */
2217 flush_workqueue(dev_priv->wq);
2219 mutex_lock(&dev->struct_mutex);
2220 i915_gem_free_all_phys_object(dev);
2221 i915_gem_cleanup_ringbuffer(dev);
2222 mutex_unlock(&dev->struct_mutex);
2223 i915_gem_cleanup_aliasing_ppgtt(dev);
2224 if (I915_HAS_FBC(dev) && i915_powersave)
2225 i915_cleanup_compression(dev);
2226 drm_mm_takedown(&dev_priv->mm.stolen);
2228 intel_cleanup_overlay(dev);
2230 if (!I915_NEED_GFX_HWS(dev))
2234 if (dev_priv->regs != NULL)
2235 pci_iounmap(dev->pdev, dev_priv->regs);
2237 intel_teardown_gmbus(dev);
2238 intel_teardown_mchbar(dev);
2240 destroy_workqueue(dev_priv->wq);
2242 pci_dev_put(dev_priv->bridge_dev);
2243 kfree(dev->dev_private);
2248 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2250 struct drm_i915_file_private *file_priv;
2252 DRM_DEBUG_DRIVER("\n");
2253 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2257 file->driver_priv = file_priv;
2259 spin_lock_init(&file_priv->mm.lock);
2260 INIT_LIST_HEAD(&file_priv->mm.request_list);
2266 * i915_driver_lastclose - clean up after all DRM clients have exited
2269 * Take care of cleaning up after all DRM clients have exited. In the
2270 * mode setting case, we want to restore the kernel's initial mode (just
2271 * in case the last client left us in a bad state).
2273 * Additionally, in the non-mode setting case, we'll tear down the AGP
2274 * and DMA structures, since the kernel won't be using them, and clea
2277 void i915_driver_lastclose(struct drm_device * dev)
2279 drm_i915_private_t *dev_priv = dev->dev_private;
2281 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2282 intel_fb_restore_mode(dev);
2283 vga_switcheroo_process_delayed_switch();
2287 i915_gem_lastclose(dev);
2289 i915_dma_cleanup(dev);
2292 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2294 i915_gem_release(dev, file_priv);
2297 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2299 struct drm_i915_file_private *file_priv = file->driver_priv;
2304 struct drm_ioctl_desc i915_ioctls[] = {
2305 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2306 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2307 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2308 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2309 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2310 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2311 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2312 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2313 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2314 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2315 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2316 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2317 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2318 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2319 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2320 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2321 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2322 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2323 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2324 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2325 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2326 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2327 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2328 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2329 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2330 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2331 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2332 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2333 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2334 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2335 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2336 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2337 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2338 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2339 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2340 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2341 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2342 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2343 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2344 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2345 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2346 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2349 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2352 * Determine if the device really is AGP or not.
2354 * All Intel graphics chipsets are treated as AGP, even if they are really
2357 * \param dev The device to be tested.
2360 * A value of 1 is always retured to indictate every i9x5 is AGP.
2362 int i915_driver_device_is_agp(struct drm_device * dev)