drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/async.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_legacy.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_vgpu.h"
  40 #include "i915_trace.h"
  41 #include <linux/pci.h>
  42 #include <linux/console.h>
  43 #include <linux/vt.h>
  44 #include <linux/vgaarb.h>
  45 #include <linux/acpi.h>
  46 #include <linux/pnp.h>
  47 #include <linux/vga_switcheroo.h>
  48 #include <linux/slab.h>
  49 #include <acpi/video.h>
  50 #include <linux/pm.h>
  51 #include <linux/pm_runtime.h>
  52 #include <linux/oom.h>
  53
  54
  55 static int i915_getparam(struct drm_device *dev, void *data,
  56                          struct drm_file *file_priv)
  57 {
  58         struct drm_i915_private *dev_priv = dev->dev_private;
  59         drm_i915_getparam_t *param = data;
  60         int value;
  61
  62         switch (param->param) {
  63         case I915_PARAM_IRQ_ACTIVE:
  64         case I915_PARAM_ALLOW_BATCHBUFFER:
  65         case I915_PARAM_LAST_DISPATCH:
  66                 /* Reject all old ums/dri params. */
  67                 return -ENODEV;
  68         case I915_PARAM_CHIPSET_ID:
  69                 value = dev->pdev->device;
  70                 break;
  71         case I915_PARAM_REVISION:
  72                 value = dev->pdev->revision;
  73                 break;
  74         case I915_PARAM_HAS_GEM:
  75                 value = 1;
  76                 break;
  77         case I915_PARAM_NUM_FENCES_AVAIL:
  78                 value = dev_priv->num_fence_regs;
  79                 break;
  80         case I915_PARAM_HAS_OVERLAY:
  81                 value = dev_priv->overlay ? 1 : 0;
  82                 break;
  83         case I915_PARAM_HAS_PAGEFLIPPING:
  84                 value = 1;
  85                 break;
  86         case I915_PARAM_HAS_EXECBUF2:
  87                 /* depends on GEM */
  88                 value = 1;
  89                 break;
  90         case I915_PARAM_HAS_BSD:
  91                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  92                 break;
  93         case I915_PARAM_HAS_BLT:
  94                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  95                 break;
  96         case I915_PARAM_HAS_VEBOX:
  97                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  98                 break;
  99         case I915_PARAM_HAS_BSD2:
 100                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
 101                 break;
 102         case I915_PARAM_HAS_RELAXED_FENCING:
 103                 value = 1;
 104                 break;
 105         case I915_PARAM_HAS_COHERENT_RINGS:
 106                 value = 1;
 107                 break;
 108         case I915_PARAM_HAS_EXEC_CONSTANTS:
 109                 value = INTEL_INFO(dev)->gen >= 4;
 110                 break;
 111         case I915_PARAM_HAS_RELAXED_DELTA:
 112                 value = 1;
 113                 break;
 114         case I915_PARAM_HAS_GEN7_SOL_RESET:
 115                 value = 1;
 116                 break;
 117         case I915_PARAM_HAS_LLC:
 118                 value = HAS_LLC(dev);
 119                 break;
 120         case I915_PARAM_HAS_WT:
 121                 value = HAS_WT(dev);
 122                 break;
 123         case I915_PARAM_HAS_ALIASING_PPGTT:
 124                 value = USES_PPGTT(dev);
 125                 break;
 126         case I915_PARAM_HAS_WAIT_TIMEOUT:
 127                 value = 1;
 128                 break;
 129         case I915_PARAM_HAS_SEMAPHORES:
 130                 value = i915_semaphore_is_enabled(dev);
 131                 break;
 132         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 133                 value = 1;
 134                 break;
 135         case I915_PARAM_HAS_SECURE_BATCHES:
 136                 value = capable(CAP_SYS_ADMIN);
 137                 break;
 138         case I915_PARAM_HAS_PINNED_BATCHES:
 139                 value = 1;
 140                 break;
 141         case I915_PARAM_HAS_EXEC_NO_RELOC:
 142                 value = 1;
 143                 break;
 144         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 145                 value = 1;
 146                 break;
 147         case I915_PARAM_CMD_PARSER_VERSION:
 148                 value = i915_cmd_parser_get_version();
 149                 break;
 150         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 151                 value = 1;
 152                 break;
 153         case I915_PARAM_MMAP_VERSION:
 154                 value = 1;
 155                 break;
 156         case I915_PARAM_SUBSLICE_TOTAL:
 157                 value = INTEL_INFO(dev)->subslice_total;
 158                 if (!value)
 159                         return -ENODEV;
 160                 break;
 161         case I915_PARAM_EU_TOTAL:
 162                 value = INTEL_INFO(dev)->eu_total;
 163                 if (!value)
 164                         return -ENODEV;
 165                 break;
 166         case I915_PARAM_HAS_GPU_RESET:
 167                 value = i915.enable_hangcheck &&
 168                         intel_has_gpu_reset(dev);
 169                 break;
 170         case I915_PARAM_HAS_RESOURCE_STREAMER:
 171                 value = HAS_RESOURCE_STREAMER(dev);
 172                 break;
 173         default:
 174                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 175                 return -EINVAL;
 176         }
 177
 178         if (copy_to_user(param->value, &value, sizeof(int))) {
 179                 DRM_ERROR("copy_to_user failed\n");
 180                 return -EFAULT;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static int i915_get_bridge_dev(struct drm_device *dev)
 187 {
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189
 190         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 191         if (!dev_priv->bridge_dev) {
 192                 DRM_ERROR("bridge device not found\n");
 193                 return -1;
 194         }
 195         return 0;
 196 }
 197
 198 #define MCHBAR_I915 0x44
 199 #define MCHBAR_I965 0x48
 200 #define MCHBAR_SIZE (4*4096)
 201
 202 #define DEVEN_REG 0x54
 203 #define   DEVEN_MCHBAR_EN (1 << 28)
 204
 205 /* Allocate space for the MCH regs if needed, return nonzero on error */
 206 static int
 207 intel_alloc_mchbar_resource(struct drm_device *dev)
 208 {
 209         struct drm_i915_private *dev_priv = dev->dev_private;
 210         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 211         u32 temp_lo, temp_hi = 0;
 212         u64 mchbar_addr;
 213         int ret;
 214
 215         if (INTEL_INFO(dev)->gen >= 4)
 216                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 217         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 218         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 219
 220         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 221 #ifdef CONFIG_PNP
 222         if (mchbar_addr &&
 223             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 224                 return 0;
 225 #endif
 226
 227         /* Get some space for it */
 228         dev_priv->mch_res.name = "i915 MCHBAR";
 229         dev_priv->mch_res.flags = IORESOURCE_MEM;
 230         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 231                                      &dev_priv->mch_res,
 232                                      MCHBAR_SIZE, MCHBAR_SIZE,
 233                                      PCIBIOS_MIN_MEM,
 234                                      0, pcibios_align_resource,
 235                                      dev_priv->bridge_dev);
 236         if (ret) {
 237                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 238                 dev_priv->mch_res.start = 0;
 239                 return ret;
 240         }
 241
 242         if (INTEL_INFO(dev)->gen >= 4)
 243                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 244                                        upper_32_bits(dev_priv->mch_res.start));
 245
 246         pci_write_config_dword(dev_priv->bridge_dev, reg,
 247                                lower_32_bits(dev_priv->mch_res.start));
 248         return 0;
 249 }
 250
 251 /* Setup MCHBAR if possible, return true if we should disable it again */
 252 static void
 253 intel_setup_mchbar(struct drm_device *dev)
 254 {
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 257         u32 temp;
 258         bool enabled;
 259
 260         if (IS_VALLEYVIEW(dev))
 261                 return;
 262
 263         dev_priv->mchbar_need_disable = false;
 264
 265         if (IS_I915G(dev) || IS_I915GM(dev)) {
 266                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 267                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 268         } else {
 269                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 270                 enabled = temp & 1;
 271         }
 272
 273         /* If it's already enabled, don't have to do anything */
 274         if (enabled)
 275                 return;
 276
 277         if (intel_alloc_mchbar_resource(dev))
 278                 return;
 279
 280         dev_priv->mchbar_need_disable = true;
 281
 282         /* Space is allocated or reserved, so enable it. */
 283         if (IS_I915G(dev) || IS_I915GM(dev)) {
 284                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 285                                        temp | DEVEN_MCHBAR_EN);
 286         } else {
 287                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 288                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 289         }
 290 }
 291
 292 static void
 293 intel_teardown_mchbar(struct drm_device *dev)
 294 {
 295         struct drm_i915_private *dev_priv = dev->dev_private;
 296         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 297         u32 temp;
 298
 299         if (dev_priv->mchbar_need_disable) {
 300                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 301                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 302                         temp &= ~DEVEN_MCHBAR_EN;
 303                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 304                 } else {
 305                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 306                         temp &= ~1;
 307                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 308                 }
 309         }
 310
 311         if (dev_priv->mch_res.start)
 312                 release_resource(&dev_priv->mch_res);
 313 }
 314
 315 /* true = enable decode, false = disable decoder */
 316 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 317 {
 318         struct drm_device *dev = cookie;
 319
 320         intel_modeset_vga_set_state(dev, state);
 321         if (state)
 322                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 323                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 324         else
 325                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 326 }
 327
 328 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 329 {
 330         struct drm_device *dev = pci_get_drvdata(pdev);
 331         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 332
 333         if (state == VGA_SWITCHEROO_ON) {
 334                 pr_info("switched on\n");
 335                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 336                 /* i915 resume handler doesn't set to D0 */
 337                 pci_set_power_state(dev->pdev, PCI_D0);
 338                 i915_resume_switcheroo(dev);
 339                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 340         } else {
 341                 pr_err("switched off\n");
 342                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 343                 i915_suspend_switcheroo(dev, pmm);
 344                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 345         }
 346 }
 347
 348 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 349 {
 350         struct drm_device *dev = pci_get_drvdata(pdev);
 351
 352         /*
 353          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 354          * locking inversion with the driver load path. And the access here is
 355          * completely racy anyway. So don't bother with locking for now.
 356          */
 357         return dev->open_count == 0;
 358 }
 359
 360 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 361         .set_gpu_state = i915_switcheroo_set_state,
 362         .reprobe = NULL,
 363         .can_switch = i915_switcheroo_can_switch,
 364 };
 365
 366 static int i915_load_modeset_init(struct drm_device *dev)
 367 {
 368         struct drm_i915_private *dev_priv = dev->dev_private;
 369         int ret;
 370
 371         ret = intel_parse_bios(dev);
 372         if (ret)
 373                 DRM_INFO("failed to find VBIOS tables\n");
 374
 375         /* If we have > 1 VGA cards, then we need to arbitrate access
 376          * to the common VGA resources.
 377          *
 378          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 379          * then we do not take part in VGA arbitration and the
 380          * vga_client_register() fails with -ENODEV.
 381          */
 382         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 383         if (ret && ret != -ENODEV)
 384                 goto out;
 385
 386         intel_register_dsm_handler();
 387
 388         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 389         if (ret)
 390                 goto cleanup_vga_client;
 391
 392         /* Initialise stolen first so that we may reserve preallocated
 393          * objects for the BIOS to KMS transition.
 394          */
 395         ret = i915_gem_init_stolen(dev);
 396         if (ret)
 397                 goto cleanup_vga_switcheroo;
 398
 399         intel_power_domains_init_hw(dev_priv);
 400
 401         ret = intel_irq_install(dev_priv);
 402         if (ret)
 403                 goto cleanup_gem_stolen;
 404
 405         /* Important: The output setup functions called by modeset_init need
 406          * working irqs for e.g. gmbus and dp aux transfers. */
 407         intel_modeset_init(dev);
 408
 409         /* intel_guc_ucode_init() needs the mutex to allocate GEM objects */
 410         mutex_lock(&dev->struct_mutex);
 411         intel_guc_ucode_init(dev);
 412         mutex_unlock(&dev->struct_mutex);
 413
 414         ret = i915_gem_init(dev);
 415         if (ret)
 416                 goto cleanup_irq;
 417
 418         intel_modeset_gem_init(dev);
 419
 420         /* Always safe in the mode setting case. */
 421         /* FIXME: do pre/post-mode set stuff in core KMS code */
 422         dev->vblank_disable_allowed = true;
 423         if (INTEL_INFO(dev)->num_pipes == 0)
 424                 return 0;
 425
 426         ret = intel_fbdev_init(dev);
 427         if (ret)
 428                 goto cleanup_gem;
 429
 430         /* Only enable hotplug handling once the fbdev is fully set up. */
 431         intel_hpd_init(dev_priv);
 432
 433         /*
 434          * Some ports require correctly set-up hpd registers for detection to
 435          * work properly (leading to ghost connected connector status), e.g. VGA
 436          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 437          * irqs are fully enabled. Now we should scan for the initial config
 438          * only once hotplug handling is enabled, but due to screwed-up locking
 439          * around kms/fbdev init we can't protect the fdbev initial config
 440          * scanning against hotplug events. Hence do this first and ignore the
 441          * tiny window where we will loose hotplug notifactions.
 442          */
 443         async_schedule(intel_fbdev_initial_config, dev_priv);
 444
 445         drm_kms_helper_poll_init(dev);
 446
 447         return 0;
 448
 449 cleanup_gem:
 450         mutex_lock(&dev->struct_mutex);
 451         i915_gem_cleanup_ringbuffer(dev);
 452         i915_gem_context_fini(dev);
 453         mutex_unlock(&dev->struct_mutex);
 454 cleanup_irq:
 455         mutex_lock(&dev->struct_mutex);
 456         intel_guc_ucode_fini(dev);
 457         mutex_unlock(&dev->struct_mutex);
 458         drm_irq_uninstall(dev);
 459 cleanup_gem_stolen:
 460         i915_gem_cleanup_stolen(dev);
 461 cleanup_vga_switcheroo:
 462         vga_switcheroo_unregister_client(dev->pdev);
 463 cleanup_vga_client:
 464         vga_client_register(dev->pdev, NULL, NULL, NULL);
 465 out:
 466         return ret;
 467 }
 468
 469 #if IS_ENABLED(CONFIG_FB)
 470 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 471 {
 472         struct apertures_struct *ap;
 473         struct pci_dev *pdev = dev_priv->dev->pdev;
 474         bool primary;
 475         int ret;
 476
 477         ap = alloc_apertures(1);
 478         if (!ap)
 479                 return -ENOMEM;
 480
 481         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 482         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 483
 484         primary =
 485                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 486
 487         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 488
 489         kfree(ap);
 490
 491         return ret;
 492 }
 493 #else
 494 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 495 {
 496         return 0;
 497 }
 498 #endif
 499
 500 #if !defined(CONFIG_VGA_CONSOLE)
 501 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 502 {
 503         return 0;
 504 }
 505 #elif !defined(CONFIG_DUMMY_CONSOLE)
 506 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 507 {
 508         return -ENODEV;
 509 }
 510 #else
 511 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 512 {
 513         int ret = 0;
 514
 515         DRM_INFO("Replacing VGA console driver\n");
 516
 517         console_lock();
 518         if (con_is_bound(&vga_con))
 519                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 520         if (ret == 0) {
 521                 ret = do_unregister_con_driver(&vga_con);
 522
 523                 /* Ignore "already unregistered". */
 524                 if (ret == -ENODEV)
 525                         ret = 0;
 526         }
 527         console_unlock();
 528
 529         return ret;
 530 }
 531 #endif
 532
 533 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 534 {
 535         const struct intel_device_info *info = &dev_priv->info;
 536
 537 #define PRINT_S(name) "%s"
 538 #define SEP_EMPTY
 539 #define PRINT_FLAG(name) info->name ? #name "," : ""
 540 #define SEP_COMMA ,
 541         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 542                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 543                          info->gen,
 544                          dev_priv->dev->pdev->device,
 545                          dev_priv->dev->pdev->revision,
 546                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 547 #undef PRINT_S
 548 #undef SEP_EMPTY
 549 #undef PRINT_FLAG
 550 #undef SEP_COMMA
 551 }
 552
 553 static void cherryview_sseu_info_init(struct drm_device *dev)
 554 {
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         struct intel_device_info *info;
 557         u32 fuse, eu_dis;
 558
 559         info = (struct intel_device_info *)&dev_priv->info;
 560         fuse = I915_READ(CHV_FUSE_GT);
 561
 562         info->slice_total = 1;
 563
 564         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 565                 info->subslice_per_slice++;
 566                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 567                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 568                 info->eu_total += 8 - hweight32(eu_dis);
 569         }
 570
 571         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 572                 info->subslice_per_slice++;
 573                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 574                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 575                 info->eu_total += 8 - hweight32(eu_dis);
 576         }
 577
 578         info->subslice_total = info->subslice_per_slice;
 579         /*
 580          * CHV expected to always have a uniform distribution of EU
 581          * across subslices.
 582         */
 583         info->eu_per_subslice = info->subslice_total ?
 584                                 info->eu_total / info->subslice_total :
 585                                 0;
 586         /*
 587          * CHV supports subslice power gating on devices with more than
 588          * one subslice, and supports EU power gating on devices with
 589          * more than one EU pair per subslice.
 590         */
 591         info->has_slice_pg = 0;
 592         info->has_subslice_pg = (info->subslice_total > 1);
 593         info->has_eu_pg = (info->eu_per_subslice > 2);
 594 }
 595
 596 static void gen9_sseu_info_init(struct drm_device *dev)
 597 {
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         struct intel_device_info *info;
 600         int s_max = 3, ss_max = 4, eu_max = 8;
 601         int s, ss;
 602         u32 fuse2, s_enable, ss_disable, eu_disable;
 603         u8 eu_mask = 0xff;
 604
 605         info = (struct intel_device_info *)&dev_priv->info;
 606         fuse2 = I915_READ(GEN8_FUSE2);
 607         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 608                    GEN8_F2_S_ENA_SHIFT;
 609         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 610                      GEN9_F2_SS_DIS_SHIFT;
 611
 612         info->slice_total = hweight32(s_enable);
 613         /*
 614          * The subslice disable field is global, i.e. it applies
 615          * to each of the enabled slices.
 616         */
 617         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 618         info->subslice_total = info->slice_total *
 619                                info->subslice_per_slice;
 620
 621         /*
 622          * Iterate through enabled slices and subslices to
 623          * count the total enabled EU.
 624         */
 625         for (s = 0; s < s_max; s++) {
 626                 if (!(s_enable & (0x1 << s)))
 627                         /* skip disabled slice */
 628                         continue;
 629
 630                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 631                 for (ss = 0; ss < ss_max; ss++) {
 632                         int eu_per_ss;
 633
 634                         if (ss_disable & (0x1 << ss))
 635                                 /* skip disabled subslice */
 636                                 continue;
 637
 638                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 639                                                       eu_mask);
 640
 641                         /*
 642                          * Record which subslice(s) has(have) 7 EUs. we
 643                          * can tune the hash used to spread work among
 644                          * subslices if they are unbalanced.
 645                          */
 646                         if (eu_per_ss == 7)
 647                                 info->subslice_7eu[s] |= 1 << ss;
 648
 649                         info->eu_total += eu_per_ss;
 650                 }
 651         }
 652
 653         /*
 654          * SKL is expected to always have a uniform distribution
 655          * of EU across subslices with the exception that any one
 656          * EU in any one subslice may be fused off for die
 657          * recovery. BXT is expected to be perfectly uniform in EU
 658          * distribution.
 659         */
 660         info->eu_per_subslice = info->subslice_total ?
 661                                 DIV_ROUND_UP(info->eu_total,
 662                                              info->subslice_total) : 0;
 663         /*
 664          * SKL supports slice power gating on devices with more than
 665          * one slice, and supports EU power gating on devices with
 666          * more than one EU pair per subslice. BXT supports subslice
 667          * power gating on devices with more than one subslice, and
 668          * supports EU power gating on devices with more than one EU
 669          * pair per subslice.
 670         */
 671         info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
 672         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 673         info->has_eu_pg = (info->eu_per_subslice > 2);
 674 }
 675
 676 static void broadwell_sseu_info_init(struct drm_device *dev)
 677 {
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         struct intel_device_info *info;
 680         const int s_max = 3, ss_max = 3, eu_max = 8;
 681         int s, ss;
 682         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
 683
 684         fuse2 = I915_READ(GEN8_FUSE2);
 685         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 686         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
 687
 688         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 689         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 690                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 691                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 692         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 693                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 694                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 695
 696
 697         info = (struct intel_device_info *)&dev_priv->info;
 698         info->slice_total = hweight32(s_enable);
 699
 700         /*
 701          * The subslice disable field is global, i.e. it applies
 702          * to each of the enabled slices.
 703          */
 704         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 705         info->subslice_total = info->slice_total * info->subslice_per_slice;
 706
 707         /*
 708          * Iterate through enabled slices and subslices to
 709          * count the total enabled EU.
 710          */
 711         for (s = 0; s < s_max; s++) {
 712                 if (!(s_enable & (0x1 << s)))
 713                         /* skip disabled slice */
 714                         continue;
 715
 716                 for (ss = 0; ss < ss_max; ss++) {
 717                         u32 n_disabled;
 718
 719                         if (ss_disable & (0x1 << ss))
 720                                 /* skip disabled subslice */
 721                                 continue;
 722
 723                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 724
 725                         /*
 726                          * Record which subslices have 7 EUs.
 727                          */
 728                         if (eu_max - n_disabled == 7)
 729                                 info->subslice_7eu[s] |= 1 << ss;
 730
 731                         info->eu_total += eu_max - n_disabled;
 732                 }
 733         }
 734
 735         /*
 736          * BDW is expected to always have a uniform distribution of EU across
 737          * subslices with the exception that any one EU in any one subslice may
 738          * be fused off for die recovery.
 739          */
 740         info->eu_per_subslice = info->subslice_total ?
 741                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
 742
 743         /*
 744          * BDW supports slice power gating on devices with more than
 745          * one slice.
 746          */
 747         info->has_slice_pg = (info->slice_total > 1);
 748         info->has_subslice_pg = 0;
 749         info->has_eu_pg = 0;
 750 }
 751
 752 /*
 753  * Determine various intel_device_info fields at runtime.
 754  *
 755  * Use it when either:
 756  *   - it's judged too laborious to fill n static structures with the limit
 757  *     when a simple if statement does the job,
 758  *   - run-time checks (eg read fuse/strap registers) are needed.
 759  *
 760  * This function needs to be called:
 761  *   - after the MMIO has been setup as we are reading registers,
 762  *   - after the PCH has been detected,
 763  *   - before the first usage of the fields it can tweak.
 764  */
 765 static void intel_device_info_runtime_init(struct drm_device *dev)
 766 {
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         struct intel_device_info *info;
 769         enum pipe pipe;
 770
 771         info = (struct intel_device_info *)&dev_priv->info;
 772
 773         /*
 774          * Skylake and Broxton currently don't expose the topmost plane as its
 775          * use is exclusive with the legacy cursor and we only want to expose
 776          * one of those, not both. Until we can safely expose the topmost plane
 777          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 778          * we don't expose the topmost plane at all to prevent ABI breakage
 779          * down the line.
 780          */
 781         if (IS_BROXTON(dev)) {
 782                 info->num_sprites[PIPE_A] = 2;
 783                 info->num_sprites[PIPE_B] = 2;
 784                 info->num_sprites[PIPE_C] = 1;
 785         } else if (IS_VALLEYVIEW(dev))
 786                 for_each_pipe(dev_priv, pipe)
 787                         info->num_sprites[pipe] = 2;
 788         else
 789                 for_each_pipe(dev_priv, pipe)
 790                         info->num_sprites[pipe] = 1;
 791
 792         if (i915.disable_display) {
 793                 DRM_INFO("Display disabled (module parameter)\n");
 794                 info->num_pipes = 0;
 795         } else if (info->num_pipes > 0 &&
 796                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 797                    !IS_VALLEYVIEW(dev)) {
 798                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 799                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 800
 801                 /*
 802                  * SFUSE_STRAP is supposed to have a bit signalling the display
 803                  * is fused off. Unfortunately it seems that, at least in
 804                  * certain cases, fused off display means that PCH display
 805                  * reads don't land anywhere. In that case, we read 0s.
 806                  *
 807                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 808                  * should be set when taking over after the firmware.
 809                  */
 810                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 811                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 812                     (dev_priv->pch_type == PCH_CPT &&
 813                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 814                         DRM_INFO("Display fused off, disabling\n");
 815                         info->num_pipes = 0;
 816                 }
 817         }
 818
 819         /* Initialize slice/subslice/EU info */
 820         if (IS_CHERRYVIEW(dev))
 821                 cherryview_sseu_info_init(dev);
 822         else if (IS_BROADWELL(dev))
 823                 broadwell_sseu_info_init(dev);
 824         else if (INTEL_INFO(dev)->gen >= 9)
 825                 gen9_sseu_info_init(dev);
 826
 827         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 828         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 829         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 830         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 831         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 832         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 833                          info->has_slice_pg ? "y" : "n");
 834         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 835                          info->has_subslice_pg ? "y" : "n");
 836         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 837                          info->has_eu_pg ? "y" : "n");
 838 }
 839
 840 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 841 {
 842         if (!IS_VALLEYVIEW(dev_priv))
 843                 return;
 844
 845         /*
 846          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 847          * CHV x1 PHY (DP/HDMI D)
 848          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 849          */
 850         if (IS_CHERRYVIEW(dev_priv)) {
 851                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 852                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 853         } else {
 854                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 855         }
 856 }
 857
 858 /**
 859  * i915_driver_load - setup chip and create an initial config
 860  * @dev: DRM device
 861  * @flags: startup flags
 862  *
 863  * The driver load routine has to do several things:
 864  *   - drive output discovery via intel_modeset_init()
 865  *   - initialize the memory manager
 866  *   - allocate initial config memory
 867  *   - setup the DRM framebuffer with the allocated memory
 868  */
 869 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 870 {
 871         struct drm_i915_private *dev_priv;
 872         struct intel_device_info *info, *device_info;
 873         int ret = 0, mmio_bar, mmio_size;
 874         uint32_t aperture_size;
 875
 876         info = (struct intel_device_info *) flags;
 877
 878         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 879         if (dev_priv == NULL)
 880                 return -ENOMEM;
 881
 882         dev->dev_private = dev_priv;
 883         dev_priv->dev = dev;
 884
 885         /* Setup the write-once "constant" device info */
 886         device_info = (struct intel_device_info *)&dev_priv->info;
 887         memcpy(device_info, info, sizeof(dev_priv->info));
 888         device_info->device_id = dev->pdev->device;
 889
 890         spin_lock_init(&dev_priv->irq_lock);
 891         spin_lock_init(&dev_priv->gpu_error.lock);
 892         mutex_init(&dev_priv->backlight_lock);
 893         spin_lock_init(&dev_priv->uncore.lock);
 894         spin_lock_init(&dev_priv->mm.object_stat_lock);
 895         spin_lock_init(&dev_priv->mmio_flip_lock);
 896         mutex_init(&dev_priv->sb_lock);
 897         mutex_init(&dev_priv->modeset_restore_lock);
 898         mutex_init(&dev_priv->csr_lock);
 899         mutex_init(&dev_priv->av_mutex);
 900
 901         intel_pm_setup(dev);
 902
 903         intel_display_crc_init(dev);
 904
 905         i915_dump_device_info(dev_priv);
 906
 907         /* Not all pre-production machines fall into this category, only the
 908          * very first ones. Almost everything should work, except for maybe
 909          * suspend/resume. And we don't implement workarounds that affect only
 910          * pre-production machines. */
 911         if (IS_HSW_EARLY_SDV(dev))
 912                 DRM_INFO("This is an early pre-production Haswell machine. "
 913                          "It may not be fully functional.\n");
 914
 915         if (i915_get_bridge_dev(dev)) {
 916                 ret = -EIO;
 917                 goto free_priv;
 918         }
 919
 920         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 921         /* Before gen4, the registers and the GTT are behind different BARs.
 922          * However, from gen4 onwards, the registers and the GTT are shared
 923          * in the same BAR, so we want to restrict this ioremap from
 924          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 925          * the register BAR remains the same size for all the earlier
 926          * generations up to Ironlake.
 927          */
 928         if (info->gen < 5)
 929                 mmio_size = 512*1024;
 930         else
 931                 mmio_size = 2*1024*1024;
 932
 933         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 934         if (!dev_priv->regs) {
 935                 DRM_ERROR("failed to map registers\n");
 936                 ret = -EIO;
 937                 goto put_bridge;
 938         }
 939
 940         /* This must be called before any calls to HAS_PCH_* */
 941         intel_detect_pch(dev);
 942
 943         intel_uncore_init(dev);
 944
 945         /* Load CSR Firmware for SKL */
 946         intel_csr_ucode_init(dev);
 947
 948         ret = i915_gem_gtt_init(dev);
 949         if (ret)
 950                 goto out_freecsr;
 951
 952         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 953          * otherwise the vga fbdev driver falls over. */
 954         ret = i915_kick_out_firmware_fb(dev_priv);
 955         if (ret) {
 956                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 957                 goto out_gtt;
 958         }
 959
 960         ret = i915_kick_out_vgacon(dev_priv);
 961         if (ret) {
 962                 DRM_ERROR("failed to remove conflicting VGA console\n");
 963                 goto out_gtt;
 964         }
 965
 966         pci_set_master(dev->pdev);
 967
 968         /* overlay on gen2 is broken and can't address above 1G */
 969         if (IS_GEN2(dev))
 970                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 971
 972         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 973          * using 32bit addressing, overwriting memory if HWS is located
 974          * above 4GB.
 975          *
 976          * The documentation also mentions an issue with undefined
 977          * behaviour if any general state is accessed within a page above 4GB,
 978          * which also needs to be handled carefully.
 979          */
 980         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 981                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 982
 983         aperture_size = dev_priv->gtt.mappable_end;
 984
 985         dev_priv->gtt.mappable =
 986                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 987                                      aperture_size);
 988         if (dev_priv->gtt.mappable == NULL) {
 989                 ret = -EIO;
 990                 goto out_gtt;
 991         }
 992
 993         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 994                                               aperture_size);
 995
 996         /* The i915 workqueue is primarily used for batched retirement of
 997          * requests (and thus managing bo) once the task has been completed
 998          * by the GPU. i915_gem_retire_requests() is called directly when we
 999          * need high-priority retirement, such as waiting for an explicit
1000          * bo.
1001          *
1002          * It is also used for periodic low-priority events, such as
1003          * idle-timers and recording error state.
1004          *
1005          * All tasks on the workqueue are expected to acquire the dev mutex
1006          * so there is no point in running more than one instance of the
1007          * workqueue at any time.  Use an ordered one.
1008          */
1009         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1010         if (dev_priv->wq == NULL) {
1011                 DRM_ERROR("Failed to create our workqueue.\n");
1012                 ret = -ENOMEM;
1013                 goto out_mtrrfree;
1014         }
1015
1016         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1017         if (dev_priv->hotplug.dp_wq == NULL) {
1018                 DRM_ERROR("Failed to create our dp workqueue.\n");
1019                 ret = -ENOMEM;
1020                 goto out_freewq;
1021         }
1022
1023         dev_priv->gpu_error.hangcheck_wq =
1024                 alloc_ordered_workqueue("i915-hangcheck", 0);
1025         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1026                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1027                 ret = -ENOMEM;
1028                 goto out_freedpwq;
1029         }
1030
1031         intel_irq_init(dev_priv);
1032         intel_uncore_sanitize(dev);
1033
1034         /* Try to make sure MCHBAR is enabled before poking at it */
1035         intel_setup_mchbar(dev);
1036         intel_setup_gmbus(dev);
1037         intel_opregion_setup(dev);
1038
1039         i915_gem_load(dev);
1040
1041         /* On the 945G/GM, the chipset reports the MSI capability on the
1042          * integrated graphics even though the support isn't actually there
1043          * according to the published specs.  It doesn't appear to function
1044          * correctly in testing on 945G.
1045          * This may be a side effect of MSI having been made available for PEG
1046          * and the registers being closely associated.
1047          *
1048          * According to chipset errata, on the 965GM, MSI interrupts may
1049          * be lost or delayed, but we use them anyways to avoid
1050          * stuck interrupts on some machines.
1051          */
1052         if (!IS_I945G(dev) && !IS_I945GM(dev))
1053                 pci_enable_msi(dev->pdev);
1054
1055         intel_device_info_runtime_init(dev);
1056
1057         intel_init_dpio(dev_priv);
1058
1059         if (INTEL_INFO(dev)->num_pipes) {
1060                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1061                 if (ret)
1062                         goto out_gem_unload;
1063         }
1064
1065         intel_power_domains_init(dev_priv);
1066
1067         ret = i915_load_modeset_init(dev);
1068         if (ret < 0) {
1069                 DRM_ERROR("failed to init modeset\n");
1070                 goto out_power_well;
1071         }
1072
1073         /*
1074          * Notify a valid surface after modesetting,
1075          * when running inside a VM.
1076          */
1077         if (intel_vgpu_active(dev))
1078                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1079
1080         i915_setup_sysfs(dev);
1081
1082         if (INTEL_INFO(dev)->num_pipes) {
1083                 /* Must be done after probing outputs */
1084                 intel_opregion_init(dev);
1085                 acpi_video_register();
1086         }
1087
1088         if (IS_GEN5(dev))
1089                 intel_gpu_ips_init(dev_priv);
1090
1091         intel_runtime_pm_enable(dev_priv);
1092
1093         i915_audio_component_init(dev_priv);
1094
1095         return 0;
1096
1097 out_power_well:
1098         intel_power_domains_fini(dev_priv);
1099         drm_vblank_cleanup(dev);
1100 out_gem_unload:
1101         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1102         unregister_shrinker(&dev_priv->mm.shrinker);
1103
1104         if (dev->pdev->msi_enabled)
1105                 pci_disable_msi(dev->pdev);
1106
1107         intel_teardown_gmbus(dev);
1108         intel_teardown_mchbar(dev);
1109         pm_qos_remove_request(&dev_priv->pm_qos);
1110         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1111 out_freedpwq:
1112         destroy_workqueue(dev_priv->hotplug.dp_wq);
1113 out_freewq:
1114         destroy_workqueue(dev_priv->wq);
1115 out_mtrrfree:
1116         arch_phys_wc_del(dev_priv->gtt.mtrr);
1117         io_mapping_free(dev_priv->gtt.mappable);
1118 out_gtt:
1119         i915_global_gtt_cleanup(dev);
1120 out_freecsr:
1121         intel_csr_ucode_fini(dev);
1122         intel_uncore_fini(dev);
1123         pci_iounmap(dev->pdev, dev_priv->regs);
1124 put_bridge:
1125         pci_dev_put(dev_priv->bridge_dev);
1126 free_priv:
1127         kmem_cache_destroy(dev_priv->requests);
1128         kmem_cache_destroy(dev_priv->vmas);
1129         kmem_cache_destroy(dev_priv->objects);
1130         kfree(dev_priv);
1131         return ret;
1132 }
1133
1134 int i915_driver_unload(struct drm_device *dev)
1135 {
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         int ret;
1138
1139         i915_audio_component_cleanup(dev_priv);
1140
1141         ret = i915_gem_suspend(dev);
1142         if (ret) {
1143                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1144                 return ret;
1145         }
1146
1147         intel_power_domains_fini(dev_priv);
1148
1149         intel_gpu_ips_teardown();
1150
1151         i915_teardown_sysfs(dev);
1152
1153         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1154         unregister_shrinker(&dev_priv->mm.shrinker);
1155
1156         io_mapping_free(dev_priv->gtt.mappable);
1157         arch_phys_wc_del(dev_priv->gtt.mtrr);
1158
1159         acpi_video_unregister();
1160
1161         intel_fbdev_fini(dev);
1162
1163         drm_vblank_cleanup(dev);
1164
1165         intel_modeset_cleanup(dev);
1166
1167         /*
1168          * free the memory space allocated for the child device
1169          * config parsed from VBT
1170          */
1171         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1172                 kfree(dev_priv->vbt.child_dev);
1173                 dev_priv->vbt.child_dev = NULL;
1174                 dev_priv->vbt.child_dev_num = 0;
1175         }
1176         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1177         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1178         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1179         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1180
1181         vga_switcheroo_unregister_client(dev->pdev);
1182         vga_client_register(dev->pdev, NULL, NULL, NULL);
1183
1184         /* Free error state after interrupts are fully disabled. */
1185         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1186         i915_destroy_error_state(dev);
1187
1188         if (dev->pdev->msi_enabled)
1189                 pci_disable_msi(dev->pdev);
1190
1191         intel_opregion_fini(dev);
1192
1193         /* Flush any outstanding unpin_work. */
1194         flush_workqueue(dev_priv->wq);
1195
1196         mutex_lock(&dev->struct_mutex);
1197         intel_guc_ucode_fini(dev);
1198         i915_gem_cleanup_ringbuffer(dev);
1199         i915_gem_context_fini(dev);
1200         mutex_unlock(&dev->struct_mutex);
1201         intel_fbc_cleanup_cfb(dev_priv);
1202         i915_gem_cleanup_stolen(dev);
1203
1204         intel_csr_ucode_fini(dev);
1205
1206         intel_teardown_gmbus(dev);
1207         intel_teardown_mchbar(dev);
1208
1209         destroy_workqueue(dev_priv->hotplug.dp_wq);
1210         destroy_workqueue(dev_priv->wq);
1211         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1212         pm_qos_remove_request(&dev_priv->pm_qos);
1213
1214         i915_global_gtt_cleanup(dev);
1215
1216         intel_uncore_fini(dev);
1217         if (dev_priv->regs != NULL)
1218                 pci_iounmap(dev->pdev, dev_priv->regs);
1219
1220         kmem_cache_destroy(dev_priv->requests);
1221         kmem_cache_destroy(dev_priv->vmas);
1222         kmem_cache_destroy(dev_priv->objects);
1223         pci_dev_put(dev_priv->bridge_dev);
1224         kfree(dev_priv);
1225
1226         return 0;
1227 }
1228
1229 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1230 {
1231         int ret;
1232
1233         ret = i915_gem_open(dev, file);
1234         if (ret)
1235                 return ret;
1236
1237         return 0;
1238 }
1239
1240 /**
1241  * i915_driver_lastclose - clean up after all DRM clients have exited
1242  * @dev: DRM device
1243  *
1244  * Take care of cleaning up after all DRM clients have exited.  In the
1245  * mode setting case, we want to restore the kernel's initial mode (just
1246  * in case the last client left us in a bad state).
1247  *
1248  * Additionally, in the non-mode setting case, we'll tear down the GTT
1249  * and DMA structures, since the kernel won't be using them, and clea
1250  * up any GEM state.
1251  */
1252 void i915_driver_lastclose(struct drm_device *dev)
1253 {
1254         intel_fbdev_restore_mode(dev);
1255         vga_switcheroo_process_delayed_switch();
1256 }
1257
1258 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1259 {
1260         mutex_lock(&dev->struct_mutex);
1261         i915_gem_context_close(dev, file);
1262         i915_gem_release(dev, file);
1263         mutex_unlock(&dev->struct_mutex);
1264
1265         intel_modeset_preclose(dev, file);
1266 }
1267
1268 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1269 {
1270         struct drm_i915_file_private *file_priv = file->driver_priv;
1271
1272         if (file_priv && file_priv->bsd_ring)
1273                 file_priv->bsd_ring = NULL;
1274         kfree(file_priv);
1275 }
1276
1277 static int
1278 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1279                           struct drm_file *file)
1280 {
1281         return -ENODEV;
1282 }
1283
1284 const struct drm_ioctl_desc i915_ioctls[] = {
1285         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1286         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1287         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1288         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1289         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1290         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1291         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1292         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1293         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1294         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1295         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1296         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1297         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1298         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1299         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1300         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1301         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1302         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1303         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1304         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1305         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1306         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1307         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1308         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1309         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1310         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1311         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1312         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1313         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1314         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1315         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1316         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1317         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1318         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1319         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1320         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1321         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1322         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1323         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1324         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1325         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1326         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1327         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1328         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1329         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1330         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1331         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1332         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1333         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1334         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1335         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1336         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1337 };
1338
1339 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);